2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
40 #include "../benode.h"
42 #include "../beutil.h"
43 #include "../betranshlp.h"
44 #include "../beabihelper.h"
47 #include "bearch_arm_t.h"
48 #include "arm_nodes_attr.h"
49 #include "arm_transform.h"
50 #include "arm_optimize.h"
51 #include "arm_new_nodes.h"
52 #include "arm_map_regs.h"
53 #include "arm_cconv.h"
55 #include "gen_arm_regalloc_if.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static const arch_register_t *sp_reg = &arm_registers[REG_SP];
62 static ir_mode *mode_gp;
63 static ir_mode *mode_fp;
64 static beabi_helper_env_t *abihelper;
65 static calling_convention_t *cconv = NULL;
66 static arm_isa_t *isa;
68 static pmap *node_to_stack;
70 static bool mode_needs_gp_reg(ir_mode *mode)
72 return mode_is_int(mode) || mode_is_reference(mode);
76 * create firm graph for a constant
78 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
85 /* We only have 8 bit immediates. So we possibly have to combine several
86 * operations to construct the desired value.
88 * we can either create the value by adding bits to 0 or by removing bits
89 * from an register with all bits set. Try which alternative needs fewer
91 arm_gen_vals_from_word(value, &v);
92 arm_gen_vals_from_word(~value, &vn);
96 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
97 be_dep_on_frame(result);
99 for (cnt = 1; cnt < vn.ops; ++cnt) {
100 result = new_bd_arm_Bic_imm(dbgi, block, result,
101 vn.values[cnt], vn.rors[cnt]);
105 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
106 be_dep_on_frame(result);
108 for (cnt = 1; cnt < v.ops; ++cnt) {
109 result = new_bd_arm_Or_imm(dbgi, block, result,
110 v.values[cnt], v.rors[cnt]);
117 * Create a DAG constructing a given Const.
119 * @param irn a Firm const
121 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
123 tarval *tv = get_Const_tarval(irn);
124 ir_mode *mode = get_tarval_mode(tv);
127 if (mode_is_reference(mode)) {
128 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
129 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
130 tv = tarval_convert_to(tv, mode_Iu);
132 value = get_tarval_long(tv);
133 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
137 * Create an And that will zero out upper bits.
139 * @param dbgi debug info
140 * @param block the basic block
141 * @param op the original node
142 * param src_bits number of lower bits that will remain
144 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
148 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
149 } else if (src_bits == 16) {
150 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
151 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
154 panic("zero extension only supported for 8 and 16 bits");
159 * Generate code for a sign extension.
161 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
164 int shift_width = 32 - src_bits;
165 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
166 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
170 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
173 int bits = get_mode_size_bits(orig_mode);
177 if (mode_is_signed(orig_mode)) {
178 return gen_sign_extension(dbgi, block, op, bits);
180 return gen_zero_extension(dbgi, block, op, bits);
185 * returns true if it is assured, that the upper bits of a node are "clean"
186 * which means for a 16 or 8 bit value, that the upper bits in the register
187 * are 0 for unsigned and a copy of the last significant bit for signed
190 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
192 (void) transformed_node;
199 * Transforms a Conv node.
201 * @return The created ia32 Conv node
203 static ir_node *gen_Conv(ir_node *node)
205 ir_node *block = be_transform_node(get_nodes_block(node));
206 ir_node *op = get_Conv_op(node);
207 ir_node *new_op = be_transform_node(op);
208 ir_mode *src_mode = get_irn_mode(op);
209 ir_mode *dst_mode = get_irn_mode(node);
210 dbg_info *dbg = get_irn_dbg_info(node);
212 if (src_mode == dst_mode)
215 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
217 if (mode_is_float(src_mode)) {
218 if (mode_is_float(dst_mode)) {
219 /* from float to float */
220 return new_bd_arm_Mvf(dbg, block, new_op, dst_mode);
222 /* from float to int */
226 /* from int to float */
227 if (!mode_is_signed(src_mode)) {
230 return new_bd_arm_FltX(dbg, block, new_op, dst_mode);
233 } else if (USE_VFP(isa)) {
234 panic("VFP not supported yet");
236 panic("Softfloat not supported yet");
238 } else { /* complete in gp registers */
239 int src_bits = get_mode_size_bits(src_mode);
240 int dst_bits = get_mode_size_bits(dst_mode);
244 if (src_bits == dst_bits) {
245 /* kill unnecessary conv */
249 if (src_bits < dst_bits) {
257 if (upper_bits_clean(new_op, min_mode)) {
261 if (mode_is_signed(min_mode)) {
262 return gen_sign_extension(dbg, block, new_op, min_bits);
264 return gen_zero_extension(dbg, block, new_op, min_bits);
274 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
276 unsigned val, low_pos, high_pos;
281 val = get_tarval_long(get_Const_tarval(node));
293 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
295 So we determine the smallest even position with a bit set
296 and the highest even position with no bit set anymore.
297 If the difference between these 2 is <= 8, then we can encode the value
300 low_pos = ntz(val) & ~1u;
301 high_pos = (32-nlz(val)+1) & ~1u;
303 if (high_pos - low_pos <= 8) {
304 res->imm_8 = val >> low_pos;
305 res->rot = 32 - low_pos;
310 res->rot = 34 - high_pos;
311 val = val >> (32-res->rot) | val << (res->rot);
321 static bool is_downconv(const ir_node *node)
329 /* we only want to skip the conv when we're the only user
330 * (not optimal but for now...)
332 if (get_irn_n_edges(node) > 1)
335 src_mode = get_irn_mode(get_Conv_op(node));
336 dest_mode = get_irn_mode(node);
338 mode_needs_gp_reg(src_mode) &&
339 mode_needs_gp_reg(dest_mode) &&
340 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
343 static ir_node *arm_skip_downconv(ir_node *node)
345 while (is_downconv(node))
346 node = get_Conv_op(node);
352 MATCH_COMMUTATIVE = 1 << 0, /**< commutative node */
353 MATCH_REVERSE = 1 << 1, /**< support reverse opcode */
354 MATCH_SIZE_NEUTRAL = 1 << 2,
355 MATCH_SKIP_NOT = 1 << 3, /**< skip Not on ONE input */
359 * possible binop constructors.
361 typedef struct arm_binop_factory_t {
362 /** normal reg op reg operation. */
363 ir_node *(*new_binop_reg)(dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
364 /** normal reg op imm operation. */
365 ir_node *(*new_binop_imm)(dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
366 /** barrel shifter reg op (reg shift reg operation. */
367 ir_node *(*new_binop_reg_shift_reg)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *shift, arm_shift_modifier_t shift_modifier);
368 /** barrel shifter reg op (reg shift imm operation. */
369 ir_node *(*new_binop_reg_shift_imm)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, arm_shift_modifier_t shift_modifier, unsigned shift_immediate);
370 } arm_binop_factory_t;
372 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
373 const arm_binop_factory_t *factory)
375 ir_node *block = be_transform_node(get_nodes_block(node));
376 ir_node *op1 = get_binop_left(node);
378 ir_node *op2 = get_binop_right(node);
380 dbg_info *dbgi = get_irn_dbg_info(node);
383 if (flags & MATCH_SKIP_NOT) {
385 op1 = get_Not_op(op1);
386 else if (is_Not(op2))
387 op2 = get_Not_op(op2);
389 panic("cannot execute MATCH_SKIP_NOT");
391 if (flags & MATCH_SIZE_NEUTRAL) {
392 op1 = arm_skip_downconv(op1);
393 op2 = arm_skip_downconv(op2);
395 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
398 if (try_encode_as_immediate(op2, &imm)) {
399 ir_node *new_op1 = be_transform_node(op1);
400 return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
402 new_op2 = be_transform_node(op2);
403 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && try_encode_as_immediate(op1, &imm)) {
404 if (flags & MATCH_REVERSE)
405 return factory[1].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
407 return factory[0].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
409 new_op1 = be_transform_node(op1);
411 /* check if we can fold in a Mov */
412 if (is_arm_Mov(new_op2)) {
413 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op2);
415 switch (attr->shift_modifier) {
417 case ARM_SHF_ASR_IMM:
418 case ARM_SHF_LSL_IMM:
419 case ARM_SHF_LSR_IMM:
420 case ARM_SHF_ROR_IMM:
421 if (factory->new_binop_reg_shift_imm) {
422 ir_node *mov_op = get_irn_n(new_op2, 0);
423 return factory->new_binop_reg_shift_imm(dbgi, block, new_op1, mov_op,
424 attr->shift_modifier, attr->shift_immediate);
428 case ARM_SHF_ASR_REG:
429 case ARM_SHF_LSL_REG:
430 case ARM_SHF_LSR_REG:
431 case ARM_SHF_ROR_REG:
432 if (factory->new_binop_reg_shift_reg) {
433 ir_node *mov_op = get_irn_n(new_op2, 0);
434 ir_node *mov_sft = get_irn_n(new_op2, 1);
435 return factory->new_binop_reg_shift_reg(dbgi, block, new_op1, mov_op, mov_sft,
436 attr->shift_modifier);
442 case ARM_SHF_INVALID:
443 panic("invalid shift");
446 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && is_arm_Mov(new_op1)) {
447 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op1);
448 int idx = flags & MATCH_REVERSE ? 1 : 0;
450 switch (attr->shift_modifier) {
451 ir_node *mov_op, *mov_sft;
454 case ARM_SHF_ASR_IMM:
455 case ARM_SHF_LSL_IMM:
456 case ARM_SHF_LSR_IMM:
457 case ARM_SHF_ROR_IMM:
458 if (factory[idx].new_binop_reg_shift_imm) {
459 mov_op = get_irn_n(new_op1, 0);
460 return factory[idx].new_binop_reg_shift_imm(dbgi, block, new_op2, mov_op,
461 attr->shift_modifier, attr->shift_immediate);
465 case ARM_SHF_ASR_REG:
466 case ARM_SHF_LSL_REG:
467 case ARM_SHF_LSR_REG:
468 case ARM_SHF_ROR_REG:
469 if (factory[idx].new_binop_reg_shift_reg) {
470 mov_op = get_irn_n(new_op1, 0);
471 mov_sft = get_irn_n(new_op1, 1);
472 return factory[idx].new_binop_reg_shift_reg(dbgi, block, new_op2, mov_op, mov_sft,
473 attr->shift_modifier);
480 case ARM_SHF_INVALID:
481 panic("invalid shift");
484 return factory->new_binop_reg(dbgi, block, new_op1, new_op2);
488 * Creates an ARM Add.
490 * @return the created arm Add node
492 static ir_node *gen_Add(ir_node *node)
494 static const arm_binop_factory_t add_factory = {
497 new_bd_arm_Add_reg_shift_reg,
498 new_bd_arm_Add_reg_shift_imm
501 ir_mode *mode = get_irn_mode(node);
503 if (mode_is_float(mode)) {
504 ir_node *block = be_transform_node(get_nodes_block(node));
505 ir_node *op1 = get_Add_left(node);
506 ir_node *op2 = get_Add_right(node);
507 dbg_info *dbgi = get_irn_dbg_info(node);
508 ir_node *new_op1 = be_transform_node(op1);
509 ir_node *new_op2 = be_transform_node(op2);
511 return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
512 } else if (USE_VFP(isa)) {
513 assert(mode != mode_E && "IEEE Extended FP not supported");
514 panic("VFP not supported yet");
516 panic("Softfloat not supported yet");
521 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
523 new_op2 = get_irn_n(new_op1, 1);
524 new_op1 = get_irn_n(new_op1, 0);
526 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
528 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
530 new_op1 = get_irn_n(new_op2, 0);
531 new_op2 = get_irn_n(new_op2, 1);
533 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
537 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &add_factory);
542 * Creates an ARM Mul.
544 * @return the created arm Mul node
546 static ir_node *gen_Mul(ir_node *node)
548 ir_node *block = be_transform_node(get_nodes_block(node));
549 ir_node *op1 = get_Mul_left(node);
550 ir_node *new_op1 = be_transform_node(op1);
551 ir_node *op2 = get_Mul_right(node);
552 ir_node *new_op2 = be_transform_node(op2);
553 ir_mode *mode = get_irn_mode(node);
554 dbg_info *dbg = get_irn_dbg_info(node);
556 if (mode_is_float(mode)) {
558 return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
559 } else if (USE_VFP(isa)) {
560 assert(mode != mode_E && "IEEE Extended FP not supported");
561 panic("VFP not supported yet");
563 panic("Softfloat not supported yet");
566 assert(mode_is_data(mode));
567 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
570 static ir_node *gen_Quot(ir_node *node)
572 ir_node *block = be_transform_node(get_nodes_block(node));
573 ir_node *op1 = get_Quot_left(node);
574 ir_node *new_op1 = be_transform_node(op1);
575 ir_node *op2 = get_Quot_right(node);
576 ir_node *new_op2 = be_transform_node(op2);
577 ir_mode *mode = get_irn_mode(node);
578 dbg_info *dbg = get_irn_dbg_info(node);
580 assert(mode != mode_E && "IEEE Extended FP not supported");
583 return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
584 } else if (USE_VFP(isa)) {
585 assert(mode != mode_E && "IEEE Extended FP not supported");
586 panic("VFP not supported yet");
588 panic("Softfloat not supported yet");
592 static ir_node *gen_And(ir_node *node)
594 static const arm_binop_factory_t and_factory = {
597 new_bd_arm_And_reg_shift_reg,
598 new_bd_arm_And_reg_shift_imm
600 static const arm_binop_factory_t bic_factory = {
603 new_bd_arm_Bic_reg_shift_reg,
604 new_bd_arm_Bic_reg_shift_imm
607 /* check for and not */
608 ir_node *left = get_And_left(node);
609 ir_node *right = get_And_right(node);
611 if (is_Not(left) || is_Not(right)) {
612 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL | MATCH_SKIP_NOT,
616 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &and_factory);
619 static ir_node *gen_Or(ir_node *node)
621 static const arm_binop_factory_t or_factory = {
624 new_bd_arm_Or_reg_shift_reg,
625 new_bd_arm_Or_reg_shift_imm
628 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &or_factory);
631 static ir_node *gen_Eor(ir_node *node)
633 static const arm_binop_factory_t eor_factory = {
636 new_bd_arm_Eor_reg_shift_reg,
637 new_bd_arm_Eor_reg_shift_imm
640 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &eor_factory);
643 static ir_node *gen_Sub(ir_node *node)
645 static const arm_binop_factory_t sub_rsb_factory[2] = {
649 new_bd_arm_Sub_reg_shift_reg,
650 new_bd_arm_Sub_reg_shift_imm
655 new_bd_arm_Rsb_reg_shift_reg,
656 new_bd_arm_Rsb_reg_shift_imm
660 ir_node *block = be_transform_node(get_nodes_block(node));
661 ir_node *op1 = get_Sub_left(node);
662 ir_node *new_op1 = be_transform_node(op1);
663 ir_node *op2 = get_Sub_right(node);
664 ir_node *new_op2 = be_transform_node(op2);
665 ir_mode *mode = get_irn_mode(node);
666 dbg_info *dbgi = get_irn_dbg_info(node);
668 if (mode_is_float(mode)) {
670 return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
671 } else if (USE_VFP(isa)) {
672 assert(mode != mode_E && "IEEE Extended FP not supported");
673 panic("VFP not supported yet");
675 panic("Softfloat not supported yet");
678 return gen_int_binop(node, MATCH_SIZE_NEUTRAL | MATCH_REVERSE, sub_rsb_factory);
683 * Checks if a given value can be used as an immediate for the given
686 static bool can_use_shift_constant(unsigned int val,
687 arm_shift_modifier_t modifier)
691 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
697 * generate an ARM shift instruction.
699 * @param node the node
700 * @param flags matching flags
701 * @param shift_modifier initial encoding of the desired shift operation
703 static ir_node *make_shift(ir_node *node, match_flags_t flags,
704 arm_shift_modifier_t shift_modifier)
706 ir_node *block = be_transform_node(get_nodes_block(node));
707 ir_node *op1 = get_binop_left(node);
708 ir_node *op2 = get_binop_right(node);
709 dbg_info *dbgi = get_irn_dbg_info(node);
713 if (flags & MATCH_SIZE_NEUTRAL) {
714 op1 = arm_skip_downconv(op1);
715 op2 = arm_skip_downconv(op2);
718 new_op1 = be_transform_node(op1);
720 tarval *tv = get_Const_tarval(op2);
721 unsigned int val = get_tarval_long(tv);
722 assert(tarval_is_long(tv));
723 if (can_use_shift_constant(val, shift_modifier)) {
724 switch (shift_modifier) {
725 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
726 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
727 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
728 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
729 default: panic("unexpected shift modifier");
731 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
732 shift_modifier, val);
736 new_op2 = be_transform_node(op2);
737 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
741 static ir_node *gen_Shl(ir_node *node)
743 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
746 static ir_node *gen_Shr(ir_node *node)
748 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
751 static ir_node *gen_Shrs(ir_node *node)
753 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
756 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
758 ir_node *block = be_transform_node(get_nodes_block(node));
759 ir_node *new_op1 = be_transform_node(op1);
760 dbg_info *dbgi = get_irn_dbg_info(node);
761 ir_node *new_op2 = be_transform_node(op2);
763 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
767 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
769 ir_node *block = be_transform_node(get_nodes_block(node));
770 ir_node *new_op1 = be_transform_node(op1);
771 dbg_info *dbgi = get_irn_dbg_info(node);
772 ir_node *new_op2 = be_transform_node(op2);
774 /* Note: there is no Rol on arm, we have to use Ror */
775 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
776 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
780 static ir_node *gen_Rotl(ir_node *node)
782 ir_node *rotate = NULL;
783 ir_node *op1 = get_Rotl_left(node);
784 ir_node *op2 = get_Rotl_right(node);
786 /* Firm has only RotL, so we are looking for a right (op2)
787 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
788 that means we can create a RotR. */
791 ir_node *right = get_Add_right(op2);
792 if (is_Const(right)) {
793 tarval *tv = get_Const_tarval(right);
794 ir_mode *mode = get_irn_mode(node);
795 long bits = get_mode_size_bits(mode);
796 ir_node *left = get_Add_left(op2);
798 if (is_Minus(left) &&
799 tarval_is_long(tv) &&
800 get_tarval_long(tv) == bits &&
802 rotate = gen_Ror(node, op1, get_Minus_op(left));
804 } else if (is_Sub(op2)) {
805 ir_node *left = get_Sub_left(op2);
806 if (is_Const(left)) {
807 tarval *tv = get_Const_tarval(left);
808 ir_mode *mode = get_irn_mode(node);
809 long bits = get_mode_size_bits(mode);
810 ir_node *right = get_Sub_right(op2);
812 if (tarval_is_long(tv) &&
813 get_tarval_long(tv) == bits &&
815 rotate = gen_Ror(node, op1, right);
817 } else if (is_Const(op2)) {
818 tarval *tv = get_Const_tarval(op2);
819 ir_mode *mode = get_irn_mode(node);
820 long bits = get_mode_size_bits(mode);
822 if (tarval_is_long(tv) && bits == 32) {
823 ir_node *block = be_transform_node(get_nodes_block(node));
824 ir_node *new_op1 = be_transform_node(op1);
825 dbg_info *dbgi = get_irn_dbg_info(node);
827 bits = (bits - get_tarval_long(tv)) & 31;
828 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
832 if (rotate == NULL) {
833 rotate = gen_Rol(node, op1, op2);
839 static ir_node *gen_Not(ir_node *node)
841 ir_node *block = be_transform_node(get_nodes_block(node));
842 ir_node *op = get_Not_op(node);
843 ir_node *new_op = be_transform_node(op);
844 dbg_info *dbgi = get_irn_dbg_info(node);
846 /* check if we can fold in a Mov */
847 if (is_arm_Mov(new_op)) {
848 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op);
850 switch (attr->shift_modifier) {
851 ir_node *mov_op, *mov_sft;
854 case ARM_SHF_ASR_IMM:
855 case ARM_SHF_LSL_IMM:
856 case ARM_SHF_LSR_IMM:
857 case ARM_SHF_ROR_IMM:
858 mov_op = get_irn_n(new_op, 0);
859 return new_bd_arm_Mvn_reg_shift_imm(dbgi, block, mov_op,
860 attr->shift_modifier, attr->shift_immediate);
862 case ARM_SHF_ASR_REG:
863 case ARM_SHF_LSL_REG:
864 case ARM_SHF_LSR_REG:
865 case ARM_SHF_ROR_REG:
866 mov_op = get_irn_n(new_op, 0);
867 mov_sft = get_irn_n(new_op, 1);
868 return new_bd_arm_Mvn_reg_shift_reg(dbgi, block, mov_op, mov_sft,
869 attr->shift_modifier);
874 case ARM_SHF_INVALID:
875 panic("invalid shift");
879 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
882 static ir_node *gen_Minus(ir_node *node)
884 ir_node *block = be_transform_node(get_nodes_block(node));
885 ir_node *op = get_Minus_op(node);
886 ir_node *new_op = be_transform_node(op);
887 dbg_info *dbgi = get_irn_dbg_info(node);
888 ir_mode *mode = get_irn_mode(node);
890 if (mode_is_float(mode)) {
892 return new_bd_arm_Mvf(dbgi, block, op, mode);
893 } else if (USE_VFP(isa)) {
894 assert(mode != mode_E && "IEEE Extended FP not supported");
895 panic("VFP not supported yet");
897 panic("Softfloat not supported yet");
900 assert(mode_is_data(mode));
901 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
904 static ir_node *gen_Load(ir_node *node)
906 ir_node *block = be_transform_node(get_nodes_block(node));
907 ir_node *ptr = get_Load_ptr(node);
908 ir_node *new_ptr = be_transform_node(ptr);
909 ir_node *mem = get_Load_mem(node);
910 ir_node *new_mem = be_transform_node(mem);
911 ir_mode *mode = get_Load_mode(node);
912 dbg_info *dbgi = get_irn_dbg_info(node);
913 ir_node *new_load = NULL;
915 if (mode_is_float(mode)) {
917 new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
919 } else if (USE_VFP(isa)) {
920 assert(mode != mode_E && "IEEE Extended FP not supported");
921 panic("VFP not supported yet");
923 panic("Softfloat not supported yet");
926 assert(mode_is_data(mode) && "unsupported mode for Load");
928 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
930 set_irn_pinned(new_load, get_irn_pinned(node));
932 /* check for special case: the loaded value might not be used */
933 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
934 /* add a result proj and a Keep to produce a pseudo use */
935 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
936 be_new_Keep(block, 1, &proj);
942 static ir_node *gen_Store(ir_node *node)
944 ir_node *block = be_transform_node(get_nodes_block(node));
945 ir_node *ptr = get_Store_ptr(node);
946 ir_node *new_ptr = be_transform_node(ptr);
947 ir_node *mem = get_Store_mem(node);
948 ir_node *new_mem = be_transform_node(mem);
949 ir_node *val = get_Store_value(node);
950 ir_node *new_val = be_transform_node(val);
951 ir_mode *mode = get_irn_mode(val);
952 dbg_info *dbgi = get_irn_dbg_info(node);
953 ir_node *new_store = NULL;
955 if (mode_is_float(mode)) {
957 new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
958 new_mem, mode, NULL, 0, 0, false);
959 } else if (USE_VFP(isa)) {
960 assert(mode != mode_E && "IEEE Extended FP not supported");
961 panic("VFP not supported yet");
963 panic("Softfloat not supported yet");
966 assert(mode_is_data(mode) && "unsupported mode for Store");
967 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
970 set_irn_pinned(new_store, get_irn_pinned(node));
974 static ir_node *gen_Jmp(ir_node *node)
976 ir_node *block = get_nodes_block(node);
977 ir_node *new_block = be_transform_node(block);
978 dbg_info *dbgi = get_irn_dbg_info(node);
980 return new_bd_arm_Jmp(dbgi, new_block);
983 static ir_node *gen_SwitchJmp(ir_node *node)
985 ir_node *block = be_transform_node(get_nodes_block(node));
986 ir_node *selector = get_Cond_selector(node);
987 dbg_info *dbgi = get_irn_dbg_info(node);
988 ir_node *new_op = be_transform_node(selector);
989 ir_node *const_graph;
993 const ir_edge_t *edge;
1000 foreach_out_edge(node, edge) {
1001 proj = get_edge_src_irn(edge);
1002 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1004 pn = get_Proj_proj(proj);
1006 min = pn<min ? pn : min;
1007 max = pn>max ? pn : max;
1010 n_projs = max - translation + 1;
1012 foreach_out_edge(node, edge) {
1013 proj = get_edge_src_irn(edge);
1014 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1016 pn = get_Proj_proj(proj) - translation;
1017 set_Proj_proj(proj, pn);
1020 const_graph = create_const_graph_value(dbgi, block, translation);
1021 sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
1022 return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
1025 static ir_node *gen_Cmp(ir_node *node)
1027 ir_node *block = be_transform_node(get_nodes_block(node));
1028 ir_node *op1 = get_Cmp_left(node);
1029 ir_node *op2 = get_Cmp_right(node);
1030 ir_mode *cmp_mode = get_irn_mode(op1);
1031 dbg_info *dbgi = get_irn_dbg_info(node);
1036 if (mode_is_float(cmp_mode)) {
1037 /* TODO: this is broken... */
1038 new_op1 = be_transform_node(op1);
1039 new_op2 = be_transform_node(op2);
1041 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
1044 assert(get_irn_mode(op2) == cmp_mode);
1045 is_unsigned = !mode_is_signed(cmp_mode);
1047 /* integer compare, TODO: use shifter_op in all its combinations */
1048 new_op1 = be_transform_node(op1);
1049 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
1050 new_op2 = be_transform_node(op2);
1051 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
1052 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
1056 static ir_node *gen_Cond(ir_node *node)
1058 ir_node *selector = get_Cond_selector(node);
1059 ir_mode *mode = get_irn_mode(selector);
1064 if (mode != mode_b) {
1065 return gen_SwitchJmp(node);
1067 assert(is_Proj(selector));
1069 block = be_transform_node(get_nodes_block(node));
1070 dbgi = get_irn_dbg_info(node);
1071 flag_node = be_transform_node(get_Proj_pred(selector));
1073 return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector));
1076 static tarval *fpa_imm[3][fpa_max];
1080 * Check, if a floating point tarval is an fpa immediate, i.e.
1081 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
1083 static int is_fpa_immediate(tarval *tv)
1085 ir_mode *mode = get_tarval_mode(tv);
1088 switch (get_mode_size_bits(mode)) {
1099 if (tarval_is_negative(tv)) {
1100 tv = tarval_neg(tv);
1104 for (j = 0; j < fpa_max; ++j) {
1105 if (tv == fpa_imm[i][j])
1112 static ir_node *gen_Const(ir_node *node)
1114 ir_node *block = be_transform_node(get_nodes_block(node));
1115 ir_mode *mode = get_irn_mode(node);
1116 dbg_info *dbg = get_irn_dbg_info(node);
1118 if (mode_is_float(mode)) {
1120 tarval *tv = get_Const_tarval(node);
1121 node = new_bd_arm_fConst(dbg, block, tv);
1122 be_dep_on_frame(node);
1124 } else if (USE_VFP(isa)) {
1125 assert(mode != mode_E && "IEEE Extended FP not supported");
1126 panic("VFP not supported yet");
1128 panic("Softfloat not supported yet");
1131 return create_const_graph(node, block);
1134 static ir_node *gen_SymConst(ir_node *node)
1136 ir_node *block = be_transform_node(get_nodes_block(node));
1137 ir_entity *entity = get_SymConst_entity(node);
1138 dbg_info *dbgi = get_irn_dbg_info(node);
1141 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
1142 be_dep_on_frame(new_node);
1146 static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0,
1149 /* the good way to do this would be to use the stm (store multiple)
1150 * instructions, since our input is nearly always 2 consecutive 32bit
1152 ir_graph *irg = current_ir_graph;
1153 ir_node *stack = get_irg_frame(irg);
1154 ir_node *nomem = new_r_NoMem(irg);
1155 ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp,
1157 ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp,
1159 ir_node *in[2] = { str0, str1 };
1160 ir_node *sync = new_r_Sync(block, 2, in);
1162 set_irn_pinned(str0, op_pin_state_floats);
1163 set_irn_pinned(str1, op_pin_state_floats);
1165 ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true);
1166 set_irn_pinned(ldf, op_pin_state_floats);
1168 return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1171 static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node)
1173 ir_graph *irg = current_ir_graph;
1174 ir_node *stack = get_irg_frame(irg);
1175 ir_node *nomem = new_r_NoMem(irg);
1176 ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp,
1179 set_irn_pinned(str, op_pin_state_floats);
1181 ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true);
1182 set_irn_pinned(ldf, op_pin_state_floats);
1184 return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1187 static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node)
1189 ir_graph *irg = current_ir_graph;
1190 ir_node *stack = get_irg_frame(irg);
1191 ir_node *nomem = new_r_NoMem(irg);
1192 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F,
1195 set_irn_pinned(stf, op_pin_state_floats);
1197 ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1198 set_irn_pinned(ldr, op_pin_state_floats);
1200 return new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1203 static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node,
1204 ir_node **out_value0, ir_node **out_value1)
1206 ir_graph *irg = current_ir_graph;
1207 ir_node *stack = get_irg_frame(irg);
1208 ir_node *nomem = new_r_NoMem(irg);
1209 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D,
1211 ir_node *ldr0, *ldr1;
1212 set_irn_pinned(stf, op_pin_state_floats);
1214 ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1215 set_irn_pinned(ldr0, op_pin_state_floats);
1216 ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true);
1217 set_irn_pinned(ldr1, op_pin_state_floats);
1219 *out_value0 = new_r_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
1220 *out_value1 = new_r_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
1223 static ir_node *gen_CopyB(ir_node *node)
1225 ir_node *block = be_transform_node(get_nodes_block(node));
1226 ir_node *src = get_CopyB_src(node);
1227 ir_node *new_src = be_transform_node(src);
1228 ir_node *dst = get_CopyB_dst(node);
1229 ir_node *new_dst = be_transform_node(dst);
1230 ir_node *mem = get_CopyB_mem(node);
1231 ir_node *new_mem = be_transform_node(mem);
1232 dbg_info *dbg = get_irn_dbg_info(node);
1233 int size = get_type_size_bytes(get_CopyB_type(node));
1237 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
1238 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
1240 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1241 new_bd_arm_EmptyReg(dbg, block),
1242 new_bd_arm_EmptyReg(dbg, block),
1243 new_bd_arm_EmptyReg(dbg, block),
1248 * Transform builtin clz.
1250 static ir_node *gen_clz(ir_node *node)
1252 ir_node *block = be_transform_node(get_nodes_block(node));
1253 dbg_info *dbg = get_irn_dbg_info(node);
1254 ir_node *op = get_irn_n(node, 1);
1255 ir_node *new_op = be_transform_node(op);
1257 /* TODO armv5 instruction, otherwise create a call */
1258 return new_bd_arm_Clz(dbg, block, new_op);
1262 * Transform Builtin node.
1264 static ir_node *gen_Builtin(ir_node *node)
1266 ir_builtin_kind kind = get_Builtin_kind(node);
1270 case ir_bk_debugbreak:
1271 case ir_bk_return_address:
1272 case ir_bk_frame_address:
1273 case ir_bk_prefetch:
1277 return gen_clz(node);
1280 case ir_bk_popcount:
1284 case ir_bk_inner_trampoline:
1287 panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
1291 * Transform Proj(Builtin) node.
1293 static ir_node *gen_Proj_Builtin(ir_node *proj)
1295 ir_node *node = get_Proj_pred(proj);
1296 ir_node *new_node = be_transform_node(node);
1297 ir_builtin_kind kind = get_Builtin_kind(node);
1300 case ir_bk_return_address:
1301 case ir_bk_frame_address:
1306 case ir_bk_popcount:
1308 assert(get_Proj_proj(proj) == pn_Builtin_1_result);
1311 case ir_bk_debugbreak:
1312 case ir_bk_prefetch:
1314 assert(get_Proj_proj(proj) == pn_Builtin_M);
1317 case ir_bk_inner_trampoline:
1320 panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
1323 static ir_node *gen_Proj_Load(ir_node *node)
1325 ir_node *load = get_Proj_pred(node);
1326 ir_node *new_load = be_transform_node(load);
1327 dbg_info *dbgi = get_irn_dbg_info(node);
1328 long proj = get_Proj_proj(node);
1330 /* renumber the proj */
1331 switch (get_arm_irn_opcode(new_load)) {
1333 /* handle all gp loads equal: they have the same proj numbers. */
1334 if (proj == pn_Load_res) {
1335 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1336 } else if (proj == pn_Load_M) {
1337 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1341 if (proj == pn_Load_res) {
1342 ir_mode *mode = get_Load_mode(load);
1343 return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res);
1344 } else if (proj == pn_Load_M) {
1345 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M);
1351 panic("Unsupported Proj from Load");
1354 static ir_node *gen_Proj_CopyB(ir_node *node)
1356 ir_node *pred = get_Proj_pred(node);
1357 ir_node *new_pred = be_transform_node(pred);
1358 dbg_info *dbgi = get_irn_dbg_info(node);
1359 long proj = get_Proj_proj(node);
1363 if (is_arm_CopyB(new_pred)) {
1364 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1370 panic("Unsupported Proj from CopyB");
1373 static ir_node *gen_Proj_Quot(ir_node *node)
1375 ir_node *pred = get_Proj_pred(node);
1376 ir_node *new_pred = be_transform_node(pred);
1377 dbg_info *dbgi = get_irn_dbg_info(node);
1378 ir_mode *mode = get_irn_mode(node);
1379 long proj = get_Proj_proj(node);
1383 if (is_arm_Dvf(new_pred)) {
1384 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
1388 if (is_arm_Dvf(new_pred)) {
1389 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
1395 panic("Unsupported Proj from Quot");
1399 * Transform the Projs from a Cmp.
1401 static ir_node *gen_Proj_Cmp(ir_node *node)
1404 /* we should only be here in case of a Mux node */
1408 static ir_node *gen_Proj_Start(ir_node *node)
1410 ir_node *block = get_nodes_block(node);
1411 ir_node *new_block = be_transform_node(block);
1412 ir_node *barrier = be_transform_node(get_Proj_pred(node));
1413 long proj = get_Proj_proj(node);
1415 switch ((pn_Start) proj) {
1416 case pn_Start_X_initial_exec:
1417 /* we exchange the ProjX with a jump */
1418 return new_bd_arm_Jmp(NULL, new_block);
1421 return new_r_Proj(barrier, mode_M, 0);
1423 case pn_Start_T_args:
1426 case pn_Start_P_frame_base:
1427 return be_prolog_get_reg_value(abihelper, sp_reg);
1429 case pn_Start_P_tls:
1430 return new_r_Bad(get_irn_irg(node));
1435 panic("unexpected start proj: %ld\n", proj);
1438 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1440 long pn = get_Proj_proj(node);
1441 ir_node *block = get_nodes_block(node);
1442 ir_node *new_block = be_transform_node(block);
1443 ir_entity *entity = get_irg_entity(current_ir_graph);
1444 ir_type *method_type = get_entity_type(entity);
1445 ir_type *param_type = get_method_param_type(method_type, pn);
1446 const reg_or_stackslot_t *param;
1448 /* Proj->Proj->Start must be a method argument */
1449 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1451 param = &cconv->parameters[pn];
1453 if (param->reg0 != NULL) {
1454 /* argument transmitted in register */
1455 ir_mode *mode = get_type_mode(param_type);
1456 ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0);
1458 if (mode_is_float(mode)) {
1459 ir_node *value1 = NULL;
1461 if (param->reg1 != NULL) {
1462 value1 = be_prolog_get_reg_value(abihelper, param->reg1);
1463 } else if (param->entity != NULL) {
1464 ir_graph *irg = get_irn_irg(node);
1465 ir_node *fp = get_irg_frame(irg);
1466 ir_node *mem = be_prolog_get_memory(abihelper);
1467 ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem,
1468 mode_gp, param->entity,
1470 value1 = new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1473 /* convert integer value to float */
1474 if (value1 == NULL) {
1475 value = int_to_float(NULL, new_block, value);
1477 value = ints_to_double(NULL, new_block, value, value1);
1482 /* argument transmitted on stack */
1483 ir_graph *irg = get_irn_irg(node);
1484 ir_node *fp = get_irg_frame(irg);
1485 ir_node *mem = be_prolog_get_memory(abihelper);
1486 ir_mode *mode = get_type_mode(param->type);
1490 if (mode_is_float(mode)) {
1491 load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode,
1492 param->entity, 0, 0, true);
1493 value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res);
1495 load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1496 param->entity, 0, 0, true);
1497 value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1499 set_irn_pinned(load, op_pin_state_floats);
1506 * Finds number of output value of a mode_T node which is constrained to
1507 * a single specific register.
1509 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1511 int n_outs = arch_irn_get_n_outs(node);
1514 for (o = 0; o < n_outs; ++o) {
1515 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1516 if (req == reg->single_req)
1522 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1524 long pn = get_Proj_proj(node);
1525 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1526 ir_node *new_call = be_transform_node(call);
1527 ir_type *function_type = get_Call_type(call);
1528 calling_convention_t *cconv = arm_decide_calling_convention(function_type);
1529 const reg_or_stackslot_t *res = &cconv->results[pn];
1533 /* TODO 64bit modes */
1534 assert(res->reg0 != NULL && res->reg1 == NULL);
1535 regn = find_out_for_reg(new_call, res->reg0);
1537 panic("Internal error in calling convention for return %+F", node);
1539 mode = res->reg0->reg_class->mode;
1541 arm_free_calling_convention(cconv);
1543 return new_r_Proj(new_call, mode, regn);
1546 static ir_node *gen_Proj_Call(ir_node *node)
1548 long pn = get_Proj_proj(node);
1549 ir_node *call = get_Proj_pred(node);
1550 ir_node *new_call = be_transform_node(call);
1552 switch ((pn_Call) pn) {
1554 return new_r_Proj(new_call, mode_M, 0);
1555 case pn_Call_X_regular:
1556 case pn_Call_X_except:
1557 case pn_Call_T_result:
1558 case pn_Call_P_value_res_base:
1562 panic("Unexpected Call proj %ld\n", pn);
1566 * Transform a Proj node.
1568 static ir_node *gen_Proj(ir_node *node)
1570 ir_node *pred = get_Proj_pred(node);
1571 long proj = get_Proj_proj(node);
1573 switch (get_irn_opcode(pred)) {
1575 if (proj == pn_Store_M) {
1576 return be_transform_node(pred);
1578 panic("Unsupported Proj from Store");
1581 return gen_Proj_Load(node);
1583 return gen_Proj_Call(node);
1585 return gen_Proj_CopyB(node);
1587 return gen_Proj_Quot(node);
1589 return gen_Proj_Cmp(node);
1591 return gen_Proj_Start(node);
1594 return be_duplicate_node(node);
1596 ir_node *pred_pred = get_Proj_pred(pred);
1597 if (is_Call(pred_pred)) {
1598 return gen_Proj_Proj_Call(node);
1599 } else if (is_Start(pred_pred)) {
1600 return gen_Proj_Proj_Start(node);
1605 return gen_Proj_Builtin(node);
1607 panic("code selection didn't expect Proj after %+F\n", pred);
1611 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1613 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
1614 create_const_node_func func,
1615 const arch_register_t* reg)
1617 ir_node *block, *res;
1622 block = get_irg_start_block(irg);
1623 res = func(NULL, block);
1624 arch_set_irn_register(res, reg);
1629 static ir_node *gen_Unknown(ir_node *node)
1631 ir_node *block = get_nodes_block(node);
1632 ir_node *new_block = be_transform_node(block);
1633 dbg_info *dbgi = get_irn_dbg_info(node);
1635 /* just produce a 0 */
1636 ir_mode *mode = get_irn_mode(node);
1637 if (mode_is_float(mode)) {
1638 tarval *tv = get_mode_null(mode);
1639 ir_node *node = new_bd_arm_fConst(dbgi, new_block, tv);
1640 be_dep_on_frame(node);
1642 } else if (mode_needs_gp_reg(mode)) {
1643 return create_const_graph_value(dbgi, new_block, 0);
1646 panic("Unexpected Unknown mode");
1650 * Produces the type which sits between the stack args and the locals on the
1651 * stack. It will contain the return address and space to store the old base
1653 * @return The Firm type modeling the ABI between type.
1655 static ir_type *arm_get_between_type(void)
1657 static ir_type *between_type = NULL;
1659 if (between_type == NULL) {
1660 between_type = new_type_class(new_id_from_str("arm_between_type"));
1661 set_type_size_bytes(between_type, 0);
1664 return between_type;
1667 static void create_stacklayout(ir_graph *irg)
1669 ir_entity *entity = get_irg_entity(irg);
1670 ir_type *function_type = get_entity_type(entity);
1671 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1676 /* calling conventions must be decided by now */
1677 assert(cconv != NULL);
1679 /* construct argument type */
1680 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1681 n_params = get_method_n_params(function_type);
1682 for (p = 0; p < n_params; ++p) {
1683 reg_or_stackslot_t *param = &cconv->parameters[p];
1687 if (param->type == NULL)
1690 snprintf(buf, sizeof(buf), "param_%d", p);
1691 id = new_id_from_str(buf);
1692 param->entity = new_entity(arg_type, id, param->type);
1693 set_entity_offset(param->entity, param->offset);
1696 /* TODO: what about external functions? we don't know most of the stack
1697 * layout for them. And probably don't need all of this... */
1698 memset(layout, 0, sizeof(*layout));
1700 layout->frame_type = get_irg_frame_type(irg);
1701 layout->between_type = arm_get_between_type();
1702 layout->arg_type = arg_type;
1703 layout->param_map = NULL; /* TODO */
1704 layout->initial_offset = 0;
1705 layout->initial_bias = 0;
1706 layout->stack_dir = -1;
1707 layout->sp_relative = true;
1709 assert(N_FRAME_TYPES == 3);
1710 layout->order[0] = layout->frame_type;
1711 layout->order[1] = layout->between_type;
1712 layout->order[2] = layout->arg_type;
1716 * transform the start node to the prolog code + initial barrier
1718 static ir_node *gen_Start(ir_node *node)
1720 ir_graph *irg = get_irn_irg(node);
1721 ir_entity *entity = get_irg_entity(irg);
1722 ir_type *function_type = get_entity_type(entity);
1723 ir_node *block = get_nodes_block(node);
1724 ir_node *new_block = be_transform_node(block);
1725 dbg_info *dbgi = get_irn_dbg_info(node);
1732 /* stackpointer is important at function prolog */
1733 be_prolog_add_reg(abihelper, sp_reg,
1734 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1735 /* function parameters in registers */
1736 for (i = 0; i < get_method_n_params(function_type); ++i) {
1737 const reg_or_stackslot_t *param = &cconv->parameters[i];
1738 if (param->reg0 != NULL)
1739 be_prolog_add_reg(abihelper, param->reg0, 0);
1740 if (param->reg1 != NULL)
1741 be_prolog_add_reg(abihelper, param->reg1, 0);
1743 /* announce that we need the values of the callee save regs */
1744 for (i = 0; i < (int) (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
1745 be_prolog_add_reg(abihelper, callee_saves[i], 0);
1748 start = be_prolog_create_start(abihelper, dbgi, new_block);
1749 sp = be_prolog_get_reg_value(abihelper, sp_reg);
1750 incsp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
1751 be_prolog_set_reg_value(abihelper, sp_reg, incsp);
1752 barrier = be_prolog_create_barrier(abihelper, new_block);
1757 static ir_node *get_stack_pointer_for(ir_node *node)
1759 /* get predecessor in stack_order list */
1760 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1761 ir_node *stack_pred_transformed;
1764 if (stack_pred == NULL) {
1765 /* first stack user in the current block. We can simply use the
1766 * initial sp_proj for it */
1767 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1771 stack_pred_transformed = be_transform_node(stack_pred);
1772 stack = pmap_get(node_to_stack, stack_pred);
1773 if (stack == NULL) {
1774 return get_stack_pointer_for(stack_pred);
1781 * transform a Return node into epilogue code + return statement
1783 static ir_node *gen_Return(ir_node *node)
1785 ir_node *block = get_nodes_block(node);
1786 ir_node *new_block = be_transform_node(block);
1787 dbg_info *dbgi = get_irn_dbg_info(node);
1788 ir_node *mem = get_Return_mem(node);
1789 ir_node *new_mem = be_transform_node(mem);
1790 int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
1791 ir_node *sp_proj = get_stack_pointer_for(node);
1792 int n_res = get_Return_n_ress(node);
1797 be_epilog_begin(abihelper);
1798 be_epilog_set_memory(abihelper, new_mem);
1799 /* connect stack pointer with initial stack pointer. fix_stack phase
1800 will later serialize all stack pointer adjusting nodes */
1801 be_epilog_add_reg(abihelper, sp_reg,
1802 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1806 for (i = 0; i < n_res; ++i) {
1807 ir_node *res_value = get_Return_res(node, i);
1808 ir_node *new_res_value = be_transform_node(res_value);
1809 const reg_or_stackslot_t *slot = &cconv->results[i];
1810 const arch_register_t *reg = slot->reg0;
1811 assert(slot->reg1 == NULL);
1812 be_epilog_add_reg(abihelper, reg, 0, new_res_value);
1815 /* connect callee saves with their values at the function begin */
1816 for (i = 0; i < n_callee_saves; ++i) {
1817 const arch_register_t *reg = callee_saves[i];
1818 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1819 be_epilog_add_reg(abihelper, reg, 0, value);
1822 /* create the barrier before the epilog code */
1823 be_epilog_create_barrier(abihelper, new_block);
1825 /* epilog code: an incsp */
1826 sp_proj = be_epilog_get_reg_value(abihelper, sp_reg);
1827 incsp = be_new_IncSP(sp_reg, new_block, sp_proj,
1828 BE_STACK_FRAME_SIZE_SHRINK, 0);
1829 be_epilog_set_reg_value(abihelper, sp_reg, incsp);
1831 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1837 static ir_node *gen_Call(ir_node *node)
1839 ir_graph *irg = get_irn_irg(node);
1840 ir_node *callee = get_Call_ptr(node);
1841 ir_node *block = get_nodes_block(node);
1842 ir_node *new_block = be_transform_node(block);
1843 ir_node *mem = get_Call_mem(node);
1844 ir_node *new_mem = be_transform_node(mem);
1845 dbg_info *dbgi = get_irn_dbg_info(node);
1846 ir_type *type = get_Call_type(node);
1847 calling_convention_t *cconv = arm_decide_calling_convention(type);
1848 int n_params = get_Call_n_params(node);
1849 int n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
1850 /* max inputs: memory, callee, register arguments */
1851 int max_inputs = 2 + n_param_regs;
1852 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1853 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1854 struct obstack *obst = be_get_be_obst(irg);
1855 const arch_register_req_t **in_req
1856 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1860 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1861 ir_entity *entity = NULL;
1862 ir_node *incsp = NULL;
1869 assert(n_params == get_method_n_params(type));
1871 /* construct arguments */
1874 in_req[in_arity] = arch_no_register_req;
1878 for (p = 0; p < n_params; ++p) {
1879 ir_node *value = get_Call_param(node, p);
1880 ir_node *new_value = be_transform_node(value);
1881 ir_node *new_value1 = NULL;
1882 const reg_or_stackslot_t *param = &cconv->parameters[p];
1883 ir_type *param_type = get_method_param_type(type, p);
1884 ir_mode *mode = get_type_mode(param_type);
1887 if (mode_is_float(mode) && param->reg0 != NULL) {
1888 unsigned size_bits = get_mode_size_bits(mode);
1889 if (size_bits == 64) {
1890 double_to_ints(dbgi, new_block, new_value, &new_value,
1893 assert(size_bits == 32);
1894 new_value = float_to_int(dbgi, new_block, new_value);
1898 /* put value into registers */
1899 if (param->reg0 != NULL) {
1900 in[in_arity] = new_value;
1901 in_req[in_arity] = param->reg0->single_req;
1903 if (new_value1 == NULL)
1906 if (param->reg1 != NULL) {
1907 assert(new_value1 != NULL);
1908 in[in_arity] = new_value1;
1909 in_req[in_arity] = param->reg1->single_req;
1914 /* we need a store if we're here */
1915 if (new_value1 != NULL) {
1916 new_value = new_value1;
1920 /* create a parameter frame if necessary */
1921 if (incsp == NULL) {
1922 ir_node *new_frame = get_stack_pointer_for(node);
1923 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1924 cconv->param_stack_size, 1);
1926 if (mode_is_float(mode)) {
1927 str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem,
1928 mode, NULL, 0, param->offset, true);
1930 str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem,
1931 mode, NULL, 0, param->offset, true);
1933 sync_ins[sync_arity++] = str;
1935 assert(in_arity <= max_inputs);
1937 /* construct memory input */
1938 if (sync_arity == 0) {
1939 in[mem_pos] = new_mem;
1940 } else if (sync_arity == 1) {
1941 in[mem_pos] = sync_ins[0];
1943 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1946 /* TODO: use a generic symconst matcher here */
1947 if (is_SymConst(callee)) {
1948 entity = get_SymConst_entity(callee);
1950 /* TODO: finish load matcher here */
1953 if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) {
1954 ir_node *load = get_Proj_pred(callee);
1955 ir_node *ptr = get_Load_ptr(load);
1956 ir_node *new_ptr = be_transform_node(ptr);
1957 ir_node *mem = get_Load_mem(load);
1958 ir_node *new_mem = be_transform_node(mem);
1959 ir_mode *mode = get_Load_mode(node);
1963 in[in_arity] = be_transform_node(callee);
1964 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1973 out_arity = 1 + n_caller_saves;
1975 if (entity != NULL) {
1976 /* TODO: use a generic symconst matcher here
1977 * so we can also handle entity+offset, etc. */
1978 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1981 * - use a proper shifter_operand matcher
1982 * - we could also use LinkLdrPC
1984 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1988 if (incsp != NULL) {
1989 /* IncSP to destroy the call stackframe */
1990 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
1992 /* if we are the last IncSP producer in a block then we have to keep
1994 * Note: This here keeps all producers which is more than necessary */
1995 add_irn_dep(incsp, res);
1998 pmap_insert(node_to_stack, node, incsp);
2001 arch_set_in_register_reqs(res, in_req);
2003 /* create output register reqs */
2004 arch_set_out_register_req(res, 0, arch_no_register_req);
2005 for (o = 0; o < n_caller_saves; ++o) {
2006 const arch_register_t *reg = caller_saves[o];
2007 arch_set_out_register_req(res, o+1, reg->single_req);
2010 /* copy pinned attribute */
2011 set_irn_pinned(res, get_irn_pinned(node));
2013 arm_free_calling_convention(cconv);
2017 static ir_node *gen_Sel(ir_node *node)
2019 dbg_info *dbgi = get_irn_dbg_info(node);
2020 ir_node *block = get_nodes_block(node);
2021 ir_node *new_block = be_transform_node(block);
2022 ir_node *ptr = get_Sel_ptr(node);
2023 ir_node *new_ptr = be_transform_node(ptr);
2024 ir_entity *entity = get_Sel_entity(node);
2026 /* must be the frame pointer all other sels must have been lowered
2028 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
2029 /* we should not have value types from parameters anymore - they should be
2031 assert(get_entity_owner(entity) !=
2032 get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
2034 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
2038 * Change some phi modes
2040 static ir_node *gen_Phi(ir_node *node)
2042 const arch_register_req_t *req;
2043 ir_node *block = be_transform_node(get_nodes_block(node));
2044 ir_graph *irg = current_ir_graph;
2045 dbg_info *dbgi = get_irn_dbg_info(node);
2046 ir_mode *mode = get_irn_mode(node);
2049 if (mode_needs_gp_reg(mode)) {
2050 /* we shouldn't have any 64bit stuff around anymore */
2051 assert(get_mode_size_bits(mode) <= 32);
2052 /* all integer operations are on 32bit registers now */
2054 req = arm_reg_classes[CLASS_arm_gp].class_req;
2056 req = arch_no_register_req;
2059 /* phi nodes allow loops, so we use the old arguments for now
2060 * and fix this later */
2061 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
2062 get_irn_in(node) + 1);
2063 copy_node_attr(irg, node, phi);
2064 be_duplicate_deps(node, phi);
2066 arch_set_out_register_req(phi, 0, req);
2068 be_enqueue_preds(node);
2075 * Enters all transform functions into the generic pointer
2077 static void arm_register_transformers(void)
2079 be_start_transform_setup();
2081 be_set_transform_function(op_Add, gen_Add);
2082 be_set_transform_function(op_And, gen_And);
2083 be_set_transform_function(op_Call, gen_Call);
2084 be_set_transform_function(op_Cmp, gen_Cmp);
2085 be_set_transform_function(op_Cond, gen_Cond);
2086 be_set_transform_function(op_Const, gen_Const);
2087 be_set_transform_function(op_Conv, gen_Conv);
2088 be_set_transform_function(op_CopyB, gen_CopyB);
2089 be_set_transform_function(op_Eor, gen_Eor);
2090 be_set_transform_function(op_Jmp, gen_Jmp);
2091 be_set_transform_function(op_Load, gen_Load);
2092 be_set_transform_function(op_Minus, gen_Minus);
2093 be_set_transform_function(op_Mul, gen_Mul);
2094 be_set_transform_function(op_Not, gen_Not);
2095 be_set_transform_function(op_Or, gen_Or);
2096 be_set_transform_function(op_Phi, gen_Phi);
2097 be_set_transform_function(op_Proj, gen_Proj);
2098 be_set_transform_function(op_Quot, gen_Quot);
2099 be_set_transform_function(op_Return, gen_Return);
2100 be_set_transform_function(op_Rotl, gen_Rotl);
2101 be_set_transform_function(op_Sel, gen_Sel);
2102 be_set_transform_function(op_Shl, gen_Shl);
2103 be_set_transform_function(op_Shr, gen_Shr);
2104 be_set_transform_function(op_Shrs, gen_Shrs);
2105 be_set_transform_function(op_Start, gen_Start);
2106 be_set_transform_function(op_Store, gen_Store);
2107 be_set_transform_function(op_Sub, gen_Sub);
2108 be_set_transform_function(op_SymConst, gen_SymConst);
2109 be_set_transform_function(op_Unknown, gen_Unknown);
2110 be_set_transform_function(op_Builtin, gen_Builtin);
2114 * Initialize fpa Immediate support.
2116 static void arm_init_fpa_immediate(void)
2118 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
2119 fpa_imm[0][fpa_null] = get_mode_null(mode_F);
2120 fpa_imm[0][fpa_one] = get_mode_one(mode_F);
2121 fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
2122 fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
2123 fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
2124 fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
2125 fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
2126 fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
2128 fpa_imm[1][fpa_null] = get_mode_null(mode_D);
2129 fpa_imm[1][fpa_one] = get_mode_one(mode_D);
2130 fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
2131 fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
2132 fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
2133 fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
2134 fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
2135 fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
2137 fpa_imm[2][fpa_null] = get_mode_null(mode_E);
2138 fpa_imm[2][fpa_one] = get_mode_one(mode_E);
2139 fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
2140 fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
2141 fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
2142 fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
2143 fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
2144 fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
2148 * Transform a Firm graph into an ARM graph.
2150 void arm_transform_graph(ir_graph *irg)
2152 static int imm_initialized = 0;
2153 ir_entity *entity = get_irg_entity(irg);
2154 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
2155 ir_type *frame_type;
2160 if (! imm_initialized) {
2161 arm_init_fpa_immediate();
2162 imm_initialized = 1;
2164 arm_register_transformers();
2166 isa = (arm_isa_t*) arch_env;
2168 node_to_stack = pmap_create();
2170 assert(abihelper == NULL);
2171 abihelper = be_abihelper_prepare(irg);
2172 be_collect_stacknodes(abihelper);
2173 assert(cconv == NULL);
2174 cconv = arm_decide_calling_convention(get_entity_type(entity));
2175 create_stacklayout(irg);
2177 be_transform_graph(irg, NULL);
2179 be_abihelper_finish(abihelper);
2182 arm_free_calling_convention(cconv);
2185 frame_type = get_irg_frame_type(irg);
2186 if (get_type_state(frame_type) == layout_undefined) {
2187 default_layout_compound_type(frame_type);
2190 pmap_destroy(node_to_stack);
2191 node_to_stack = NULL;
2193 be_add_missing_keeps(irg);
2196 void arm_init_transform(void)
2198 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");