2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
40 #include "../benode.h"
42 #include "../beutil.h"
43 #include "../betranshlp.h"
44 #include "../beabihelper.h"
47 #include "bearch_arm_t.h"
48 #include "arm_nodes_attr.h"
49 #include "arm_transform.h"
50 #include "arm_optimize.h"
51 #include "arm_new_nodes.h"
52 #include "arm_map_regs.h"
53 #include "arm_cconv.h"
55 #include "gen_arm_regalloc_if.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static const arch_register_t *sp_reg = &arm_registers[REG_SP];
62 static ir_mode *mode_gp;
63 static ir_mode *mode_fp;
64 static beabi_helper_env_t *abihelper;
65 static calling_convention_t *cconv = NULL;
66 static arm_isa_t *isa;
68 static pmap *node_to_stack;
70 static bool mode_needs_gp_reg(ir_mode *mode)
72 return mode_is_int(mode) || mode_is_reference(mode);
76 * create firm graph for a constant
78 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
85 /* We only have 8 bit immediates. So we possibly have to combine several
86 * operations to construct the desired value.
88 * we can either create the value by adding bits to 0 or by removing bits
89 * from an register with all bits set. Try which alternative needs fewer
91 arm_gen_vals_from_word(value, &v);
92 arm_gen_vals_from_word(~value, &vn);
96 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
97 be_dep_on_frame(result);
99 for (cnt = 1; cnt < vn.ops; ++cnt) {
100 result = new_bd_arm_Bic_imm(dbgi, block, result,
101 vn.values[cnt], vn.rors[cnt]);
105 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
106 be_dep_on_frame(result);
108 for (cnt = 1; cnt < v.ops; ++cnt) {
109 result = new_bd_arm_Or_imm(dbgi, block, result,
110 v.values[cnt], v.rors[cnt]);
117 * Create a DAG constructing a given Const.
119 * @param irn a Firm const
121 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
123 ir_tarval *tv = get_Const_tarval(irn);
124 ir_mode *mode = get_tarval_mode(tv);
127 if (mode_is_reference(mode)) {
128 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
129 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
130 tv = tarval_convert_to(tv, mode_Iu);
132 value = get_tarval_long(tv);
133 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
137 * Create an And that will zero out upper bits.
139 * @param dbgi debug info
140 * @param block the basic block
141 * @param op the original node
142 * param src_bits number of lower bits that will remain
144 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
148 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
149 } else if (src_bits == 16) {
150 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
151 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
154 panic("zero extension only supported for 8 and 16 bits");
159 * Generate code for a sign extension.
161 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
164 int shift_width = 32 - src_bits;
165 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
166 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
170 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
173 int bits = get_mode_size_bits(orig_mode);
177 if (mode_is_signed(orig_mode)) {
178 return gen_sign_extension(dbgi, block, op, bits);
180 return gen_zero_extension(dbgi, block, op, bits);
185 * returns true if it is assured, that the upper bits of a node are "clean"
186 * which means for a 16 or 8 bit value, that the upper bits in the register
187 * are 0 for unsigned and a copy of the last significant bit for signed
190 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
192 (void) transformed_node;
199 * Transforms a Conv node.
201 * @return The created ia32 Conv node
203 static ir_node *gen_Conv(ir_node *node)
205 ir_node *block = be_transform_node(get_nodes_block(node));
206 ir_node *op = get_Conv_op(node);
207 ir_node *new_op = be_transform_node(op);
208 ir_mode *src_mode = get_irn_mode(op);
209 ir_mode *dst_mode = get_irn_mode(node);
210 dbg_info *dbg = get_irn_dbg_info(node);
212 if (src_mode == dst_mode)
215 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
217 if (mode_is_float(src_mode)) {
218 if (mode_is_float(dst_mode)) {
219 /* from float to float */
220 return new_bd_arm_Mvf(dbg, block, new_op, dst_mode);
222 /* from float to int */
226 /* from int to float */
227 if (!mode_is_signed(src_mode)) {
230 return new_bd_arm_FltX(dbg, block, new_op, dst_mode);
233 } else if (USE_VFP(isa)) {
234 panic("VFP not supported yet");
236 panic("Softfloat not supported yet");
238 } else { /* complete in gp registers */
239 int src_bits = get_mode_size_bits(src_mode);
240 int dst_bits = get_mode_size_bits(dst_mode);
244 if (src_bits == dst_bits) {
245 /* kill unnecessary conv */
249 if (src_bits < dst_bits) {
257 if (upper_bits_clean(new_op, min_mode)) {
261 if (mode_is_signed(min_mode)) {
262 return gen_sign_extension(dbg, block, new_op, min_bits);
264 return gen_zero_extension(dbg, block, new_op, min_bits);
274 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
276 unsigned val, low_pos, high_pos;
281 val = get_tarval_long(get_Const_tarval(node));
293 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
295 So we determine the smallest even position with a bit set
296 and the highest even position with no bit set anymore.
297 If the difference between these 2 is <= 8, then we can encode the value
300 low_pos = ntz(val) & ~1u;
301 high_pos = (32-nlz(val)+1) & ~1u;
303 if (high_pos - low_pos <= 8) {
304 res->imm_8 = val >> low_pos;
305 res->rot = 32 - low_pos;
310 res->rot = 34 - high_pos;
311 val = val >> (32-res->rot) | val << (res->rot);
321 static bool is_downconv(const ir_node *node)
329 /* we only want to skip the conv when we're the only user
330 * (not optimal but for now...)
332 if (get_irn_n_edges(node) > 1)
335 src_mode = get_irn_mode(get_Conv_op(node));
336 dest_mode = get_irn_mode(node);
338 mode_needs_gp_reg(src_mode) &&
339 mode_needs_gp_reg(dest_mode) &&
340 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
343 static ir_node *arm_skip_downconv(ir_node *node)
345 while (is_downconv(node))
346 node = get_Conv_op(node);
352 MATCH_COMMUTATIVE = 1 << 0, /**< commutative node */
353 MATCH_REVERSE = 1 << 1, /**< support reverse opcode */
354 MATCH_SIZE_NEUTRAL = 1 << 2,
355 MATCH_SKIP_NOT = 1 << 3, /**< skip Not on ONE input */
357 ENUM_BITSET(match_flags_t)
360 * possible binop constructors.
362 typedef struct arm_binop_factory_t {
363 /** normal reg op reg operation. */
364 ir_node *(*new_binop_reg)(dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
365 /** normal reg op imm operation. */
366 ir_node *(*new_binop_imm)(dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
367 /** barrel shifter reg op (reg shift reg operation. */
368 ir_node *(*new_binop_reg_shift_reg)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *shift, arm_shift_modifier_t shift_modifier);
369 /** barrel shifter reg op (reg shift imm operation. */
370 ir_node *(*new_binop_reg_shift_imm)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, arm_shift_modifier_t shift_modifier, unsigned shift_immediate);
371 } arm_binop_factory_t;
373 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
374 const arm_binop_factory_t *factory)
376 ir_node *block = be_transform_node(get_nodes_block(node));
377 ir_node *op1 = get_binop_left(node);
379 ir_node *op2 = get_binop_right(node);
381 dbg_info *dbgi = get_irn_dbg_info(node);
384 if (flags & MATCH_SKIP_NOT) {
386 op1 = get_Not_op(op1);
387 else if (is_Not(op2))
388 op2 = get_Not_op(op2);
390 panic("cannot execute MATCH_SKIP_NOT");
392 if (flags & MATCH_SIZE_NEUTRAL) {
393 op1 = arm_skip_downconv(op1);
394 op2 = arm_skip_downconv(op2);
396 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
399 if (try_encode_as_immediate(op2, &imm)) {
400 ir_node *new_op1 = be_transform_node(op1);
401 return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
403 new_op2 = be_transform_node(op2);
404 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && try_encode_as_immediate(op1, &imm)) {
405 if (flags & MATCH_REVERSE)
406 return factory[1].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
408 return factory[0].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
410 new_op1 = be_transform_node(op1);
412 /* check if we can fold in a Mov */
413 if (is_arm_Mov(new_op2)) {
414 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op2);
416 switch (attr->shift_modifier) {
418 case ARM_SHF_ASR_IMM:
419 case ARM_SHF_LSL_IMM:
420 case ARM_SHF_LSR_IMM:
421 case ARM_SHF_ROR_IMM:
422 if (factory->new_binop_reg_shift_imm) {
423 ir_node *mov_op = get_irn_n(new_op2, 0);
424 return factory->new_binop_reg_shift_imm(dbgi, block, new_op1, mov_op,
425 attr->shift_modifier, attr->shift_immediate);
429 case ARM_SHF_ASR_REG:
430 case ARM_SHF_LSL_REG:
431 case ARM_SHF_LSR_REG:
432 case ARM_SHF_ROR_REG:
433 if (factory->new_binop_reg_shift_reg) {
434 ir_node *mov_op = get_irn_n(new_op2, 0);
435 ir_node *mov_sft = get_irn_n(new_op2, 1);
436 return factory->new_binop_reg_shift_reg(dbgi, block, new_op1, mov_op, mov_sft,
437 attr->shift_modifier);
443 case ARM_SHF_INVALID:
444 panic("invalid shift");
447 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && is_arm_Mov(new_op1)) {
448 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op1);
449 int idx = flags & MATCH_REVERSE ? 1 : 0;
451 switch (attr->shift_modifier) {
452 ir_node *mov_op, *mov_sft;
455 case ARM_SHF_ASR_IMM:
456 case ARM_SHF_LSL_IMM:
457 case ARM_SHF_LSR_IMM:
458 case ARM_SHF_ROR_IMM:
459 if (factory[idx].new_binop_reg_shift_imm) {
460 mov_op = get_irn_n(new_op1, 0);
461 return factory[idx].new_binop_reg_shift_imm(dbgi, block, new_op2, mov_op,
462 attr->shift_modifier, attr->shift_immediate);
466 case ARM_SHF_ASR_REG:
467 case ARM_SHF_LSL_REG:
468 case ARM_SHF_LSR_REG:
469 case ARM_SHF_ROR_REG:
470 if (factory[idx].new_binop_reg_shift_reg) {
471 mov_op = get_irn_n(new_op1, 0);
472 mov_sft = get_irn_n(new_op1, 1);
473 return factory[idx].new_binop_reg_shift_reg(dbgi, block, new_op2, mov_op, mov_sft,
474 attr->shift_modifier);
481 case ARM_SHF_INVALID:
482 panic("invalid shift");
485 return factory->new_binop_reg(dbgi, block, new_op1, new_op2);
489 * Creates an ARM Add.
491 * @return the created arm Add node
493 static ir_node *gen_Add(ir_node *node)
495 static const arm_binop_factory_t add_factory = {
498 new_bd_arm_Add_reg_shift_reg,
499 new_bd_arm_Add_reg_shift_imm
502 ir_mode *mode = get_irn_mode(node);
504 if (mode_is_float(mode)) {
505 ir_node *block = be_transform_node(get_nodes_block(node));
506 ir_node *op1 = get_Add_left(node);
507 ir_node *op2 = get_Add_right(node);
508 dbg_info *dbgi = get_irn_dbg_info(node);
509 ir_node *new_op1 = be_transform_node(op1);
510 ir_node *new_op2 = be_transform_node(op2);
512 return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
513 } else if (USE_VFP(isa)) {
514 assert(mode != mode_E && "IEEE Extended FP not supported");
515 panic("VFP not supported yet");
517 panic("Softfloat not supported yet");
522 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
524 new_op2 = get_irn_n(new_op1, 1);
525 new_op1 = get_irn_n(new_op1, 0);
527 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
529 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
531 new_op1 = get_irn_n(new_op2, 0);
532 new_op2 = get_irn_n(new_op2, 1);
534 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
538 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &add_factory);
543 * Creates an ARM Mul.
545 * @return the created arm Mul node
547 static ir_node *gen_Mul(ir_node *node)
549 ir_node *block = be_transform_node(get_nodes_block(node));
550 ir_node *op1 = get_Mul_left(node);
551 ir_node *new_op1 = be_transform_node(op1);
552 ir_node *op2 = get_Mul_right(node);
553 ir_node *new_op2 = be_transform_node(op2);
554 ir_mode *mode = get_irn_mode(node);
555 dbg_info *dbg = get_irn_dbg_info(node);
557 if (mode_is_float(mode)) {
559 return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
560 } else if (USE_VFP(isa)) {
561 assert(mode != mode_E && "IEEE Extended FP not supported");
562 panic("VFP not supported yet");
564 panic("Softfloat not supported yet");
567 assert(mode_is_data(mode));
568 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
571 static ir_node *gen_Div(ir_node *node)
573 ir_node *block = be_transform_node(get_nodes_block(node));
574 ir_node *op1 = get_Div_left(node);
575 ir_node *new_op1 = be_transform_node(op1);
576 ir_node *op2 = get_Div_right(node);
577 ir_node *new_op2 = be_transform_node(op2);
578 ir_mode *mode = get_Div_resmode(node);
579 dbg_info *dbg = get_irn_dbg_info(node);
581 assert(mode != mode_E && "IEEE Extended FP not supported");
582 /* integer division should be replaced by builtin call */
583 assert(mode_is_float(mode));
586 return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
587 } else if (USE_VFP(isa)) {
588 assert(mode != mode_E && "IEEE Extended FP not supported");
589 panic("VFP not supported yet");
591 panic("Softfloat not supported yet");
595 static ir_node *gen_And(ir_node *node)
597 static const arm_binop_factory_t and_factory = {
600 new_bd_arm_And_reg_shift_reg,
601 new_bd_arm_And_reg_shift_imm
603 static const arm_binop_factory_t bic_factory = {
606 new_bd_arm_Bic_reg_shift_reg,
607 new_bd_arm_Bic_reg_shift_imm
610 /* check for and not */
611 ir_node *left = get_And_left(node);
612 ir_node *right = get_And_right(node);
614 if (is_Not(left) || is_Not(right)) {
615 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL | MATCH_SKIP_NOT,
619 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &and_factory);
622 static ir_node *gen_Or(ir_node *node)
624 static const arm_binop_factory_t or_factory = {
627 new_bd_arm_Or_reg_shift_reg,
628 new_bd_arm_Or_reg_shift_imm
631 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &or_factory);
634 static ir_node *gen_Eor(ir_node *node)
636 static const arm_binop_factory_t eor_factory = {
639 new_bd_arm_Eor_reg_shift_reg,
640 new_bd_arm_Eor_reg_shift_imm
643 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &eor_factory);
646 static ir_node *gen_Sub(ir_node *node)
648 static const arm_binop_factory_t sub_rsb_factory[2] = {
652 new_bd_arm_Sub_reg_shift_reg,
653 new_bd_arm_Sub_reg_shift_imm
658 new_bd_arm_Rsb_reg_shift_reg,
659 new_bd_arm_Rsb_reg_shift_imm
663 ir_node *block = be_transform_node(get_nodes_block(node));
664 ir_node *op1 = get_Sub_left(node);
665 ir_node *new_op1 = be_transform_node(op1);
666 ir_node *op2 = get_Sub_right(node);
667 ir_node *new_op2 = be_transform_node(op2);
668 ir_mode *mode = get_irn_mode(node);
669 dbg_info *dbgi = get_irn_dbg_info(node);
671 if (mode_is_float(mode)) {
673 return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
674 } else if (USE_VFP(isa)) {
675 assert(mode != mode_E && "IEEE Extended FP not supported");
676 panic("VFP not supported yet");
678 panic("Softfloat not supported yet");
681 return gen_int_binop(node, MATCH_SIZE_NEUTRAL | MATCH_REVERSE, sub_rsb_factory);
686 * Checks if a given value can be used as an immediate for the given
689 static bool can_use_shift_constant(unsigned int val,
690 arm_shift_modifier_t modifier)
694 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
700 * generate an ARM shift instruction.
702 * @param node the node
703 * @param flags matching flags
704 * @param shift_modifier initial encoding of the desired shift operation
706 static ir_node *make_shift(ir_node *node, match_flags_t flags,
707 arm_shift_modifier_t shift_modifier)
709 ir_node *block = be_transform_node(get_nodes_block(node));
710 ir_node *op1 = get_binop_left(node);
711 ir_node *op2 = get_binop_right(node);
712 dbg_info *dbgi = get_irn_dbg_info(node);
716 if (flags & MATCH_SIZE_NEUTRAL) {
717 op1 = arm_skip_downconv(op1);
718 op2 = arm_skip_downconv(op2);
721 new_op1 = be_transform_node(op1);
723 ir_tarval *tv = get_Const_tarval(op2);
724 unsigned int val = get_tarval_long(tv);
725 assert(tarval_is_long(tv));
726 if (can_use_shift_constant(val, shift_modifier)) {
727 switch (shift_modifier) {
728 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
729 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
730 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
731 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
732 default: panic("unexpected shift modifier");
734 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
735 shift_modifier, val);
739 new_op2 = be_transform_node(op2);
740 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
744 static ir_node *gen_Shl(ir_node *node)
746 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
749 static ir_node *gen_Shr(ir_node *node)
751 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
754 static ir_node *gen_Shrs(ir_node *node)
756 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
759 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
761 ir_node *block = be_transform_node(get_nodes_block(node));
762 ir_node *new_op1 = be_transform_node(op1);
763 dbg_info *dbgi = get_irn_dbg_info(node);
764 ir_node *new_op2 = be_transform_node(op2);
766 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
770 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
772 ir_node *block = be_transform_node(get_nodes_block(node));
773 ir_node *new_op1 = be_transform_node(op1);
774 dbg_info *dbgi = get_irn_dbg_info(node);
775 ir_node *new_op2 = be_transform_node(op2);
777 /* Note: there is no Rol on arm, we have to use Ror */
778 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
779 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
783 static ir_node *gen_Rotl(ir_node *node)
785 ir_node *rotate = NULL;
786 ir_node *op1 = get_Rotl_left(node);
787 ir_node *op2 = get_Rotl_right(node);
789 /* Firm has only RotL, so we are looking for a right (op2)
790 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
791 that means we can create a RotR. */
794 ir_node *right = get_Add_right(op2);
795 if (is_Const(right)) {
796 ir_tarval *tv = get_Const_tarval(right);
797 ir_mode *mode = get_irn_mode(node);
798 long bits = get_mode_size_bits(mode);
799 ir_node *left = get_Add_left(op2);
801 if (is_Minus(left) &&
802 tarval_is_long(tv) &&
803 get_tarval_long(tv) == bits &&
805 rotate = gen_Ror(node, op1, get_Minus_op(left));
807 } else if (is_Sub(op2)) {
808 ir_node *left = get_Sub_left(op2);
809 if (is_Const(left)) {
810 ir_tarval *tv = get_Const_tarval(left);
811 ir_mode *mode = get_irn_mode(node);
812 long bits = get_mode_size_bits(mode);
813 ir_node *right = get_Sub_right(op2);
815 if (tarval_is_long(tv) &&
816 get_tarval_long(tv) == bits &&
818 rotate = gen_Ror(node, op1, right);
820 } else if (is_Const(op2)) {
821 ir_tarval *tv = get_Const_tarval(op2);
822 ir_mode *mode = get_irn_mode(node);
823 long bits = get_mode_size_bits(mode);
825 if (tarval_is_long(tv) && bits == 32) {
826 ir_node *block = be_transform_node(get_nodes_block(node));
827 ir_node *new_op1 = be_transform_node(op1);
828 dbg_info *dbgi = get_irn_dbg_info(node);
830 bits = (bits - get_tarval_long(tv)) & 31;
831 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
835 if (rotate == NULL) {
836 rotate = gen_Rol(node, op1, op2);
842 static ir_node *gen_Not(ir_node *node)
844 ir_node *block = be_transform_node(get_nodes_block(node));
845 ir_node *op = get_Not_op(node);
846 ir_node *new_op = be_transform_node(op);
847 dbg_info *dbgi = get_irn_dbg_info(node);
849 /* check if we can fold in a Mov */
850 if (is_arm_Mov(new_op)) {
851 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op);
853 switch (attr->shift_modifier) {
854 ir_node *mov_op, *mov_sft;
857 case ARM_SHF_ASR_IMM:
858 case ARM_SHF_LSL_IMM:
859 case ARM_SHF_LSR_IMM:
860 case ARM_SHF_ROR_IMM:
861 mov_op = get_irn_n(new_op, 0);
862 return new_bd_arm_Mvn_reg_shift_imm(dbgi, block, mov_op,
863 attr->shift_modifier, attr->shift_immediate);
865 case ARM_SHF_ASR_REG:
866 case ARM_SHF_LSL_REG:
867 case ARM_SHF_LSR_REG:
868 case ARM_SHF_ROR_REG:
869 mov_op = get_irn_n(new_op, 0);
870 mov_sft = get_irn_n(new_op, 1);
871 return new_bd_arm_Mvn_reg_shift_reg(dbgi, block, mov_op, mov_sft,
872 attr->shift_modifier);
877 case ARM_SHF_INVALID:
878 panic("invalid shift");
882 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
885 static ir_node *gen_Minus(ir_node *node)
887 ir_node *block = be_transform_node(get_nodes_block(node));
888 ir_node *op = get_Minus_op(node);
889 ir_node *new_op = be_transform_node(op);
890 dbg_info *dbgi = get_irn_dbg_info(node);
891 ir_mode *mode = get_irn_mode(node);
893 if (mode_is_float(mode)) {
895 return new_bd_arm_Mvf(dbgi, block, op, mode);
896 } else if (USE_VFP(isa)) {
897 assert(mode != mode_E && "IEEE Extended FP not supported");
898 panic("VFP not supported yet");
900 panic("Softfloat not supported yet");
903 assert(mode_is_data(mode));
904 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
907 static ir_node *gen_Load(ir_node *node)
909 ir_node *block = be_transform_node(get_nodes_block(node));
910 ir_node *ptr = get_Load_ptr(node);
911 ir_node *new_ptr = be_transform_node(ptr);
912 ir_node *mem = get_Load_mem(node);
913 ir_node *new_mem = be_transform_node(mem);
914 ir_mode *mode = get_Load_mode(node);
915 dbg_info *dbgi = get_irn_dbg_info(node);
916 ir_node *new_load = NULL;
918 if (mode_is_float(mode)) {
920 new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
922 } else if (USE_VFP(isa)) {
923 assert(mode != mode_E && "IEEE Extended FP not supported");
924 panic("VFP not supported yet");
926 panic("Softfloat not supported yet");
929 assert(mode_is_data(mode) && "unsupported mode for Load");
931 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
933 set_irn_pinned(new_load, get_irn_pinned(node));
935 /* check for special case: the loaded value might not be used */
936 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
937 /* add a result proj and a Keep to produce a pseudo use */
938 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
939 be_new_Keep(block, 1, &proj);
945 static ir_node *gen_Store(ir_node *node)
947 ir_node *block = be_transform_node(get_nodes_block(node));
948 ir_node *ptr = get_Store_ptr(node);
949 ir_node *new_ptr = be_transform_node(ptr);
950 ir_node *mem = get_Store_mem(node);
951 ir_node *new_mem = be_transform_node(mem);
952 ir_node *val = get_Store_value(node);
953 ir_node *new_val = be_transform_node(val);
954 ir_mode *mode = get_irn_mode(val);
955 dbg_info *dbgi = get_irn_dbg_info(node);
956 ir_node *new_store = NULL;
958 if (mode_is_float(mode)) {
960 new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
961 new_mem, mode, NULL, 0, 0, false);
962 } else if (USE_VFP(isa)) {
963 assert(mode != mode_E && "IEEE Extended FP not supported");
964 panic("VFP not supported yet");
966 panic("Softfloat not supported yet");
969 assert(mode_is_data(mode) && "unsupported mode for Store");
970 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
973 set_irn_pinned(new_store, get_irn_pinned(node));
977 static ir_node *gen_Jmp(ir_node *node)
979 ir_node *block = get_nodes_block(node);
980 ir_node *new_block = be_transform_node(block);
981 dbg_info *dbgi = get_irn_dbg_info(node);
983 return new_bd_arm_Jmp(dbgi, new_block);
986 static ir_node *gen_SwitchJmp(ir_node *node)
988 ir_node *block = be_transform_node(get_nodes_block(node));
989 ir_node *selector = get_Cond_selector(node);
990 dbg_info *dbgi = get_irn_dbg_info(node);
991 ir_node *new_op = be_transform_node(selector);
992 ir_node *const_graph;
996 const ir_edge_t *edge;
1003 foreach_out_edge(node, edge) {
1004 proj = get_edge_src_irn(edge);
1005 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1007 pn = get_Proj_proj(proj);
1009 min = pn<min ? pn : min;
1010 max = pn>max ? pn : max;
1013 n_projs = max - translation + 1;
1015 foreach_out_edge(node, edge) {
1016 proj = get_edge_src_irn(edge);
1017 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1019 pn = get_Proj_proj(proj) - translation;
1020 set_Proj_proj(proj, pn);
1023 const_graph = create_const_graph_value(dbgi, block, translation);
1024 sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
1025 return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
1028 static ir_node *gen_Cmp(ir_node *node)
1030 ir_node *block = be_transform_node(get_nodes_block(node));
1031 ir_node *op1 = get_Cmp_left(node);
1032 ir_node *op2 = get_Cmp_right(node);
1033 ir_mode *cmp_mode = get_irn_mode(op1);
1034 dbg_info *dbgi = get_irn_dbg_info(node);
1039 if (mode_is_float(cmp_mode)) {
1040 /* TODO: this is broken... */
1041 new_op1 = be_transform_node(op1);
1042 new_op2 = be_transform_node(op2);
1044 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
1047 assert(get_irn_mode(op2) == cmp_mode);
1048 is_unsigned = !mode_is_signed(cmp_mode);
1050 /* integer compare, TODO: use shifter_op in all its combinations */
1051 new_op1 = be_transform_node(op1);
1052 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
1053 new_op2 = be_transform_node(op2);
1054 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
1055 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
1059 static ir_node *gen_Cond(ir_node *node)
1061 ir_node *selector = get_Cond_selector(node);
1062 ir_mode *mode = get_irn_mode(selector);
1063 ir_relation relation;
1068 if (mode != mode_b) {
1069 return gen_SwitchJmp(node);
1071 assert(is_Cmp(selector));
1073 block = be_transform_node(get_nodes_block(node));
1074 dbgi = get_irn_dbg_info(node);
1075 flag_node = be_transform_node(selector);
1076 relation = get_Cmp_relation(selector);
1078 return new_bd_arm_B(dbgi, block, flag_node, relation);
1084 FPA_IMM_EXTENDED = 2,
1085 FPA_IMM_MAX = FPA_IMM_EXTENDED
1088 static ir_tarval *fpa_imm[FPA_IMM_MAX + 1][fpa_max];
1092 * Check, if a floating point tarval is an fpa immediate, i.e.
1093 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
1095 static int is_fpa_immediate(tarval *tv)
1097 ir_mode *mode = get_tarval_mode(tv);
1100 switch (get_mode_size_bits(mode)) {
1108 i = FPA_IMM_EXTENDED;
1111 if (tarval_is_negative(tv)) {
1112 tv = tarval_neg(tv);
1116 for (j = 0; j < fpa_max; ++j) {
1117 if (tv == fpa_imm[i][j])
1124 static ir_node *gen_Const(ir_node *node)
1126 ir_node *block = be_transform_node(get_nodes_block(node));
1127 ir_mode *mode = get_irn_mode(node);
1128 dbg_info *dbg = get_irn_dbg_info(node);
1130 if (mode_is_float(mode)) {
1132 ir_tarval *tv = get_Const_tarval(node);
1133 node = new_bd_arm_fConst(dbg, block, tv);
1134 be_dep_on_frame(node);
1136 } else if (USE_VFP(isa)) {
1137 assert(mode != mode_E && "IEEE Extended FP not supported");
1138 panic("VFP not supported yet");
1140 panic("Softfloat not supported yet");
1143 return create_const_graph(node, block);
1146 static ir_node *gen_SymConst(ir_node *node)
1148 ir_node *block = be_transform_node(get_nodes_block(node));
1149 ir_entity *entity = get_SymConst_entity(node);
1150 dbg_info *dbgi = get_irn_dbg_info(node);
1153 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
1154 be_dep_on_frame(new_node);
1158 static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0,
1161 /* the good way to do this would be to use the stm (store multiple)
1162 * instructions, since our input is nearly always 2 consecutive 32bit
1164 ir_graph *irg = current_ir_graph;
1165 ir_node *stack = get_irg_frame(irg);
1166 ir_node *nomem = new_r_NoMem(irg);
1167 ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp,
1169 ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp,
1171 ir_node *in[2] = { str0, str1 };
1172 ir_node *sync = new_r_Sync(block, 2, in);
1174 set_irn_pinned(str0, op_pin_state_floats);
1175 set_irn_pinned(str1, op_pin_state_floats);
1177 ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true);
1178 set_irn_pinned(ldf, op_pin_state_floats);
1180 return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1183 static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node)
1185 ir_graph *irg = current_ir_graph;
1186 ir_node *stack = get_irg_frame(irg);
1187 ir_node *nomem = new_r_NoMem(irg);
1188 ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp,
1191 set_irn_pinned(str, op_pin_state_floats);
1193 ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true);
1194 set_irn_pinned(ldf, op_pin_state_floats);
1196 return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1199 static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node)
1201 ir_graph *irg = current_ir_graph;
1202 ir_node *stack = get_irg_frame(irg);
1203 ir_node *nomem = new_r_NoMem(irg);
1204 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F,
1207 set_irn_pinned(stf, op_pin_state_floats);
1209 ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1210 set_irn_pinned(ldr, op_pin_state_floats);
1212 return new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1215 static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node,
1216 ir_node **out_value0, ir_node **out_value1)
1218 ir_graph *irg = current_ir_graph;
1219 ir_node *stack = get_irg_frame(irg);
1220 ir_node *nomem = new_r_NoMem(irg);
1221 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D,
1223 ir_node *ldr0, *ldr1;
1224 set_irn_pinned(stf, op_pin_state_floats);
1226 ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1227 set_irn_pinned(ldr0, op_pin_state_floats);
1228 ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true);
1229 set_irn_pinned(ldr1, op_pin_state_floats);
1231 *out_value0 = new_r_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
1232 *out_value1 = new_r_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
1235 static ir_node *gen_CopyB(ir_node *node)
1237 ir_node *block = be_transform_node(get_nodes_block(node));
1238 ir_node *src = get_CopyB_src(node);
1239 ir_node *new_src = be_transform_node(src);
1240 ir_node *dst = get_CopyB_dst(node);
1241 ir_node *new_dst = be_transform_node(dst);
1242 ir_node *mem = get_CopyB_mem(node);
1243 ir_node *new_mem = be_transform_node(mem);
1244 dbg_info *dbg = get_irn_dbg_info(node);
1245 int size = get_type_size_bytes(get_CopyB_type(node));
1249 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
1250 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
1252 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1253 new_bd_arm_EmptyReg(dbg, block),
1254 new_bd_arm_EmptyReg(dbg, block),
1255 new_bd_arm_EmptyReg(dbg, block),
1260 * Transform builtin clz.
1262 static ir_node *gen_clz(ir_node *node)
1264 ir_node *block = be_transform_node(get_nodes_block(node));
1265 dbg_info *dbg = get_irn_dbg_info(node);
1266 ir_node *op = get_irn_n(node, 1);
1267 ir_node *new_op = be_transform_node(op);
1269 /* TODO armv5 instruction, otherwise create a call */
1270 return new_bd_arm_Clz(dbg, block, new_op);
1274 * Transform Builtin node.
1276 static ir_node *gen_Builtin(ir_node *node)
1278 ir_builtin_kind kind = get_Builtin_kind(node);
1282 case ir_bk_debugbreak:
1283 case ir_bk_return_address:
1284 case ir_bk_frame_address:
1285 case ir_bk_prefetch:
1289 return gen_clz(node);
1292 case ir_bk_popcount:
1296 case ir_bk_inner_trampoline:
1299 panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
1303 * Transform Proj(Builtin) node.
1305 static ir_node *gen_Proj_Builtin(ir_node *proj)
1307 ir_node *node = get_Proj_pred(proj);
1308 ir_node *new_node = be_transform_node(node);
1309 ir_builtin_kind kind = get_Builtin_kind(node);
1312 case ir_bk_return_address:
1313 case ir_bk_frame_address:
1318 case ir_bk_popcount:
1320 assert(get_Proj_proj(proj) == pn_Builtin_1_result);
1323 case ir_bk_debugbreak:
1324 case ir_bk_prefetch:
1326 assert(get_Proj_proj(proj) == pn_Builtin_M);
1329 case ir_bk_inner_trampoline:
1332 panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
1335 static ir_node *gen_Proj_Load(ir_node *node)
1337 ir_node *load = get_Proj_pred(node);
1338 ir_node *new_load = be_transform_node(load);
1339 dbg_info *dbgi = get_irn_dbg_info(node);
1340 long proj = get_Proj_proj(node);
1342 /* renumber the proj */
1343 switch (get_arm_irn_opcode(new_load)) {
1345 /* handle all gp loads equal: they have the same proj numbers. */
1346 if (proj == pn_Load_res) {
1347 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1348 } else if (proj == pn_Load_M) {
1349 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1353 if (proj == pn_Load_res) {
1354 ir_mode *mode = get_Load_mode(load);
1355 return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res);
1356 } else if (proj == pn_Load_M) {
1357 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M);
1363 panic("Unsupported Proj from Load");
1366 static ir_node *gen_Proj_CopyB(ir_node *node)
1368 ir_node *pred = get_Proj_pred(node);
1369 ir_node *new_pred = be_transform_node(pred);
1370 dbg_info *dbgi = get_irn_dbg_info(node);
1371 long proj = get_Proj_proj(node);
1375 if (is_arm_CopyB(new_pred)) {
1376 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1382 panic("Unsupported Proj from CopyB");
1385 static ir_node *gen_Proj_Div(ir_node *node)
1387 ir_node *pred = get_Proj_pred(node);
1388 ir_node *new_pred = be_transform_node(pred);
1389 dbg_info *dbgi = get_irn_dbg_info(node);
1390 ir_mode *mode = get_irn_mode(node);
1391 long proj = get_Proj_proj(node);
1395 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
1397 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
1401 panic("Unsupported Proj from Div");
1405 * Transform the Projs from a Cmp.
1407 static ir_node *gen_Proj_Cmp(ir_node *node)
1410 /* we should only be here in case of a Mux node */
1414 static ir_node *gen_Proj_Start(ir_node *node)
1416 ir_node *block = get_nodes_block(node);
1417 ir_node *new_block = be_transform_node(block);
1418 ir_node *barrier = be_transform_node(get_Proj_pred(node));
1419 long proj = get_Proj_proj(node);
1421 switch ((pn_Start) proj) {
1422 case pn_Start_X_initial_exec:
1423 /* we exchange the ProjX with a jump */
1424 return new_bd_arm_Jmp(NULL, new_block);
1427 return new_r_Proj(barrier, mode_M, 0);
1429 case pn_Start_T_args:
1432 case pn_Start_P_frame_base:
1433 return be_prolog_get_reg_value(abihelper, sp_reg);
1435 case pn_Start_P_tls:
1436 return new_r_Bad(get_irn_irg(node));
1441 panic("unexpected start proj: %ld\n", proj);
1444 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1446 long pn = get_Proj_proj(node);
1447 ir_node *block = get_nodes_block(node);
1448 ir_node *new_block = be_transform_node(block);
1449 ir_entity *entity = get_irg_entity(current_ir_graph);
1450 ir_type *method_type = get_entity_type(entity);
1451 ir_type *param_type = get_method_param_type(method_type, pn);
1452 const reg_or_stackslot_t *param;
1454 /* Proj->Proj->Start must be a method argument */
1455 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1457 param = &cconv->parameters[pn];
1459 if (param->reg0 != NULL) {
1460 /* argument transmitted in register */
1461 ir_mode *mode = get_type_mode(param_type);
1462 ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0);
1464 if (mode_is_float(mode)) {
1465 ir_node *value1 = NULL;
1467 if (param->reg1 != NULL) {
1468 value1 = be_prolog_get_reg_value(abihelper, param->reg1);
1469 } else if (param->entity != NULL) {
1470 ir_graph *irg = get_irn_irg(node);
1471 ir_node *fp = get_irg_frame(irg);
1472 ir_node *mem = be_prolog_get_memory(abihelper);
1473 ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem,
1474 mode_gp, param->entity,
1476 value1 = new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1479 /* convert integer value to float */
1480 if (value1 == NULL) {
1481 value = int_to_float(NULL, new_block, value);
1483 value = ints_to_double(NULL, new_block, value, value1);
1488 /* argument transmitted on stack */
1489 ir_graph *irg = get_irn_irg(node);
1490 ir_node *fp = get_irg_frame(irg);
1491 ir_node *mem = be_prolog_get_memory(abihelper);
1492 ir_mode *mode = get_type_mode(param->type);
1496 if (mode_is_float(mode)) {
1497 load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode,
1498 param->entity, 0, 0, true);
1499 value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res);
1501 load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1502 param->entity, 0, 0, true);
1503 value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1505 set_irn_pinned(load, op_pin_state_floats);
1512 * Finds number of output value of a mode_T node which is constrained to
1513 * a single specific register.
1515 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1517 int n_outs = arch_irn_get_n_outs(node);
1520 for (o = 0; o < n_outs; ++o) {
1521 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1522 if (req == reg->single_req)
1528 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1530 long pn = get_Proj_proj(node);
1531 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1532 ir_node *new_call = be_transform_node(call);
1533 ir_type *function_type = get_Call_type(call);
1534 calling_convention_t *cconv
1535 = arm_decide_calling_convention(NULL, function_type);
1536 const reg_or_stackslot_t *res = &cconv->results[pn];
1540 /* TODO 64bit modes */
1541 assert(res->reg0 != NULL && res->reg1 == NULL);
1542 regn = find_out_for_reg(new_call, res->reg0);
1544 panic("Internal error in calling convention for return %+F", node);
1546 mode = res->reg0->reg_class->mode;
1548 arm_free_calling_convention(cconv);
1550 return new_r_Proj(new_call, mode, regn);
1553 static ir_node *gen_Proj_Call(ir_node *node)
1555 long pn = get_Proj_proj(node);
1556 ir_node *call = get_Proj_pred(node);
1557 ir_node *new_call = be_transform_node(call);
1559 switch ((pn_Call) pn) {
1561 return new_r_Proj(new_call, mode_M, 0);
1562 case pn_Call_X_regular:
1563 case pn_Call_X_except:
1564 case pn_Call_T_result:
1565 case pn_Call_P_value_res_base:
1569 panic("Unexpected Call proj %ld\n", pn);
1573 * Transform a Proj node.
1575 static ir_node *gen_Proj(ir_node *node)
1577 ir_node *pred = get_Proj_pred(node);
1578 long proj = get_Proj_proj(node);
1580 switch (get_irn_opcode(pred)) {
1582 if (proj == pn_Store_M) {
1583 return be_transform_node(pred);
1585 panic("Unsupported Proj from Store");
1588 return gen_Proj_Load(node);
1590 return gen_Proj_Call(node);
1592 return gen_Proj_CopyB(node);
1594 return gen_Proj_Div(node);
1596 return gen_Proj_Cmp(node);
1598 return gen_Proj_Start(node);
1601 return be_duplicate_node(node);
1603 ir_node *pred_pred = get_Proj_pred(pred);
1604 if (is_Call(pred_pred)) {
1605 return gen_Proj_Proj_Call(node);
1606 } else if (is_Start(pred_pred)) {
1607 return gen_Proj_Proj_Start(node);
1612 return gen_Proj_Builtin(node);
1614 panic("code selection didn't expect Proj after %+F\n", pred);
1618 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1620 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
1621 create_const_node_func func,
1622 const arch_register_t* reg)
1624 ir_node *block, *res;
1629 block = get_irg_start_block(irg);
1630 res = func(NULL, block);
1631 arch_set_irn_register(res, reg);
1636 static ir_node *gen_Unknown(ir_node *node)
1638 ir_node *block = get_nodes_block(node);
1639 ir_node *new_block = be_transform_node(block);
1640 dbg_info *dbgi = get_irn_dbg_info(node);
1642 /* just produce a 0 */
1643 ir_mode *mode = get_irn_mode(node);
1644 if (mode_is_float(mode)) {
1645 ir_tarval *tv = get_mode_null(mode);
1646 ir_node *node = new_bd_arm_fConst(dbgi, new_block, tv);
1647 be_dep_on_frame(node);
1649 } else if (mode_needs_gp_reg(mode)) {
1650 return create_const_graph_value(dbgi, new_block, 0);
1653 panic("Unexpected Unknown mode");
1657 * Produces the type which sits between the stack args and the locals on the
1658 * stack. It will contain the return address and space to store the old base
1660 * @return The Firm type modeling the ABI between type.
1662 static ir_type *arm_get_between_type(void)
1664 static ir_type *between_type = NULL;
1666 if (between_type == NULL) {
1667 between_type = new_type_class(new_id_from_str("arm_between_type"));
1668 set_type_size_bytes(between_type, 0);
1671 return between_type;
1674 static void create_stacklayout(ir_graph *irg)
1676 ir_entity *entity = get_irg_entity(irg);
1677 ir_type *function_type = get_entity_type(entity);
1678 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1683 /* calling conventions must be decided by now */
1684 assert(cconv != NULL);
1686 /* construct argument type */
1687 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1688 n_params = get_method_n_params(function_type);
1689 for (p = 0; p < n_params; ++p) {
1690 reg_or_stackslot_t *param = &cconv->parameters[p];
1694 if (param->type == NULL)
1697 snprintf(buf, sizeof(buf), "param_%d", p);
1698 id = new_id_from_str(buf);
1699 param->entity = new_entity(arg_type, id, param->type);
1700 set_entity_offset(param->entity, param->offset);
1703 /* TODO: what about external functions? we don't know most of the stack
1704 * layout for them. And probably don't need all of this... */
1705 memset(layout, 0, sizeof(*layout));
1707 layout->frame_type = get_irg_frame_type(irg);
1708 layout->between_type = arm_get_between_type();
1709 layout->arg_type = arg_type;
1710 layout->param_map = NULL; /* TODO */
1711 layout->initial_offset = 0;
1712 layout->initial_bias = 0;
1713 layout->stack_dir = -1;
1714 layout->sp_relative = true;
1716 assert(N_FRAME_TYPES == 3);
1717 layout->order[0] = layout->frame_type;
1718 layout->order[1] = layout->between_type;
1719 layout->order[2] = layout->arg_type;
1723 * transform the start node to the prolog code + initial barrier
1725 static ir_node *gen_Start(ir_node *node)
1727 ir_graph *irg = get_irn_irg(node);
1728 ir_entity *entity = get_irg_entity(irg);
1729 ir_type *function_type = get_entity_type(entity);
1730 ir_node *block = get_nodes_block(node);
1731 ir_node *new_block = be_transform_node(block);
1732 dbg_info *dbgi = get_irn_dbg_info(node);
1739 /* stackpointer is important at function prolog */
1740 be_prolog_add_reg(abihelper, sp_reg,
1741 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1742 /* function parameters in registers */
1743 for (i = 0; i < get_method_n_params(function_type); ++i) {
1744 const reg_or_stackslot_t *param = &cconv->parameters[i];
1745 if (param->reg0 != NULL)
1746 be_prolog_add_reg(abihelper, param->reg0, arch_register_req_type_none);
1747 if (param->reg1 != NULL)
1748 be_prolog_add_reg(abihelper, param->reg1, arch_register_req_type_none);
1750 /* announce that we need the values of the callee save regs */
1751 for (i = 0; i < (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
1752 be_prolog_add_reg(abihelper, callee_saves[i], arch_register_req_type_none);
1755 start = be_prolog_create_start(abihelper, dbgi, new_block);
1756 sp = be_prolog_get_reg_value(abihelper, sp_reg);
1757 incsp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
1758 be_prolog_set_reg_value(abihelper, sp_reg, incsp);
1759 barrier = be_prolog_create_barrier(abihelper, new_block);
1764 static ir_node *get_stack_pointer_for(ir_node *node)
1766 /* get predecessor in stack_order list */
1767 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1768 ir_node *stack_pred_transformed;
1771 if (stack_pred == NULL) {
1772 /* first stack user in the current block. We can simply use the
1773 * initial sp_proj for it */
1774 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1778 stack_pred_transformed = be_transform_node(stack_pred);
1779 stack = (ir_node*)pmap_get(node_to_stack, stack_pred);
1780 if (stack == NULL) {
1781 return get_stack_pointer_for(stack_pred);
1788 * transform a Return node into epilogue code + return statement
1790 static ir_node *gen_Return(ir_node *node)
1792 ir_node *block = get_nodes_block(node);
1793 ir_node *new_block = be_transform_node(block);
1794 dbg_info *dbgi = get_irn_dbg_info(node);
1795 ir_node *mem = get_Return_mem(node);
1796 ir_node *new_mem = be_transform_node(mem);
1797 int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
1798 ir_node *sp_proj = get_stack_pointer_for(node);
1799 int n_res = get_Return_n_ress(node);
1804 be_epilog_begin(abihelper);
1805 be_epilog_set_memory(abihelper, new_mem);
1806 /* connect stack pointer with initial stack pointer. fix_stack phase
1807 will later serialize all stack pointer adjusting nodes */
1808 be_epilog_add_reg(abihelper, sp_reg,
1809 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1813 for (i = 0; i < n_res; ++i) {
1814 ir_node *res_value = get_Return_res(node, i);
1815 ir_node *new_res_value = be_transform_node(res_value);
1816 const reg_or_stackslot_t *slot = &cconv->results[i];
1817 const arch_register_t *reg = slot->reg0;
1818 assert(slot->reg1 == NULL);
1819 be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, new_res_value);
1822 /* connect callee saves with their values at the function begin */
1823 for (i = 0; i < n_callee_saves; ++i) {
1824 const arch_register_t *reg = callee_saves[i];
1825 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1826 be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, value);
1829 /* create the barrier before the epilog code */
1830 be_epilog_create_barrier(abihelper, new_block);
1832 /* epilog code: an incsp */
1833 sp_proj = be_epilog_get_reg_value(abihelper, sp_reg);
1834 incsp = be_new_IncSP(sp_reg, new_block, sp_proj,
1835 BE_STACK_FRAME_SIZE_SHRINK, 0);
1836 be_epilog_set_reg_value(abihelper, sp_reg, incsp);
1838 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1844 static ir_node *gen_Call(ir_node *node)
1846 ir_graph *irg = get_irn_irg(node);
1847 ir_node *callee = get_Call_ptr(node);
1848 ir_node *block = get_nodes_block(node);
1849 ir_node *new_block = be_transform_node(block);
1850 ir_node *mem = get_Call_mem(node);
1851 ir_node *new_mem = be_transform_node(mem);
1852 dbg_info *dbgi = get_irn_dbg_info(node);
1853 ir_type *type = get_Call_type(node);
1854 calling_convention_t *cconv = arm_decide_calling_convention(NULL, type);
1855 size_t n_params = get_Call_n_params(node);
1856 size_t n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
1857 /* max inputs: memory, callee, register arguments */
1858 int max_inputs = 2 + n_param_regs;
1859 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1860 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1861 struct obstack *obst = be_get_be_obst(irg);
1862 const arch_register_req_t **in_req
1863 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1867 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1868 ir_entity *entity = NULL;
1869 ir_node *incsp = NULL;
1876 assert(n_params == get_method_n_params(type));
1878 /* construct arguments */
1881 in_req[in_arity] = arch_no_register_req;
1885 for (p = 0; p < n_params; ++p) {
1886 ir_node *value = get_Call_param(node, p);
1887 ir_node *new_value = be_transform_node(value);
1888 ir_node *new_value1 = NULL;
1889 const reg_or_stackslot_t *param = &cconv->parameters[p];
1890 ir_type *param_type = get_method_param_type(type, p);
1891 ir_mode *mode = get_type_mode(param_type);
1894 if (mode_is_float(mode) && param->reg0 != NULL) {
1895 unsigned size_bits = get_mode_size_bits(mode);
1896 if (size_bits == 64) {
1897 double_to_ints(dbgi, new_block, new_value, &new_value,
1900 assert(size_bits == 32);
1901 new_value = float_to_int(dbgi, new_block, new_value);
1905 /* put value into registers */
1906 if (param->reg0 != NULL) {
1907 in[in_arity] = new_value;
1908 in_req[in_arity] = param->reg0->single_req;
1910 if (new_value1 == NULL)
1913 if (param->reg1 != NULL) {
1914 assert(new_value1 != NULL);
1915 in[in_arity] = new_value1;
1916 in_req[in_arity] = param->reg1->single_req;
1921 /* we need a store if we're here */
1922 if (new_value1 != NULL) {
1923 new_value = new_value1;
1927 /* create a parameter frame if necessary */
1928 if (incsp == NULL) {
1929 ir_node *new_frame = get_stack_pointer_for(node);
1930 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1931 cconv->param_stack_size, 1);
1933 if (mode_is_float(mode)) {
1934 str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem,
1935 mode, NULL, 0, param->offset, true);
1937 str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem,
1938 mode, NULL, 0, param->offset, true);
1940 sync_ins[sync_arity++] = str;
1942 assert(in_arity <= max_inputs);
1944 /* construct memory input */
1945 if (sync_arity == 0) {
1946 in[mem_pos] = new_mem;
1947 } else if (sync_arity == 1) {
1948 in[mem_pos] = sync_ins[0];
1950 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1953 /* TODO: use a generic symconst matcher here */
1954 if (is_SymConst(callee)) {
1955 entity = get_SymConst_entity(callee);
1957 /* TODO: finish load matcher here */
1960 if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) {
1961 ir_node *load = get_Proj_pred(callee);
1962 ir_node *ptr = get_Load_ptr(load);
1963 ir_node *new_ptr = be_transform_node(ptr);
1964 ir_node *mem = get_Load_mem(load);
1965 ir_node *new_mem = be_transform_node(mem);
1966 ir_mode *mode = get_Load_mode(node);
1970 in[in_arity] = be_transform_node(callee);
1971 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1980 out_arity = 1 + n_caller_saves;
1982 if (entity != NULL) {
1983 /* TODO: use a generic symconst matcher here
1984 * so we can also handle entity+offset, etc. */
1985 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1988 * - use a proper shifter_operand matcher
1989 * - we could also use LinkLdrPC
1991 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1995 if (incsp != NULL) {
1996 /* IncSP to destroy the call stackframe */
1997 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
1999 /* if we are the last IncSP producer in a block then we have to keep
2001 * Note: This here keeps all producers which is more than necessary */
2002 add_irn_dep(incsp, res);
2005 pmap_insert(node_to_stack, node, incsp);
2008 arch_set_in_register_reqs(res, in_req);
2010 /* create output register reqs */
2011 arch_set_out_register_req(res, 0, arch_no_register_req);
2012 for (o = 0; o < n_caller_saves; ++o) {
2013 const arch_register_t *reg = caller_saves[o];
2014 arch_set_out_register_req(res, o+1, reg->single_req);
2017 /* copy pinned attribute */
2018 set_irn_pinned(res, get_irn_pinned(node));
2020 arm_free_calling_convention(cconv);
2024 static ir_node *gen_Sel(ir_node *node)
2026 dbg_info *dbgi = get_irn_dbg_info(node);
2027 ir_node *block = get_nodes_block(node);
2028 ir_node *new_block = be_transform_node(block);
2029 ir_node *ptr = get_Sel_ptr(node);
2030 ir_node *new_ptr = be_transform_node(ptr);
2031 ir_entity *entity = get_Sel_entity(node);
2033 /* must be the frame pointer all other sels must have been lowered
2035 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
2036 /* we should not have value types from parameters anymore - they should be
2038 assert(get_entity_owner(entity) !=
2039 get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
2041 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
2045 * Change some phi modes
2047 static ir_node *gen_Phi(ir_node *node)
2049 const arch_register_req_t *req;
2050 ir_node *block = be_transform_node(get_nodes_block(node));
2051 ir_graph *irg = current_ir_graph;
2052 dbg_info *dbgi = get_irn_dbg_info(node);
2053 ir_mode *mode = get_irn_mode(node);
2056 if (mode_needs_gp_reg(mode)) {
2057 /* we shouldn't have any 64bit stuff around anymore */
2058 assert(get_mode_size_bits(mode) <= 32);
2059 /* all integer operations are on 32bit registers now */
2061 req = arm_reg_classes[CLASS_arm_gp].class_req;
2063 req = arch_no_register_req;
2066 /* phi nodes allow loops, so we use the old arguments for now
2067 * and fix this later */
2068 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
2069 get_irn_in(node) + 1);
2070 copy_node_attr(irg, node, phi);
2071 be_duplicate_deps(node, phi);
2073 arch_set_out_register_req(phi, 0, req);
2075 be_enqueue_preds(node);
2082 * Enters all transform functions into the generic pointer
2084 static void arm_register_transformers(void)
2086 be_start_transform_setup();
2088 be_set_transform_function(op_Add, gen_Add);
2089 be_set_transform_function(op_And, gen_And);
2090 be_set_transform_function(op_Call, gen_Call);
2091 be_set_transform_function(op_Cmp, gen_Cmp);
2092 be_set_transform_function(op_Cond, gen_Cond);
2093 be_set_transform_function(op_Const, gen_Const);
2094 be_set_transform_function(op_Conv, gen_Conv);
2095 be_set_transform_function(op_CopyB, gen_CopyB);
2096 be_set_transform_function(op_Div, gen_Div);
2097 be_set_transform_function(op_Eor, gen_Eor);
2098 be_set_transform_function(op_Jmp, gen_Jmp);
2099 be_set_transform_function(op_Load, gen_Load);
2100 be_set_transform_function(op_Minus, gen_Minus);
2101 be_set_transform_function(op_Mul, gen_Mul);
2102 be_set_transform_function(op_Not, gen_Not);
2103 be_set_transform_function(op_Or, gen_Or);
2104 be_set_transform_function(op_Phi, gen_Phi);
2105 be_set_transform_function(op_Proj, gen_Proj);
2106 be_set_transform_function(op_Return, gen_Return);
2107 be_set_transform_function(op_Rotl, gen_Rotl);
2108 be_set_transform_function(op_Sel, gen_Sel);
2109 be_set_transform_function(op_Shl, gen_Shl);
2110 be_set_transform_function(op_Shr, gen_Shr);
2111 be_set_transform_function(op_Shrs, gen_Shrs);
2112 be_set_transform_function(op_Start, gen_Start);
2113 be_set_transform_function(op_Store, gen_Store);
2114 be_set_transform_function(op_Sub, gen_Sub);
2115 be_set_transform_function(op_SymConst, gen_SymConst);
2116 be_set_transform_function(op_Unknown, gen_Unknown);
2117 be_set_transform_function(op_Builtin, gen_Builtin);
2121 * Initialize fpa Immediate support.
2123 static void arm_init_fpa_immediate(void)
2125 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
2126 fpa_imm[FPA_IMM_FLOAT][fpa_null] = get_mode_null(mode_F);
2127 fpa_imm[FPA_IMM_FLOAT][fpa_one] = get_mode_one(mode_F);
2128 fpa_imm[FPA_IMM_FLOAT][fpa_two] = new_tarval_from_str("2", 1, mode_F);
2129 fpa_imm[FPA_IMM_FLOAT][fpa_three] = new_tarval_from_str("3", 1, mode_F);
2130 fpa_imm[FPA_IMM_FLOAT][fpa_four] = new_tarval_from_str("4", 1, mode_F);
2131 fpa_imm[FPA_IMM_FLOAT][fpa_five] = new_tarval_from_str("5", 1, mode_F);
2132 fpa_imm[FPA_IMM_FLOAT][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
2133 fpa_imm[FPA_IMM_FLOAT][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
2135 fpa_imm[FPA_IMM_DOUBLE][fpa_null] = get_mode_null(mode_D);
2136 fpa_imm[FPA_IMM_DOUBLE][fpa_one] = get_mode_one(mode_D);
2137 fpa_imm[FPA_IMM_DOUBLE][fpa_two] = new_tarval_from_str("2", 1, mode_D);
2138 fpa_imm[FPA_IMM_DOUBLE][fpa_three] = new_tarval_from_str("3", 1, mode_D);
2139 fpa_imm[FPA_IMM_DOUBLE][fpa_four] = new_tarval_from_str("4", 1, mode_D);
2140 fpa_imm[FPA_IMM_DOUBLE][fpa_five] = new_tarval_from_str("5", 1, mode_D);
2141 fpa_imm[FPA_IMM_DOUBLE][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
2142 fpa_imm[FPA_IMM_DOUBLE][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
2144 fpa_imm[FPA_IMM_EXTENDED][fpa_null] = get_mode_null(mode_E);
2145 fpa_imm[FPA_IMM_EXTENDED][fpa_one] = get_mode_one(mode_E);
2146 fpa_imm[FPA_IMM_EXTENDED][fpa_two] = new_tarval_from_str("2", 1, mode_E);
2147 fpa_imm[FPA_IMM_EXTENDED][fpa_three] = new_tarval_from_str("3", 1, mode_E);
2148 fpa_imm[FPA_IMM_EXTENDED][fpa_four] = new_tarval_from_str("4", 1, mode_E);
2149 fpa_imm[FPA_IMM_EXTENDED][fpa_five] = new_tarval_from_str("5", 1, mode_E);
2150 fpa_imm[FPA_IMM_EXTENDED][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
2151 fpa_imm[FPA_IMM_EXTENDED][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
2155 * Transform a Firm graph into an ARM graph.
2157 void arm_transform_graph(ir_graph *irg)
2159 static int imm_initialized = 0;
2160 ir_entity *entity = get_irg_entity(irg);
2161 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
2162 ir_type *frame_type;
2167 if (! imm_initialized) {
2168 arm_init_fpa_immediate();
2169 imm_initialized = 1;
2171 arm_register_transformers();
2173 isa = (arm_isa_t*) arch_env;
2175 node_to_stack = pmap_create();
2177 assert(abihelper == NULL);
2178 abihelper = be_abihelper_prepare(irg);
2179 be_collect_stacknodes(abihelper);
2180 assert(cconv == NULL);
2181 cconv = arm_decide_calling_convention(irg, get_entity_type(entity));
2182 create_stacklayout(irg);
2184 be_transform_graph(irg, NULL);
2186 be_abihelper_finish(abihelper);
2189 arm_free_calling_convention(cconv);
2192 frame_type = get_irg_frame_type(irg);
2193 if (get_type_state(frame_type) == layout_undefined) {
2194 default_layout_compound_type(frame_type);
2197 pmap_destroy(node_to_stack);
2198 node_to_stack = NULL;
2200 be_add_missing_keeps(irg);
2203 void arm_init_transform(void)
2205 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");