2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
41 #include "../benode.h"
43 #include "../beutil.h"
44 #include "../betranshlp.h"
45 #include "../beabihelper.h"
48 #include "bearch_arm_t.h"
49 #include "arm_nodes_attr.h"
50 #include "arm_transform.h"
51 #include "arm_optimize.h"
52 #include "arm_new_nodes.h"
53 #include "arm_map_regs.h"
54 #include "arm_cconv.h"
56 #include "gen_arm_regalloc_if.h"
60 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 /** hold the current code generator during transformation */
63 static arm_code_gen_t *env_cg;
65 static const arch_register_t *sp_reg = &arm_gp_regs[REG_SP];
66 static ir_mode *mode_gp;
67 static ir_mode *mode_fp;
68 static beabi_helper_env_t *abihelper;
69 static calling_convention_t *cconv = NULL;
71 static pmap *node_to_stack;
73 static bool mode_needs_gp_reg(ir_mode *mode)
75 return mode_is_int(mode) || mode_is_reference(mode);
79 * create firm graph for a constant
81 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
88 /* We only have 8 bit immediates. So we possibly have to combine several
89 * operations to construct the desired value.
91 * we can either create the value by adding bits to 0 or by removing bits
92 * from an register with all bits set. Try which alternative needs fewer
94 arm_gen_vals_from_word(value, &v);
95 arm_gen_vals_from_word(~value, &vn);
99 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
100 be_dep_on_frame(result);
102 for (cnt = 1; cnt < vn.ops; ++cnt) {
103 result = new_bd_arm_Bic_imm(dbgi, block, result,
104 vn.values[cnt], vn.rors[cnt]);
108 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
109 be_dep_on_frame(result);
111 for (cnt = 1; cnt < v.ops; ++cnt) {
112 result = new_bd_arm_Or_imm(dbgi, block, result,
113 v.values[cnt], v.rors[cnt]);
120 * Create a DAG constructing a given Const.
122 * @param irn a Firm const
124 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
126 tarval *tv = get_Const_tarval(irn);
127 ir_mode *mode = get_tarval_mode(tv);
130 if (mode_is_reference(mode)) {
131 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
132 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
133 tv = tarval_convert_to(tv, mode_Iu);
135 value = get_tarval_long(tv);
136 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
140 * Create an And that will zero out upper bits.
142 * @param dbgi debug info
143 * @param block the basic block
144 * @param op the original node
145 * param src_bits number of lower bits that will remain
147 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
151 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
152 } else if (src_bits == 16) {
153 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
154 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
157 panic("zero extension only supported for 8 and 16 bits");
162 * Generate code for a sign extension.
164 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
167 int shift_width = 32 - src_bits;
168 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
169 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
173 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
176 int bits = get_mode_size_bits(orig_mode);
180 if (mode_is_signed(orig_mode)) {
181 return gen_sign_extension(dbgi, block, op, bits);
183 return gen_zero_extension(dbgi, block, op, bits);
188 * returns true if it is assured, that the upper bits of a node are "clean"
189 * which means for a 16 or 8 bit value, that the upper bits in the register
190 * are 0 for unsigned and a copy of the last significant bit for signed
193 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
195 (void) transformed_node;
202 * Transforms a Conv node.
204 * @return The created ia32 Conv node
206 static ir_node *gen_Conv(ir_node *node)
208 ir_node *block = be_transform_node(get_nodes_block(node));
209 ir_node *op = get_Conv_op(node);
210 ir_node *new_op = be_transform_node(op);
211 ir_mode *src_mode = get_irn_mode(op);
212 ir_mode *dst_mode = get_irn_mode(node);
213 dbg_info *dbg = get_irn_dbg_info(node);
215 if (src_mode == dst_mode)
218 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
219 if (USE_FPA(env_cg->isa)) {
220 if (mode_is_float(src_mode)) {
221 if (mode_is_float(dst_mode)) {
222 /* from float to float */
223 return new_bd_arm_Mvf(dbg, block, new_op, dst_mode);
225 /* from float to int */
229 /* from int to float */
230 if (!mode_is_signed(src_mode)) {
233 return new_bd_arm_FltX(dbg, block, new_op, dst_mode);
236 } else if (USE_VFP(env_cg->isa)) {
237 panic("VFP not supported yet");
239 panic("Softfloat not supported yet");
241 } else { /* complete in gp registers */
242 int src_bits = get_mode_size_bits(src_mode);
243 int dst_bits = get_mode_size_bits(dst_mode);
247 if (src_bits == dst_bits) {
248 /* kill unnecessary conv */
252 if (src_bits < dst_bits) {
260 if (upper_bits_clean(new_op, min_mode)) {
264 if (mode_is_signed(min_mode)) {
265 return gen_sign_extension(dbg, block, new_op, min_bits);
267 return gen_zero_extension(dbg, block, new_op, min_bits);
277 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
279 unsigned val, low_pos, high_pos;
284 val = get_tarval_long(get_Const_tarval(node));
296 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
298 So we determine the smallest even position with a bit set
299 and the highest even position with no bit set anymore.
300 If the difference between these 2 is <= 8, then we can encode the value
303 low_pos = ntz(val) & ~1u;
304 high_pos = (32-nlz(val)+1) & ~1u;
306 if (high_pos - low_pos <= 8) {
307 res->imm_8 = val >> low_pos;
308 res->rot = 32 - low_pos;
313 res->rot = 34 - high_pos;
314 val = val >> (32-res->rot) | val << (res->rot);
324 static bool is_downconv(const ir_node *node)
332 /* we only want to skip the conv when we're the only user
333 * (not optimal but for now...)
335 if (get_irn_n_edges(node) > 1)
338 src_mode = get_irn_mode(get_Conv_op(node));
339 dest_mode = get_irn_mode(node);
341 mode_needs_gp_reg(src_mode) &&
342 mode_needs_gp_reg(dest_mode) &&
343 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
346 static ir_node *arm_skip_downconv(ir_node *node)
348 while (is_downconv(node))
349 node = get_Conv_op(node);
355 MATCH_COMMUTATIVE = 1 << 0,
356 MATCH_SIZE_NEUTRAL = 1 << 1,
360 * possible binop constructors.
362 typedef struct arm_binop_factory_t {
363 /** normal reg op reg operation. */
364 ir_node *(*new_binop_reg)(dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
365 /** normal reg op imm operation. */
366 ir_node *(*new_binop_imm)(dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
367 /** barrel shifter reg op (reg shift reg operation. */
368 ir_node *(*new_binop_reg_shift_reg)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *shift, arm_shift_modifier_t shift_modifier);
369 /** barrel shifter reg op (reg shift imm operation. */
370 ir_node *(*new_binop_reg_shift_imm)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, arm_shift_modifier_t shift_modifier, unsigned shift_immediate);
371 } arm_binop_factory_t;
373 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
374 const arm_binop_factory_t *factory)
376 ir_node *block = be_transform_node(get_nodes_block(node));
377 ir_node *op1 = get_binop_left(node);
379 ir_node *op2 = get_binop_right(node);
381 dbg_info *dbgi = get_irn_dbg_info(node);
384 if (flags & MATCH_SIZE_NEUTRAL) {
385 op1 = arm_skip_downconv(op1);
386 op2 = arm_skip_downconv(op2);
388 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
391 if (try_encode_as_immediate(op2, &imm)) {
392 ir_node *new_op1 = be_transform_node(op1);
393 return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
395 new_op2 = be_transform_node(op2);
396 if ((flags & MATCH_COMMUTATIVE) && try_encode_as_immediate(op1, &imm)) {
397 return factory->new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
399 new_op1 = be_transform_node(op1);
401 /* check if we can fold in a Mov */
402 if (is_arm_Mov(new_op2)) {
403 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op2);
405 switch (attr->shift_modifier) {
406 ir_node *mov_op, *mov_sft;
409 case ARM_SHF_ASR_IMM:
410 case ARM_SHF_LSL_IMM:
411 case ARM_SHF_LSR_IMM:
412 case ARM_SHF_ROR_IMM:
413 if (factory->new_binop_reg_shift_imm) {
414 mov_op = get_irn_n(new_op2, 0);
415 return factory->new_binop_reg_shift_imm(dbgi, block, new_op1, mov_op,
416 attr->shift_modifier, attr->shift_immediate);
420 case ARM_SHF_ASR_REG:
421 case ARM_SHF_LSL_REG:
422 case ARM_SHF_LSR_REG:
423 case ARM_SHF_ROR_REG:
424 if (factory->new_binop_reg_shift_reg) {
425 mov_op = get_irn_n(new_op2, 0);
426 mov_sft = get_irn_n(new_op2, 1);
427 return factory->new_binop_reg_shift_reg(dbgi, block, new_op1, mov_op, mov_sft,
428 attr->shift_modifier);
433 if ((flags & MATCH_COMMUTATIVE) && is_arm_Mov(new_op1)) {
434 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op1);
436 switch (attr->shift_modifier) {
437 ir_node *mov_op, *mov_sft;
440 case ARM_SHF_ASR_IMM:
441 case ARM_SHF_LSL_IMM:
442 case ARM_SHF_LSR_IMM:
443 case ARM_SHF_ROR_IMM:
444 if (factory->new_binop_reg_shift_imm) {
445 mov_op = get_irn_n(new_op1, 0);
446 return factory->new_binop_reg_shift_imm(dbgi, block, new_op2, mov_op,
447 attr->shift_modifier, attr->shift_immediate);
451 case ARM_SHF_ASR_REG:
452 case ARM_SHF_LSL_REG:
453 case ARM_SHF_LSR_REG:
454 case ARM_SHF_ROR_REG:
455 if (factory->new_binop_reg_shift_reg) {
456 mov_op = get_irn_n(new_op1, 0);
457 mov_sft = get_irn_n(new_op1, 1);
458 return factory->new_binop_reg_shift_reg(dbgi, block, new_op2, mov_op, mov_sft,
459 attr->shift_modifier);
464 return factory->new_binop_reg(dbgi, block, new_op1, new_op2);
468 * Creates an ARM Add.
470 * @return the created arm Add node
472 static ir_node *gen_Add(ir_node *node)
474 static const arm_binop_factory_t add_factory = {
477 new_bd_arm_Add_reg_shift_reg,
478 new_bd_arm_Add_reg_shift_imm
481 ir_mode *mode = get_irn_mode(node);
483 if (mode_is_float(mode)) {
484 ir_node *block = be_transform_node(get_nodes_block(node));
485 ir_node *op1 = get_Add_left(node);
486 ir_node *op2 = get_Add_right(node);
487 dbg_info *dbgi = get_irn_dbg_info(node);
488 ir_node *new_op1 = be_transform_node(op1);
489 ir_node *new_op2 = be_transform_node(op2);
490 if (USE_FPA(env_cg->isa)) {
491 return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
492 } else if (USE_VFP(env_cg->isa)) {
493 assert(mode != mode_E && "IEEE Extended FP not supported");
494 panic("VFP not supported yet");
496 panic("Softfloat not supported yet");
501 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
503 new_op2 = get_irn_n(new_op1, 1);
504 new_op1 = get_irn_n(new_op1, 0);
506 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
508 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
510 new_op1 = get_irn_n(new_op2, 0);
511 new_op2 = get_irn_n(new_op2, 1);
513 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
517 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &add_factory);
522 * Creates an ARM Mul.
524 * @return the created arm Mul node
526 static ir_node *gen_Mul(ir_node *node)
528 ir_node *block = be_transform_node(get_nodes_block(node));
529 ir_node *op1 = get_Mul_left(node);
530 ir_node *new_op1 = be_transform_node(op1);
531 ir_node *op2 = get_Mul_right(node);
532 ir_node *new_op2 = be_transform_node(op2);
533 ir_mode *mode = get_irn_mode(node);
534 dbg_info *dbg = get_irn_dbg_info(node);
536 if (mode_is_float(mode)) {
537 if (USE_FPA(env_cg->isa)) {
538 return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
539 } else if (USE_VFP(env_cg->isa)) {
540 assert(mode != mode_E && "IEEE Extended FP not supported");
541 panic("VFP not supported yet");
543 panic("Softfloat not supported yet");
546 assert(mode_is_data(mode));
547 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
550 static ir_node *gen_Quot(ir_node *node)
552 ir_node *block = be_transform_node(get_nodes_block(node));
553 ir_node *op1 = get_Quot_left(node);
554 ir_node *new_op1 = be_transform_node(op1);
555 ir_node *op2 = get_Quot_right(node);
556 ir_node *new_op2 = be_transform_node(op2);
557 ir_mode *mode = get_irn_mode(node);
558 dbg_info *dbg = get_irn_dbg_info(node);
560 assert(mode != mode_E && "IEEE Extended FP not supported");
562 if (USE_FPA(env_cg->isa)) {
563 return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
564 } else if (USE_VFP(env_cg->isa)) {
565 assert(mode != mode_E && "IEEE Extended FP not supported");
566 panic("VFP not supported yet");
568 panic("Softfloat not supported yet");
572 static ir_node *gen_And(ir_node *node)
574 static const arm_binop_factory_t and_factory = {
577 new_bd_arm_And_reg_shift_reg,
578 new_bd_arm_And_reg_shift_imm
581 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &and_factory);
584 static ir_node *gen_Or(ir_node *node)
586 static const arm_binop_factory_t or_factory = {
589 new_bd_arm_Or_reg_shift_reg,
590 new_bd_arm_Or_reg_shift_imm
593 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &or_factory);
596 static ir_node *gen_Eor(ir_node *node)
598 static const arm_binop_factory_t eor_factory = {
601 new_bd_arm_Eor_reg_shift_reg,
602 new_bd_arm_Eor_reg_shift_imm
605 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &eor_factory);
608 static ir_node *gen_Sub(ir_node *node)
610 static const arm_binop_factory_t sub_factory = {
613 new_bd_arm_Sub_reg_shift_reg,
614 new_bd_arm_Sub_reg_shift_imm
617 ir_node *block = be_transform_node(get_nodes_block(node));
618 ir_node *op1 = get_Sub_left(node);
619 ir_node *new_op1 = be_transform_node(op1);
620 ir_node *op2 = get_Sub_right(node);
621 ir_node *new_op2 = be_transform_node(op2);
622 ir_mode *mode = get_irn_mode(node);
623 dbg_info *dbgi = get_irn_dbg_info(node);
625 if (mode_is_float(mode)) {
626 if (USE_FPA(env_cg->isa)) {
627 return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
628 } else if (USE_VFP(env_cg->isa)) {
629 assert(mode != mode_E && "IEEE Extended FP not supported");
630 panic("VFP not supported yet");
632 panic("Softfloat not supported yet");
635 return gen_int_binop(node, MATCH_SIZE_NEUTRAL, &sub_factory);
640 * Checks if a given value can be used as an immediate for the given
643 static bool can_use_shift_constant(unsigned int val,
644 arm_shift_modifier_t modifier)
648 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
654 * generate an ARM shift instruction.
656 * @param node the node
657 * @param flags matching flags
658 * @param shift_modifier initial encoding of the desired shift operation
660 static ir_node *make_shift(ir_node *node, match_flags_t flags,
661 arm_shift_modifier_t shift_modifier)
663 ir_node *block = be_transform_node(get_nodes_block(node));
664 ir_node *op1 = get_binop_left(node);
665 ir_node *op2 = get_binop_right(node);
666 dbg_info *dbgi = get_irn_dbg_info(node);
670 if (flags & MATCH_SIZE_NEUTRAL) {
671 op1 = arm_skip_downconv(op1);
672 op2 = arm_skip_downconv(op2);
675 new_op1 = be_transform_node(op1);
677 tarval *tv = get_Const_tarval(op2);
678 unsigned int val = get_tarval_long(tv);
679 assert(tarval_is_long(tv));
680 if (can_use_shift_constant(val, shift_modifier)) {
681 switch (shift_modifier) {
682 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
683 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
684 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
685 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
686 default: panic("unexpected shift modifier");
688 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
689 shift_modifier, val);
693 new_op2 = be_transform_node(op2);
694 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
698 static ir_node *gen_Shl(ir_node *node)
700 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
703 static ir_node *gen_Shr(ir_node *node)
705 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
708 static ir_node *gen_Shrs(ir_node *node)
710 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
713 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
715 ir_node *block = be_transform_node(get_nodes_block(node));
716 ir_node *new_op1 = be_transform_node(op1);
717 dbg_info *dbgi = get_irn_dbg_info(node);
718 ir_node *new_op2 = be_transform_node(op2);
720 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
724 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
726 ir_node *block = be_transform_node(get_nodes_block(node));
727 ir_node *new_op1 = be_transform_node(op1);
728 dbg_info *dbgi = get_irn_dbg_info(node);
729 ir_node *new_op2 = be_transform_node(op2);
731 /* Note: there is no Rol on arm, we have to use Ror */
732 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
733 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
737 static ir_node *gen_Rotl(ir_node *node)
739 ir_node *rotate = NULL;
740 ir_node *op1 = get_Rotl_left(node);
741 ir_node *op2 = get_Rotl_right(node);
743 /* Firm has only RotL, so we are looking for a right (op2)
744 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
745 that means we can create a RotR. */
748 ir_node *right = get_Add_right(op2);
749 if (is_Const(right)) {
750 tarval *tv = get_Const_tarval(right);
751 ir_mode *mode = get_irn_mode(node);
752 long bits = get_mode_size_bits(mode);
753 ir_node *left = get_Add_left(op2);
755 if (is_Minus(left) &&
756 tarval_is_long(tv) &&
757 get_tarval_long(tv) == bits &&
759 rotate = gen_Ror(node, op1, get_Minus_op(left));
761 } else if (is_Sub(op2)) {
762 ir_node *left = get_Sub_left(op2);
763 if (is_Const(left)) {
764 tarval *tv = get_Const_tarval(left);
765 ir_mode *mode = get_irn_mode(node);
766 long bits = get_mode_size_bits(mode);
767 ir_node *right = get_Sub_right(op2);
769 if (tarval_is_long(tv) &&
770 get_tarval_long(tv) == bits &&
772 rotate = gen_Ror(node, op1, right);
774 } else if (is_Const(op2)) {
775 tarval *tv = get_Const_tarval(op2);
776 ir_mode *mode = get_irn_mode(node);
777 long bits = get_mode_size_bits(mode);
779 if (tarval_is_long(tv) && bits == 32) {
780 ir_node *block = be_transform_node(get_nodes_block(node));
781 ir_node *new_op1 = be_transform_node(op1);
782 dbg_info *dbgi = get_irn_dbg_info(node);
784 bits = (bits - get_tarval_long(tv)) & 31;
785 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
789 if (rotate == NULL) {
790 rotate = gen_Rol(node, op1, op2);
796 static ir_node *gen_Not(ir_node *node)
798 ir_node *block = be_transform_node(get_nodes_block(node));
799 ir_node *op = get_Not_op(node);
800 ir_node *new_op = be_transform_node(op);
801 dbg_info *dbgi = get_irn_dbg_info(node);
803 /* TODO: we could do alot more here with all the Mvn variations */
805 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
808 static ir_node *gen_Minus(ir_node *node)
810 ir_node *block = be_transform_node(get_nodes_block(node));
811 ir_node *op = get_Minus_op(node);
812 ir_node *new_op = be_transform_node(op);
813 dbg_info *dbgi = get_irn_dbg_info(node);
814 ir_mode *mode = get_irn_mode(node);
816 if (mode_is_float(mode)) {
817 if (USE_FPA(env_cg->isa)) {
818 return new_bd_arm_Mvf(dbgi, block, op, mode);
819 } else if (USE_VFP(env_cg->isa)) {
820 assert(mode != mode_E && "IEEE Extended FP not supported");
821 panic("VFP not supported yet");
823 panic("Softfloat not supported yet");
826 assert(mode_is_data(mode));
827 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
830 static ir_node *gen_Load(ir_node *node)
832 ir_node *block = be_transform_node(get_nodes_block(node));
833 ir_node *ptr = get_Load_ptr(node);
834 ir_node *new_ptr = be_transform_node(ptr);
835 ir_node *mem = get_Load_mem(node);
836 ir_node *new_mem = be_transform_node(mem);
837 ir_mode *mode = get_Load_mode(node);
838 dbg_info *dbgi = get_irn_dbg_info(node);
839 ir_node *new_load = NULL;
841 if (mode_is_float(mode)) {
842 if (USE_FPA(env_cg->isa)) {
843 new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
845 } else if (USE_VFP(env_cg->isa)) {
846 assert(mode != mode_E && "IEEE Extended FP not supported");
847 panic("VFP not supported yet");
849 panic("Softfloat not supported yet");
852 assert(mode_is_data(mode) && "unsupported mode for Load");
854 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
856 set_irn_pinned(new_load, get_irn_pinned(node));
858 /* check for special case: the loaded value might not be used */
859 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
860 /* add a result proj and a Keep to produce a pseudo use */
861 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
862 be_new_Keep(block, 1, &proj);
868 static ir_node *gen_Store(ir_node *node)
870 ir_node *block = be_transform_node(get_nodes_block(node));
871 ir_node *ptr = get_Store_ptr(node);
872 ir_node *new_ptr = be_transform_node(ptr);
873 ir_node *mem = get_Store_mem(node);
874 ir_node *new_mem = be_transform_node(mem);
875 ir_node *val = get_Store_value(node);
876 ir_node *new_val = be_transform_node(val);
877 ir_mode *mode = get_irn_mode(val);
878 dbg_info *dbgi = get_irn_dbg_info(node);
879 ir_node *new_store = NULL;
881 if (mode_is_float(mode)) {
882 if (USE_FPA(env_cg->isa)) {
883 new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
884 new_mem, mode, NULL, 0, 0, false);
885 } else if (USE_VFP(env_cg->isa)) {
886 assert(mode != mode_E && "IEEE Extended FP not supported");
887 panic("VFP not supported yet");
889 panic("Softfloat not supported yet");
892 assert(mode_is_data(mode) && "unsupported mode for Store");
893 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
896 set_irn_pinned(new_store, get_irn_pinned(node));
900 static ir_node *gen_Jmp(ir_node *node)
902 ir_node *block = get_nodes_block(node);
903 ir_node *new_block = be_transform_node(block);
904 dbg_info *dbgi = get_irn_dbg_info(node);
906 return new_bd_arm_Jmp(dbgi, new_block);
909 static ir_node *gen_SwitchJmp(ir_node *node)
911 ir_node *block = be_transform_node(get_nodes_block(node));
912 ir_node *selector = get_Cond_selector(node);
913 dbg_info *dbgi = get_irn_dbg_info(node);
914 ir_node *new_op = be_transform_node(selector);
915 ir_node *const_graph;
919 const ir_edge_t *edge;
926 foreach_out_edge(node, edge) {
927 proj = get_edge_src_irn(edge);
928 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
930 pn = get_Proj_proj(proj);
932 min = pn<min ? pn : min;
933 max = pn>max ? pn : max;
936 n_projs = max - translation + 1;
938 foreach_out_edge(node, edge) {
939 proj = get_edge_src_irn(edge);
940 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
942 pn = get_Proj_proj(proj) - translation;
943 set_Proj_proj(proj, pn);
946 const_graph = create_const_graph_value(dbgi, block, translation);
947 sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
948 return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
951 static ir_node *gen_Cmp(ir_node *node)
953 ir_node *block = be_transform_node(get_nodes_block(node));
954 ir_node *op1 = get_Cmp_left(node);
955 ir_node *op2 = get_Cmp_right(node);
956 ir_mode *cmp_mode = get_irn_mode(op1);
957 dbg_info *dbgi = get_irn_dbg_info(node);
962 if (mode_is_float(cmp_mode)) {
963 /* TODO: this is broken... */
964 new_op1 = be_transform_node(op1);
965 new_op2 = be_transform_node(op2);
967 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
969 panic("FloatCmp NIY");
971 ir_node *new_op2 = be_transform_node(op2);
972 /* floating point compare */
973 pn_Cmp pnc = get_Proj_proj(selector);
975 if (pnc & pn_Cmp_Uo) {
976 /* check for unordered, need cmf */
977 return new_bd_arm_CmfBra(dbgi, block, new_op1, new_op2, pnc);
979 /* Hmm: use need cmfe */
980 return new_bd_arm_CmfeBra(dbgi, block, new_op1, new_op2, pnc);
984 assert(get_irn_mode(op2) == cmp_mode);
985 is_unsigned = !mode_is_signed(cmp_mode);
987 /* compare with 0 can be done with Tst */
988 if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) {
989 new_op1 = be_transform_node(op1);
990 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
991 return new_bd_arm_Tst_reg(dbgi, block, new_op1, new_op1, false,
994 if (is_Const(op1) && tarval_is_null(get_Const_tarval(op1))) {
995 new_op2 = be_transform_node(op2);
996 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
997 return new_bd_arm_Tst_reg(dbgi, block, new_op2, new_op2, true,
1001 /* integer compare, TODO: use shifter_op in all its combinations */
1002 new_op1 = be_transform_node(op1);
1003 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
1004 new_op2 = be_transform_node(op2);
1005 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
1006 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
1010 static ir_node *gen_Cond(ir_node *node)
1012 ir_node *selector = get_Cond_selector(node);
1013 ir_mode *mode = get_irn_mode(selector);
1018 if (mode != mode_b) {
1019 return gen_SwitchJmp(node);
1021 assert(is_Proj(selector));
1023 block = be_transform_node(get_nodes_block(node));
1024 dbgi = get_irn_dbg_info(node);
1025 flag_node = be_transform_node(get_Proj_pred(selector));
1027 return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector));
1030 static tarval *fpa_imm[3][fpa_max];
1034 * Check, if a floating point tarval is an fpa immediate, i.e.
1035 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
1037 static int is_fpa_immediate(tarval *tv)
1039 ir_mode *mode = get_tarval_mode(tv);
1042 switch (get_mode_size_bits(mode)) {
1053 if (tarval_is_negative(tv)) {
1054 tv = tarval_neg(tv);
1058 for (j = 0; j < fpa_max; ++j) {
1059 if (tv == fpa_imm[i][j])
1066 static ir_node *gen_Const(ir_node *node)
1068 ir_node *block = be_transform_node(get_nodes_block(node));
1069 ir_mode *mode = get_irn_mode(node);
1070 dbg_info *dbg = get_irn_dbg_info(node);
1072 if (mode_is_float(mode)) {
1073 if (USE_FPA(env_cg->isa)) {
1074 tarval *tv = get_Const_tarval(node);
1075 node = new_bd_arm_fConst(dbg, block, tv);
1076 be_dep_on_frame(node);
1078 } else if (USE_VFP(env_cg->isa)) {
1079 assert(mode != mode_E && "IEEE Extended FP not supported");
1080 panic("VFP not supported yet");
1082 panic("Softfloat not supported yet");
1085 return create_const_graph(node, block);
1088 static ir_node *gen_SymConst(ir_node *node)
1090 ir_node *block = be_transform_node(get_nodes_block(node));
1091 ir_entity *entity = get_SymConst_entity(node);
1092 dbg_info *dbgi = get_irn_dbg_info(node);
1095 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
1096 be_dep_on_frame(new_node);
1100 static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0,
1103 /* the good way to do this would be to use the stm (store multiple)
1104 * instructions, since our input is nearly always 2 consecutive 32bit
1106 ir_graph *irg = current_ir_graph;
1107 ir_node *stack = get_irg_frame(irg);
1108 ir_node *nomem = new_NoMem();
1109 ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp,
1111 ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp,
1113 ir_node *in[2] = { str0, str1 };
1114 ir_node *sync = new_r_Sync(block, 2, in);
1116 set_irn_pinned(str0, op_pin_state_floats);
1117 set_irn_pinned(str1, op_pin_state_floats);
1119 ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true);
1120 set_irn_pinned(ldf, op_pin_state_floats);
1122 return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1125 static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node)
1127 ir_graph *irg = current_ir_graph;
1128 ir_node *stack = get_irg_frame(irg);
1129 ir_node *nomem = new_NoMem();
1130 ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp,
1133 set_irn_pinned(str, op_pin_state_floats);
1135 ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true);
1136 set_irn_pinned(ldf, op_pin_state_floats);
1138 return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1141 static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node)
1143 ir_graph *irg = current_ir_graph;
1144 ir_node *stack = get_irg_frame(irg);
1145 ir_node *nomem = new_NoMem();
1146 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F,
1149 set_irn_pinned(stf, op_pin_state_floats);
1151 ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1152 set_irn_pinned(ldr, op_pin_state_floats);
1154 return new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1157 static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node,
1158 ir_node **out_value0, ir_node **out_value1)
1160 ir_graph *irg = current_ir_graph;
1161 ir_node *stack = get_irg_frame(irg);
1162 ir_node *nomem = new_NoMem();
1163 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D,
1165 ir_node *ldr0, *ldr1;
1166 set_irn_pinned(stf, op_pin_state_floats);
1168 ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1169 set_irn_pinned(ldr0, op_pin_state_floats);
1170 ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true);
1171 set_irn_pinned(ldr1, op_pin_state_floats);
1173 *out_value0 = new_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
1174 *out_value1 = new_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
1177 static ir_node *gen_CopyB(ir_node *node)
1179 ir_node *block = be_transform_node(get_nodes_block(node));
1180 ir_node *src = get_CopyB_src(node);
1181 ir_node *new_src = be_transform_node(src);
1182 ir_node *dst = get_CopyB_dst(node);
1183 ir_node *new_dst = be_transform_node(dst);
1184 ir_node *mem = get_CopyB_mem(node);
1185 ir_node *new_mem = be_transform_node(mem);
1186 dbg_info *dbg = get_irn_dbg_info(node);
1187 int size = get_type_size_bytes(get_CopyB_type(node));
1191 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
1192 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
1194 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1195 new_bd_arm_EmptyReg(dbg, block),
1196 new_bd_arm_EmptyReg(dbg, block),
1197 new_bd_arm_EmptyReg(dbg, block),
1201 static ir_node *gen_Proj_Load(ir_node *node)
1203 ir_node *load = get_Proj_pred(node);
1204 ir_node *new_load = be_transform_node(load);
1205 dbg_info *dbgi = get_irn_dbg_info(node);
1206 long proj = get_Proj_proj(node);
1208 /* renumber the proj */
1209 switch (get_arm_irn_opcode(new_load)) {
1211 /* handle all gp loads equal: they have the same proj numbers. */
1212 if (proj == pn_Load_res) {
1213 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1214 } else if (proj == pn_Load_M) {
1215 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1219 if (proj == pn_Load_res) {
1220 ir_mode *mode = get_Load_mode(load);
1221 return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res);
1222 } else if (proj == pn_Load_M) {
1223 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M);
1229 panic("Unsupported Proj from Load");
1232 static ir_node *gen_Proj_CopyB(ir_node *node)
1234 ir_node *pred = get_Proj_pred(node);
1235 ir_node *new_pred = be_transform_node(pred);
1236 dbg_info *dbgi = get_irn_dbg_info(node);
1237 long proj = get_Proj_proj(node);
1241 if (is_arm_CopyB(new_pred)) {
1242 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1248 panic("Unsupported Proj from CopyB");
1251 static ir_node *gen_Proj_Quot(ir_node *node)
1253 ir_node *pred = get_Proj_pred(node);
1254 ir_node *new_pred = be_transform_node(pred);
1255 dbg_info *dbgi = get_irn_dbg_info(node);
1256 ir_mode *mode = get_irn_mode(node);
1257 long proj = get_Proj_proj(node);
1261 if (is_arm_Dvf(new_pred)) {
1262 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
1266 if (is_arm_Dvf(new_pred)) {
1267 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
1273 panic("Unsupported Proj from Quot");
1277 * Transform the Projs from a Cmp.
1279 static ir_node *gen_Proj_Cmp(ir_node *node)
1282 /* we should only be here in case of a Mux node */
1286 static ir_node *gen_Proj_Start(ir_node *node)
1288 ir_node *block = get_nodes_block(node);
1289 ir_node *new_block = be_transform_node(block);
1290 ir_node *barrier = be_transform_node(get_Proj_pred(node));
1291 long proj = get_Proj_proj(node);
1293 switch ((pn_Start) proj) {
1294 case pn_Start_X_initial_exec:
1295 /* we exchange the ProjX with a jump */
1296 return new_bd_arm_Jmp(NULL, new_block);
1299 return new_r_Proj(barrier, mode_M, 0);
1301 case pn_Start_T_args:
1304 case pn_Start_P_frame_base:
1305 return be_prolog_get_reg_value(abihelper, sp_reg);
1307 case pn_Start_P_tls:
1313 panic("unexpected start proj: %ld\n", proj);
1316 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1318 long pn = get_Proj_proj(node);
1319 ir_node *block = get_nodes_block(node);
1320 ir_node *new_block = be_transform_node(block);
1321 ir_entity *entity = get_irg_entity(current_ir_graph);
1322 ir_type *method_type = get_entity_type(entity);
1323 ir_type *param_type = get_method_param_type(method_type, pn);
1324 const reg_or_stackslot_t *param;
1326 /* Proj->Proj->Start must be a method argument */
1327 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1329 param = &cconv->parameters[pn];
1331 if (param->reg0 != NULL) {
1332 /* argument transmitted in register */
1333 ir_mode *mode = get_type_mode(param_type);
1334 ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0);
1336 if (mode_is_float(mode)) {
1337 ir_node *value1 = NULL;
1339 if (param->reg1 != NULL) {
1340 value1 = be_prolog_get_reg_value(abihelper, param->reg1);
1341 } else if (param->entity != NULL) {
1342 ir_graph *irg = get_irn_irg(node);
1343 ir_node *fp = get_irg_frame(irg);
1344 ir_node *mem = be_prolog_get_memory(abihelper);
1345 ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem,
1346 mode_gp, param->entity,
1348 value1 = new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1351 /* convert integer value to float */
1352 if (value1 == NULL) {
1353 value = int_to_float(NULL, new_block, value);
1355 value = ints_to_double(NULL, new_block, value, value1);
1360 /* argument transmitted on stack */
1361 ir_graph *irg = get_irn_irg(node);
1362 ir_node *fp = get_irg_frame(irg);
1363 ir_node *mem = be_prolog_get_memory(abihelper);
1364 ir_mode *mode = get_type_mode(param->type);
1368 if (mode_is_float(mode)) {
1369 load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode,
1370 param->entity, 0, 0, true);
1371 value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res);
1373 load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1374 param->entity, 0, 0, true);
1375 value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1377 set_irn_pinned(load, op_pin_state_floats);
1384 * Finds number of output value of a mode_T node which is constrained to
1385 * a single specific register.
1387 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1389 int n_outs = arch_irn_get_n_outs(node);
1392 for (o = 0; o < n_outs; ++o) {
1393 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1394 if (req == reg->single_req)
1400 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1402 long pn = get_Proj_proj(node);
1403 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1404 ir_node *new_call = be_transform_node(call);
1405 ir_type *function_type = get_Call_type(call);
1406 calling_convention_t *cconv = arm_decide_calling_convention(function_type);
1407 const reg_or_stackslot_t *res = &cconv->results[pn];
1411 /* TODO 64bit modes */
1412 assert(res->reg0 != NULL && res->reg1 == NULL);
1413 regn = find_out_for_reg(new_call, res->reg0);
1415 panic("Internal error in calling convention for return %+F", node);
1417 mode = res->reg0->reg_class->mode;
1419 arm_free_calling_convention(cconv);
1421 return new_r_Proj(new_call, mode, regn);
1424 static ir_node *gen_Proj_Call(ir_node *node)
1426 long pn = get_Proj_proj(node);
1427 ir_node *call = get_Proj_pred(node);
1428 ir_node *new_call = be_transform_node(call);
1430 switch ((pn_Call) pn) {
1432 return new_r_Proj(new_call, mode_M, 0);
1433 case pn_Call_X_regular:
1434 case pn_Call_X_except:
1435 case pn_Call_T_result:
1436 case pn_Call_P_value_res_base:
1440 panic("Unexpected Call proj %ld\n", pn);
1444 * Transform a Proj node.
1446 static ir_node *gen_Proj(ir_node *node)
1448 ir_node *pred = get_Proj_pred(node);
1449 long proj = get_Proj_proj(node);
1451 switch (get_irn_opcode(pred)) {
1453 if (proj == pn_Store_M) {
1454 return be_transform_node(pred);
1456 panic("Unsupported Proj from Store");
1459 return gen_Proj_Load(node);
1461 return gen_Proj_Call(node);
1463 return gen_Proj_CopyB(node);
1465 return gen_Proj_Quot(node);
1467 return gen_Proj_Cmp(node);
1469 return gen_Proj_Start(node);
1472 return be_duplicate_node(node);
1474 ir_node *pred_pred = get_Proj_pred(pred);
1475 if (is_Call(pred_pred)) {
1476 return gen_Proj_Proj_Call(node);
1477 } else if (is_Start(pred_pred)) {
1478 return gen_Proj_Proj_Start(node);
1483 panic("code selection didn't expect Proj after %+F\n", pred);
1487 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1489 static inline ir_node *create_const(ir_node **place,
1490 create_const_node_func func,
1491 const arch_register_t* reg)
1493 ir_node *block, *res;
1498 block = get_irg_start_block(env_cg->irg);
1499 res = func(NULL, block);
1500 arch_set_irn_register(res, reg);
1505 static ir_node *gen_Unknown(ir_node *node)
1507 ir_node *block = get_nodes_block(node);
1508 ir_node *new_block = be_transform_node(block);
1509 dbg_info *dbgi = get_irn_dbg_info(node);
1511 /* just produce a 0 */
1512 ir_mode *mode = get_irn_mode(node);
1513 if (mode_is_float(mode)) {
1514 tarval *tv = get_mode_null(mode);
1515 ir_node *node = new_bd_arm_fConst(dbgi, new_block, tv);
1516 be_dep_on_frame(node);
1518 } else if (mode_needs_gp_reg(mode)) {
1519 return create_const_graph_value(dbgi, new_block, 0);
1522 panic("Unexpected Unknown mode");
1526 * Produces the type which sits between the stack args and the locals on the
1527 * stack. It will contain the return address and space to store the old base
1529 * @return The Firm type modeling the ABI between type.
1531 static ir_type *arm_get_between_type(void)
1533 static ir_type *between_type = NULL;
1535 if (between_type == NULL) {
1536 between_type = new_type_class(new_id_from_str("arm_between_type"));
1537 set_type_size_bytes(between_type, 0);
1540 return between_type;
1543 static void create_stacklayout(ir_graph *irg)
1545 ir_entity *entity = get_irg_entity(irg);
1546 ir_type *function_type = get_entity_type(entity);
1547 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1552 /* calling conventions must be decided by now */
1553 assert(cconv != NULL);
1555 /* construct argument type */
1556 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1557 n_params = get_method_n_params(function_type);
1558 for (p = 0; p < n_params; ++p) {
1559 reg_or_stackslot_t *param = &cconv->parameters[p];
1563 if (param->type == NULL)
1566 snprintf(buf, sizeof(buf), "param_%d", p);
1567 id = new_id_from_str(buf);
1568 param->entity = new_entity(arg_type, id, param->type);
1569 set_entity_offset(param->entity, param->offset);
1572 /* TODO: what about external functions? we don't know most of the stack
1573 * layout for them. And probably don't need all of this... */
1574 memset(layout, 0, sizeof(*layout));
1576 layout->frame_type = get_irg_frame_type(irg);
1577 layout->between_type = arm_get_between_type();
1578 layout->arg_type = arg_type;
1579 layout->param_map = NULL; /* TODO */
1580 layout->initial_offset = 0;
1581 layout->initial_bias = 0;
1582 layout->stack_dir = -1;
1583 layout->sp_relative = true;
1585 assert(N_FRAME_TYPES == 3);
1586 layout->order[0] = layout->frame_type;
1587 layout->order[1] = layout->between_type;
1588 layout->order[2] = layout->arg_type;
1592 * transform the start node to the prolog code + initial barrier
1594 static ir_node *gen_Start(ir_node *node)
1596 ir_graph *irg = get_irn_irg(node);
1597 ir_entity *entity = get_irg_entity(irg);
1598 ir_type *function_type = get_entity_type(entity);
1599 ir_node *block = get_nodes_block(node);
1600 ir_node *new_block = be_transform_node(block);
1601 dbg_info *dbgi = get_irn_dbg_info(node);
1608 /* stackpointer is important at function prolog */
1609 be_prolog_add_reg(abihelper, sp_reg,
1610 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1611 /* function parameters in registers */
1612 for (i = 0; i < get_method_n_params(function_type); ++i) {
1613 const reg_or_stackslot_t *param = &cconv->parameters[i];
1614 if (param->reg0 != NULL)
1615 be_prolog_add_reg(abihelper, param->reg0, 0);
1616 if (param->reg1 != NULL)
1617 be_prolog_add_reg(abihelper, param->reg1, 0);
1619 /* announce that we need the values of the callee save regs */
1620 for (i = 0; i < (int) (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
1621 be_prolog_add_reg(abihelper, callee_saves[i], 0);
1624 start = be_prolog_create_start(abihelper, dbgi, new_block);
1625 sp = be_prolog_get_reg_value(abihelper, sp_reg);
1626 incsp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
1627 be_prolog_set_reg_value(abihelper, sp_reg, incsp);
1628 barrier = be_prolog_create_barrier(abihelper, new_block);
1633 static ir_node *get_stack_pointer_for(ir_node *node)
1635 /* get predecessor in stack_order list */
1636 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1637 ir_node *stack_pred_transformed;
1640 if (stack_pred == NULL) {
1641 /* first stack user in the current block. We can simply use the
1642 * initial sp_proj for it */
1643 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1647 stack_pred_transformed = be_transform_node(stack_pred);
1648 stack = pmap_get(node_to_stack, stack_pred);
1649 if (stack == NULL) {
1650 return get_stack_pointer_for(stack_pred);
1657 * transform a Return node into epilogue code + return statement
1659 static ir_node *gen_Return(ir_node *node)
1661 ir_node *block = get_nodes_block(node);
1662 ir_node *new_block = be_transform_node(block);
1663 dbg_info *dbgi = get_irn_dbg_info(node);
1664 ir_node *mem = get_Return_mem(node);
1665 ir_node *new_mem = be_transform_node(mem);
1666 int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
1667 ir_node *sp_proj = get_stack_pointer_for(node);
1668 int n_res = get_Return_n_ress(node);
1673 be_epilog_begin(abihelper);
1674 be_epilog_set_memory(abihelper, new_mem);
1675 /* connect stack pointer with initial stack pointer. fix_stack phase
1676 will later serialize all stack pointer adjusting nodes */
1677 be_epilog_add_reg(abihelper, sp_reg,
1678 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1682 for (i = 0; i < n_res; ++i) {
1683 ir_node *res_value = get_Return_res(node, i);
1684 ir_node *new_res_value = be_transform_node(res_value);
1685 const reg_or_stackslot_t *slot = &cconv->results[i];
1686 const arch_register_t *reg = slot->reg0;
1687 assert(slot->reg1 == NULL);
1688 be_epilog_add_reg(abihelper, reg, 0, new_res_value);
1691 /* connect callee saves with their values at the function begin */
1692 for (i = 0; i < n_callee_saves; ++i) {
1693 const arch_register_t *reg = callee_saves[i];
1694 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1695 be_epilog_add_reg(abihelper, reg, 0, value);
1698 /* create the barrier before the epilog code */
1699 be_epilog_create_barrier(abihelper, new_block);
1701 /* epilog code: an incsp */
1702 sp_proj = be_epilog_get_reg_value(abihelper, sp_reg);
1703 incsp = be_new_IncSP(sp_reg, new_block, sp_proj,
1704 BE_STACK_FRAME_SIZE_SHRINK, 0);
1705 be_epilog_set_reg_value(abihelper, sp_reg, incsp);
1707 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1713 static ir_node *gen_Call(ir_node *node)
1715 ir_graph *irg = get_irn_irg(node);
1716 ir_node *callee = get_Call_ptr(node);
1717 ir_node *block = get_nodes_block(node);
1718 ir_node *new_block = be_transform_node(block);
1719 ir_node *mem = get_Call_mem(node);
1720 ir_node *new_mem = be_transform_node(mem);
1721 dbg_info *dbgi = get_irn_dbg_info(node);
1722 ir_type *type = get_Call_type(node);
1723 calling_convention_t *cconv = arm_decide_calling_convention(type);
1724 int n_params = get_Call_n_params(node);
1725 int n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
1726 /* max inputs: memory, callee, register arguments */
1727 int max_inputs = 2 + n_param_regs;
1728 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1729 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1730 struct obstack *obst = be_get_be_obst(irg);
1731 const arch_register_req_t **in_req
1732 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1736 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1737 ir_entity *entity = NULL;
1738 ir_node *incsp = NULL;
1745 assert(n_params == get_method_n_params(type));
1747 /* construct arguments */
1750 in_req[in_arity] = arch_no_register_req;
1754 for (p = 0; p < n_params; ++p) {
1755 ir_node *value = get_Call_param(node, p);
1756 ir_node *new_value = be_transform_node(value);
1757 ir_node *new_value1 = NULL;
1758 const reg_or_stackslot_t *param = &cconv->parameters[p];
1759 ir_type *param_type = get_method_param_type(type, p);
1760 ir_mode *mode = get_type_mode(param_type);
1763 if (mode_is_float(mode) && param->reg0 != NULL) {
1764 unsigned size_bits = get_mode_size_bits(mode);
1765 if (size_bits == 64) {
1766 double_to_ints(dbgi, new_block, new_value, &new_value,
1769 assert(size_bits == 32);
1770 new_value = float_to_int(dbgi, new_block, new_value);
1774 /* put value into registers */
1775 if (param->reg0 != NULL) {
1776 in[in_arity] = new_value;
1777 in_req[in_arity] = param->reg0->single_req;
1779 if (new_value1 == NULL)
1782 if (param->reg1 != NULL) {
1783 assert(new_value1 != NULL);
1784 in[in_arity] = new_value1;
1785 in_req[in_arity] = param->reg1->single_req;
1790 /* we need a store if we're here */
1791 if (new_value1 != NULL) {
1792 new_value = new_value1;
1796 /* create a parameter frame if necessary */
1797 if (incsp == NULL) {
1798 ir_node *new_frame = get_stack_pointer_for(node);
1799 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1800 cconv->param_stack_size, 1);
1802 if (mode_is_float(mode)) {
1803 str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem,
1804 mode, NULL, 0, param->offset, true);
1806 str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem,
1807 mode, NULL, 0, param->offset, true);
1809 sync_ins[sync_arity++] = str;
1811 assert(in_arity <= max_inputs);
1813 /* construct memory input */
1814 if (sync_arity == 0) {
1815 in[mem_pos] = new_mem;
1816 } else if (sync_arity == 1) {
1817 in[mem_pos] = sync_ins[0];
1819 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1822 /* TODO: use a generic symconst matcher here */
1823 if (is_SymConst(callee)) {
1824 entity = get_SymConst_entity(callee);
1826 /* TODO: finish load matcher here */
1829 if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) {
1830 ir_node *load = get_Proj_pred(callee);
1831 ir_node *ptr = get_Load_ptr(load);
1832 ir_node *new_ptr = be_transform_node(ptr);
1833 ir_node *mem = get_Load_mem(load);
1834 ir_node *new_mem = be_transform_node(mem);
1835 ir_mode *mode = get_Load_mode(node);
1839 in[in_arity] = be_transform_node(callee);
1840 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1849 out_arity = 1 + n_caller_saves;
1851 if (entity != NULL) {
1852 /* TODO: use a generic symconst matcher here
1853 * so we can also handle entity+offset, etc. */
1854 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1857 * - use a proper shifter_operand matcher
1858 * - we could also use LinkLdrPC
1860 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1864 if (incsp != NULL) {
1865 /* IncSP to destroy the call stackframe */
1866 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
1868 /* if we are the last IncSP producer in a block then we have to keep
1870 * Note: This here keeps all producers which is more than necessary */
1871 add_irn_dep(incsp, res);
1874 pmap_insert(node_to_stack, node, incsp);
1877 set_arm_in_req_all(res, in_req);
1879 /* create output register reqs */
1880 arch_set_out_register_req(res, 0, arch_no_register_req);
1881 for (o = 0; o < n_caller_saves; ++o) {
1882 const arch_register_t *reg = caller_saves[o];
1883 arch_set_out_register_req(res, o+1, reg->single_req);
1886 /* copy pinned attribute */
1887 set_irn_pinned(res, get_irn_pinned(node));
1889 arm_free_calling_convention(cconv);
1893 static ir_node *gen_Sel(ir_node *node)
1895 dbg_info *dbgi = get_irn_dbg_info(node);
1896 ir_node *block = get_nodes_block(node);
1897 ir_node *new_block = be_transform_node(block);
1898 ir_node *ptr = get_Sel_ptr(node);
1899 ir_node *new_ptr = be_transform_node(ptr);
1900 ir_entity *entity = get_Sel_entity(node);
1902 /* must be the frame pointer all other sels must have been lowered
1904 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1905 /* we should not have value types from parameters anymore - they should be
1907 assert(get_entity_owner(entity) !=
1908 get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
1910 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1914 * Change some phi modes
1916 static ir_node *gen_Phi(ir_node *node)
1918 const arch_register_req_t *req;
1919 ir_node *block = be_transform_node(get_nodes_block(node));
1920 ir_graph *irg = current_ir_graph;
1921 dbg_info *dbgi = get_irn_dbg_info(node);
1922 ir_mode *mode = get_irn_mode(node);
1925 if (mode_needs_gp_reg(mode)) {
1926 /* we shouldn't have any 64bit stuff around anymore */
1927 assert(get_mode_size_bits(mode) <= 32);
1928 /* all integer operations are on 32bit registers now */
1930 req = arm_reg_classes[CLASS_arm_gp].class_req;
1932 req = arch_no_register_req;
1935 /* phi nodes allow loops, so we use the old arguments for now
1936 * and fix this later */
1937 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
1938 get_irn_in(node) + 1);
1939 copy_node_attr(irg, node, phi);
1940 be_duplicate_deps(node, phi);
1942 arch_set_out_register_req(phi, 0, req);
1944 be_enqueue_preds(node);
1951 * Enters all transform functions into the generic pointer
1953 static void arm_register_transformers(void)
1955 be_start_transform_setup();
1957 be_set_transform_function(op_Add, gen_Add);
1958 be_set_transform_function(op_And, gen_And);
1959 be_set_transform_function(op_Call, gen_Call);
1960 be_set_transform_function(op_Cmp, gen_Cmp);
1961 be_set_transform_function(op_Cond, gen_Cond);
1962 be_set_transform_function(op_Const, gen_Const);
1963 be_set_transform_function(op_Conv, gen_Conv);
1964 be_set_transform_function(op_CopyB, gen_CopyB);
1965 be_set_transform_function(op_Eor, gen_Eor);
1966 be_set_transform_function(op_Jmp, gen_Jmp);
1967 be_set_transform_function(op_Load, gen_Load);
1968 be_set_transform_function(op_Minus, gen_Minus);
1969 be_set_transform_function(op_Mul, gen_Mul);
1970 be_set_transform_function(op_Not, gen_Not);
1971 be_set_transform_function(op_Or, gen_Or);
1972 be_set_transform_function(op_Phi, gen_Phi);
1973 be_set_transform_function(op_Proj, gen_Proj);
1974 be_set_transform_function(op_Quot, gen_Quot);
1975 be_set_transform_function(op_Return, gen_Return);
1976 be_set_transform_function(op_Rotl, gen_Rotl);
1977 be_set_transform_function(op_Sel, gen_Sel);
1978 be_set_transform_function(op_Shl, gen_Shl);
1979 be_set_transform_function(op_Shr, gen_Shr);
1980 be_set_transform_function(op_Shrs, gen_Shrs);
1981 be_set_transform_function(op_Start, gen_Start);
1982 be_set_transform_function(op_Store, gen_Store);
1983 be_set_transform_function(op_Sub, gen_Sub);
1984 be_set_transform_function(op_SymConst, gen_SymConst);
1985 be_set_transform_function(op_Unknown, gen_Unknown);
1989 * Initialize fpa Immediate support.
1991 static void arm_init_fpa_immediate(void)
1993 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
1994 fpa_imm[0][fpa_null] = get_mode_null(mode_F);
1995 fpa_imm[0][fpa_one] = get_mode_one(mode_F);
1996 fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
1997 fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
1998 fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
1999 fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
2000 fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
2001 fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
2003 fpa_imm[1][fpa_null] = get_mode_null(mode_D);
2004 fpa_imm[1][fpa_one] = get_mode_one(mode_D);
2005 fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
2006 fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
2007 fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
2008 fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
2009 fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
2010 fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
2012 fpa_imm[2][fpa_null] = get_mode_null(mode_E);
2013 fpa_imm[2][fpa_one] = get_mode_one(mode_E);
2014 fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
2015 fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
2016 fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
2017 fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
2018 fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
2019 fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
2023 * Transform a Firm graph into an ARM graph.
2025 void arm_transform_graph(arm_code_gen_t *cg)
2027 static int imm_initialized = 0;
2028 ir_graph *irg = cg->irg;
2029 ir_entity *entity = get_irg_entity(irg);
2030 ir_type *frame_type;
2035 if (! imm_initialized) {
2036 arm_init_fpa_immediate();
2037 imm_initialized = 1;
2039 arm_register_transformers();
2042 node_to_stack = pmap_create();
2044 assert(abihelper == NULL);
2045 abihelper = be_abihelper_prepare(irg);
2046 be_collect_stacknodes(abihelper);
2047 assert(cconv == NULL);
2048 cconv = arm_decide_calling_convention(get_entity_type(entity));
2049 create_stacklayout(irg);
2051 be_transform_graph(cg->irg, NULL);
2053 be_abihelper_finish(abihelper);
2056 arm_free_calling_convention(cconv);
2059 frame_type = get_irg_frame_type(irg);
2060 if (get_type_state(frame_type) == layout_undefined) {
2061 default_layout_compound_type(frame_type);
2064 pmap_destroy(node_to_stack);
2065 node_to_stack = NULL;
2067 be_add_missing_keeps(irg);
2070 void arm_init_transform(void)
2072 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");