2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
41 #include "../benode.h"
43 #include "../beutil.h"
44 #include "../betranshlp.h"
45 #include "../beabihelper.h"
48 #include "bearch_arm_t.h"
49 #include "arm_nodes_attr.h"
50 #include "arm_transform.h"
51 #include "arm_optimize.h"
52 #include "arm_new_nodes.h"
53 #include "arm_map_regs.h"
54 #include "arm_cconv.h"
56 #include "gen_arm_regalloc_if.h"
60 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 /** hold the current code generator during transformation */
63 static arm_code_gen_t *env_cg;
65 static const arch_register_t *sp_reg = &arm_gp_regs[REG_SP];
66 static ir_mode *mode_gp;
67 static beabi_helper_env_t *abihelper;
68 static calling_convention_t *cconv = NULL;
70 static pmap *node_to_stack;
72 static bool mode_needs_gp_reg(ir_mode *mode)
74 return mode_is_int(mode) || mode_is_reference(mode);
78 * create firm graph for a constant
80 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
87 /* We only have 8 bit immediates. So we possibly have to combine several
88 * operations to construct the desired value.
90 * we can either create the value by adding bits to 0 or by removing bits
91 * from an register with all bits set. Try which alternative needs fewer
93 arm_gen_vals_from_word(value, &v);
94 arm_gen_vals_from_word(~value, &vn);
98 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
99 be_dep_on_frame(result);
101 for (cnt = 1; cnt < vn.ops; ++cnt) {
102 result = new_bd_arm_Bic_imm(dbgi, block, result,
103 vn.values[cnt], vn.rors[cnt]);
107 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
108 be_dep_on_frame(result);
110 for (cnt = 1; cnt < v.ops; ++cnt) {
111 result = new_bd_arm_Or_imm(dbgi, block, result,
112 v.values[cnt], v.rors[cnt]);
119 * Create a DAG constructing a given Const.
121 * @param irn a Firm const
123 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
125 tarval *tv = get_Const_tarval(irn);
126 ir_mode *mode = get_tarval_mode(tv);
129 if (mode_is_reference(mode)) {
130 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
131 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
132 tv = tarval_convert_to(tv, mode_Iu);
134 value = get_tarval_long(tv);
135 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
139 * Create an And that will zero out upper bits.
141 * @param dbgi debug info
142 * @param block the basic block
143 * @param op the original node
144 * param src_bits number of lower bits that will remain
146 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
150 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
151 } else if (src_bits == 16) {
152 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
153 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
156 panic("zero extension only supported for 8 and 16 bits");
161 * Generate code for a sign extension.
163 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
166 int shift_width = 32 - src_bits;
167 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
168 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
172 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
175 int bits = get_mode_size_bits(orig_mode);
179 if (mode_is_signed(orig_mode)) {
180 return gen_sign_extension(dbgi, block, op, bits);
182 return gen_zero_extension(dbgi, block, op, bits);
187 * returns true if it is assured, that the upper bits of a node are "clean"
188 * which means for a 16 or 8 bit value, that the upper bits in the register
189 * are 0 for unsigned and a copy of the last significant bit for signed
192 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
194 (void) transformed_node;
201 * Transforms a Conv node.
203 * @return The created ia32 Conv node
205 static ir_node *gen_Conv(ir_node *node)
207 ir_node *block = be_transform_node(get_nodes_block(node));
208 ir_node *op = get_Conv_op(node);
209 ir_node *new_op = be_transform_node(op);
210 ir_mode *src_mode = get_irn_mode(op);
211 ir_mode *dst_mode = get_irn_mode(node);
212 dbg_info *dbg = get_irn_dbg_info(node);
214 if (src_mode == dst_mode)
217 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
218 if (USE_FPA(env_cg->isa)) {
219 if (mode_is_float(src_mode)) {
220 if (mode_is_float(dst_mode)) {
221 /* from float to float */
222 return new_bd_arm_fpaMvf(dbg, block, new_op, dst_mode);
224 /* from float to int */
225 return new_bd_arm_fpaFix(dbg, block, new_op, dst_mode);
228 /* from int to float */
229 return new_bd_arm_fpaFlt(dbg, block, new_op, dst_mode);
231 } else if (USE_VFP(env_cg->isa)) {
232 panic("VFP not supported yet");
234 panic("Softfloat not supported yet");
236 } else { /* complete in gp registers */
237 int src_bits = get_mode_size_bits(src_mode);
238 int dst_bits = get_mode_size_bits(dst_mode);
242 if (src_bits == dst_bits) {
243 /* kill unnecessary conv */
247 if (src_bits < dst_bits) {
255 if (upper_bits_clean(new_op, min_mode)) {
259 if (mode_is_signed(min_mode)) {
260 return gen_sign_extension(dbg, block, new_op, min_bits);
262 return gen_zero_extension(dbg, block, new_op, min_bits);
272 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
274 unsigned val, low_pos, high_pos;
279 val = get_tarval_long(get_Const_tarval(node));
291 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
293 So we determine the smallest even position with a bit set
294 and the highest even position with no bit set anymore.
295 If the difference between these 2 is <= 8, then we can encode the value
298 low_pos = ntz(val) & ~1u;
299 high_pos = (32-nlz(val)+1) & ~1u;
301 if (high_pos - low_pos <= 8) {
302 res->imm_8 = val >> low_pos;
303 res->rot = 32 - low_pos;
308 res->rot = 34 - high_pos;
309 val = val >> (32-res->rot) | val << (res->rot);
319 static bool is_downconv(const ir_node *node)
327 /* we only want to skip the conv when we're the only user
328 * (not optimal but for now...)
330 if (get_irn_n_edges(node) > 1)
333 src_mode = get_irn_mode(get_Conv_op(node));
334 dest_mode = get_irn_mode(node);
336 mode_needs_gp_reg(src_mode) &&
337 mode_needs_gp_reg(dest_mode) &&
338 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
341 static ir_node *arm_skip_downconv(ir_node *node)
343 while (is_downconv(node))
344 node = get_Conv_op(node);
350 MATCH_COMMUTATIVE = 1 << 0,
351 MATCH_SIZE_NEUTRAL = 1 << 1,
354 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
355 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
357 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
358 new_binop_reg_func new_reg, new_binop_imm_func new_imm)
360 ir_node *block = be_transform_node(get_nodes_block(node));
361 ir_node *op1 = get_binop_left(node);
363 ir_node *op2 = get_binop_right(node);
365 dbg_info *dbgi = get_irn_dbg_info(node);
368 if (flags & MATCH_SIZE_NEUTRAL) {
369 op1 = arm_skip_downconv(op1);
370 op2 = arm_skip_downconv(op2);
372 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
375 if (try_encode_as_immediate(op2, &imm)) {
376 ir_node *new_op1 = be_transform_node(op1);
377 return new_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
379 new_op2 = be_transform_node(op2);
380 if ((flags & MATCH_COMMUTATIVE) && try_encode_as_immediate(op1, &imm)) {
381 return new_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
383 new_op1 = be_transform_node(op1);
385 return new_reg(dbgi, block, new_op1, new_op2);
389 * Creates an ARM Add.
391 * @return the created arm Add node
393 static ir_node *gen_Add(ir_node *node)
395 ir_mode *mode = get_irn_mode(node);
397 if (mode_is_float(mode)) {
398 ir_node *block = be_transform_node(get_nodes_block(node));
399 ir_node *op1 = get_Add_left(node);
400 ir_node *op2 = get_Add_right(node);
401 dbg_info *dbgi = get_irn_dbg_info(node);
402 ir_node *new_op1 = be_transform_node(op1);
403 ir_node *new_op2 = be_transform_node(op2);
404 if (USE_FPA(env_cg->isa)) {
406 if (is_arm_fpaMvf_i(new_op1))
407 return new_bd_arm_fpaAdf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1));
408 if (is_arm_fpaMvf_i(new_op2))
409 return new_bd_arm_fpaAdf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2));
411 return new_bd_arm_fpaAdf(dbgi, block, new_op1, new_op2, mode);
412 } else if (USE_VFP(env_cg->isa)) {
413 assert(mode != mode_E && "IEEE Extended FP not supported");
414 panic("VFP not supported yet");
416 panic("Softfloat not supported yet");
421 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
423 new_op2 = get_irn_n(new_op1, 1);
424 new_op1 = get_irn_n(new_op1, 0);
426 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
428 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
430 new_op1 = get_irn_n(new_op2, 0);
431 new_op2 = get_irn_n(new_op2, 1);
433 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
437 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
438 new_bd_arm_Add_reg, new_bd_arm_Add_imm);
443 * Creates an ARM Mul.
445 * @return the created arm Mul node
447 static ir_node *gen_Mul(ir_node *node)
449 ir_node *block = be_transform_node(get_nodes_block(node));
450 ir_node *op1 = get_Mul_left(node);
451 ir_node *new_op1 = be_transform_node(op1);
452 ir_node *op2 = get_Mul_right(node);
453 ir_node *new_op2 = be_transform_node(op2);
454 ir_mode *mode = get_irn_mode(node);
455 dbg_info *dbg = get_irn_dbg_info(node);
457 if (mode_is_float(mode)) {
458 if (USE_FPA(env_cg->isa)) {
460 if (is_arm_Mov_i(new_op1))
461 return new_bd_arm_fpaMuf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
462 if (is_arm_Mov_i(new_op2))
463 return new_bd_arm_fpaMuf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
465 return new_bd_arm_fpaMuf(dbg, block, new_op1, new_op2, mode);
466 } else if (USE_VFP(env_cg->isa)) {
467 assert(mode != mode_E && "IEEE Extended FP not supported");
468 panic("VFP not supported yet");
470 panic("Softfloat not supported yet");
473 assert(mode_is_data(mode));
474 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
477 static ir_node *gen_Quot(ir_node *node)
479 ir_node *block = be_transform_node(get_nodes_block(node));
480 ir_node *op1 = get_Quot_left(node);
481 ir_node *new_op1 = be_transform_node(op1);
482 ir_node *op2 = get_Quot_right(node);
483 ir_node *new_op2 = be_transform_node(op2);
484 ir_mode *mode = get_irn_mode(node);
485 dbg_info *dbg = get_irn_dbg_info(node);
487 assert(mode != mode_E && "IEEE Extended FP not supported");
489 if (USE_FPA(env_cg->isa)) {
491 if (is_arm_Mov_i(new_op1))
492 return new_bd_arm_fpaRdf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
493 if (is_arm_Mov_i(new_op2))
494 return new_bd_arm_fpaDvf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
496 return new_bd_arm_fpaDvf(dbg, block, new_op1, new_op2, mode);
497 } else if (USE_VFP(env_cg->isa)) {
498 assert(mode != mode_E && "IEEE Extended FP not supported");
499 panic("VFP not supported yet");
501 panic("Softfloat not supported yet");
505 static ir_node *gen_And(ir_node *node)
507 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
508 new_bd_arm_And_reg, new_bd_arm_And_imm);
511 static ir_node *gen_Or(ir_node *node)
513 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
514 new_bd_arm_Or_reg, new_bd_arm_Or_imm);
517 static ir_node *gen_Eor(ir_node *node)
519 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
520 new_bd_arm_Eor_reg, new_bd_arm_Eor_imm);
523 static ir_node *gen_Sub(ir_node *node)
525 ir_node *block = be_transform_node(get_nodes_block(node));
526 ir_node *op1 = get_Sub_left(node);
527 ir_node *new_op1 = be_transform_node(op1);
528 ir_node *op2 = get_Sub_right(node);
529 ir_node *new_op2 = be_transform_node(op2);
530 ir_mode *mode = get_irn_mode(node);
531 dbg_info *dbgi = get_irn_dbg_info(node);
533 if (mode_is_float(mode)) {
534 if (USE_FPA(env_cg->isa)) {
536 if (is_arm_Mov_i(new_op1))
537 return new_bd_arm_fpaRsf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1));
538 if (is_arm_Mov_i(new_op2))
539 return new_bd_arm_fpaSuf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2));
541 return new_bd_arm_fpaSuf(dbgi, block, new_op1, new_op2, mode);
542 } else if (USE_VFP(env_cg->isa)) {
543 assert(mode != mode_E && "IEEE Extended FP not supported");
544 panic("VFP not supported yet");
546 panic("Softfloat not supported yet");
549 return gen_int_binop(node, MATCH_SIZE_NEUTRAL,
550 new_bd_arm_Sub_reg, new_bd_arm_Sub_imm);
555 * Checks if a given value can be used as an immediate for the given
558 static bool can_use_shift_constant(unsigned int val,
559 arm_shift_modifier_t modifier)
563 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
569 * generate an ARM shift instruction.
571 * @param node the node
572 * @param flags matching flags
573 * @param shift_modifier initial encoding of the desired shift operation
575 static ir_node *make_shift(ir_node *node, match_flags_t flags,
576 arm_shift_modifier_t shift_modifier)
578 ir_node *block = be_transform_node(get_nodes_block(node));
579 ir_node *op1 = get_binop_left(node);
580 ir_node *op2 = get_binop_right(node);
581 dbg_info *dbgi = get_irn_dbg_info(node);
585 if (flags & MATCH_SIZE_NEUTRAL) {
586 op1 = arm_skip_downconv(op1);
587 op2 = arm_skip_downconv(op2);
590 new_op1 = be_transform_node(op1);
592 tarval *tv = get_Const_tarval(op2);
593 unsigned int val = get_tarval_long(tv);
594 assert(tarval_is_long(tv));
595 if (can_use_shift_constant(val, shift_modifier)) {
596 switch (shift_modifier) {
597 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
598 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
599 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
600 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
601 default: panic("unexpected shift modifier");
603 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
604 shift_modifier, val);
608 new_op2 = be_transform_node(op2);
609 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
613 static ir_node *gen_Shl(ir_node *node)
615 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
618 static ir_node *gen_Shr(ir_node *node)
620 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
623 static ir_node *gen_Shrs(ir_node *node)
625 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
628 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
630 ir_node *block = be_transform_node(get_nodes_block(node));
631 ir_node *new_op1 = be_transform_node(op1);
632 dbg_info *dbgi = get_irn_dbg_info(node);
633 ir_node *new_op2 = be_transform_node(op2);
635 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
639 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
641 ir_node *block = be_transform_node(get_nodes_block(node));
642 ir_node *new_op1 = be_transform_node(op1);
643 dbg_info *dbgi = get_irn_dbg_info(node);
644 ir_node *new_op2 = be_transform_node(op2);
646 /* Note: there is no Rol on arm, we have to use Ror */
647 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
648 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
652 static ir_node *gen_Rotl(ir_node *node)
654 ir_node *rotate = NULL;
655 ir_node *op1 = get_Rotl_left(node);
656 ir_node *op2 = get_Rotl_right(node);
658 /* Firm has only RotL, so we are looking for a right (op2)
659 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
660 that means we can create a RotR. */
663 ir_node *right = get_Add_right(op2);
664 if (is_Const(right)) {
665 tarval *tv = get_Const_tarval(right);
666 ir_mode *mode = get_irn_mode(node);
667 long bits = get_mode_size_bits(mode);
668 ir_node *left = get_Add_left(op2);
670 if (is_Minus(left) &&
671 tarval_is_long(tv) &&
672 get_tarval_long(tv) == bits &&
674 rotate = gen_Ror(node, op1, get_Minus_op(left));
676 } else if (is_Sub(op2)) {
677 ir_node *left = get_Sub_left(op2);
678 if (is_Const(left)) {
679 tarval *tv = get_Const_tarval(left);
680 ir_mode *mode = get_irn_mode(node);
681 long bits = get_mode_size_bits(mode);
682 ir_node *right = get_Sub_right(op2);
684 if (tarval_is_long(tv) &&
685 get_tarval_long(tv) == bits &&
687 rotate = gen_Ror(node, op1, right);
689 } else if (is_Const(op2)) {
690 tarval *tv = get_Const_tarval(op2);
691 ir_mode *mode = get_irn_mode(node);
692 long bits = get_mode_size_bits(mode);
694 if (tarval_is_long(tv) && bits == 32) {
695 ir_node *block = be_transform_node(get_nodes_block(node));
696 ir_node *new_op1 = be_transform_node(op1);
697 dbg_info *dbgi = get_irn_dbg_info(node);
699 bits = (bits - get_tarval_long(tv)) & 31;
700 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
704 if (rotate == NULL) {
705 rotate = gen_Rol(node, op1, op2);
711 static ir_node *gen_Not(ir_node *node)
713 ir_node *block = be_transform_node(get_nodes_block(node));
714 ir_node *op = get_Not_op(node);
715 ir_node *new_op = be_transform_node(op);
716 dbg_info *dbgi = get_irn_dbg_info(node);
718 /* TODO: we could do alot more here with all the Mvn variations */
720 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
723 static ir_node *gen_Abs(ir_node *node)
725 ir_node *block = be_transform_node(get_nodes_block(node));
726 ir_node *op = get_Abs_op(node);
727 ir_node *new_op = be_transform_node(op);
728 dbg_info *dbgi = get_irn_dbg_info(node);
729 ir_mode *mode = get_irn_mode(node);
731 if (mode_is_float(mode)) {
732 if (USE_FPA(env_cg->isa)) {
733 return new_bd_arm_fpaAbs(dbgi, block, new_op, mode);
734 } else if (USE_VFP(env_cg->isa)) {
735 assert(mode != mode_E && "IEEE Extended FP not supported");
736 panic("VFP not supported yet");
738 panic("Softfloat not supported yet");
741 assert(mode_is_data(mode));
742 return new_bd_arm_Abs(dbgi, block, new_op);
745 static ir_node *gen_Minus(ir_node *node)
747 ir_node *block = be_transform_node(get_nodes_block(node));
748 ir_node *op = get_Minus_op(node);
749 ir_node *new_op = be_transform_node(op);
750 dbg_info *dbgi = get_irn_dbg_info(node);
751 ir_mode *mode = get_irn_mode(node);
753 if (mode_is_float(mode)) {
754 if (USE_FPA(env_cg->isa)) {
755 return new_bd_arm_fpaMvf(dbgi, block, op, mode);
756 } else if (USE_VFP(env_cg->isa)) {
757 assert(mode != mode_E && "IEEE Extended FP not supported");
758 panic("VFP not supported yet");
760 panic("Softfloat not supported yet");
763 assert(mode_is_data(mode));
764 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
767 static ir_node *gen_Load(ir_node *node)
769 ir_node *block = be_transform_node(get_nodes_block(node));
770 ir_node *ptr = get_Load_ptr(node);
771 ir_node *new_ptr = be_transform_node(ptr);
772 ir_node *mem = get_Load_mem(node);
773 ir_node *new_mem = be_transform_node(mem);
774 ir_mode *mode = get_Load_mode(node);
775 dbg_info *dbgi = get_irn_dbg_info(node);
776 ir_node *new_load = NULL;
778 if (mode_is_float(mode)) {
779 if (USE_FPA(env_cg->isa)) {
780 new_load = new_bd_arm_fpaLdf(dbgi, block, new_ptr, new_mem, mode);
781 } else if (USE_VFP(env_cg->isa)) {
782 assert(mode != mode_E && "IEEE Extended FP not supported");
783 panic("VFP not supported yet");
785 panic("Softfloat not supported yet");
788 assert(mode_is_data(mode) && "unsupported mode for Load");
790 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
792 set_irn_pinned(new_load, get_irn_pinned(node));
794 /* check for special case: the loaded value might not be used */
795 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
796 /* add a result proj and a Keep to produce a pseudo use */
797 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
798 be_new_Keep(block, 1, &proj);
804 static ir_node *gen_Store(ir_node *node)
806 ir_node *block = be_transform_node(get_nodes_block(node));
807 ir_node *ptr = get_Store_ptr(node);
808 ir_node *new_ptr = be_transform_node(ptr);
809 ir_node *mem = get_Store_mem(node);
810 ir_node *new_mem = be_transform_node(mem);
811 ir_node *val = get_Store_value(node);
812 ir_node *new_val = be_transform_node(val);
813 ir_mode *mode = get_irn_mode(val);
814 dbg_info *dbgi = get_irn_dbg_info(node);
815 ir_node *new_store = NULL;
817 if (mode_is_float(mode)) {
818 if (USE_FPA(env_cg->isa)) {
819 new_store = new_bd_arm_fpaStf(dbgi, block, new_ptr, new_val,
821 } else if (USE_VFP(env_cg->isa)) {
822 assert(mode != mode_E && "IEEE Extended FP not supported");
823 panic("VFP not supported yet");
825 panic("Softfloat not supported yet");
828 assert(mode_is_data(mode) && "unsupported mode for Store");
829 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
832 set_irn_pinned(new_store, get_irn_pinned(node));
836 static ir_node *gen_Jmp(ir_node *node)
838 ir_node *block = get_nodes_block(node);
839 ir_node *new_block = be_transform_node(block);
840 dbg_info *dbgi = get_irn_dbg_info(node);
842 return new_bd_arm_Jmp(dbgi, new_block);
845 static ir_node *gen_SwitchJmp(ir_node *node)
847 ir_node *block = be_transform_node(get_nodes_block(node));
848 ir_node *selector = get_Cond_selector(node);
849 dbg_info *dbgi = get_irn_dbg_info(node);
850 ir_node *new_op = be_transform_node(selector);
851 ir_node *const_graph;
855 const ir_edge_t *edge;
862 foreach_out_edge(node, edge) {
863 proj = get_edge_src_irn(edge);
864 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
866 pn = get_Proj_proj(proj);
868 min = pn<min ? pn : min;
869 max = pn>max ? pn : max;
872 n_projs = max - translation + 1;
874 foreach_out_edge(node, edge) {
875 proj = get_edge_src_irn(edge);
876 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
878 pn = get_Proj_proj(proj) - translation;
879 set_Proj_proj(proj, pn);
882 const_graph = create_const_graph_value(dbgi, block, translation);
883 sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
884 return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
887 static ir_node *gen_Cmp(ir_node *node)
889 ir_node *block = be_transform_node(get_nodes_block(node));
890 ir_node *op1 = get_Cmp_left(node);
891 ir_node *op2 = get_Cmp_right(node);
892 ir_mode *cmp_mode = get_irn_mode(op1);
893 dbg_info *dbgi = get_irn_dbg_info(node);
898 if (mode_is_float(cmp_mode)) {
899 /* TODO: this is broken... */
900 new_op1 = be_transform_node(op1);
901 new_op2 = be_transform_node(op2);
903 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
905 panic("FloatCmp NIY");
907 ir_node *new_op2 = be_transform_node(op2);
908 /* floating point compare */
909 pn_Cmp pnc = get_Proj_proj(selector);
911 if (pnc & pn_Cmp_Uo) {
912 /* check for unordered, need cmf */
913 return new_bd_arm_fpaCmfBra(dbgi, block, new_op1, new_op2, pnc);
915 /* Hmm: use need cmfe */
916 return new_bd_arm_fpaCmfeBra(dbgi, block, new_op1, new_op2, pnc);
920 assert(get_irn_mode(op2) == cmp_mode);
921 is_unsigned = !mode_is_signed(cmp_mode);
923 /* compare with 0 can be done with Tst */
924 if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) {
925 new_op1 = be_transform_node(op1);
926 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
927 return new_bd_arm_Tst_reg(dbgi, block, new_op1, new_op1, false,
930 if (is_Const(op1) && tarval_is_null(get_Const_tarval(op1))) {
931 new_op2 = be_transform_node(op2);
932 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
933 return new_bd_arm_Tst_reg(dbgi, block, new_op2, new_op2, true,
937 /* integer compare, TODO: use shifter_op in all its combinations */
938 new_op1 = be_transform_node(op1);
939 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
940 new_op2 = be_transform_node(op2);
941 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
942 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
946 static ir_node *gen_Cond(ir_node *node)
948 ir_node *selector = get_Cond_selector(node);
949 ir_mode *mode = get_irn_mode(selector);
954 if (mode != mode_b) {
955 return gen_SwitchJmp(node);
957 assert(is_Proj(selector));
959 block = be_transform_node(get_nodes_block(node));
960 dbgi = get_irn_dbg_info(node);
961 flag_node = be_transform_node(get_Proj_pred(selector));
963 return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector));
966 static tarval *fpa_imm[3][fpa_max];
970 * Check, if a floating point tarval is an fpa immediate, i.e.
971 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
973 static int is_fpa_immediate(tarval *tv)
975 ir_mode *mode = get_tarval_mode(tv);
978 switch (get_mode_size_bits(mode)) {
989 if (tarval_is_negative(tv)) {
994 for (j = 0; j < fpa_max; ++j) {
995 if (tv == fpa_imm[i][j])
1002 static ir_node *gen_Const(ir_node *node)
1004 ir_node *block = be_transform_node(get_nodes_block(node));
1005 ir_mode *mode = get_irn_mode(node);
1006 dbg_info *dbg = get_irn_dbg_info(node);
1008 if (mode_is_float(mode)) {
1009 if (USE_FPA(env_cg->isa)) {
1010 tarval *tv = get_Const_tarval(node);
1012 int imm = is_fpa_immediate(tv);
1014 if (imm != fpa_max) {
1016 node = new_bd_arm_fpaMvf_i(dbg, block, mode, imm);
1018 node = new_bd_arm_fpaMnf_i(dbg, block, mode, -imm);
1023 node = new_bd_arm_fpaConst(dbg, block, tv);
1025 be_dep_on_frame(node);
1027 } else if (USE_VFP(env_cg->isa)) {
1028 assert(mode != mode_E && "IEEE Extended FP not supported");
1029 panic("VFP not supported yet");
1031 panic("Softfloat not supported yet");
1034 return create_const_graph(node, block);
1037 static ir_node *gen_SymConst(ir_node *node)
1039 ir_node *block = be_transform_node(get_nodes_block(node));
1040 ir_entity *entity = get_SymConst_entity(node);
1041 dbg_info *dbgi = get_irn_dbg_info(node);
1044 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
1045 be_dep_on_frame(new_node);
1049 static ir_node *gen_CopyB(ir_node *node)
1051 ir_node *block = be_transform_node(get_nodes_block(node));
1052 ir_node *src = get_CopyB_src(node);
1053 ir_node *new_src = be_transform_node(src);
1054 ir_node *dst = get_CopyB_dst(node);
1055 ir_node *new_dst = be_transform_node(dst);
1056 ir_node *mem = get_CopyB_mem(node);
1057 ir_node *new_mem = be_transform_node(mem);
1058 dbg_info *dbg = get_irn_dbg_info(node);
1059 int size = get_type_size_bytes(get_CopyB_type(node));
1063 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
1064 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
1066 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1067 new_bd_arm_EmptyReg(dbg, block),
1068 new_bd_arm_EmptyReg(dbg, block),
1069 new_bd_arm_EmptyReg(dbg, block),
1073 static ir_node *gen_Proj_Load(ir_node *node)
1075 ir_node *load = get_Proj_pred(node);
1076 ir_node *new_load = be_transform_node(load);
1077 dbg_info *dbgi = get_irn_dbg_info(node);
1078 long proj = get_Proj_proj(node);
1080 /* renumber the proj */
1081 switch (get_arm_irn_opcode(new_load)) {
1083 /* handle all gp loads equal: they have the same proj numbers. */
1084 if (proj == pn_Load_res) {
1085 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1086 } else if (proj == pn_Load_M) {
1087 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1090 case iro_arm_fpaLdf:
1091 if (proj == pn_Load_res) {
1092 ir_mode *mode = get_Load_mode(load);
1093 return new_rd_Proj(dbgi, new_load, mode, pn_arm_fpaLdf_res);
1094 } else if (proj == pn_Load_M) {
1095 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_fpaLdf_M);
1101 panic("Unsupported Proj from Load");
1104 static ir_node *gen_Proj_CopyB(ir_node *node)
1106 ir_node *pred = get_Proj_pred(node);
1107 ir_node *new_pred = be_transform_node(pred);
1108 dbg_info *dbgi = get_irn_dbg_info(node);
1109 long proj = get_Proj_proj(node);
1113 if (is_arm_CopyB(new_pred)) {
1114 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1120 panic("Unsupported Proj from CopyB");
1123 static ir_node *gen_Proj_Quot(ir_node *node)
1125 ir_node *pred = get_Proj_pred(node);
1126 ir_node *new_pred = be_transform_node(pred);
1127 dbg_info *dbgi = get_irn_dbg_info(node);
1128 ir_mode *mode = get_irn_mode(node);
1129 long proj = get_Proj_proj(node);
1133 if (is_arm_fpaDvf(new_pred)) {
1134 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaDvf_M);
1135 } else if (is_arm_fpaRdf(new_pred)) {
1136 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaRdf_M);
1137 } else if (is_arm_fpaFdv(new_pred)) {
1138 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaFdv_M);
1139 } else if (is_arm_fpaFrd(new_pred)) {
1140 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaFrd_M);
1144 if (is_arm_fpaDvf(new_pred)) {
1145 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaDvf_res);
1146 } else if (is_arm_fpaRdf(new_pred)) {
1147 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaRdf_res);
1148 } else if (is_arm_fpaFdv(new_pred)) {
1149 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaFdv_res);
1150 } else if (is_arm_fpaFrd(new_pred)) {
1151 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaFrd_res);
1157 panic("Unsupported Proj from Quot");
1161 * Transform the Projs from a Cmp.
1163 static ir_node *gen_Proj_Cmp(ir_node *node)
1166 /* we should only be here in case of a Mux node */
1170 static ir_node *gen_Proj_Start(ir_node *node)
1172 ir_node *block = get_nodes_block(node);
1173 ir_node *new_block = be_transform_node(block);
1174 ir_node *barrier = be_transform_node(get_Proj_pred(node));
1175 long proj = get_Proj_proj(node);
1177 switch ((pn_Start) proj) {
1178 case pn_Start_X_initial_exec:
1179 /* we exchange the ProjX with a jump */
1180 return new_bd_arm_Jmp(NULL, new_block);
1183 return new_r_Proj(barrier, mode_M, 0);
1185 case pn_Start_T_args:
1188 case pn_Start_P_frame_base:
1189 return be_prolog_get_reg_value(abihelper, sp_reg);
1191 case pn_Start_P_tls:
1192 return new_bd_arm_LdTls(NULL, new_block);
1197 panic("unexpected start proj: %ld\n", proj);
1200 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1202 long pn = get_Proj_proj(node);
1203 const reg_or_stackslot_t *param;
1205 /* Proj->Proj->Start must be a method argument */
1206 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1208 param = &cconv->parameters[pn];
1210 if (param->reg0 != NULL) {
1211 /* argument transmitted in register */
1212 return be_prolog_get_reg_value(abihelper, param->reg0);
1214 /* argument transmitted on stack */
1215 ir_graph *irg = get_irn_irg(node);
1216 ir_node *block = get_nodes_block(node);
1217 ir_node *new_block = be_transform_node(block);
1218 ir_node *fp = get_irg_frame(irg);
1219 ir_node *mem = be_prolog_get_memory(abihelper);
1220 ir_mode *mode = get_type_mode(param->type);
1221 ir_node *load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1222 param->entity, 0, 0, true);
1223 ir_node *value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1224 set_irn_pinned(load, op_pin_state_floats);
1231 * Finds number of output value of a mode_T node which is constrained to
1232 * a single specific register.
1234 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1236 int n_outs = arch_irn_get_n_outs(node);
1239 for (o = 0; o < n_outs; ++o) {
1240 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1241 if (req == reg->single_req)
1247 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1249 long pn = get_Proj_proj(node);
1250 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1251 ir_node *new_call = be_transform_node(call);
1252 ir_type *function_type = get_Call_type(call);
1253 calling_convention_t *cconv = decide_calling_convention(function_type);
1254 const reg_or_stackslot_t *res = &cconv->results[pn];
1258 /* TODO 64bit modes */
1259 assert(res->reg0 != NULL && res->reg1 == NULL);
1260 regn = find_out_for_reg(new_call, res->reg0);
1262 panic("Internal error in calling convention for return %+F", node);
1264 mode = res->reg0->reg_class->mode;
1266 free_calling_convention(cconv);
1268 return new_r_Proj(new_call, mode, regn);
1271 static ir_node *gen_Proj_Call(ir_node *node)
1273 long pn = get_Proj_proj(node);
1274 ir_node *call = get_Proj_pred(node);
1275 ir_node *new_call = be_transform_node(call);
1277 switch ((pn_Call) pn) {
1279 return new_r_Proj(new_call, mode_M, 0);
1280 case pn_Call_X_regular:
1281 case pn_Call_X_except:
1282 case pn_Call_T_result:
1283 case pn_Call_P_value_res_base:
1287 panic("Unexpected Call proj %ld\n", pn);
1291 * Transform a Proj node.
1293 static ir_node *gen_Proj(ir_node *node)
1295 ir_node *pred = get_Proj_pred(node);
1296 long proj = get_Proj_proj(node);
1298 switch (get_irn_opcode(pred)) {
1300 if (proj == pn_Store_M) {
1301 return be_transform_node(pred);
1303 panic("Unsupported Proj from Store");
1306 return gen_Proj_Load(node);
1308 return gen_Proj_Call(node);
1310 return gen_Proj_CopyB(node);
1312 return gen_Proj_Quot(node);
1314 return gen_Proj_Cmp(node);
1316 return gen_Proj_Start(node);
1319 return be_duplicate_node(node);
1321 ir_node *pred_pred = get_Proj_pred(pred);
1322 if (is_Call(pred_pred)) {
1323 return gen_Proj_Proj_Call(node);
1324 } else if (is_Start(pred_pred)) {
1325 return gen_Proj_Proj_Start(node);
1330 panic("code selection didn't expect Proj after %+F\n", pred);
1334 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1336 static inline ir_node *create_const(ir_node **place,
1337 create_const_node_func func,
1338 const arch_register_t* reg)
1340 ir_node *block, *res;
1345 block = get_irg_start_block(env_cg->irg);
1346 res = func(NULL, block);
1347 arch_set_irn_register(res, reg);
1352 static ir_node *gen_Unknown(ir_node *node)
1354 ir_node *block = get_nodes_block(node);
1355 ir_node *new_block = be_transform_node(block);
1356 dbg_info *dbgi = get_irn_dbg_info(node);
1358 /* just produce a 0 */
1359 ir_mode *mode = get_irn_mode(node);
1360 if (mode_is_float(mode)) {
1361 tarval *tv = get_mode_null(mode);
1362 ir_node *node = new_bd_arm_fpaConst(dbgi, new_block, tv);
1363 be_dep_on_frame(node);
1365 } else if (mode_needs_gp_reg(mode)) {
1366 return create_const_graph_value(dbgi, new_block, 0);
1369 panic("Unexpected Unknown mode");
1373 * Produces the type which sits between the stack args and the locals on the
1374 * stack. It will contain the return address and space to store the old base
1376 * @return The Firm type modeling the ABI between type.
1378 static ir_type *arm_get_between_type(void)
1380 static ir_type *between_type = NULL;
1382 if (between_type == NULL) {
1383 between_type = new_type_class(new_id_from_str("arm_between_type"));
1384 set_type_size_bytes(between_type, 0);
1387 return between_type;
1390 static void create_stacklayout(ir_graph *irg)
1392 ir_entity *entity = get_irg_entity(irg);
1393 ir_type *function_type = get_entity_type(entity);
1394 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1399 /* calling conventions must be decided by now */
1400 assert(cconv != NULL);
1402 /* construct argument type */
1403 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1404 n_params = get_method_n_params(function_type);
1405 for (p = 0; p < n_params; ++p) {
1406 reg_or_stackslot_t *param = &cconv->parameters[p];
1410 if (param->type == NULL)
1413 snprintf(buf, sizeof(buf), "param_%d", p);
1414 id = new_id_from_str(buf);
1415 param->entity = new_entity(arg_type, id, param->type);
1416 set_entity_offset(param->entity, param->offset);
1419 /* TODO: what about external functions? we don't know most of the stack
1420 * layout for them. And probably don't need all of this... */
1421 memset(layout, 0, sizeof(*layout));
1423 layout->frame_type = get_irg_frame_type(irg);
1424 layout->between_type = arm_get_between_type();
1425 layout->arg_type = arg_type;
1426 layout->param_map = NULL; /* TODO */
1427 layout->initial_offset = 0;
1428 layout->initial_bias = 0;
1429 layout->stack_dir = -1;
1430 layout->sp_relative = true;
1432 assert(N_FRAME_TYPES == 3);
1433 layout->order[0] = layout->frame_type;
1434 layout->order[1] = layout->between_type;
1435 layout->order[2] = layout->arg_type;
1439 * transform the start node to the prolog code + initial barrier
1441 static ir_node *gen_Start(ir_node *node)
1443 ir_graph *irg = get_irn_irg(node);
1444 ir_entity *entity = get_irg_entity(irg);
1445 ir_type *function_type = get_entity_type(entity);
1446 ir_node *block = get_nodes_block(node);
1447 ir_node *new_block = be_transform_node(block);
1448 dbg_info *dbgi = get_irn_dbg_info(node);
1455 /* stackpointer is important at function prolog */
1456 be_prolog_add_reg(abihelper, sp_reg,
1457 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1458 /* function parameters in registers */
1459 for (i = 0; i < get_method_n_params(function_type); ++i) {
1460 const reg_or_stackslot_t *param = &cconv->parameters[i];
1461 if (param->reg0 != NULL)
1462 be_prolog_add_reg(abihelper, param->reg0, 0);
1463 if (param->reg1 != NULL)
1464 be_prolog_add_reg(abihelper, param->reg1, 0);
1466 /* announce that we need the values of the callee save regs */
1467 for (i = 0; i < (int) (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
1468 be_prolog_add_reg(abihelper, callee_saves[i], 0);
1471 start = be_prolog_create_start(abihelper, dbgi, new_block);
1472 sp = be_prolog_get_reg_value(abihelper, sp_reg);
1473 incsp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
1474 be_prolog_set_reg_value(abihelper, sp_reg, incsp);
1475 barrier = be_prolog_create_barrier(abihelper, new_block);
1480 static ir_node *get_stack_pointer_for(ir_node *node)
1482 /* get predecessor in stack_order list */
1483 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1484 ir_node *stack_pred_transformed;
1487 if (stack_pred == NULL) {
1488 /* first stack user in the current block. We can simply use the
1489 * initial sp_proj for it */
1490 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1494 stack_pred_transformed = be_transform_node(stack_pred);
1495 stack = pmap_get(node_to_stack, stack_pred);
1496 if (stack == NULL) {
1497 return get_stack_pointer_for(stack_pred);
1504 * transform a Return node into epilogue code + return statement
1506 static ir_node *gen_Return(ir_node *node)
1508 ir_node *block = get_nodes_block(node);
1509 ir_node *new_block = be_transform_node(block);
1510 dbg_info *dbgi = get_irn_dbg_info(node);
1511 ir_node *mem = get_Return_mem(node);
1512 ir_node *new_mem = be_transform_node(mem);
1513 int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
1514 ir_node *sp_proj = get_stack_pointer_for(node);
1519 const arch_register_t *const result_regs[] = {
1520 &arm_gp_regs[REG_R0],
1521 &arm_gp_regs[REG_R1]
1524 be_epilog_begin(abihelper);
1525 be_epilog_set_memory(abihelper, new_mem);
1526 /* connect stack pointer with initial stack pointer. fix_stack phase
1527 will later serialize all stack pointer adjusting nodes */
1528 be_epilog_add_reg(abihelper, sp_reg,
1529 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1533 n_res = get_Return_n_ress(node);
1534 if (n_res > (int) (sizeof(result_regs)/sizeof(result_regs[0]))) {
1535 panic("Too many return values for arm backend (%+F)", node);
1537 for (i = 0; i < n_res; ++i) {
1538 ir_node *res_value = get_Return_res(node, i);
1539 ir_node *new_res_value = be_transform_node(res_value);
1540 const arch_register_t *reg = result_regs[i];
1541 be_epilog_add_reg(abihelper, reg, 0, new_res_value);
1544 /* connect callee saves with their values at the function begin */
1545 for (i = 0; i < n_callee_saves; ++i) {
1546 const arch_register_t *reg = callee_saves[i];
1547 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1548 be_epilog_add_reg(abihelper, reg, 0, value);
1551 /* create the barrier before the epilog code */
1552 be_epilog_create_barrier(abihelper, new_block);
1554 /* epilog code: an incsp */
1555 sp_proj = be_epilog_get_reg_value(abihelper, sp_reg);
1556 incsp = be_new_IncSP(sp_reg, new_block, sp_proj,
1557 BE_STACK_FRAME_SIZE_SHRINK, 0);
1558 be_epilog_set_reg_value(abihelper, sp_reg, incsp);
1560 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1566 static ir_node *gen_Call(ir_node *node)
1568 ir_graph *irg = get_irn_irg(node);
1569 ir_node *callee = get_Call_ptr(node);
1570 ir_node *block = get_nodes_block(node);
1571 ir_node *new_block = be_transform_node(block);
1572 ir_node *mem = get_Call_mem(node);
1573 ir_node *new_mem = be_transform_node(mem);
1574 dbg_info *dbgi = get_irn_dbg_info(node);
1575 ir_type *type = get_Call_type(node);
1576 calling_convention_t *cconv = decide_calling_convention(type);
1577 int n_params = get_Call_n_params(node);
1578 int n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
1579 /* max inputs: memory, callee, register arguments */
1580 int max_inputs = 2 + n_param_regs;
1581 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1582 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1583 struct obstack *obst = be_get_be_obst(irg);
1584 const arch_register_req_t **in_req
1585 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1589 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1590 ir_entity *entity = NULL;
1591 ir_node *incsp = NULL;
1598 assert(n_params == get_method_n_params(type));
1600 /* construct arguments */
1603 in_req[in_arity] = arch_no_register_req;
1607 for (p = 0; p < n_params; ++p) {
1608 ir_node *value = get_Call_param(node, p);
1609 ir_node *new_value = be_transform_node(value);
1610 const reg_or_stackslot_t *param = &cconv->parameters[p];
1611 const arch_register_t *reg = param->reg0;
1613 /* double not implemented yet */
1614 assert(get_mode_size_bits(get_irn_mode(value)) <= 32);
1615 assert(param->reg1 == NULL);
1618 in[in_arity] = new_value;
1619 /* this should not happen, LR cannot be a parameter register ... */
1620 assert(reg != &arm_gp_regs[REG_LR]);
1621 in_req[in_arity] = reg->single_req;
1626 if (incsp == NULL) {
1627 /* create a parameter frame */
1628 ir_node *new_frame = get_stack_pointer_for(node);
1629 incsp = be_new_IncSP(sp_reg, new_block, new_frame, cconv->param_stack_size, 1);
1631 mode = get_irn_mode(value);
1632 str = new_bd_arm_Str(dbgi, new_block, incsp, value, new_mem, mode,
1633 NULL, 0, param->offset, true);
1635 sync_ins[sync_arity++] = str;
1638 assert(in_arity <= max_inputs);
1640 /* construct memory input */
1641 if (sync_arity == 0) {
1642 in[mem_pos] = new_mem;
1643 } else if (sync_arity == 1) {
1644 in[mem_pos] = sync_ins[0];
1646 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1649 /* TODO: use a generic symconst matcher here */
1650 if (is_SymConst(callee)) {
1651 entity = get_SymConst_entity(callee);
1653 /* TODO: finish load matcher here */
1656 if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) {
1657 ir_node *load = get_Proj_pred(callee);
1658 ir_node *ptr = get_Load_ptr(load);
1659 ir_node *new_ptr = be_transform_node(ptr);
1660 ir_node *mem = get_Load_mem(load);
1661 ir_node *new_mem = be_transform_node(mem);
1662 ir_mode *mode = get_Load_mode(node);
1666 in[in_arity] = be_transform_node(callee);
1667 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1676 out_arity = 1 + n_caller_saves;
1678 if (entity != NULL) {
1679 /* TODO: use a generic symconst matcher here
1680 * so we can also handle entity+offset, etc. */
1681 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1684 * - use a proper shifter_operand matcher
1685 * - we could also use LinkLdrPC
1687 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1691 if (incsp != NULL) {
1692 /* IncSP to destroy the call stackframe */
1693 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
1695 /* if we are the last IncSP producer in a block then we have to keep
1697 * Note: This here keeps all producers which is more than necessary */
1698 add_irn_dep(incsp, res);
1701 pmap_insert(node_to_stack, node, incsp);
1704 set_arm_in_req_all(res, in_req);
1706 /* create output register reqs */
1707 arch_set_out_register_req(res, 0, arch_no_register_req);
1708 for (o = 0; o < n_caller_saves; ++o) {
1709 const arch_register_t *reg = caller_saves[o];
1710 arch_set_out_register_req(res, o+1, reg->single_req);
1713 /* copy pinned attribute */
1714 set_irn_pinned(res, get_irn_pinned(node));
1716 free_calling_convention(cconv);
1720 static ir_node *gen_Sel(ir_node *node)
1722 dbg_info *dbgi = get_irn_dbg_info(node);
1723 ir_node *block = get_nodes_block(node);
1724 ir_node *new_block = be_transform_node(block);
1725 ir_node *ptr = get_Sel_ptr(node);
1726 ir_node *new_ptr = be_transform_node(ptr);
1727 ir_entity *entity = get_Sel_entity(node);
1729 /* must be the frame pointer all other sels must have been lowered
1731 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1732 /* we should not have value types from parameters anymore - they should be
1734 assert(get_entity_owner(entity) !=
1735 get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
1737 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1741 * Change some phi modes
1743 static ir_node *gen_Phi(ir_node *node)
1745 const arch_register_req_t *req;
1746 ir_node *block = be_transform_node(get_nodes_block(node));
1747 ir_graph *irg = current_ir_graph;
1748 dbg_info *dbgi = get_irn_dbg_info(node);
1749 ir_mode *mode = get_irn_mode(node);
1752 if (mode_needs_gp_reg(mode)) {
1753 /* we shouldn't have any 64bit stuff around anymore */
1754 assert(get_mode_size_bits(mode) <= 32);
1755 /* all integer operations are on 32bit registers now */
1757 req = arm_reg_classes[CLASS_arm_gp].class_req;
1759 req = arch_no_register_req;
1762 /* phi nodes allow loops, so we use the old arguments for now
1763 * and fix this later */
1764 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
1765 get_irn_in(node) + 1);
1766 copy_node_attr(irg, node, phi);
1767 be_duplicate_deps(node, phi);
1769 arch_set_out_register_req(phi, 0, req);
1771 be_enqueue_preds(node);
1778 * Enters all transform functions into the generic pointer
1780 static void arm_register_transformers(void)
1782 be_start_transform_setup();
1784 be_set_transform_function(op_Abs, gen_Abs);
1785 be_set_transform_function(op_Add, gen_Add);
1786 be_set_transform_function(op_And, gen_And);
1787 be_set_transform_function(op_Call, gen_Call);
1788 be_set_transform_function(op_Cmp, gen_Cmp);
1789 be_set_transform_function(op_Cond, gen_Cond);
1790 be_set_transform_function(op_Const, gen_Const);
1791 be_set_transform_function(op_Conv, gen_Conv);
1792 be_set_transform_function(op_CopyB, gen_CopyB);
1793 be_set_transform_function(op_Eor, gen_Eor);
1794 be_set_transform_function(op_Jmp, gen_Jmp);
1795 be_set_transform_function(op_Load, gen_Load);
1796 be_set_transform_function(op_Minus, gen_Minus);
1797 be_set_transform_function(op_Mul, gen_Mul);
1798 be_set_transform_function(op_Not, gen_Not);
1799 be_set_transform_function(op_Or, gen_Or);
1800 be_set_transform_function(op_Phi, gen_Phi);
1801 be_set_transform_function(op_Proj, gen_Proj);
1802 be_set_transform_function(op_Quot, gen_Quot);
1803 be_set_transform_function(op_Return, gen_Return);
1804 be_set_transform_function(op_Rotl, gen_Rotl);
1805 be_set_transform_function(op_Sel, gen_Sel);
1806 be_set_transform_function(op_Shl, gen_Shl);
1807 be_set_transform_function(op_Shr, gen_Shr);
1808 be_set_transform_function(op_Shrs, gen_Shrs);
1809 be_set_transform_function(op_Start, gen_Start);
1810 be_set_transform_function(op_Store, gen_Store);
1811 be_set_transform_function(op_Sub, gen_Sub);
1812 be_set_transform_function(op_SymConst, gen_SymConst);
1813 be_set_transform_function(op_Unknown, gen_Unknown);
1817 * Initialize fpa Immediate support.
1819 static void arm_init_fpa_immediate(void)
1821 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
1822 fpa_imm[0][fpa_null] = get_mode_null(mode_F);
1823 fpa_imm[0][fpa_one] = get_mode_one(mode_F);
1824 fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
1825 fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
1826 fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
1827 fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
1828 fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
1829 fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
1831 fpa_imm[1][fpa_null] = get_mode_null(mode_D);
1832 fpa_imm[1][fpa_one] = get_mode_one(mode_D);
1833 fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
1834 fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
1835 fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
1836 fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
1837 fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
1838 fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
1840 fpa_imm[2][fpa_null] = get_mode_null(mode_E);
1841 fpa_imm[2][fpa_one] = get_mode_one(mode_E);
1842 fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
1843 fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
1844 fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
1845 fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
1846 fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
1847 fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
1851 * Transform a Firm graph into an ARM graph.
1853 void arm_transform_graph(arm_code_gen_t *cg)
1855 static int imm_initialized = 0;
1856 ir_graph *irg = cg->irg;
1857 ir_entity *entity = get_irg_entity(irg);
1858 ir_type *frame_type;
1862 if (! imm_initialized) {
1863 arm_init_fpa_immediate();
1864 imm_initialized = 1;
1866 arm_register_transformers();
1869 node_to_stack = pmap_create();
1871 assert(abihelper == NULL);
1872 abihelper = be_abihelper_prepare(irg);
1873 be_collect_stacknodes(abihelper);
1874 assert(cconv == NULL);
1875 cconv = decide_calling_convention(get_entity_type(entity));
1876 create_stacklayout(irg);
1878 be_transform_graph(cg->irg, NULL);
1880 be_abihelper_finish(abihelper);
1883 free_calling_convention(cconv);
1886 frame_type = get_irg_frame_type(irg);
1887 if (get_type_state(frame_type) == layout_undefined) {
1888 default_layout_compound_type(frame_type);
1891 pmap_destroy(node_to_stack);
1892 node_to_stack = NULL;
1894 be_add_missing_keeps(irg);
1897 void arm_init_transform(void)
1899 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");