2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
40 #include "../benode.h"
42 #include "../beutil.h"
43 #include "../betranshlp.h"
44 #include "../beabihelper.h"
47 #include "bearch_arm_t.h"
48 #include "arm_nodes_attr.h"
49 #include "arm_transform.h"
50 #include "arm_optimize.h"
51 #include "arm_new_nodes.h"
52 #include "arm_map_regs.h"
53 #include "arm_cconv.h"
55 #include "gen_arm_regalloc_if.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static const arch_register_t *sp_reg = &arm_registers[REG_SP];
62 static ir_mode *mode_gp;
63 static ir_mode *mode_fp;
64 static beabi_helper_env_t *abihelper;
65 static calling_convention_t *cconv = NULL;
66 static arm_isa_t *isa;
68 static pmap *node_to_stack;
70 static bool mode_needs_gp_reg(ir_mode *mode)
72 return mode_is_int(mode) || mode_is_reference(mode);
76 * create firm graph for a constant
78 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
85 /* We only have 8 bit immediates. So we possibly have to combine several
86 * operations to construct the desired value.
88 * we can either create the value by adding bits to 0 or by removing bits
89 * from an register with all bits set. Try which alternative needs fewer
91 arm_gen_vals_from_word(value, &v);
92 arm_gen_vals_from_word(~value, &vn);
96 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
97 be_dep_on_frame(result);
99 for (cnt = 1; cnt < vn.ops; ++cnt) {
100 result = new_bd_arm_Bic_imm(dbgi, block, result,
101 vn.values[cnt], vn.rors[cnt]);
105 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
106 be_dep_on_frame(result);
108 for (cnt = 1; cnt < v.ops; ++cnt) {
109 result = new_bd_arm_Or_imm(dbgi, block, result,
110 v.values[cnt], v.rors[cnt]);
117 * Create a DAG constructing a given Const.
119 * @param irn a Firm const
121 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
123 ir_tarval *tv = get_Const_tarval(irn);
124 ir_mode *mode = get_tarval_mode(tv);
127 if (mode_is_reference(mode)) {
128 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
129 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
130 tv = tarval_convert_to(tv, mode_Iu);
132 value = get_tarval_long(tv);
133 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
137 * Create an And that will zero out upper bits.
139 * @param dbgi debug info
140 * @param block the basic block
141 * @param op the original node
142 * param src_bits number of lower bits that will remain
144 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
148 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
149 } else if (src_bits == 16) {
150 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
151 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
154 panic("zero extension only supported for 8 and 16 bits");
159 * Generate code for a sign extension.
161 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
164 int shift_width = 32 - src_bits;
165 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
166 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
170 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
173 int bits = get_mode_size_bits(orig_mode);
177 if (mode_is_signed(orig_mode)) {
178 return gen_sign_extension(dbgi, block, op, bits);
180 return gen_zero_extension(dbgi, block, op, bits);
185 * returns true if it is assured, that the upper bits of a node are "clean"
186 * which means for a 16 or 8 bit value, that the upper bits in the register
187 * are 0 for unsigned and a copy of the last significant bit for signed
190 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
192 (void) transformed_node;
199 * Transforms a Conv node.
201 * @return The created ia32 Conv node
203 static ir_node *gen_Conv(ir_node *node)
205 ir_node *block = be_transform_node(get_nodes_block(node));
206 ir_node *op = get_Conv_op(node);
207 ir_node *new_op = be_transform_node(op);
208 ir_mode *src_mode = get_irn_mode(op);
209 ir_mode *dst_mode = get_irn_mode(node);
210 dbg_info *dbg = get_irn_dbg_info(node);
212 if (src_mode == dst_mode)
215 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
217 if (mode_is_float(src_mode)) {
218 if (mode_is_float(dst_mode)) {
219 /* from float to float */
220 return new_bd_arm_Mvf(dbg, block, new_op, dst_mode);
222 /* from float to int */
226 /* from int to float */
227 if (!mode_is_signed(src_mode)) {
230 return new_bd_arm_FltX(dbg, block, new_op, dst_mode);
233 } else if (USE_VFP(isa)) {
234 panic("VFP not supported yet");
236 panic("Softfloat not supported yet");
238 } else { /* complete in gp registers */
239 int src_bits = get_mode_size_bits(src_mode);
240 int dst_bits = get_mode_size_bits(dst_mode);
244 if (src_bits == dst_bits) {
245 /* kill unnecessary conv */
249 if (src_bits < dst_bits) {
257 if (upper_bits_clean(new_op, min_mode)) {
261 if (mode_is_signed(min_mode)) {
262 return gen_sign_extension(dbg, block, new_op, min_bits);
264 return gen_zero_extension(dbg, block, new_op, min_bits);
274 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
276 unsigned val, low_pos, high_pos;
281 val = get_tarval_long(get_Const_tarval(node));
293 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
295 So we determine the smallest even position with a bit set
296 and the highest even position with no bit set anymore.
297 If the difference between these 2 is <= 8, then we can encode the value
300 low_pos = ntz(val) & ~1u;
301 high_pos = (32-nlz(val)+1) & ~1u;
303 if (high_pos - low_pos <= 8) {
304 res->imm_8 = val >> low_pos;
305 res->rot = 32 - low_pos;
310 res->rot = 34 - high_pos;
311 val = val >> (32-res->rot) | val << (res->rot);
321 static bool is_downconv(const ir_node *node)
329 /* we only want to skip the conv when we're the only user
330 * (not optimal but for now...)
332 if (get_irn_n_edges(node) > 1)
335 src_mode = get_irn_mode(get_Conv_op(node));
336 dest_mode = get_irn_mode(node);
338 mode_needs_gp_reg(src_mode) &&
339 mode_needs_gp_reg(dest_mode) &&
340 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
343 static ir_node *arm_skip_downconv(ir_node *node)
345 while (is_downconv(node))
346 node = get_Conv_op(node);
352 MATCH_COMMUTATIVE = 1 << 0, /**< commutative node */
353 MATCH_REVERSE = 1 << 1, /**< support reverse opcode */
354 MATCH_SIZE_NEUTRAL = 1 << 2,
355 MATCH_SKIP_NOT = 1 << 3, /**< skip Not on ONE input */
357 ENUM_BITSET(match_flags_t)
360 * possible binop constructors.
362 typedef struct arm_binop_factory_t {
363 /** normal reg op reg operation. */
364 ir_node *(*new_binop_reg)(dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
365 /** normal reg op imm operation. */
366 ir_node *(*new_binop_imm)(dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
367 /** barrel shifter reg op (reg shift reg operation. */
368 ir_node *(*new_binop_reg_shift_reg)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *shift, arm_shift_modifier_t shift_modifier);
369 /** barrel shifter reg op (reg shift imm operation. */
370 ir_node *(*new_binop_reg_shift_imm)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, arm_shift_modifier_t shift_modifier, unsigned shift_immediate);
371 } arm_binop_factory_t;
373 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
374 const arm_binop_factory_t *factory)
376 ir_node *block = be_transform_node(get_nodes_block(node));
377 ir_node *op1 = get_binop_left(node);
379 ir_node *op2 = get_binop_right(node);
381 dbg_info *dbgi = get_irn_dbg_info(node);
384 if (flags & MATCH_SKIP_NOT) {
386 op1 = get_Not_op(op1);
387 else if (is_Not(op2))
388 op2 = get_Not_op(op2);
390 panic("cannot execute MATCH_SKIP_NOT");
392 if (flags & MATCH_SIZE_NEUTRAL) {
393 op1 = arm_skip_downconv(op1);
394 op2 = arm_skip_downconv(op2);
396 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
399 if (try_encode_as_immediate(op2, &imm)) {
400 ir_node *new_op1 = be_transform_node(op1);
401 return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
403 new_op2 = be_transform_node(op2);
404 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && try_encode_as_immediate(op1, &imm)) {
405 if (flags & MATCH_REVERSE)
406 return factory[1].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
408 return factory[0].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
410 new_op1 = be_transform_node(op1);
412 /* check if we can fold in a Mov */
413 if (is_arm_Mov(new_op2)) {
414 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op2);
416 switch (attr->shift_modifier) {
418 case ARM_SHF_ASR_IMM:
419 case ARM_SHF_LSL_IMM:
420 case ARM_SHF_LSR_IMM:
421 case ARM_SHF_ROR_IMM:
422 if (factory->new_binop_reg_shift_imm) {
423 ir_node *mov_op = get_irn_n(new_op2, 0);
424 return factory->new_binop_reg_shift_imm(dbgi, block, new_op1, mov_op,
425 attr->shift_modifier, attr->shift_immediate);
429 case ARM_SHF_ASR_REG:
430 case ARM_SHF_LSL_REG:
431 case ARM_SHF_LSR_REG:
432 case ARM_SHF_ROR_REG:
433 if (factory->new_binop_reg_shift_reg) {
434 ir_node *mov_op = get_irn_n(new_op2, 0);
435 ir_node *mov_sft = get_irn_n(new_op2, 1);
436 return factory->new_binop_reg_shift_reg(dbgi, block, new_op1, mov_op, mov_sft,
437 attr->shift_modifier);
443 case ARM_SHF_INVALID:
444 panic("invalid shift");
447 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && is_arm_Mov(new_op1)) {
448 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op1);
449 int idx = flags & MATCH_REVERSE ? 1 : 0;
451 switch (attr->shift_modifier) {
452 ir_node *mov_op, *mov_sft;
455 case ARM_SHF_ASR_IMM:
456 case ARM_SHF_LSL_IMM:
457 case ARM_SHF_LSR_IMM:
458 case ARM_SHF_ROR_IMM:
459 if (factory[idx].new_binop_reg_shift_imm) {
460 mov_op = get_irn_n(new_op1, 0);
461 return factory[idx].new_binop_reg_shift_imm(dbgi, block, new_op2, mov_op,
462 attr->shift_modifier, attr->shift_immediate);
466 case ARM_SHF_ASR_REG:
467 case ARM_SHF_LSL_REG:
468 case ARM_SHF_LSR_REG:
469 case ARM_SHF_ROR_REG:
470 if (factory[idx].new_binop_reg_shift_reg) {
471 mov_op = get_irn_n(new_op1, 0);
472 mov_sft = get_irn_n(new_op1, 1);
473 return factory[idx].new_binop_reg_shift_reg(dbgi, block, new_op2, mov_op, mov_sft,
474 attr->shift_modifier);
481 case ARM_SHF_INVALID:
482 panic("invalid shift");
485 return factory->new_binop_reg(dbgi, block, new_op1, new_op2);
489 * Creates an ARM Add.
491 * @return the created arm Add node
493 static ir_node *gen_Add(ir_node *node)
495 static const arm_binop_factory_t add_factory = {
498 new_bd_arm_Add_reg_shift_reg,
499 new_bd_arm_Add_reg_shift_imm
502 ir_mode *mode = get_irn_mode(node);
504 if (mode_is_float(mode)) {
505 ir_node *block = be_transform_node(get_nodes_block(node));
506 ir_node *op1 = get_Add_left(node);
507 ir_node *op2 = get_Add_right(node);
508 dbg_info *dbgi = get_irn_dbg_info(node);
509 ir_node *new_op1 = be_transform_node(op1);
510 ir_node *new_op2 = be_transform_node(op2);
512 return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
513 } else if (USE_VFP(isa)) {
514 assert(mode != mode_E && "IEEE Extended FP not supported");
515 panic("VFP not supported yet");
517 panic("Softfloat not supported yet");
522 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
524 new_op2 = get_irn_n(new_op1, 1);
525 new_op1 = get_irn_n(new_op1, 0);
527 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
529 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
531 new_op1 = get_irn_n(new_op2, 0);
532 new_op2 = get_irn_n(new_op2, 1);
534 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
538 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &add_factory);
543 * Creates an ARM Mul.
545 * @return the created arm Mul node
547 static ir_node *gen_Mul(ir_node *node)
549 ir_node *block = be_transform_node(get_nodes_block(node));
550 ir_node *op1 = get_Mul_left(node);
551 ir_node *new_op1 = be_transform_node(op1);
552 ir_node *op2 = get_Mul_right(node);
553 ir_node *new_op2 = be_transform_node(op2);
554 ir_mode *mode = get_irn_mode(node);
555 dbg_info *dbg = get_irn_dbg_info(node);
557 if (mode_is_float(mode)) {
559 return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
560 } else if (USE_VFP(isa)) {
561 assert(mode != mode_E && "IEEE Extended FP not supported");
562 panic("VFP not supported yet");
564 panic("Softfloat not supported yet");
567 assert(mode_is_data(mode));
568 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
571 static ir_node *gen_Quot(ir_node *node)
573 ir_node *block = be_transform_node(get_nodes_block(node));
574 ir_node *op1 = get_Quot_left(node);
575 ir_node *new_op1 = be_transform_node(op1);
576 ir_node *op2 = get_Quot_right(node);
577 ir_node *new_op2 = be_transform_node(op2);
578 ir_mode *mode = get_irn_mode(node);
579 dbg_info *dbg = get_irn_dbg_info(node);
581 assert(mode != mode_E && "IEEE Extended FP not supported");
584 return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
585 } else if (USE_VFP(isa)) {
586 assert(mode != mode_E && "IEEE Extended FP not supported");
587 panic("VFP not supported yet");
589 panic("Softfloat not supported yet");
593 static ir_node *gen_And(ir_node *node)
595 static const arm_binop_factory_t and_factory = {
598 new_bd_arm_And_reg_shift_reg,
599 new_bd_arm_And_reg_shift_imm
601 static const arm_binop_factory_t bic_factory = {
604 new_bd_arm_Bic_reg_shift_reg,
605 new_bd_arm_Bic_reg_shift_imm
608 /* check for and not */
609 ir_node *left = get_And_left(node);
610 ir_node *right = get_And_right(node);
612 if (is_Not(left) || is_Not(right)) {
613 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL | MATCH_SKIP_NOT,
617 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &and_factory);
620 static ir_node *gen_Or(ir_node *node)
622 static const arm_binop_factory_t or_factory = {
625 new_bd_arm_Or_reg_shift_reg,
626 new_bd_arm_Or_reg_shift_imm
629 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &or_factory);
632 static ir_node *gen_Eor(ir_node *node)
634 static const arm_binop_factory_t eor_factory = {
637 new_bd_arm_Eor_reg_shift_reg,
638 new_bd_arm_Eor_reg_shift_imm
641 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &eor_factory);
644 static ir_node *gen_Sub(ir_node *node)
646 static const arm_binop_factory_t sub_rsb_factory[2] = {
650 new_bd_arm_Sub_reg_shift_reg,
651 new_bd_arm_Sub_reg_shift_imm
656 new_bd_arm_Rsb_reg_shift_reg,
657 new_bd_arm_Rsb_reg_shift_imm
661 ir_node *block = be_transform_node(get_nodes_block(node));
662 ir_node *op1 = get_Sub_left(node);
663 ir_node *new_op1 = be_transform_node(op1);
664 ir_node *op2 = get_Sub_right(node);
665 ir_node *new_op2 = be_transform_node(op2);
666 ir_mode *mode = get_irn_mode(node);
667 dbg_info *dbgi = get_irn_dbg_info(node);
669 if (mode_is_float(mode)) {
671 return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
672 } else if (USE_VFP(isa)) {
673 assert(mode != mode_E && "IEEE Extended FP not supported");
674 panic("VFP not supported yet");
676 panic("Softfloat not supported yet");
679 return gen_int_binop(node, MATCH_SIZE_NEUTRAL | MATCH_REVERSE, sub_rsb_factory);
684 * Checks if a given value can be used as an immediate for the given
687 static bool can_use_shift_constant(unsigned int val,
688 arm_shift_modifier_t modifier)
692 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
698 * generate an ARM shift instruction.
700 * @param node the node
701 * @param flags matching flags
702 * @param shift_modifier initial encoding of the desired shift operation
704 static ir_node *make_shift(ir_node *node, match_flags_t flags,
705 arm_shift_modifier_t shift_modifier)
707 ir_node *block = be_transform_node(get_nodes_block(node));
708 ir_node *op1 = get_binop_left(node);
709 ir_node *op2 = get_binop_right(node);
710 dbg_info *dbgi = get_irn_dbg_info(node);
714 if (flags & MATCH_SIZE_NEUTRAL) {
715 op1 = arm_skip_downconv(op1);
716 op2 = arm_skip_downconv(op2);
719 new_op1 = be_transform_node(op1);
721 ir_tarval *tv = get_Const_tarval(op2);
722 unsigned int val = get_tarval_long(tv);
723 assert(tarval_is_long(tv));
724 if (can_use_shift_constant(val, shift_modifier)) {
725 switch (shift_modifier) {
726 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
727 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
728 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
729 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
730 default: panic("unexpected shift modifier");
732 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
733 shift_modifier, val);
737 new_op2 = be_transform_node(op2);
738 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
742 static ir_node *gen_Shl(ir_node *node)
744 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
747 static ir_node *gen_Shr(ir_node *node)
749 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
752 static ir_node *gen_Shrs(ir_node *node)
754 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
757 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
759 ir_node *block = be_transform_node(get_nodes_block(node));
760 ir_node *new_op1 = be_transform_node(op1);
761 dbg_info *dbgi = get_irn_dbg_info(node);
762 ir_node *new_op2 = be_transform_node(op2);
764 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
768 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
770 ir_node *block = be_transform_node(get_nodes_block(node));
771 ir_node *new_op1 = be_transform_node(op1);
772 dbg_info *dbgi = get_irn_dbg_info(node);
773 ir_node *new_op2 = be_transform_node(op2);
775 /* Note: there is no Rol on arm, we have to use Ror */
776 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
777 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
781 static ir_node *gen_Rotl(ir_node *node)
783 ir_node *rotate = NULL;
784 ir_node *op1 = get_Rotl_left(node);
785 ir_node *op2 = get_Rotl_right(node);
787 /* Firm has only RotL, so we are looking for a right (op2)
788 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
789 that means we can create a RotR. */
792 ir_node *right = get_Add_right(op2);
793 if (is_Const(right)) {
794 ir_tarval *tv = get_Const_tarval(right);
795 ir_mode *mode = get_irn_mode(node);
796 long bits = get_mode_size_bits(mode);
797 ir_node *left = get_Add_left(op2);
799 if (is_Minus(left) &&
800 tarval_is_long(tv) &&
801 get_tarval_long(tv) == bits &&
803 rotate = gen_Ror(node, op1, get_Minus_op(left));
805 } else if (is_Sub(op2)) {
806 ir_node *left = get_Sub_left(op2);
807 if (is_Const(left)) {
808 ir_tarval *tv = get_Const_tarval(left);
809 ir_mode *mode = get_irn_mode(node);
810 long bits = get_mode_size_bits(mode);
811 ir_node *right = get_Sub_right(op2);
813 if (tarval_is_long(tv) &&
814 get_tarval_long(tv) == bits &&
816 rotate = gen_Ror(node, op1, right);
818 } else if (is_Const(op2)) {
819 ir_tarval *tv = get_Const_tarval(op2);
820 ir_mode *mode = get_irn_mode(node);
821 long bits = get_mode_size_bits(mode);
823 if (tarval_is_long(tv) && bits == 32) {
824 ir_node *block = be_transform_node(get_nodes_block(node));
825 ir_node *new_op1 = be_transform_node(op1);
826 dbg_info *dbgi = get_irn_dbg_info(node);
828 bits = (bits - get_tarval_long(tv)) & 31;
829 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
833 if (rotate == NULL) {
834 rotate = gen_Rol(node, op1, op2);
840 static ir_node *gen_Not(ir_node *node)
842 ir_node *block = be_transform_node(get_nodes_block(node));
843 ir_node *op = get_Not_op(node);
844 ir_node *new_op = be_transform_node(op);
845 dbg_info *dbgi = get_irn_dbg_info(node);
847 /* check if we can fold in a Mov */
848 if (is_arm_Mov(new_op)) {
849 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op);
851 switch (attr->shift_modifier) {
852 ir_node *mov_op, *mov_sft;
855 case ARM_SHF_ASR_IMM:
856 case ARM_SHF_LSL_IMM:
857 case ARM_SHF_LSR_IMM:
858 case ARM_SHF_ROR_IMM:
859 mov_op = get_irn_n(new_op, 0);
860 return new_bd_arm_Mvn_reg_shift_imm(dbgi, block, mov_op,
861 attr->shift_modifier, attr->shift_immediate);
863 case ARM_SHF_ASR_REG:
864 case ARM_SHF_LSL_REG:
865 case ARM_SHF_LSR_REG:
866 case ARM_SHF_ROR_REG:
867 mov_op = get_irn_n(new_op, 0);
868 mov_sft = get_irn_n(new_op, 1);
869 return new_bd_arm_Mvn_reg_shift_reg(dbgi, block, mov_op, mov_sft,
870 attr->shift_modifier);
875 case ARM_SHF_INVALID:
876 panic("invalid shift");
880 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
883 static ir_node *gen_Minus(ir_node *node)
885 ir_node *block = be_transform_node(get_nodes_block(node));
886 ir_node *op = get_Minus_op(node);
887 ir_node *new_op = be_transform_node(op);
888 dbg_info *dbgi = get_irn_dbg_info(node);
889 ir_mode *mode = get_irn_mode(node);
891 if (mode_is_float(mode)) {
893 return new_bd_arm_Mvf(dbgi, block, op, mode);
894 } else if (USE_VFP(isa)) {
895 assert(mode != mode_E && "IEEE Extended FP not supported");
896 panic("VFP not supported yet");
898 panic("Softfloat not supported yet");
901 assert(mode_is_data(mode));
902 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
905 static ir_node *gen_Load(ir_node *node)
907 ir_node *block = be_transform_node(get_nodes_block(node));
908 ir_node *ptr = get_Load_ptr(node);
909 ir_node *new_ptr = be_transform_node(ptr);
910 ir_node *mem = get_Load_mem(node);
911 ir_node *new_mem = be_transform_node(mem);
912 ir_mode *mode = get_Load_mode(node);
913 dbg_info *dbgi = get_irn_dbg_info(node);
914 ir_node *new_load = NULL;
916 if (mode_is_float(mode)) {
918 new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
920 } else if (USE_VFP(isa)) {
921 assert(mode != mode_E && "IEEE Extended FP not supported");
922 panic("VFP not supported yet");
924 panic("Softfloat not supported yet");
927 assert(mode_is_data(mode) && "unsupported mode for Load");
929 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
931 set_irn_pinned(new_load, get_irn_pinned(node));
933 /* check for special case: the loaded value might not be used */
934 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
935 /* add a result proj and a Keep to produce a pseudo use */
936 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
937 be_new_Keep(block, 1, &proj);
943 static ir_node *gen_Store(ir_node *node)
945 ir_node *block = be_transform_node(get_nodes_block(node));
946 ir_node *ptr = get_Store_ptr(node);
947 ir_node *new_ptr = be_transform_node(ptr);
948 ir_node *mem = get_Store_mem(node);
949 ir_node *new_mem = be_transform_node(mem);
950 ir_node *val = get_Store_value(node);
951 ir_node *new_val = be_transform_node(val);
952 ir_mode *mode = get_irn_mode(val);
953 dbg_info *dbgi = get_irn_dbg_info(node);
954 ir_node *new_store = NULL;
956 if (mode_is_float(mode)) {
958 new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
959 new_mem, mode, NULL, 0, 0, false);
960 } else if (USE_VFP(isa)) {
961 assert(mode != mode_E && "IEEE Extended FP not supported");
962 panic("VFP not supported yet");
964 panic("Softfloat not supported yet");
967 assert(mode_is_data(mode) && "unsupported mode for Store");
968 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
971 set_irn_pinned(new_store, get_irn_pinned(node));
975 static ir_node *gen_Jmp(ir_node *node)
977 ir_node *block = get_nodes_block(node);
978 ir_node *new_block = be_transform_node(block);
979 dbg_info *dbgi = get_irn_dbg_info(node);
981 return new_bd_arm_Jmp(dbgi, new_block);
984 static ir_node *gen_SwitchJmp(ir_node *node)
986 ir_node *block = be_transform_node(get_nodes_block(node));
987 ir_node *selector = get_Cond_selector(node);
988 dbg_info *dbgi = get_irn_dbg_info(node);
989 ir_node *new_op = be_transform_node(selector);
990 ir_node *const_graph;
994 const ir_edge_t *edge;
1001 foreach_out_edge(node, edge) {
1002 proj = get_edge_src_irn(edge);
1003 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1005 pn = get_Proj_proj(proj);
1007 min = pn<min ? pn : min;
1008 max = pn>max ? pn : max;
1011 n_projs = max - translation + 1;
1013 foreach_out_edge(node, edge) {
1014 proj = get_edge_src_irn(edge);
1015 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1017 pn = get_Proj_proj(proj) - translation;
1018 set_Proj_proj(proj, pn);
1021 const_graph = create_const_graph_value(dbgi, block, translation);
1022 sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
1023 return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
1026 static ir_node *gen_Cmp(ir_node *node)
1028 ir_node *block = be_transform_node(get_nodes_block(node));
1029 ir_node *op1 = get_Cmp_left(node);
1030 ir_node *op2 = get_Cmp_right(node);
1031 ir_mode *cmp_mode = get_irn_mode(op1);
1032 dbg_info *dbgi = get_irn_dbg_info(node);
1037 if (mode_is_float(cmp_mode)) {
1038 /* TODO: this is broken... */
1039 new_op1 = be_transform_node(op1);
1040 new_op2 = be_transform_node(op2);
1042 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
1045 assert(get_irn_mode(op2) == cmp_mode);
1046 is_unsigned = !mode_is_signed(cmp_mode);
1048 /* integer compare, TODO: use shifter_op in all its combinations */
1049 new_op1 = be_transform_node(op1);
1050 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
1051 new_op2 = be_transform_node(op2);
1052 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
1053 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
1057 static ir_node *gen_Cond(ir_node *node)
1059 ir_node *selector = get_Cond_selector(node);
1060 ir_mode *mode = get_irn_mode(selector);
1065 if (mode != mode_b) {
1066 return gen_SwitchJmp(node);
1068 assert(is_Proj(selector));
1070 block = be_transform_node(get_nodes_block(node));
1071 dbgi = get_irn_dbg_info(node);
1072 flag_node = be_transform_node(get_Proj_pred(selector));
1074 return new_bd_arm_B(dbgi, block, flag_node, get_Proj_pn_cmp(selector));
1080 FPA_IMM_EXTENDED = 2,
1081 FPA_IMM_MAX = FPA_IMM_EXTENDED
1084 static ir_tarval *fpa_imm[FPA_IMM_MAX + 1][fpa_max];
1088 * Check, if a floating point tarval is an fpa immediate, i.e.
1089 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
1091 static int is_fpa_immediate(tarval *tv)
1093 ir_mode *mode = get_tarval_mode(tv);
1096 switch (get_mode_size_bits(mode)) {
1104 i = FPA_IMM_EXTENDED;
1107 if (tarval_is_negative(tv)) {
1108 tv = tarval_neg(tv);
1112 for (j = 0; j < fpa_max; ++j) {
1113 if (tv == fpa_imm[i][j])
1120 static ir_node *gen_Const(ir_node *node)
1122 ir_node *block = be_transform_node(get_nodes_block(node));
1123 ir_mode *mode = get_irn_mode(node);
1124 dbg_info *dbg = get_irn_dbg_info(node);
1126 if (mode_is_float(mode)) {
1128 ir_tarval *tv = get_Const_tarval(node);
1129 node = new_bd_arm_fConst(dbg, block, tv);
1130 be_dep_on_frame(node);
1132 } else if (USE_VFP(isa)) {
1133 assert(mode != mode_E && "IEEE Extended FP not supported");
1134 panic("VFP not supported yet");
1136 panic("Softfloat not supported yet");
1139 return create_const_graph(node, block);
1142 static ir_node *gen_SymConst(ir_node *node)
1144 ir_node *block = be_transform_node(get_nodes_block(node));
1145 ir_entity *entity = get_SymConst_entity(node);
1146 dbg_info *dbgi = get_irn_dbg_info(node);
1149 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
1150 be_dep_on_frame(new_node);
1154 static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0,
1157 /* the good way to do this would be to use the stm (store multiple)
1158 * instructions, since our input is nearly always 2 consecutive 32bit
1160 ir_graph *irg = current_ir_graph;
1161 ir_node *stack = get_irg_frame(irg);
1162 ir_node *nomem = new_r_NoMem(irg);
1163 ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp,
1165 ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp,
1167 ir_node *in[2] = { str0, str1 };
1168 ir_node *sync = new_r_Sync(block, 2, in);
1170 set_irn_pinned(str0, op_pin_state_floats);
1171 set_irn_pinned(str1, op_pin_state_floats);
1173 ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true);
1174 set_irn_pinned(ldf, op_pin_state_floats);
1176 return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1179 static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node)
1181 ir_graph *irg = current_ir_graph;
1182 ir_node *stack = get_irg_frame(irg);
1183 ir_node *nomem = new_r_NoMem(irg);
1184 ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp,
1187 set_irn_pinned(str, op_pin_state_floats);
1189 ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true);
1190 set_irn_pinned(ldf, op_pin_state_floats);
1192 return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1195 static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node)
1197 ir_graph *irg = current_ir_graph;
1198 ir_node *stack = get_irg_frame(irg);
1199 ir_node *nomem = new_r_NoMem(irg);
1200 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F,
1203 set_irn_pinned(stf, op_pin_state_floats);
1205 ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1206 set_irn_pinned(ldr, op_pin_state_floats);
1208 return new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1211 static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node,
1212 ir_node **out_value0, ir_node **out_value1)
1214 ir_graph *irg = current_ir_graph;
1215 ir_node *stack = get_irg_frame(irg);
1216 ir_node *nomem = new_r_NoMem(irg);
1217 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D,
1219 ir_node *ldr0, *ldr1;
1220 set_irn_pinned(stf, op_pin_state_floats);
1222 ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1223 set_irn_pinned(ldr0, op_pin_state_floats);
1224 ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true);
1225 set_irn_pinned(ldr1, op_pin_state_floats);
1227 *out_value0 = new_r_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
1228 *out_value1 = new_r_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
1231 static ir_node *gen_CopyB(ir_node *node)
1233 ir_node *block = be_transform_node(get_nodes_block(node));
1234 ir_node *src = get_CopyB_src(node);
1235 ir_node *new_src = be_transform_node(src);
1236 ir_node *dst = get_CopyB_dst(node);
1237 ir_node *new_dst = be_transform_node(dst);
1238 ir_node *mem = get_CopyB_mem(node);
1239 ir_node *new_mem = be_transform_node(mem);
1240 dbg_info *dbg = get_irn_dbg_info(node);
1241 int size = get_type_size_bytes(get_CopyB_type(node));
1245 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
1246 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
1248 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1249 new_bd_arm_EmptyReg(dbg, block),
1250 new_bd_arm_EmptyReg(dbg, block),
1251 new_bd_arm_EmptyReg(dbg, block),
1256 * Transform builtin clz.
1258 static ir_node *gen_clz(ir_node *node)
1260 ir_node *block = be_transform_node(get_nodes_block(node));
1261 dbg_info *dbg = get_irn_dbg_info(node);
1262 ir_node *op = get_irn_n(node, 1);
1263 ir_node *new_op = be_transform_node(op);
1265 /* TODO armv5 instruction, otherwise create a call */
1266 return new_bd_arm_Clz(dbg, block, new_op);
1270 * Transform Builtin node.
1272 static ir_node *gen_Builtin(ir_node *node)
1274 ir_builtin_kind kind = get_Builtin_kind(node);
1278 case ir_bk_debugbreak:
1279 case ir_bk_return_address:
1280 case ir_bk_frame_address:
1281 case ir_bk_prefetch:
1285 return gen_clz(node);
1288 case ir_bk_popcount:
1292 case ir_bk_inner_trampoline:
1295 panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
1299 * Transform Proj(Builtin) node.
1301 static ir_node *gen_Proj_Builtin(ir_node *proj)
1303 ir_node *node = get_Proj_pred(proj);
1304 ir_node *new_node = be_transform_node(node);
1305 ir_builtin_kind kind = get_Builtin_kind(node);
1308 case ir_bk_return_address:
1309 case ir_bk_frame_address:
1314 case ir_bk_popcount:
1316 assert(get_Proj_proj(proj) == pn_Builtin_1_result);
1319 case ir_bk_debugbreak:
1320 case ir_bk_prefetch:
1322 assert(get_Proj_proj(proj) == pn_Builtin_M);
1325 case ir_bk_inner_trampoline:
1328 panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
1331 static ir_node *gen_Proj_Load(ir_node *node)
1333 ir_node *load = get_Proj_pred(node);
1334 ir_node *new_load = be_transform_node(load);
1335 dbg_info *dbgi = get_irn_dbg_info(node);
1336 long proj = get_Proj_proj(node);
1338 /* renumber the proj */
1339 switch (get_arm_irn_opcode(new_load)) {
1341 /* handle all gp loads equal: they have the same proj numbers. */
1342 if (proj == pn_Load_res) {
1343 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1344 } else if (proj == pn_Load_M) {
1345 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1349 if (proj == pn_Load_res) {
1350 ir_mode *mode = get_Load_mode(load);
1351 return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res);
1352 } else if (proj == pn_Load_M) {
1353 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M);
1359 panic("Unsupported Proj from Load");
1362 static ir_node *gen_Proj_CopyB(ir_node *node)
1364 ir_node *pred = get_Proj_pred(node);
1365 ir_node *new_pred = be_transform_node(pred);
1366 dbg_info *dbgi = get_irn_dbg_info(node);
1367 long proj = get_Proj_proj(node);
1371 if (is_arm_CopyB(new_pred)) {
1372 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1378 panic("Unsupported Proj from CopyB");
1381 static ir_node *gen_Proj_Quot(ir_node *node)
1383 ir_node *pred = get_Proj_pred(node);
1384 ir_node *new_pred = be_transform_node(pred);
1385 dbg_info *dbgi = get_irn_dbg_info(node);
1386 ir_mode *mode = get_irn_mode(node);
1387 long proj = get_Proj_proj(node);
1391 if (is_arm_Dvf(new_pred)) {
1392 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
1396 if (is_arm_Dvf(new_pred)) {
1397 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
1403 panic("Unsupported Proj from Quot");
1407 * Transform the Projs from a Cmp.
1409 static ir_node *gen_Proj_Cmp(ir_node *node)
1412 /* we should only be here in case of a Mux node */
1416 static ir_node *gen_Proj_Start(ir_node *node)
1418 ir_node *block = get_nodes_block(node);
1419 ir_node *new_block = be_transform_node(block);
1420 ir_node *barrier = be_transform_node(get_Proj_pred(node));
1421 long proj = get_Proj_proj(node);
1423 switch ((pn_Start) proj) {
1424 case pn_Start_X_initial_exec:
1425 /* we exchange the ProjX with a jump */
1426 return new_bd_arm_Jmp(NULL, new_block);
1429 return new_r_Proj(barrier, mode_M, 0);
1431 case pn_Start_T_args:
1434 case pn_Start_P_frame_base:
1435 return be_prolog_get_reg_value(abihelper, sp_reg);
1437 case pn_Start_P_tls:
1438 return new_r_Bad(get_irn_irg(node));
1443 panic("unexpected start proj: %ld\n", proj);
1446 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1448 long pn = get_Proj_proj(node);
1449 ir_node *block = get_nodes_block(node);
1450 ir_node *new_block = be_transform_node(block);
1451 ir_entity *entity = get_irg_entity(current_ir_graph);
1452 ir_type *method_type = get_entity_type(entity);
1453 ir_type *param_type = get_method_param_type(method_type, pn);
1454 const reg_or_stackslot_t *param;
1456 /* Proj->Proj->Start must be a method argument */
1457 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1459 param = &cconv->parameters[pn];
1461 if (param->reg0 != NULL) {
1462 /* argument transmitted in register */
1463 ir_mode *mode = get_type_mode(param_type);
1464 ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0);
1466 if (mode_is_float(mode)) {
1467 ir_node *value1 = NULL;
1469 if (param->reg1 != NULL) {
1470 value1 = be_prolog_get_reg_value(abihelper, param->reg1);
1471 } else if (param->entity != NULL) {
1472 ir_graph *irg = get_irn_irg(node);
1473 ir_node *fp = get_irg_frame(irg);
1474 ir_node *mem = be_prolog_get_memory(abihelper);
1475 ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem,
1476 mode_gp, param->entity,
1478 value1 = new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1481 /* convert integer value to float */
1482 if (value1 == NULL) {
1483 value = int_to_float(NULL, new_block, value);
1485 value = ints_to_double(NULL, new_block, value, value1);
1490 /* argument transmitted on stack */
1491 ir_graph *irg = get_irn_irg(node);
1492 ir_node *fp = get_irg_frame(irg);
1493 ir_node *mem = be_prolog_get_memory(abihelper);
1494 ir_mode *mode = get_type_mode(param->type);
1498 if (mode_is_float(mode)) {
1499 load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode,
1500 param->entity, 0, 0, true);
1501 value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res);
1503 load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1504 param->entity, 0, 0, true);
1505 value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1507 set_irn_pinned(load, op_pin_state_floats);
1514 * Finds number of output value of a mode_T node which is constrained to
1515 * a single specific register.
1517 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1519 int n_outs = arch_irn_get_n_outs(node);
1522 for (o = 0; o < n_outs; ++o) {
1523 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1524 if (req == reg->single_req)
1530 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1532 long pn = get_Proj_proj(node);
1533 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1534 ir_node *new_call = be_transform_node(call);
1535 ir_type *function_type = get_Call_type(call);
1536 calling_convention_t *cconv
1537 = arm_decide_calling_convention(NULL, function_type);
1538 const reg_or_stackslot_t *res = &cconv->results[pn];
1542 /* TODO 64bit modes */
1543 assert(res->reg0 != NULL && res->reg1 == NULL);
1544 regn = find_out_for_reg(new_call, res->reg0);
1546 panic("Internal error in calling convention for return %+F", node);
1548 mode = res->reg0->reg_class->mode;
1550 arm_free_calling_convention(cconv);
1552 return new_r_Proj(new_call, mode, regn);
1555 static ir_node *gen_Proj_Call(ir_node *node)
1557 long pn = get_Proj_proj(node);
1558 ir_node *call = get_Proj_pred(node);
1559 ir_node *new_call = be_transform_node(call);
1561 switch ((pn_Call) pn) {
1563 return new_r_Proj(new_call, mode_M, 0);
1564 case pn_Call_X_regular:
1565 case pn_Call_X_except:
1566 case pn_Call_T_result:
1567 case pn_Call_P_value_res_base:
1571 panic("Unexpected Call proj %ld\n", pn);
1575 * Transform a Proj node.
1577 static ir_node *gen_Proj(ir_node *node)
1579 ir_node *pred = get_Proj_pred(node);
1580 long proj = get_Proj_proj(node);
1582 switch (get_irn_opcode(pred)) {
1584 if (proj == pn_Store_M) {
1585 return be_transform_node(pred);
1587 panic("Unsupported Proj from Store");
1590 return gen_Proj_Load(node);
1592 return gen_Proj_Call(node);
1594 return gen_Proj_CopyB(node);
1596 return gen_Proj_Quot(node);
1598 return gen_Proj_Cmp(node);
1600 return gen_Proj_Start(node);
1603 return be_duplicate_node(node);
1605 ir_node *pred_pred = get_Proj_pred(pred);
1606 if (is_Call(pred_pred)) {
1607 return gen_Proj_Proj_Call(node);
1608 } else if (is_Start(pred_pred)) {
1609 return gen_Proj_Proj_Start(node);
1614 return gen_Proj_Builtin(node);
1616 panic("code selection didn't expect Proj after %+F\n", pred);
1620 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1622 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
1623 create_const_node_func func,
1624 const arch_register_t* reg)
1626 ir_node *block, *res;
1631 block = get_irg_start_block(irg);
1632 res = func(NULL, block);
1633 arch_set_irn_register(res, reg);
1638 static ir_node *gen_Unknown(ir_node *node)
1640 ir_node *block = get_nodes_block(node);
1641 ir_node *new_block = be_transform_node(block);
1642 dbg_info *dbgi = get_irn_dbg_info(node);
1644 /* just produce a 0 */
1645 ir_mode *mode = get_irn_mode(node);
1646 if (mode_is_float(mode)) {
1647 ir_tarval *tv = get_mode_null(mode);
1648 ir_node *node = new_bd_arm_fConst(dbgi, new_block, tv);
1649 be_dep_on_frame(node);
1651 } else if (mode_needs_gp_reg(mode)) {
1652 return create_const_graph_value(dbgi, new_block, 0);
1655 panic("Unexpected Unknown mode");
1659 * Produces the type which sits between the stack args and the locals on the
1660 * stack. It will contain the return address and space to store the old base
1662 * @return The Firm type modeling the ABI between type.
1664 static ir_type *arm_get_between_type(void)
1666 static ir_type *between_type = NULL;
1668 if (between_type == NULL) {
1669 between_type = new_type_class(new_id_from_str("arm_between_type"));
1670 set_type_size_bytes(between_type, 0);
1673 return between_type;
1676 static void create_stacklayout(ir_graph *irg)
1678 ir_entity *entity = get_irg_entity(irg);
1679 ir_type *function_type = get_entity_type(entity);
1680 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1685 /* calling conventions must be decided by now */
1686 assert(cconv != NULL);
1688 /* construct argument type */
1689 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1690 n_params = get_method_n_params(function_type);
1691 for (p = 0; p < n_params; ++p) {
1692 reg_or_stackslot_t *param = &cconv->parameters[p];
1696 if (param->type == NULL)
1699 snprintf(buf, sizeof(buf), "param_%d", p);
1700 id = new_id_from_str(buf);
1701 param->entity = new_entity(arg_type, id, param->type);
1702 set_entity_offset(param->entity, param->offset);
1705 /* TODO: what about external functions? we don't know most of the stack
1706 * layout for them. And probably don't need all of this... */
1707 memset(layout, 0, sizeof(*layout));
1709 layout->frame_type = get_irg_frame_type(irg);
1710 layout->between_type = arm_get_between_type();
1711 layout->arg_type = arg_type;
1712 layout->param_map = NULL; /* TODO */
1713 layout->initial_offset = 0;
1714 layout->initial_bias = 0;
1715 layout->stack_dir = -1;
1716 layout->sp_relative = true;
1718 assert(N_FRAME_TYPES == 3);
1719 layout->order[0] = layout->frame_type;
1720 layout->order[1] = layout->between_type;
1721 layout->order[2] = layout->arg_type;
1725 * transform the start node to the prolog code + initial barrier
1727 static ir_node *gen_Start(ir_node *node)
1729 ir_graph *irg = get_irn_irg(node);
1730 ir_entity *entity = get_irg_entity(irg);
1731 ir_type *function_type = get_entity_type(entity);
1732 ir_node *block = get_nodes_block(node);
1733 ir_node *new_block = be_transform_node(block);
1734 dbg_info *dbgi = get_irn_dbg_info(node);
1741 /* stackpointer is important at function prolog */
1742 be_prolog_add_reg(abihelper, sp_reg,
1743 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1744 /* function parameters in registers */
1745 for (i = 0; i < get_method_n_params(function_type); ++i) {
1746 const reg_or_stackslot_t *param = &cconv->parameters[i];
1747 if (param->reg0 != NULL)
1748 be_prolog_add_reg(abihelper, param->reg0, arch_register_req_type_none);
1749 if (param->reg1 != NULL)
1750 be_prolog_add_reg(abihelper, param->reg1, arch_register_req_type_none);
1752 /* announce that we need the values of the callee save regs */
1753 for (i = 0; i < (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
1754 be_prolog_add_reg(abihelper, callee_saves[i], arch_register_req_type_none);
1757 start = be_prolog_create_start(abihelper, dbgi, new_block);
1758 sp = be_prolog_get_reg_value(abihelper, sp_reg);
1759 incsp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
1760 be_prolog_set_reg_value(abihelper, sp_reg, incsp);
1761 barrier = be_prolog_create_barrier(abihelper, new_block);
1766 static ir_node *get_stack_pointer_for(ir_node *node)
1768 /* get predecessor in stack_order list */
1769 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1770 ir_node *stack_pred_transformed;
1773 if (stack_pred == NULL) {
1774 /* first stack user in the current block. We can simply use the
1775 * initial sp_proj for it */
1776 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1780 stack_pred_transformed = be_transform_node(stack_pred);
1781 stack = (ir_node*)pmap_get(node_to_stack, stack_pred);
1782 if (stack == NULL) {
1783 return get_stack_pointer_for(stack_pred);
1790 * transform a Return node into epilogue code + return statement
1792 static ir_node *gen_Return(ir_node *node)
1794 ir_node *block = get_nodes_block(node);
1795 ir_node *new_block = be_transform_node(block);
1796 dbg_info *dbgi = get_irn_dbg_info(node);
1797 ir_node *mem = get_Return_mem(node);
1798 ir_node *new_mem = be_transform_node(mem);
1799 int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
1800 ir_node *sp_proj = get_stack_pointer_for(node);
1801 int n_res = get_Return_n_ress(node);
1806 be_epilog_begin(abihelper);
1807 be_epilog_set_memory(abihelper, new_mem);
1808 /* connect stack pointer with initial stack pointer. fix_stack phase
1809 will later serialize all stack pointer adjusting nodes */
1810 be_epilog_add_reg(abihelper, sp_reg,
1811 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1815 for (i = 0; i < n_res; ++i) {
1816 ir_node *res_value = get_Return_res(node, i);
1817 ir_node *new_res_value = be_transform_node(res_value);
1818 const reg_or_stackslot_t *slot = &cconv->results[i];
1819 const arch_register_t *reg = slot->reg0;
1820 assert(slot->reg1 == NULL);
1821 be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, new_res_value);
1824 /* connect callee saves with their values at the function begin */
1825 for (i = 0; i < n_callee_saves; ++i) {
1826 const arch_register_t *reg = callee_saves[i];
1827 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1828 be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, value);
1831 /* create the barrier before the epilog code */
1832 be_epilog_create_barrier(abihelper, new_block);
1834 /* epilog code: an incsp */
1835 sp_proj = be_epilog_get_reg_value(abihelper, sp_reg);
1836 incsp = be_new_IncSP(sp_reg, new_block, sp_proj,
1837 BE_STACK_FRAME_SIZE_SHRINK, 0);
1838 be_epilog_set_reg_value(abihelper, sp_reg, incsp);
1840 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1846 static ir_node *gen_Call(ir_node *node)
1848 ir_graph *irg = get_irn_irg(node);
1849 ir_node *callee = get_Call_ptr(node);
1850 ir_node *block = get_nodes_block(node);
1851 ir_node *new_block = be_transform_node(block);
1852 ir_node *mem = get_Call_mem(node);
1853 ir_node *new_mem = be_transform_node(mem);
1854 dbg_info *dbgi = get_irn_dbg_info(node);
1855 ir_type *type = get_Call_type(node);
1856 calling_convention_t *cconv = arm_decide_calling_convention(NULL, type);
1857 size_t n_params = get_Call_n_params(node);
1858 size_t n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
1859 /* max inputs: memory, callee, register arguments */
1860 int max_inputs = 2 + n_param_regs;
1861 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1862 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1863 struct obstack *obst = be_get_be_obst(irg);
1864 const arch_register_req_t **in_req
1865 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1869 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1870 ir_entity *entity = NULL;
1871 ir_node *incsp = NULL;
1878 assert(n_params == get_method_n_params(type));
1880 /* construct arguments */
1883 in_req[in_arity] = arch_no_register_req;
1887 for (p = 0; p < n_params; ++p) {
1888 ir_node *value = get_Call_param(node, p);
1889 ir_node *new_value = be_transform_node(value);
1890 ir_node *new_value1 = NULL;
1891 const reg_or_stackslot_t *param = &cconv->parameters[p];
1892 ir_type *param_type = get_method_param_type(type, p);
1893 ir_mode *mode = get_type_mode(param_type);
1896 if (mode_is_float(mode) && param->reg0 != NULL) {
1897 unsigned size_bits = get_mode_size_bits(mode);
1898 if (size_bits == 64) {
1899 double_to_ints(dbgi, new_block, new_value, &new_value,
1902 assert(size_bits == 32);
1903 new_value = float_to_int(dbgi, new_block, new_value);
1907 /* put value into registers */
1908 if (param->reg0 != NULL) {
1909 in[in_arity] = new_value;
1910 in_req[in_arity] = param->reg0->single_req;
1912 if (new_value1 == NULL)
1915 if (param->reg1 != NULL) {
1916 assert(new_value1 != NULL);
1917 in[in_arity] = new_value1;
1918 in_req[in_arity] = param->reg1->single_req;
1923 /* we need a store if we're here */
1924 if (new_value1 != NULL) {
1925 new_value = new_value1;
1929 /* create a parameter frame if necessary */
1930 if (incsp == NULL) {
1931 ir_node *new_frame = get_stack_pointer_for(node);
1932 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1933 cconv->param_stack_size, 1);
1935 if (mode_is_float(mode)) {
1936 str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem,
1937 mode, NULL, 0, param->offset, true);
1939 str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem,
1940 mode, NULL, 0, param->offset, true);
1942 sync_ins[sync_arity++] = str;
1944 assert(in_arity <= max_inputs);
1946 /* construct memory input */
1947 if (sync_arity == 0) {
1948 in[mem_pos] = new_mem;
1949 } else if (sync_arity == 1) {
1950 in[mem_pos] = sync_ins[0];
1952 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1955 /* TODO: use a generic symconst matcher here */
1956 if (is_SymConst(callee)) {
1957 entity = get_SymConst_entity(callee);
1959 /* TODO: finish load matcher here */
1962 if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) {
1963 ir_node *load = get_Proj_pred(callee);
1964 ir_node *ptr = get_Load_ptr(load);
1965 ir_node *new_ptr = be_transform_node(ptr);
1966 ir_node *mem = get_Load_mem(load);
1967 ir_node *new_mem = be_transform_node(mem);
1968 ir_mode *mode = get_Load_mode(node);
1972 in[in_arity] = be_transform_node(callee);
1973 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1982 out_arity = 1 + n_caller_saves;
1984 if (entity != NULL) {
1985 /* TODO: use a generic symconst matcher here
1986 * so we can also handle entity+offset, etc. */
1987 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1990 * - use a proper shifter_operand matcher
1991 * - we could also use LinkLdrPC
1993 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1997 if (incsp != NULL) {
1998 /* IncSP to destroy the call stackframe */
1999 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
2001 /* if we are the last IncSP producer in a block then we have to keep
2003 * Note: This here keeps all producers which is more than necessary */
2004 add_irn_dep(incsp, res);
2007 pmap_insert(node_to_stack, node, incsp);
2010 arch_set_in_register_reqs(res, in_req);
2012 /* create output register reqs */
2013 arch_set_out_register_req(res, 0, arch_no_register_req);
2014 for (o = 0; o < n_caller_saves; ++o) {
2015 const arch_register_t *reg = caller_saves[o];
2016 arch_set_out_register_req(res, o+1, reg->single_req);
2019 /* copy pinned attribute */
2020 set_irn_pinned(res, get_irn_pinned(node));
2022 arm_free_calling_convention(cconv);
2026 static ir_node *gen_Sel(ir_node *node)
2028 dbg_info *dbgi = get_irn_dbg_info(node);
2029 ir_node *block = get_nodes_block(node);
2030 ir_node *new_block = be_transform_node(block);
2031 ir_node *ptr = get_Sel_ptr(node);
2032 ir_node *new_ptr = be_transform_node(ptr);
2033 ir_entity *entity = get_Sel_entity(node);
2035 /* must be the frame pointer all other sels must have been lowered
2037 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
2038 /* we should not have value types from parameters anymore - they should be
2040 assert(get_entity_owner(entity) !=
2041 get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
2043 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
2047 * Change some phi modes
2049 static ir_node *gen_Phi(ir_node *node)
2051 const arch_register_req_t *req;
2052 ir_node *block = be_transform_node(get_nodes_block(node));
2053 ir_graph *irg = current_ir_graph;
2054 dbg_info *dbgi = get_irn_dbg_info(node);
2055 ir_mode *mode = get_irn_mode(node);
2058 if (mode_needs_gp_reg(mode)) {
2059 /* we shouldn't have any 64bit stuff around anymore */
2060 assert(get_mode_size_bits(mode) <= 32);
2061 /* all integer operations are on 32bit registers now */
2063 req = arm_reg_classes[CLASS_arm_gp].class_req;
2065 req = arch_no_register_req;
2068 /* phi nodes allow loops, so we use the old arguments for now
2069 * and fix this later */
2070 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
2071 get_irn_in(node) + 1);
2072 copy_node_attr(irg, node, phi);
2073 be_duplicate_deps(node, phi);
2075 arch_set_out_register_req(phi, 0, req);
2077 be_enqueue_preds(node);
2084 * Enters all transform functions into the generic pointer
2086 static void arm_register_transformers(void)
2088 be_start_transform_setup();
2090 be_set_transform_function(op_Add, gen_Add);
2091 be_set_transform_function(op_And, gen_And);
2092 be_set_transform_function(op_Call, gen_Call);
2093 be_set_transform_function(op_Cmp, gen_Cmp);
2094 be_set_transform_function(op_Cond, gen_Cond);
2095 be_set_transform_function(op_Const, gen_Const);
2096 be_set_transform_function(op_Conv, gen_Conv);
2097 be_set_transform_function(op_CopyB, gen_CopyB);
2098 be_set_transform_function(op_Eor, gen_Eor);
2099 be_set_transform_function(op_Jmp, gen_Jmp);
2100 be_set_transform_function(op_Load, gen_Load);
2101 be_set_transform_function(op_Minus, gen_Minus);
2102 be_set_transform_function(op_Mul, gen_Mul);
2103 be_set_transform_function(op_Not, gen_Not);
2104 be_set_transform_function(op_Or, gen_Or);
2105 be_set_transform_function(op_Phi, gen_Phi);
2106 be_set_transform_function(op_Proj, gen_Proj);
2107 be_set_transform_function(op_Quot, gen_Quot);
2108 be_set_transform_function(op_Return, gen_Return);
2109 be_set_transform_function(op_Rotl, gen_Rotl);
2110 be_set_transform_function(op_Sel, gen_Sel);
2111 be_set_transform_function(op_Shl, gen_Shl);
2112 be_set_transform_function(op_Shr, gen_Shr);
2113 be_set_transform_function(op_Shrs, gen_Shrs);
2114 be_set_transform_function(op_Start, gen_Start);
2115 be_set_transform_function(op_Store, gen_Store);
2116 be_set_transform_function(op_Sub, gen_Sub);
2117 be_set_transform_function(op_SymConst, gen_SymConst);
2118 be_set_transform_function(op_Unknown, gen_Unknown);
2119 be_set_transform_function(op_Builtin, gen_Builtin);
2123 * Initialize fpa Immediate support.
2125 static void arm_init_fpa_immediate(void)
2127 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
2128 fpa_imm[FPA_IMM_FLOAT][fpa_null] = get_mode_null(mode_F);
2129 fpa_imm[FPA_IMM_FLOAT][fpa_one] = get_mode_one(mode_F);
2130 fpa_imm[FPA_IMM_FLOAT][fpa_two] = new_tarval_from_str("2", 1, mode_F);
2131 fpa_imm[FPA_IMM_FLOAT][fpa_three] = new_tarval_from_str("3", 1, mode_F);
2132 fpa_imm[FPA_IMM_FLOAT][fpa_four] = new_tarval_from_str("4", 1, mode_F);
2133 fpa_imm[FPA_IMM_FLOAT][fpa_five] = new_tarval_from_str("5", 1, mode_F);
2134 fpa_imm[FPA_IMM_FLOAT][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
2135 fpa_imm[FPA_IMM_FLOAT][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
2137 fpa_imm[FPA_IMM_DOUBLE][fpa_null] = get_mode_null(mode_D);
2138 fpa_imm[FPA_IMM_DOUBLE][fpa_one] = get_mode_one(mode_D);
2139 fpa_imm[FPA_IMM_DOUBLE][fpa_two] = new_tarval_from_str("2", 1, mode_D);
2140 fpa_imm[FPA_IMM_DOUBLE][fpa_three] = new_tarval_from_str("3", 1, mode_D);
2141 fpa_imm[FPA_IMM_DOUBLE][fpa_four] = new_tarval_from_str("4", 1, mode_D);
2142 fpa_imm[FPA_IMM_DOUBLE][fpa_five] = new_tarval_from_str("5", 1, mode_D);
2143 fpa_imm[FPA_IMM_DOUBLE][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
2144 fpa_imm[FPA_IMM_DOUBLE][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
2146 fpa_imm[FPA_IMM_EXTENDED][fpa_null] = get_mode_null(mode_E);
2147 fpa_imm[FPA_IMM_EXTENDED][fpa_one] = get_mode_one(mode_E);
2148 fpa_imm[FPA_IMM_EXTENDED][fpa_two] = new_tarval_from_str("2", 1, mode_E);
2149 fpa_imm[FPA_IMM_EXTENDED][fpa_three] = new_tarval_from_str("3", 1, mode_E);
2150 fpa_imm[FPA_IMM_EXTENDED][fpa_four] = new_tarval_from_str("4", 1, mode_E);
2151 fpa_imm[FPA_IMM_EXTENDED][fpa_five] = new_tarval_from_str("5", 1, mode_E);
2152 fpa_imm[FPA_IMM_EXTENDED][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
2153 fpa_imm[FPA_IMM_EXTENDED][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
2157 * Transform a Firm graph into an ARM graph.
2159 void arm_transform_graph(ir_graph *irg)
2161 static int imm_initialized = 0;
2162 ir_entity *entity = get_irg_entity(irg);
2163 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
2164 ir_type *frame_type;
2169 if (! imm_initialized) {
2170 arm_init_fpa_immediate();
2171 imm_initialized = 1;
2173 arm_register_transformers();
2175 isa = (arm_isa_t*) arch_env;
2177 node_to_stack = pmap_create();
2179 assert(abihelper == NULL);
2180 abihelper = be_abihelper_prepare(irg);
2181 be_collect_stacknodes(abihelper);
2182 assert(cconv == NULL);
2183 cconv = arm_decide_calling_convention(irg, get_entity_type(entity));
2184 create_stacklayout(irg);
2186 be_transform_graph(irg, NULL);
2188 be_abihelper_finish(abihelper);
2191 arm_free_calling_convention(cconv);
2194 frame_type = get_irg_frame_type(irg);
2195 if (get_type_state(frame_type) == layout_undefined) {
2196 default_layout_compound_type(frame_type);
2199 pmap_destroy(node_to_stack);
2200 node_to_stack = NULL;
2202 be_add_missing_keeps(irg);
2205 void arm_init_transform(void)
2207 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");