2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
31 #include "irgraph_t.h"
43 #include "../benode_t.h"
44 #include "../beirg_t.h"
45 #include "../betranshlp.h"
46 #include "bearch_arm_t.h"
48 #include "arm_nodes_attr.h"
50 #include "arm_transform.h"
51 #include "arm_new_nodes.h"
52 #include "arm_map_regs.h"
54 #include "gen_arm_regalloc_if.h"
59 /** hold the current code generator during transformation */
60 static arm_code_gen_t *env_cg;
62 extern ir_op *get_op_Mulh(void);
65 /****************************************************************************************************
67 * | | | | / _| | | (_)
68 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
69 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
70 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
71 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
73 ****************************************************************************************************/
75 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
76 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
79 typedef struct vals_ {
81 unsigned char values[4];
82 unsigned char shifts[4];
86 static unsigned do_rol(unsigned v, unsigned rol) {
87 return (v << rol) | (v >> (32 - rol));
91 * construct 8bit values and rot amounts for a value
93 static void gen_vals_from_word(unsigned int value, vals *result)
97 memset(result, 0, sizeof(*result));
99 /* special case: we prefer shift amount 0 */
101 result->values[0] = value;
108 unsigned v = do_rol(value, 8) & 0xFFFFFF;
117 shf = (initial + shf - 8) & 0x1F;
118 result->values[result->ops] = v;
119 result->shifts[result->ops] = shf;
122 value ^= do_rol(v, shf) >> initial;
132 * Creates a arm_Const node.
134 static ir_node *create_const_node(be_abi_irg_t *abi, dbg_info *dbg, ir_node *block, long value) {
135 ir_mode *mode = mode_Iu;
136 tarval *tv = new_tarval_from_long(value, mode);
139 if (mode_needs_gp_reg(mode))
141 res = new_rd_arm_Mov_i(dbg, current_ir_graph, block, mode, tv);
142 /* ensure the const is schedules AFTER the barrier */
143 add_irn_dep(res, be_abi_get_start_barrier(abi));
148 * Creates a arm_Const_Neg node.
150 static ir_node *create_const_neg_node(be_abi_irg_t *abi, dbg_info *dbg, ir_node *block, long value) {
151 ir_mode *mode = mode_Iu;
152 tarval *tv = new_tarval_from_long(value, mode);
155 if (mode_needs_gp_reg(mode))
157 res = new_rd_arm_Mvn_i(dbg, current_ir_graph, block, mode, tv);
158 add_irn_dep(res, be_abi_get_start_barrier(abi));
159 /* ensure the const is schedules AFTER the barrier */
163 #define NEW_BINOP_NODE(opname, env, op1, op2) new_rd_arm_##opname(env->dbg, current_ir_graph, env->block, op1, op2, env->mode)
166 * Encodes an immediate with shifter operand
168 static unsigned int arm_encode_imm_w_shift(unsigned int shift, unsigned int immediate) {
169 return immediate | ((shift>>1)<<8);
173 * Decode an immediate with shifter operand
175 unsigned int arm_decode_imm_w_shift(tarval *tv) {
176 unsigned l = get_tarval_long(tv);
177 unsigned rol = (l & ~0xFF) >> 7;
179 return do_rol(l & 0xFF, rol);
183 * Creates a possible DAG for an constant.
185 static ir_node *create_const_graph_value(be_abi_irg_t *abi, dbg_info *dbg, ir_node *block, unsigned int value) {
189 ir_mode *mode = mode_Iu;
191 gen_vals_from_word(value, &v);
192 gen_vals_from_word(~value, &vn);
194 if (vn.ops < v.ops) {
196 result = create_const_neg_node(abi, dbg, block, arm_encode_imm_w_shift(vn.shifts[0], vn.values[0]));
198 for (cnt = 1; cnt < vn.ops; ++cnt) {
199 tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]), mode);
200 ir_node *bic_i_node = new_rd_arm_Bic_i(dbg, current_ir_graph, block, result, mode, tv);
206 result = create_const_node(abi, dbg, block, arm_encode_imm_w_shift(v.shifts[0], v.values[0]));
208 for (cnt = 1; cnt < v.ops; ++cnt) {
209 tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]), mode);
210 ir_node *orr_i_node = new_rd_arm_Or_i(dbg, current_ir_graph, block, result, mode, tv);
218 * Create a DAG constructing a given Const.
220 * @param irn a Firm const
222 static ir_node *create_const_graph(be_abi_irg_t *abi, ir_node *irn, ir_node *block) {
223 tarval *tv = get_Const_tarval(irn);
224 ir_mode *mode = get_tarval_mode(tv);
227 if (mode_is_reference(mode)) {
228 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
229 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
230 tv = tarval_convert_to(tv, mode_Iu);
232 value = get_tarval_long(tv);
233 return create_const_graph_value(abi, get_irn_dbg_info(irn), block, value);
237 * Create an And that will mask all upper bits
239 static ir_node *gen_zero_extension(be_abi_irg_t *abi, dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) {
240 unsigned mask_bits = (1 << result_bits) - 1;
241 ir_node *mask_node = create_const_graph_value(abi, dbg, block, mask_bits);
242 return new_rd_arm_And(dbg, current_ir_graph, block, op, mask_node, mode_Iu, ARM_SHF_NONE, NULL);
246 * Generate code for a sign extension.
248 static ir_node *gen_sign_extension(be_abi_irg_t *abi, dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) {
249 ir_graph *irg = current_ir_graph;
250 int shift_width = 32 - result_bits;
251 ir_node *shift_const_node = create_const_graph_value(abi, dbg, block, shift_width);
252 ir_node *lshift_node = new_rd_arm_Shl(dbg, irg, block, op, shift_const_node, mode_Iu);
253 ir_node *rshift_node = new_rd_arm_Shrs(dbg, irg, block, lshift_node, shift_const_node, mode_Iu);
258 * Transforms a Conv node.
260 * @return The created ia32 Conv node
262 static ir_node *gen_Conv(ir_node *node) {
263 ir_node *block = be_transform_node(get_nodes_block(node));
264 ir_node *op = get_Conv_op(node);
265 ir_node *new_op = be_transform_node(op);
266 ir_graph *irg = current_ir_graph;
267 ir_mode *src_mode = get_irn_mode(op);
268 ir_mode *dst_mode = get_irn_mode(node);
269 dbg_info *dbg = get_irn_dbg_info(node);
271 if (src_mode == dst_mode)
274 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
275 env_cg->have_fp_insn = 1;
277 if (USE_FPA(env_cg->isa)) {
278 if (mode_is_float(src_mode)) {
279 if (mode_is_float(dst_mode)) {
280 /* from float to float */
281 return new_rd_arm_fpaMov(dbg, irg, block, new_op, dst_mode);
284 /* from float to int */
285 return new_rd_arm_fpaFix(dbg, irg, block, new_op, dst_mode);
289 /* from int to float */
290 return new_rd_arm_fpaFlt(dbg, irg, block, new_op, dst_mode);
293 else if (USE_VFP(env_cg->isa)) {
294 panic("VFP not supported yet\n");
298 panic("Softfloat not supported yet\n");
302 else { /* complete in gp registers */
303 int src_bits = get_mode_size_bits(src_mode);
304 int dst_bits = get_mode_size_bits(dst_mode);
308 if (is_Load(skip_Proj(op))) {
309 if (src_bits == dst_bits) {
310 /* kill unneccessary conv */
313 /* after a load, the bit size is already converted */
317 if (src_bits == dst_bits) {
318 /* kill unneccessary conv */
320 } else if (dst_bits <= 32 && src_bits <= 32) {
321 if (src_bits < dst_bits) {
328 if (mode_is_signed(min_mode)) {
329 return gen_sign_extension(env_cg->birg->abi, dbg, block, new_op, min_bits);
331 return gen_zero_extension(env_cg->birg->abi, dbg, block, new_op, min_bits);
334 panic("Cannot handle Conv %+F->%+F with %d->%d bits\n", src_mode, dst_mode,
342 * Return true if an operand is a shifter operand
344 static int is_shifter_operand(ir_node *n, arm_shift_modifier *pmod) {
345 arm_shift_modifier mod = ARM_SHF_NONE;
348 mod = get_arm_shift_modifier(n);
351 if (mod != ARM_SHF_NONE) {
352 long v = get_tarval_long(get_arm_value(n));
360 * Creates an ARM Add.
362 * @return the created arm Add node
364 static ir_node *gen_Add(ir_node *node) {
365 ir_node *block = be_transform_node(get_nodes_block(node));
366 ir_node *op1 = get_Add_left(node);
367 ir_node *new_op1 = be_transform_node(op1);
368 ir_node *op2 = get_Add_right(node);
369 ir_node *new_op2 = be_transform_node(op2);
370 ir_mode *mode = get_irn_mode(node);
371 ir_graph *irg = current_ir_graph;
374 arm_shift_modifier mod;
375 dbg_info *dbg = get_irn_dbg_info(node);
377 if (mode_is_float(mode)) {
378 env_cg->have_fp_insn = 1;
379 if (USE_FPA(env_cg->isa))
380 return new_rd_arm_fpaAdd(dbg, irg, block, new_op1, new_op2, mode);
381 else if (USE_VFP(env_cg->isa)) {
382 assert(mode != mode_E && "IEEE Extended FP not supported");
383 panic("VFP not supported yet\n");
387 panic("Softfloat not supported yet\n");
391 assert(mode_is_numP(mode));
393 if (is_arm_Mov_i(new_op1))
394 return new_rd_arm_Add_i(dbg, irg, block, new_op2, mode, get_arm_value(new_op1));
395 if (is_arm_Mov_i(new_op2))
396 return new_rd_arm_Add_i(dbg, irg, block, new_op1, mode, get_arm_value(new_op2));
399 if (is_arm_Mul(new_op1) && get_irn_n_edges(new_op1) == 1) {
401 op2 = get_irn_n(new_op1, 1);
402 op1 = get_irn_n(new_op1, 0);
404 return new_rd_arm_Mla(dbg, irg, block, new_op1, new_op2, new_op3, mode);
406 if (is_arm_Mul(new_op2) && get_irn_n_edges(new_op2) == 1) {
408 new_op1 = get_irn_n(new_op2, 0);
409 new_op2 = get_irn_n(new_op2, 1);
411 return new_rd_arm_Mla(dbg, irg, block, new_op1, new_op2, new_op3, mode);
414 /* is the first a shifter */
415 v = is_shifter_operand(new_op1, &mod);
417 new_op1 = get_irn_n(new_op1, 0);
418 return new_rd_arm_Add(dbg, irg, block, new_op2, new_op1, mode, mod, new_tarval_from_long(v, mode_Iu));
420 /* is the second a shifter */
421 v = is_shifter_operand(new_op2, &mod);
423 new_op2 = get_irn_n(new_op2, 0);
424 return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, mod, new_tarval_from_long(v, mode_Iu));
428 return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, NULL);
433 * Creates an ARM Mul.
435 * @return the created arm Mul node
437 static ir_node *gen_Mul(ir_node *node) {
438 ir_node *block = be_transform_node(get_nodes_block(node));
439 ir_node *op1 = get_Mul_left(node);
440 ir_node *new_op1 = be_transform_node(op1);
441 ir_node *op2 = get_Mul_right(node);
442 ir_node *new_op2 = be_transform_node(op2);
443 ir_mode *mode = get_irn_mode(node);
444 ir_graph *irg = current_ir_graph;
445 dbg_info *dbg = get_irn_dbg_info(node);
447 if (mode_is_float(mode)) {
448 env_cg->have_fp_insn = 1;
449 if (USE_FPA(env_cg->isa))
450 return new_rd_arm_fpaMul(dbg, irg, block, new_op1, new_op2, mode);
451 else if (USE_VFP(env_cg->isa)) {
452 assert(mode != mode_E && "IEEE Extended FP not supported");
453 panic("VFP not supported yet\n");
456 panic("Softfloat not supported yet\n");
460 return new_rd_arm_Mul(dbg, irg, block, new_op1, new_op2, mode);
464 * Creates an ARM floating point Div.
466 * @param env The transformation environment
467 * @return the created arm fDiv node
469 static ir_node *gen_Quot(ir_node *node) {
470 ir_node *block = be_transform_node(get_nodes_block(node));
471 ir_node *op1 = get_Quot_left(node);
472 ir_node *new_op1 = be_transform_node(op1);
473 ir_node *op2 = get_Quot_right(node);
474 ir_node *new_op2 = be_transform_node(op2);
475 ir_mode *mode = get_irn_mode(node);
476 dbg_info *dbg = get_irn_dbg_info(node);
478 assert(mode != mode_E && "IEEE Extended FP not supported");
480 env_cg->have_fp_insn = 1;
481 if (USE_FPA(env_cg->isa))
482 return new_rd_arm_fpaDiv(dbg, current_ir_graph, block, new_op1, new_op2, mode);
483 else if (USE_VFP(env_cg->isa)) {
484 assert(mode != mode_E && "IEEE Extended FP not supported");
485 panic("VFP not supported yet\n");
488 panic("Softfloat not supported yet\n");
493 #define GEN_INT_OP(op) \
494 ir_node *block = be_transform_node(get_nodes_block(node)); \
495 ir_node *op1 = get_ ## op ## _left(node); \
496 ir_node *new_op1 = be_transform_node(op1); \
497 ir_node *op2 = get_ ## op ## _right(node); \
498 ir_node *new_op2 = be_transform_node(op2); \
499 ir_graph *irg = current_ir_graph; \
500 ir_mode *mode = get_irn_mode(node); \
501 dbg_info *dbg = get_irn_dbg_info(node); \
503 arm_shift_modifier mod; \
505 if (is_arm_Mov_i(new_op1)) \
506 return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op2, mode, get_arm_value(new_op1)); \
507 if (is_arm_Mov_i(new_op2)) \
508 return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op1, mode, get_arm_value(new_op2)); \
509 /* is the first a shifter */ \
510 v = is_shifter_operand(new_op1, &mod); \
512 new_op1 = get_irn_n(new_op1, 0); \
513 return new_rd_arm_ ## op(dbg, irg, block, new_op2, new_op1, mode, mod, new_tarval_from_long(v, mode_Iu)); \
515 /* is the second a shifter */ \
516 v = is_shifter_operand(new_op2, &mod); \
518 new_op2 = get_irn_n(new_op2, 0); \
519 return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, mod, new_tarval_from_long(v, mode_Iu)); \
522 return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, NULL) \
525 * Creates an ARM And.
527 * @return the created arm And node
529 static ir_node *gen_And(ir_node *node) {
534 * Creates an ARM Orr.
536 * @param env The transformation environment
537 * @return the created arm Or node
539 static ir_node *gen_Or(ir_node *node) {
544 * Creates an ARM Eor.
546 * @return the created arm Eor node
548 static ir_node *gen_Eor(ir_node *node) {
553 * Creates an ARM Sub.
555 * @return the created arm Sub node
557 static ir_node *gen_Sub(ir_node *node) {
558 ir_node *block = be_transform_node(get_nodes_block(node));
559 ir_node *op1 = get_Sub_left(node);
560 ir_node *new_op1 = be_transform_node(op1);
561 ir_node *op2 = get_Sub_right(node);
562 ir_node *new_op2 = be_transform_node(op2);
563 ir_mode *mode = get_irn_mode(node);
564 ir_graph *irg = current_ir_graph;
565 dbg_info *dbg = get_irn_dbg_info(node);
567 arm_shift_modifier mod;
569 if (mode_is_float(mode)) {
570 env_cg->have_fp_insn = 1;
571 if (USE_FPA(env_cg->isa))
572 return new_rd_arm_fpaSub(dbg, irg, block, new_op1, new_op2, mode);
573 else if (USE_VFP(env_cg->isa)) {
574 assert(mode != mode_E && "IEEE Extended FP not supported");
575 panic("VFP not supported yet\n");
579 panic("Softfloat not supported yet\n");
584 assert(mode_is_numP(mode) && "unknown mode for Sub");
586 if (is_arm_Mov_i(new_op1))
587 return new_rd_arm_Rsb_i(dbg, irg, block, new_op2, mode, get_arm_value(new_op1));
588 if (is_arm_Mov_i(new_op2))
589 return new_rd_arm_Sub_i(dbg, irg, block, new_op1, mode, get_arm_value(new_op2));
591 /* is the first a shifter */
592 v = is_shifter_operand(new_op1, &mod);
594 new_op1 = get_irn_n(new_op1, 0);
595 return new_rd_arm_Rsb(dbg, irg, block, new_op2, new_op1, mode, mod, new_tarval_from_long(v, mode_Iu));
597 /* is the second a shifter */
598 v = is_shifter_operand(new_op2, &mod);
600 new_op2 = get_irn_n(new_op2, 0);
601 return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, mod, new_tarval_from_long(v, mode_Iu));
604 return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, NULL);
609 * Creates an ARM Shl.
611 * @return the created ARM Shl node
613 static ir_node *gen_Shl(ir_node *node) {
614 ir_node *block = be_transform_node(get_nodes_block(node));
615 ir_node *op1 = get_Shl_left(node);
616 ir_node *new_op1 = be_transform_node(op1);
617 ir_node *op2 = get_Shl_right(node);
618 ir_node *new_op2 = be_transform_node(op2);
619 ir_mode *mode = get_irn_mode(node);
620 dbg_info *dbg = get_irn_dbg_info(node);
622 if (is_arm_Mov_i(new_op2)) {
623 return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSL, get_arm_value(new_op2));
625 return new_rd_arm_Shl(dbg, current_ir_graph, block, new_op1, new_op2, mode);
629 * Creates an ARM Shr.
631 * @return the created ARM Shr node
633 static ir_node *gen_Shr(ir_node *node) {
634 ir_node *block = be_transform_node(get_nodes_block(node));
635 ir_node *op1 = get_Shr_left(node);
636 ir_node *new_op1 = be_transform_node(op1);
637 ir_node *op2 = get_Shr_right(node);
638 ir_node *new_op2 = be_transform_node(op2);
639 ir_mode *mode = get_irn_mode(node);
640 dbg_info *dbg = get_irn_dbg_info(node);
642 if (is_arm_Mov_i(new_op2)) {
643 return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSR, get_arm_value(new_op2));
645 return new_rd_arm_Shr(dbg, current_ir_graph, block, new_op1, new_op2, mode);
649 * Creates an ARM Shrs.
651 * @return the created ARM Shrs node
653 static ir_node *gen_Shrs(ir_node *node) {
654 ir_node *block = be_transform_node(get_nodes_block(node));
655 ir_node *op1 = get_Shrs_left(node);
656 ir_node *new_op1 = be_transform_node(op1);
657 ir_node *op2 = get_Shrs_right(node);
658 ir_node *new_op2 = be_transform_node(op2);
659 ir_mode *mode = get_irn_mode(node);
660 dbg_info *dbg = get_irn_dbg_info(node);
662 if (is_arm_Mov_i(new_op2)) {
663 return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_ASR, get_arm_value(op2));
665 return new_rd_arm_Shrs(dbg, current_ir_graph, block, new_op1, new_op2, mode);
669 * Transforms a Not node.
671 * @return the created ARM Not node
673 static ir_node *gen_Not(ir_node *node) {
674 ir_node *block = be_transform_node(get_nodes_block(node));
675 ir_node *op = get_Not_op(node);
676 ir_node *new_op = be_transform_node(op);
677 dbg_info *dbg = get_irn_dbg_info(node);
679 arm_shift_modifier mod = ARM_SHF_NONE;
680 int v = is_shifter_operand(new_op, &mod);
683 new_op = get_irn_n(new_op, 0);
684 tv = new_tarval_from_long(v, mode_Iu);
686 return new_rd_arm_Mvn(dbg, current_ir_graph, block, new_op, get_irn_mode(node), mod, tv);
690 * Transforms an Abs node.
692 * @param env The transformation environment
693 * @return the created ARM Abs node
695 static ir_node *gen_Abs(ir_node *node) {
696 ir_node *block = be_transform_node(get_nodes_block(node));
697 ir_node *op = get_Not_op(node);
698 ir_node *new_op = be_transform_node(op);
699 dbg_info *dbg = get_irn_dbg_info(node);
700 ir_mode *mode = get_irn_mode(node);
702 if (mode_is_float(mode)) {
703 env_cg->have_fp_insn = 1;
704 if (USE_FPA(env_cg->isa))
705 return new_rd_arm_fpaAbs(dbg, current_ir_graph, block, new_op, mode);
706 else if (USE_VFP(env_cg->isa)) {
707 assert(mode != mode_E && "IEEE Extended FP not supported");
708 panic("VFP not supported yet\n");
711 panic("Softfloat not supported yet\n");
714 return new_rd_arm_Abs(dbg, current_ir_graph, block, new_op, mode);
718 * Transforms a Minus node.
720 * @return the created ARM Minus node
722 static ir_node *gen_Minus(ir_node *node) {
723 ir_node *block = be_transform_node(get_nodes_block(node));
724 ir_node *op = get_Minus_op(node);
725 ir_node *new_op = be_transform_node(op);
726 dbg_info *dbg = get_irn_dbg_info(node);
727 ir_mode *mode = get_irn_mode(node);
729 if (mode_is_float(mode)) {
730 env_cg->have_fp_insn = 1;
731 if (USE_FPA(env_cg->isa))
732 return new_rd_arm_fpaMnv(dbg, current_ir_graph, block, op, mode);
733 else if (USE_VFP(env_cg->isa)) {
734 assert(mode != mode_E && "IEEE Extended FP not supported");
735 panic("VFP not supported yet\n");
738 panic("Softfloat not supported yet\n");
741 return new_rd_arm_Rsb_i(dbg, current_ir_graph, block, new_op, mode, get_mode_null(mode));
747 * @return the created ARM Load node
749 static ir_node *gen_Load(ir_node *node) {
750 ir_node *block = be_transform_node(get_nodes_block(node));
751 ir_node *ptr = get_Load_ptr(node);
752 ir_node *new_ptr = be_transform_node(ptr);
753 ir_node *mem = get_Load_mem(node);
754 ir_node *new_mem = be_transform_node(mem);
755 ir_mode *mode = get_Load_mode(node);
756 ir_graph *irg = current_ir_graph;
757 dbg_info *dbg = get_irn_dbg_info(node);
758 ir_node *new_load = NULL;
760 if (mode_is_float(mode)) {
761 env_cg->have_fp_insn = 1;
762 if (USE_FPA(env_cg->isa))
763 new_load = new_rd_arm_fpaLdf(dbg, irg, block, new_ptr, new_mem, mode);
764 else if (USE_VFP(env_cg->isa)) {
765 assert(mode != mode_E && "IEEE Extended FP not supported");
766 panic("VFP not supported yet\n");
769 panic("Softfloat not supported yet\n");
773 assert(mode_is_numP(mode) && "unsupported mode for Load");
775 if (mode_is_signed(mode)) {
776 /* sign extended loads */
777 switch (get_mode_size_bits(mode)) {
779 new_load = new_rd_arm_Loadbs(dbg, irg, block, new_ptr, new_mem);
782 new_load = new_rd_arm_Loadhs(dbg, irg, block, new_ptr, new_mem);
785 new_load = new_rd_arm_Load(dbg, irg, block, new_ptr, new_mem);
788 panic("mode size not supported\n");
791 /* zero extended loads */
792 switch (get_mode_size_bits(mode)) {
794 new_load = new_rd_arm_Loadb(dbg, irg, block, new_ptr, new_mem);
797 new_load = new_rd_arm_Loadh(dbg, irg, block, new_ptr, new_mem);
800 new_load = new_rd_arm_Load(dbg, irg, block, new_ptr, new_mem);
803 panic("mode size not supported\n");
807 set_irn_pinned(new_load, get_irn_pinned(node));
812 * Transforms a Store.
814 * @return the created ARM Store node
816 static ir_node *gen_Store(ir_node *node) {
817 ir_node *block = be_transform_node(get_nodes_block(node));
818 ir_node *ptr = get_Store_ptr(node);
819 ir_node *new_ptr = be_transform_node(ptr);
820 ir_node *mem = get_Store_mem(node);
821 ir_node *new_mem = be_transform_node(mem);
822 ir_node *val = get_Store_value(node);
823 ir_node *new_val = be_transform_node(val);
824 ir_mode *mode = get_irn_mode(val);
825 ir_graph *irg = current_ir_graph;
826 dbg_info *dbg = get_irn_dbg_info(node);
827 ir_node *new_store = NULL;
829 if (mode_is_float(mode)) {
830 env_cg->have_fp_insn = 1;
831 if (USE_FPA(env_cg->isa))
832 new_store = new_rd_arm_fpaStf(dbg, irg, block, new_ptr, new_val, new_mem, mode);
833 else if (USE_VFP(env_cg->isa)) {
834 assert(mode != mode_E && "IEEE Extended FP not supported");
835 panic("VFP not supported yet\n");
837 panic("Softfloat not supported yet\n");
840 assert(mode_is_numP(mode) && "unsupported mode for Store");
841 switch (get_mode_size_bits(mode)) {
843 new_store = new_rd_arm_Storeb(dbg, irg, block, new_ptr, new_val, new_mem);
845 new_store = new_rd_arm_Storeh(dbg, irg, block, new_ptr, new_val, new_mem);
847 new_store = new_rd_arm_Store(dbg, irg, block, new_ptr, new_val, new_mem);
850 set_irn_pinned(new_store, get_irn_pinned(node));
857 * @return the created ARM Cond node
859 static ir_node *gen_Cond(ir_node *node) {
860 ir_node *block = be_transform_node(get_nodes_block(node));
861 ir_node *selector = get_Cond_selector(node);
862 ir_graph *irg = current_ir_graph;
863 dbg_info *dbg = get_irn_dbg_info(node);
864 ir_mode *mode = get_irn_mode(selector);
866 if (mode == mode_b) {
868 ir_node *cmp_node = get_Proj_pred(selector);
869 ir_node *op1 = get_Cmp_left(cmp_node);
870 ir_node *new_op1 = be_transform_node(op1);
871 ir_node *op2 = get_Cmp_right(cmp_node);
872 ir_node *new_op2 = be_transform_node(op2);
874 return new_rd_arm_CondJmp(dbg, irg, block, new_op1, new_op2, get_Proj_proj(selector));
877 ir_node *new_op = be_transform_node(selector);
878 ir_node *const_graph;
882 const ir_edge_t *edge;
889 foreach_out_edge(node, edge) {
890 proj = get_edge_src_irn(edge);
891 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
893 pn = get_Proj_proj(proj);
895 min = pn<min ? pn : min;
896 max = pn>max ? pn : max;
899 n_projs = max - translation + 1;
901 foreach_out_edge(node, edge) {
902 proj = get_edge_src_irn(edge);
903 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
905 pn = get_Proj_proj(proj) - translation;
906 set_Proj_proj(proj, pn);
910 const_graph = create_const_graph_value(env_cg->birg->abi, dbg, block, translation);
911 sub = new_rd_arm_Sub(dbg, irg, block, new_op, const_graph, mode, ARM_SHF_NONE, NULL);
912 return new_rd_arm_SwitchJmp(dbg, irg, block, sub, n_projs, get_Cond_defaultProj(node) - translation);
917 * Returns the name of a SymConst.
918 * @param symc the SymConst
919 * @return name of the SymConst
921 static ident *get_sc_ident(ir_node *symc) {
924 switch (get_SymConst_kind(symc)) {
925 case symconst_addr_name:
926 return get_SymConst_name(symc);
928 case symconst_addr_ent:
929 ent = get_SymConst_entity(symc);
930 mark_entity_visited(ent);
931 return get_entity_ld_ident(ent);
934 assert(0 && "Unsupported SymConst");
941 * Transforms a Const node.
943 * @return The transformed ARM node.
945 static ir_node *gen_Const(ir_node *node) {
946 ir_node *block = be_transform_node(get_nodes_block(node));
947 ir_graph *irg = current_ir_graph;
948 ir_mode *mode = get_irn_mode(node);
949 dbg_info *dbg = get_irn_dbg_info(node);
951 if (mode_is_float(mode)) {
952 env_cg->have_fp_insn = 1;
953 if (USE_FPA(env_cg->isa)) {
954 node = new_rd_arm_fpaConst(dbg, irg, block, get_Const_tarval(node));
955 /* ensure the const is schedules AFTER the barrier */
956 add_irn_dep(node, be_abi_get_start_barrier(env_cg->birg->abi));
959 else if (USE_VFP(env_cg->isa)) {
960 assert(mode != mode_E && "IEEE Extended FP not supported");
961 panic("VFP not supported yet\n");
964 panic("Softfloat not supported yet\n");
967 return create_const_graph(env_cg->birg->abi, node, block);
971 * Transforms a SymConst node.
973 * @return The transformed ARM node.
975 static ir_node *gen_SymConst(ir_node *node) {
976 ir_node *block = be_transform_node(get_nodes_block(node));
977 ir_mode *mode = get_irn_mode(node);
978 dbg_info *dbg = get_irn_dbg_info(node);
981 res = new_rd_arm_SymConst(dbg, current_ir_graph, block, mode, get_sc_ident(node));
982 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
983 /* ensure the const is schedules AFTER the barrier */
988 * Transforms a CopyB node.
990 * @return The transformed ARM node.
992 static ir_node *gen_CopyB(ir_node *node) {
993 ir_node *block = be_transform_node(get_nodes_block(node));
994 ir_node *src = get_CopyB_src(node);
995 ir_node *new_src = be_transform_node(src);
996 ir_node *dst = get_CopyB_dst(node);
997 ir_node *new_dst = be_transform_node(dst);
998 ir_node *mem = get_CopyB_mem(node);
999 ir_node *new_mem = be_transform_node(mem);
1000 ir_graph *irg = current_ir_graph;
1001 dbg_info *dbg = get_irn_dbg_info(node);
1002 int size = get_type_size_bytes(get_CopyB_type(node));
1006 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, new_src);
1007 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, new_dst);
1009 return new_rd_arm_CopyB(dbg, irg, block, dst_copy, src_copy,
1010 new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu),
1011 new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu),
1012 new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu),
1013 new_mem, new_tarval_from_long(size, mode_Iu));
1017 /********************************************
1020 * | |__ ___ _ __ ___ __| | ___ ___
1021 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1022 * | |_) | __/ | | | (_) | (_| | __/\__ \
1023 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1025 ********************************************/
1028 * Return an expanding stack offset.
1029 * Note that function is called in the transform phase
1030 * where the stack offsets are still relative regarding
1031 * the first (frame allocating) IncSP.
1032 * However this is exactly what we want because frame
1033 * access must be done relative the the fist IncSP ...
1035 static int get_sp_expand_offset(ir_node *inc_sp) {
1036 int offset = be_get_IncSP_offset(inc_sp);
1038 if (offset == BE_STACK_FRAME_SIZE_EXPAND)
1045 static ir_node *gen_StackParam(ir_node *irn) {
1046 ir_node *block = be_transform_node(get_nodes_block(node));
1047 ir_node *new_op = NULL;
1048 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1049 ir_node *mem = new_rd_NoMem(env->irg);
1050 ir_node *ptr = get_irn_n(irn, 0);
1051 ir_entity *ent = be_get_frame_entity(irn);
1052 ir_mode *mode = env->mode;
1054 // /* If the StackParam has only one user -> */
1055 // /* put it in the Block where the user resides */
1056 // if (get_irn_n_edges(node) == 1) {
1057 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1060 if (mode_is_float(mode)) {
1061 if (USE_SSE2(env->cg))
1062 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1064 env->cg->used_x87 = 1;
1065 new_op = new_rd_ia32_vfld(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1069 new_op = new_rd_ia32_Load(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1072 set_ia32_frame_ent(new_op, ent);
1073 set_ia32_use_frame(new_op);
1075 set_ia32_am_support(new_op, ia32_am_Source);
1076 set_ia32_op_type(new_op, ia32_AddrModeS);
1077 set_ia32_am_flavour(new_op, ia32_B);
1078 set_ia32_ls_mode(new_op, mode);
1080 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1082 return new_rd_Proj(env->dbg, env->irg, block, new_op, mode, 0);
1087 * Transforms a FrameAddr into an ARM Add.
1089 static ir_node *gen_be_FrameAddr(ir_node *node) {
1090 ir_node *block = be_transform_node(get_nodes_block(node));
1091 ir_entity *ent = be_get_frame_entity(node);
1092 int offset = get_entity_offset(ent);
1093 ir_node *op = be_get_FrameAddr_frame(node);
1094 ir_node *new_op = be_transform_node(op);
1095 dbg_info *dbg = get_irn_dbg_info(node);
1096 ir_mode *mode = mode_Iu;
1099 if (be_is_IncSP(op)) {
1100 /* BEWARE: we get an offset which is absolute from an offset that
1101 is relative. Both must be merged */
1102 offset += get_sp_expand_offset(op);
1104 cnst = create_const_graph_value(env_cg->birg->abi, dbg, block, (unsigned)offset);
1105 if (is_arm_Mov_i(cnst))
1106 return new_rd_arm_Add_i(dbg, current_ir_graph, block, new_op, mode, get_arm_value(cnst));
1107 return new_rd_arm_Add(dbg, current_ir_graph, block, new_op, cnst, mode, ARM_SHF_NONE, NULL);
1112 * Transforms a FrameLoad into an ARM Load.
1114 static ir_node *gen_FrameLoad(ir_node *irn) {
1115 ir_node *new_op = NULL;
1116 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1117 ir_node *mem = get_irn_n(irn, 0);
1118 ir_node *ptr = get_irn_n(irn, 1);
1119 ir_entity *ent = be_get_frame_entity(irn);
1120 ir_mode *mode = get_type_mode(get_entity_type(ent));
1122 if (mode_is_float(mode)) {
1123 if (USE_SSE2(env->cg))
1124 new_op = new_rd_ia32_fLoad(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
1126 env->cg->used_x87 = 1;
1127 new_op = new_rd_ia32_vfld(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
1131 new_op = new_rd_ia32_Load(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
1134 set_ia32_frame_ent(new_op, ent);
1135 set_ia32_use_frame(new_op);
1137 set_ia32_am_support(new_op, ia32_am_Source);
1138 set_ia32_op_type(new_op, ia32_AddrModeS);
1139 set_ia32_am_flavour(new_op, ia32_B);
1140 set_ia32_ls_mode(new_op, mode);
1142 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1149 * Transform a be_AddSP into an arm_AddSP. Eat up const sizes.
1151 static ir_node *gen_be_AddSP(ir_node *node) {
1152 ir_node *block = be_transform_node(get_nodes_block(node));
1153 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
1154 ir_node *new_sz = be_transform_node(sz);
1155 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
1156 ir_node *new_sp = be_transform_node(sp);
1157 ir_graph *irg = current_ir_graph;
1158 dbg_info *dbgi = get_irn_dbg_info(node);
1159 ir_node *nomem = new_NoMem();
1162 /* ARM stack grows in reverse direction, make a SubSP */
1163 new_op = new_rd_arm_SubSP(dbgi, irg, block, new_sp, new_sz, nomem);
1169 * Transform a be_SubSP into an arm_SubSP. Eat up const sizes.
1171 static ir_node *gen_be_SubSP(ir_node *node) {
1172 ir_node *block = be_transform_node(get_nodes_block(node));
1173 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
1174 ir_node *new_sz = be_transform_node(sz);
1175 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
1176 ir_node *new_sp = be_transform_node(sp);
1177 ir_graph *irg = current_ir_graph;
1178 dbg_info *dbgi = get_irn_dbg_info(node);
1179 ir_node *nomem = new_NoMem();
1182 /* ARM stack grows in reverse direction, make an AddSP */
1183 new_op = new_rd_arm_AddSP(dbgi, irg, block, new_sp, new_sz, nomem);
1189 * Transform a be_Copy.
1191 static ir_node *gen_be_Copy(ir_node *node) {
1192 ir_node *result = be_duplicate_node(node);
1193 ir_mode *mode = get_irn_mode(result);
1195 if (mode_needs_gp_reg(mode)) {
1196 set_irn_mode(node, mode_Iu);
1203 * Transform a Proj from a Load.
1205 static ir_node *gen_Proj_Load(ir_node *node) {
1206 ir_node *block = be_transform_node(get_nodes_block(node));
1207 ir_node *load = get_Proj_pred(node);
1208 ir_node *new_load = be_transform_node(load);
1209 ir_graph *irg = current_ir_graph;
1210 dbg_info *dbgi = get_irn_dbg_info(node);
1211 long proj = get_Proj_proj(node);
1213 /* renumber the proj */
1214 switch (get_arm_irn_opcode(new_load)) {
1217 case iro_arm_Loadbs:
1219 case iro_arm_Loadhs:
1220 /* handle all gp loads equal: they have the same proj numbers. */
1221 if (proj == pn_Load_res) {
1222 return new_rd_Proj(dbgi, irg, block, new_load, mode_Iu, pn_arm_Load_res);
1223 } else if (proj == pn_Load_M) {
1224 return new_rd_Proj(dbgi, irg, block, new_load, mode_M, pn_arm_Load_M);
1227 case iro_arm_fpaLdf:
1228 if (proj == pn_Load_res) {
1229 ir_mode *mode = get_Load_mode(load);
1230 return new_rd_Proj(dbgi, irg, block, new_load, mode, pn_arm_fpaLdf_res);
1231 } else if (proj == pn_Load_M) {
1232 return new_rd_Proj(dbgi, irg, block, new_load, mode_M, pn_arm_fpaLdf_M);
1239 return new_rd_Unknown(irg, get_irn_mode(node));
1243 * Transform and renumber the Projs from a CopyB.
1245 static ir_node *gen_Proj_CopyB(ir_node *node) {
1246 ir_node *block = be_transform_node(get_nodes_block(node));
1247 ir_node *pred = get_Proj_pred(node);
1248 ir_node *new_pred = be_transform_node(pred);
1249 ir_graph *irg = current_ir_graph;
1250 dbg_info *dbgi = get_irn_dbg_info(node);
1251 ir_mode *mode = get_irn_mode(node);
1252 long proj = get_Proj_proj(node);
1255 case pn_CopyB_M_regular:
1256 if (is_arm_CopyB(new_pred)) {
1257 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_CopyB_M);
1264 return new_rd_Unknown(irg, mode);
1268 * Transform and renumber the Projs from a Quot.
1270 static ir_node *gen_Proj_Quot(ir_node *node) {
1271 ir_node *block = be_transform_node(get_nodes_block(node));
1272 ir_node *pred = get_Proj_pred(node);
1273 ir_node *new_pred = be_transform_node(pred);
1274 ir_graph *irg = current_ir_graph;
1275 dbg_info *dbgi = get_irn_dbg_info(node);
1276 ir_mode *mode = get_irn_mode(node);
1277 long proj = get_Proj_proj(node);
1281 if (is_arm_fpaDiv(new_pred)) {
1282 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaDiv_M);
1283 } else if (is_arm_fpaRdv(new_pred)) {
1284 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaRdv_M);
1285 } else if (is_arm_fpaFDiv(new_pred)) {
1286 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaFDiv_M);
1287 } else if (is_arm_fpaFRdv(new_pred)) {
1288 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaFRdv_M);
1292 if (is_arm_fpaDiv(new_pred)) {
1293 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaDiv_res);
1294 } else if (is_arm_fpaFDiv(new_pred)) {
1295 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaRdv_res);
1296 } else if (is_arm_fpaFDiv(new_pred)) {
1297 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaFDiv_res);
1298 } else if (is_arm_fpaFDiv(new_pred)) {
1299 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaFRdv_res);
1306 return new_rd_Unknown(irg, mode);
1310 * Transform the Projs of an AddSP.
1312 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
1313 ir_node *block = be_transform_node(get_nodes_block(node));
1314 ir_node *pred = get_Proj_pred(node);
1315 ir_node *new_pred = be_transform_node(pred);
1316 ir_graph *irg = current_ir_graph;
1317 dbg_info *dbgi = get_irn_dbg_info(node);
1318 long proj = get_Proj_proj(node);
1320 if (proj == pn_be_AddSP_res) {
1321 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_arm_AddSP_stack);
1322 arch_set_irn_register(env_cg->arch_env, res, &arm_gp_regs[REG_SP]);
1324 } else if (proj == pn_be_AddSP_M) {
1325 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_AddSP_M);
1329 return new_rd_Unknown(irg, get_irn_mode(node));
1333 * Transform the Projs of a SubSP.
1335 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
1336 ir_node *block = be_transform_node(get_nodes_block(node));
1337 ir_node *pred = get_Proj_pred(node);
1338 ir_node *new_pred = be_transform_node(pred);
1339 ir_graph *irg = current_ir_graph;
1340 dbg_info *dbgi = get_irn_dbg_info(node);
1341 long proj = get_Proj_proj(node);
1343 if (proj == pn_be_SubSP_res) {
1344 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_arm_SubSP_stack);
1345 arch_set_irn_register(env_cg->arch_env, res, &arm_gp_regs[REG_SP]);
1347 } else if (proj == pn_be_SubSP_M) {
1348 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_SubSP_M);
1352 return new_rd_Unknown(irg, get_irn_mode(node));
1356 * Transform the Projs from a Cmp.
1358 static ir_node *gen_Proj_Cmp(ir_node *node) {
1364 * Transform the Thread Local Storage Proj.
1366 static ir_node *gen_Proj_tls(ir_node *node) {
1367 ir_node *block = be_transform_node(get_nodes_block(node));
1368 ir_graph *irg = current_ir_graph;
1369 dbg_info *dbgi = NULL;
1371 return new_rd_arm_LdTls(dbgi, irg, block, mode_Iu);
1375 * Transform a Proj node.
1377 static ir_node *gen_Proj(ir_node *node) {
1378 ir_graph *irg = current_ir_graph;
1379 dbg_info *dbgi = get_irn_dbg_info(node);
1380 ir_node *pred = get_Proj_pred(node);
1381 long proj = get_Proj_proj(node);
1383 if (is_Store(pred) || be_is_FrameStore(pred)) {
1384 if (proj == pn_Store_M) {
1385 return be_transform_node(pred);
1388 return new_r_Bad(irg);
1390 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
1391 return gen_Proj_Load(node);
1392 } else if (is_CopyB(pred)) {
1393 return gen_Proj_CopyB(node);
1394 } else if (is_Quot(pred)) {
1395 return gen_Proj_Quot(node);
1396 } else if (be_is_SubSP(pred)) {
1397 return gen_Proj_be_SubSP(node);
1398 } else if (be_is_AddSP(pred)) {
1399 return gen_Proj_be_AddSP(node);
1400 } else if (is_Cmp(pred)) {
1401 return gen_Proj_Cmp(node);
1402 } else if (get_irn_op(pred) == op_Start) {
1403 if (proj == pn_Start_X_initial_exec) {
1404 ir_node *block = get_nodes_block(pred);
1407 /* we exchange the ProjX with a jump */
1408 block = be_transform_node(block);
1409 jump = new_rd_Jmp(dbgi, irg, block);
1410 ir_fprintf(stderr, "created jump: %+F\n", jump);
1413 if (node == be_get_old_anchor(anchor_tls)) {
1414 return gen_Proj_tls(node);
1417 ir_node *new_pred = be_transform_node(pred);
1418 ir_mode *mode = get_irn_mode(node);
1419 if (mode_needs_gp_reg(mode)) {
1420 ir_node *block = be_transform_node(get_nodes_block(node));
1421 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
1422 get_Proj_proj(node));
1423 #ifdef DEBUG_libfirm
1424 new_proj->node_nr = node->node_nr;
1430 return be_duplicate_node(node);
1434 * This function just sets the register for the Unknown node
1435 * as this is not done during register allocation because Unknown
1436 * is an "ignore" node.
1438 static ir_node *gen_Unknown(ir_node *node) {
1439 ir_mode *mode = get_irn_mode(node);
1441 if (mode_is_float(mode)) {
1442 if (USE_FPA(env_cg->isa))
1443 return arm_new_Unknown_fpa(env_cg);
1444 else if (USE_VFP(env_cg->isa))
1445 return arm_new_Unknown_vfp(env_cg);
1447 panic("Softfloat not supported yet");
1448 } else if (mode_needs_gp_reg(mode)) {
1449 return ia32_new_Unknown_gp(env_cg);
1451 assert(0 && "unsupported Unknown-Mode");
1454 panic("Unknown NYI\n");
1459 * Change some phi modes
1461 static ir_node *gen_Phi(ir_node *node) {
1462 ir_node *block = be_transform_node(get_nodes_block(node));
1463 ir_graph *irg = current_ir_graph;
1464 dbg_info *dbgi = get_irn_dbg_info(node);
1465 ir_mode *mode = get_irn_mode(node);
1468 if (mode_needs_gp_reg(mode)) {
1469 /* we shouldn't have any 64bit stuff around anymore */
1470 assert(get_mode_size_bits(mode) <= 32);
1471 /* all integer operations are on 32bit registers now */
1475 /* phi nodes allow loops, so we use the old arguments for now
1476 * and fix this later */
1477 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
1478 copy_node_attr(node, phi);
1479 be_duplicate_deps(node, phi);
1481 be_set_transformed_node(node, phi);
1482 be_enqueue_preds(node);
1487 /*********************************************************
1490 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1491 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1492 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1493 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1495 *********************************************************/
1498 * the BAD transformer.
1500 static ir_node *bad_transform(ir_node *irn) {
1501 panic("ARM backend: Not implemented: %+F\n", irn);
1506 * Set a node emitter. Make it a bit more type safe.
1508 static INLINE void set_transformer(ir_op *op, be_transform_func arm_transform_func) {
1509 op->ops.generic = (op_func)arm_transform_func;
1513 * Enters all transform functions into the generic pointer
1515 static void arm_register_transformers(void) {
1516 ir_op *op_Max, *op_Min, *op_Mulh;
1518 /* first clear the generic function pointer for all ops */
1519 clear_irp_opcodes_generic_func();
1521 #define GEN(a) set_transformer(op_##a, gen_##a)
1522 #define BAD(a) set_transformer(op_##a, bad_transform)
1535 BAD(Rot); /* unsupported yet */
1539 /* should be lowered */
1553 BAD(ASM); /* unsupported yet */
1556 BAD(Psi); /* unsupported yet */
1566 /* we should never see these nodes */
1581 /* handle generic backend nodes */
1585 BAD(be_FrameLoad); /* unsupported yet */
1586 BAD(be_FrameStore); /* unsupported yet */
1587 BAD(be_StackParam); /* unsupported yet */
1592 /* set the register for all Unknown nodes */
1595 op_Max = get_op_Max();
1597 BAD(Max); /* unsupported yet */
1598 op_Min = get_op_Min();
1600 BAD(Min); /* unsupported yet */
1601 op_Mulh = get_op_Mulh();
1603 BAD(Mulh); /* unsupported yet */
1611 * Pre-transform all unknown and noreg nodes.
1613 static void arm_pretransform_node(void *arch_cg) {
1614 arm_code_gen_t *cg = arch_cg;
1618 * Transform a Firm graph into an ARM graph.
1620 void arm_transform_graph(arm_code_gen_t *cg) {
1621 arm_register_transformers();
1623 be_transform_graph(cg->birg, /*arm_pretransform_node*/ NULL, cg);
1626 void arm_init_transform(void) {
1627 // FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");