2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
41 #include "../benode.h"
43 #include "../beutil.h"
44 #include "../betranshlp.h"
45 #include "../beabihelper.h"
48 #include "bearch_arm_t.h"
49 #include "arm_nodes_attr.h"
50 #include "arm_transform.h"
51 #include "arm_optimize.h"
52 #include "arm_new_nodes.h"
53 #include "arm_map_regs.h"
54 #include "arm_cconv.h"
56 #include "gen_arm_regalloc_if.h"
60 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 /** hold the current code generator during transformation */
63 static arm_code_gen_t *env_cg;
65 static const arch_register_t *sp_reg = &arm_gp_regs[REG_SP];
66 static ir_mode *mode_gp;
67 static ir_mode *mode_fp;
68 static beabi_helper_env_t *abihelper;
69 static calling_convention_t *cconv = NULL;
71 static pmap *node_to_stack;
73 static bool mode_needs_gp_reg(ir_mode *mode)
75 return mode_is_int(mode) || mode_is_reference(mode);
79 * create firm graph for a constant
81 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
88 /* We only have 8 bit immediates. So we possibly have to combine several
89 * operations to construct the desired value.
91 * we can either create the value by adding bits to 0 or by removing bits
92 * from an register with all bits set. Try which alternative needs fewer
94 arm_gen_vals_from_word(value, &v);
95 arm_gen_vals_from_word(~value, &vn);
99 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
100 be_dep_on_frame(result);
102 for (cnt = 1; cnt < vn.ops; ++cnt) {
103 result = new_bd_arm_Bic_imm(dbgi, block, result,
104 vn.values[cnt], vn.rors[cnt]);
108 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
109 be_dep_on_frame(result);
111 for (cnt = 1; cnt < v.ops; ++cnt) {
112 result = new_bd_arm_Or_imm(dbgi, block, result,
113 v.values[cnt], v.rors[cnt]);
120 * Create a DAG constructing a given Const.
122 * @param irn a Firm const
124 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
126 tarval *tv = get_Const_tarval(irn);
127 ir_mode *mode = get_tarval_mode(tv);
130 if (mode_is_reference(mode)) {
131 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
132 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
133 tv = tarval_convert_to(tv, mode_Iu);
135 value = get_tarval_long(tv);
136 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
140 * Create an And that will zero out upper bits.
142 * @param dbgi debug info
143 * @param block the basic block
144 * @param op the original node
145 * param src_bits number of lower bits that will remain
147 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
151 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
152 } else if (src_bits == 16) {
153 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
154 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
157 panic("zero extension only supported for 8 and 16 bits");
162 * Generate code for a sign extension.
164 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
167 int shift_width = 32 - src_bits;
168 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
169 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
173 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
176 int bits = get_mode_size_bits(orig_mode);
180 if (mode_is_signed(orig_mode)) {
181 return gen_sign_extension(dbgi, block, op, bits);
183 return gen_zero_extension(dbgi, block, op, bits);
188 * returns true if it is assured, that the upper bits of a node are "clean"
189 * which means for a 16 or 8 bit value, that the upper bits in the register
190 * are 0 for unsigned and a copy of the last significant bit for signed
193 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
195 (void) transformed_node;
202 * Transforms a Conv node.
204 * @return The created ia32 Conv node
206 static ir_node *gen_Conv(ir_node *node)
208 ir_node *block = be_transform_node(get_nodes_block(node));
209 ir_node *op = get_Conv_op(node);
210 ir_node *new_op = be_transform_node(op);
211 ir_mode *src_mode = get_irn_mode(op);
212 ir_mode *dst_mode = get_irn_mode(node);
213 dbg_info *dbg = get_irn_dbg_info(node);
215 if (src_mode == dst_mode)
218 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
219 if (USE_FPA(env_cg->isa)) {
220 if (mode_is_float(src_mode)) {
221 if (mode_is_float(dst_mode)) {
222 /* from float to float */
223 return new_bd_arm_Mvf(dbg, block, new_op, dst_mode);
225 /* from float to int */
229 /* from int to float */
230 if (!mode_is_signed(src_mode)) {
233 return new_bd_arm_FltX(dbg, block, new_op, dst_mode);
236 } else if (USE_VFP(env_cg->isa)) {
237 panic("VFP not supported yet");
239 panic("Softfloat not supported yet");
241 } else { /* complete in gp registers */
242 int src_bits = get_mode_size_bits(src_mode);
243 int dst_bits = get_mode_size_bits(dst_mode);
247 if (src_bits == dst_bits) {
248 /* kill unnecessary conv */
252 if (src_bits < dst_bits) {
260 if (upper_bits_clean(new_op, min_mode)) {
264 if (mode_is_signed(min_mode)) {
265 return gen_sign_extension(dbg, block, new_op, min_bits);
267 return gen_zero_extension(dbg, block, new_op, min_bits);
277 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
279 unsigned val, low_pos, high_pos;
284 val = get_tarval_long(get_Const_tarval(node));
296 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
298 So we determine the smallest even position with a bit set
299 and the highest even position with no bit set anymore.
300 If the difference between these 2 is <= 8, then we can encode the value
303 low_pos = ntz(val) & ~1u;
304 high_pos = (32-nlz(val)+1) & ~1u;
306 if (high_pos - low_pos <= 8) {
307 res->imm_8 = val >> low_pos;
308 res->rot = 32 - low_pos;
313 res->rot = 34 - high_pos;
314 val = val >> (32-res->rot) | val << (res->rot);
324 static bool is_downconv(const ir_node *node)
332 /* we only want to skip the conv when we're the only user
333 * (not optimal but for now...)
335 if (get_irn_n_edges(node) > 1)
338 src_mode = get_irn_mode(get_Conv_op(node));
339 dest_mode = get_irn_mode(node);
341 mode_needs_gp_reg(src_mode) &&
342 mode_needs_gp_reg(dest_mode) &&
343 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
346 static ir_node *arm_skip_downconv(ir_node *node)
348 while (is_downconv(node))
349 node = get_Conv_op(node);
355 MATCH_COMMUTATIVE = 1 << 0, /**< commutative node */
356 MATCH_SIZE_NEUTRAL = 1 << 1,
357 MATCH_SKIP_NOT = 1 << 2, /**< skip Not on ONE input */
361 * possible binop constructors.
363 typedef struct arm_binop_factory_t {
364 /** normal reg op reg operation. */
365 ir_node *(*new_binop_reg)(dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
366 /** normal reg op imm operation. */
367 ir_node *(*new_binop_imm)(dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
368 /** barrel shifter reg op (reg shift reg operation. */
369 ir_node *(*new_binop_reg_shift_reg)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *shift, arm_shift_modifier_t shift_modifier);
370 /** barrel shifter reg op (reg shift imm operation. */
371 ir_node *(*new_binop_reg_shift_imm)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, arm_shift_modifier_t shift_modifier, unsigned shift_immediate);
372 } arm_binop_factory_t;
374 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
375 const arm_binop_factory_t *factory)
377 ir_node *block = be_transform_node(get_nodes_block(node));
378 ir_node *op1 = get_binop_left(node);
380 ir_node *op2 = get_binop_right(node);
382 dbg_info *dbgi = get_irn_dbg_info(node);
385 if (flags & MATCH_SKIP_NOT) {
387 op1 = get_Not_op(op1);
388 else if (is_Not(op2))
389 op2 = get_Not_op(op2);
391 panic("cannot execute MATCH_SKIP_NOT");
393 if (flags & MATCH_SIZE_NEUTRAL) {
394 op1 = arm_skip_downconv(op1);
395 op2 = arm_skip_downconv(op2);
397 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
400 if (try_encode_as_immediate(op2, &imm)) {
401 ir_node *new_op1 = be_transform_node(op1);
402 return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
404 new_op2 = be_transform_node(op2);
405 if ((flags & MATCH_COMMUTATIVE) && try_encode_as_immediate(op1, &imm)) {
406 return factory->new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
408 new_op1 = be_transform_node(op1);
410 /* check if we can fold in a Mov */
411 if (is_arm_Mov(new_op2)) {
412 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op2);
414 switch (attr->shift_modifier) {
415 ir_node *mov_op, *mov_sft;
418 case ARM_SHF_ASR_IMM:
419 case ARM_SHF_LSL_IMM:
420 case ARM_SHF_LSR_IMM:
421 case ARM_SHF_ROR_IMM:
422 if (factory->new_binop_reg_shift_imm) {
423 mov_op = get_irn_n(new_op2, 0);
424 return factory->new_binop_reg_shift_imm(dbgi, block, new_op1, mov_op,
425 attr->shift_modifier, attr->shift_immediate);
429 case ARM_SHF_ASR_REG:
430 case ARM_SHF_LSL_REG:
431 case ARM_SHF_LSR_REG:
432 case ARM_SHF_ROR_REG:
433 if (factory->new_binop_reg_shift_reg) {
434 mov_op = get_irn_n(new_op2, 0);
435 mov_sft = get_irn_n(new_op2, 1);
436 return factory->new_binop_reg_shift_reg(dbgi, block, new_op1, mov_op, mov_sft,
437 attr->shift_modifier);
442 if ((flags & MATCH_COMMUTATIVE) && is_arm_Mov(new_op1)) {
443 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op1);
445 switch (attr->shift_modifier) {
446 ir_node *mov_op, *mov_sft;
449 case ARM_SHF_ASR_IMM:
450 case ARM_SHF_LSL_IMM:
451 case ARM_SHF_LSR_IMM:
452 case ARM_SHF_ROR_IMM:
453 if (factory->new_binop_reg_shift_imm) {
454 mov_op = get_irn_n(new_op1, 0);
455 return factory->new_binop_reg_shift_imm(dbgi, block, new_op2, mov_op,
456 attr->shift_modifier, attr->shift_immediate);
460 case ARM_SHF_ASR_REG:
461 case ARM_SHF_LSL_REG:
462 case ARM_SHF_LSR_REG:
463 case ARM_SHF_ROR_REG:
464 if (factory->new_binop_reg_shift_reg) {
465 mov_op = get_irn_n(new_op1, 0);
466 mov_sft = get_irn_n(new_op1, 1);
467 return factory->new_binop_reg_shift_reg(dbgi, block, new_op2, mov_op, mov_sft,
468 attr->shift_modifier);
473 return factory->new_binop_reg(dbgi, block, new_op1, new_op2);
477 * Creates an ARM Add.
479 * @return the created arm Add node
481 static ir_node *gen_Add(ir_node *node)
483 static const arm_binop_factory_t add_factory = {
486 new_bd_arm_Add_reg_shift_reg,
487 new_bd_arm_Add_reg_shift_imm
490 ir_mode *mode = get_irn_mode(node);
492 if (mode_is_float(mode)) {
493 ir_node *block = be_transform_node(get_nodes_block(node));
494 ir_node *op1 = get_Add_left(node);
495 ir_node *op2 = get_Add_right(node);
496 dbg_info *dbgi = get_irn_dbg_info(node);
497 ir_node *new_op1 = be_transform_node(op1);
498 ir_node *new_op2 = be_transform_node(op2);
499 if (USE_FPA(env_cg->isa)) {
500 return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
501 } else if (USE_VFP(env_cg->isa)) {
502 assert(mode != mode_E && "IEEE Extended FP not supported");
503 panic("VFP not supported yet");
505 panic("Softfloat not supported yet");
510 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
512 new_op2 = get_irn_n(new_op1, 1);
513 new_op1 = get_irn_n(new_op1, 0);
515 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
517 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
519 new_op1 = get_irn_n(new_op2, 0);
520 new_op2 = get_irn_n(new_op2, 1);
522 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
526 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &add_factory);
531 * Creates an ARM Mul.
533 * @return the created arm Mul node
535 static ir_node *gen_Mul(ir_node *node)
537 ir_node *block = be_transform_node(get_nodes_block(node));
538 ir_node *op1 = get_Mul_left(node);
539 ir_node *new_op1 = be_transform_node(op1);
540 ir_node *op2 = get_Mul_right(node);
541 ir_node *new_op2 = be_transform_node(op2);
542 ir_mode *mode = get_irn_mode(node);
543 dbg_info *dbg = get_irn_dbg_info(node);
545 if (mode_is_float(mode)) {
546 if (USE_FPA(env_cg->isa)) {
547 return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
548 } else if (USE_VFP(env_cg->isa)) {
549 assert(mode != mode_E && "IEEE Extended FP not supported");
550 panic("VFP not supported yet");
552 panic("Softfloat not supported yet");
555 assert(mode_is_data(mode));
556 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
559 static ir_node *gen_Quot(ir_node *node)
561 ir_node *block = be_transform_node(get_nodes_block(node));
562 ir_node *op1 = get_Quot_left(node);
563 ir_node *new_op1 = be_transform_node(op1);
564 ir_node *op2 = get_Quot_right(node);
565 ir_node *new_op2 = be_transform_node(op2);
566 ir_mode *mode = get_irn_mode(node);
567 dbg_info *dbg = get_irn_dbg_info(node);
569 assert(mode != mode_E && "IEEE Extended FP not supported");
571 if (USE_FPA(env_cg->isa)) {
572 return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
573 } else if (USE_VFP(env_cg->isa)) {
574 assert(mode != mode_E && "IEEE Extended FP not supported");
575 panic("VFP not supported yet");
577 panic("Softfloat not supported yet");
581 static ir_node *gen_And(ir_node *node)
583 static const arm_binop_factory_t and_factory = {
586 new_bd_arm_And_reg_shift_reg,
587 new_bd_arm_And_reg_shift_imm
589 static const arm_binop_factory_t bic_factory = {
592 new_bd_arm_Bic_reg_shift_reg,
593 new_bd_arm_Bic_reg_shift_imm
596 /* check for and not */
597 ir_node *left = get_And_left(node);
598 ir_node *right = get_And_right(node);
600 if (is_Not(left) || is_Not(right)) {
601 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL | MATCH_SKIP_NOT,
605 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &and_factory);
608 static ir_node *gen_Or(ir_node *node)
610 static const arm_binop_factory_t or_factory = {
613 new_bd_arm_Or_reg_shift_reg,
614 new_bd_arm_Or_reg_shift_imm
617 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &or_factory);
620 static ir_node *gen_Eor(ir_node *node)
622 static const arm_binop_factory_t eor_factory = {
625 new_bd_arm_Eor_reg_shift_reg,
626 new_bd_arm_Eor_reg_shift_imm
629 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &eor_factory);
632 static ir_node *gen_Sub(ir_node *node)
634 static const arm_binop_factory_t sub_factory = {
637 new_bd_arm_Sub_reg_shift_reg,
638 new_bd_arm_Sub_reg_shift_imm
641 ir_node *block = be_transform_node(get_nodes_block(node));
642 ir_node *op1 = get_Sub_left(node);
643 ir_node *new_op1 = be_transform_node(op1);
644 ir_node *op2 = get_Sub_right(node);
645 ir_node *new_op2 = be_transform_node(op2);
646 ir_mode *mode = get_irn_mode(node);
647 dbg_info *dbgi = get_irn_dbg_info(node);
649 if (mode_is_float(mode)) {
650 if (USE_FPA(env_cg->isa)) {
651 return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
652 } else if (USE_VFP(env_cg->isa)) {
653 assert(mode != mode_E && "IEEE Extended FP not supported");
654 panic("VFP not supported yet");
656 panic("Softfloat not supported yet");
659 return gen_int_binop(node, MATCH_SIZE_NEUTRAL, &sub_factory);
664 * Checks if a given value can be used as an immediate for the given
667 static bool can_use_shift_constant(unsigned int val,
668 arm_shift_modifier_t modifier)
672 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
678 * generate an ARM shift instruction.
680 * @param node the node
681 * @param flags matching flags
682 * @param shift_modifier initial encoding of the desired shift operation
684 static ir_node *make_shift(ir_node *node, match_flags_t flags,
685 arm_shift_modifier_t shift_modifier)
687 ir_node *block = be_transform_node(get_nodes_block(node));
688 ir_node *op1 = get_binop_left(node);
689 ir_node *op2 = get_binop_right(node);
690 dbg_info *dbgi = get_irn_dbg_info(node);
694 if (flags & MATCH_SIZE_NEUTRAL) {
695 op1 = arm_skip_downconv(op1);
696 op2 = arm_skip_downconv(op2);
699 new_op1 = be_transform_node(op1);
701 tarval *tv = get_Const_tarval(op2);
702 unsigned int val = get_tarval_long(tv);
703 assert(tarval_is_long(tv));
704 if (can_use_shift_constant(val, shift_modifier)) {
705 switch (shift_modifier) {
706 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
707 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
708 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
709 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
710 default: panic("unexpected shift modifier");
712 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
713 shift_modifier, val);
717 new_op2 = be_transform_node(op2);
718 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
722 static ir_node *gen_Shl(ir_node *node)
724 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
727 static ir_node *gen_Shr(ir_node *node)
729 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
732 static ir_node *gen_Shrs(ir_node *node)
734 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
737 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
739 ir_node *block = be_transform_node(get_nodes_block(node));
740 ir_node *new_op1 = be_transform_node(op1);
741 dbg_info *dbgi = get_irn_dbg_info(node);
742 ir_node *new_op2 = be_transform_node(op2);
744 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
748 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
750 ir_node *block = be_transform_node(get_nodes_block(node));
751 ir_node *new_op1 = be_transform_node(op1);
752 dbg_info *dbgi = get_irn_dbg_info(node);
753 ir_node *new_op2 = be_transform_node(op2);
755 /* Note: there is no Rol on arm, we have to use Ror */
756 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
757 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
761 static ir_node *gen_Rotl(ir_node *node)
763 ir_node *rotate = NULL;
764 ir_node *op1 = get_Rotl_left(node);
765 ir_node *op2 = get_Rotl_right(node);
767 /* Firm has only RotL, so we are looking for a right (op2)
768 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
769 that means we can create a RotR. */
772 ir_node *right = get_Add_right(op2);
773 if (is_Const(right)) {
774 tarval *tv = get_Const_tarval(right);
775 ir_mode *mode = get_irn_mode(node);
776 long bits = get_mode_size_bits(mode);
777 ir_node *left = get_Add_left(op2);
779 if (is_Minus(left) &&
780 tarval_is_long(tv) &&
781 get_tarval_long(tv) == bits &&
783 rotate = gen_Ror(node, op1, get_Minus_op(left));
785 } else if (is_Sub(op2)) {
786 ir_node *left = get_Sub_left(op2);
787 if (is_Const(left)) {
788 tarval *tv = get_Const_tarval(left);
789 ir_mode *mode = get_irn_mode(node);
790 long bits = get_mode_size_bits(mode);
791 ir_node *right = get_Sub_right(op2);
793 if (tarval_is_long(tv) &&
794 get_tarval_long(tv) == bits &&
796 rotate = gen_Ror(node, op1, right);
798 } else if (is_Const(op2)) {
799 tarval *tv = get_Const_tarval(op2);
800 ir_mode *mode = get_irn_mode(node);
801 long bits = get_mode_size_bits(mode);
803 if (tarval_is_long(tv) && bits == 32) {
804 ir_node *block = be_transform_node(get_nodes_block(node));
805 ir_node *new_op1 = be_transform_node(op1);
806 dbg_info *dbgi = get_irn_dbg_info(node);
808 bits = (bits - get_tarval_long(tv)) & 31;
809 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
813 if (rotate == NULL) {
814 rotate = gen_Rol(node, op1, op2);
820 static ir_node *gen_Not(ir_node *node)
822 ir_node *block = be_transform_node(get_nodes_block(node));
823 ir_node *op = get_Not_op(node);
824 ir_node *new_op = be_transform_node(op);
825 dbg_info *dbgi = get_irn_dbg_info(node);
827 /* TODO: we could do alot more here with all the Mvn variations */
829 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
832 static ir_node *gen_Minus(ir_node *node)
834 ir_node *block = be_transform_node(get_nodes_block(node));
835 ir_node *op = get_Minus_op(node);
836 ir_node *new_op = be_transform_node(op);
837 dbg_info *dbgi = get_irn_dbg_info(node);
838 ir_mode *mode = get_irn_mode(node);
840 if (mode_is_float(mode)) {
841 if (USE_FPA(env_cg->isa)) {
842 return new_bd_arm_Mvf(dbgi, block, op, mode);
843 } else if (USE_VFP(env_cg->isa)) {
844 assert(mode != mode_E && "IEEE Extended FP not supported");
845 panic("VFP not supported yet");
847 panic("Softfloat not supported yet");
850 assert(mode_is_data(mode));
851 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
854 static ir_node *gen_Load(ir_node *node)
856 ir_node *block = be_transform_node(get_nodes_block(node));
857 ir_node *ptr = get_Load_ptr(node);
858 ir_node *new_ptr = be_transform_node(ptr);
859 ir_node *mem = get_Load_mem(node);
860 ir_node *new_mem = be_transform_node(mem);
861 ir_mode *mode = get_Load_mode(node);
862 dbg_info *dbgi = get_irn_dbg_info(node);
863 ir_node *new_load = NULL;
865 if (mode_is_float(mode)) {
866 if (USE_FPA(env_cg->isa)) {
867 new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
869 } else if (USE_VFP(env_cg->isa)) {
870 assert(mode != mode_E && "IEEE Extended FP not supported");
871 panic("VFP not supported yet");
873 panic("Softfloat not supported yet");
876 assert(mode_is_data(mode) && "unsupported mode for Load");
878 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
880 set_irn_pinned(new_load, get_irn_pinned(node));
882 /* check for special case: the loaded value might not be used */
883 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
884 /* add a result proj and a Keep to produce a pseudo use */
885 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
886 be_new_Keep(block, 1, &proj);
892 static ir_node *gen_Store(ir_node *node)
894 ir_node *block = be_transform_node(get_nodes_block(node));
895 ir_node *ptr = get_Store_ptr(node);
896 ir_node *new_ptr = be_transform_node(ptr);
897 ir_node *mem = get_Store_mem(node);
898 ir_node *new_mem = be_transform_node(mem);
899 ir_node *val = get_Store_value(node);
900 ir_node *new_val = be_transform_node(val);
901 ir_mode *mode = get_irn_mode(val);
902 dbg_info *dbgi = get_irn_dbg_info(node);
903 ir_node *new_store = NULL;
905 if (mode_is_float(mode)) {
906 if (USE_FPA(env_cg->isa)) {
907 new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
908 new_mem, mode, NULL, 0, 0, false);
909 } else if (USE_VFP(env_cg->isa)) {
910 assert(mode != mode_E && "IEEE Extended FP not supported");
911 panic("VFP not supported yet");
913 panic("Softfloat not supported yet");
916 assert(mode_is_data(mode) && "unsupported mode for Store");
917 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
920 set_irn_pinned(new_store, get_irn_pinned(node));
924 static ir_node *gen_Jmp(ir_node *node)
926 ir_node *block = get_nodes_block(node);
927 ir_node *new_block = be_transform_node(block);
928 dbg_info *dbgi = get_irn_dbg_info(node);
930 return new_bd_arm_Jmp(dbgi, new_block);
933 static ir_node *gen_SwitchJmp(ir_node *node)
935 ir_node *block = be_transform_node(get_nodes_block(node));
936 ir_node *selector = get_Cond_selector(node);
937 dbg_info *dbgi = get_irn_dbg_info(node);
938 ir_node *new_op = be_transform_node(selector);
939 ir_node *const_graph;
943 const ir_edge_t *edge;
950 foreach_out_edge(node, edge) {
951 proj = get_edge_src_irn(edge);
952 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
954 pn = get_Proj_proj(proj);
956 min = pn<min ? pn : min;
957 max = pn>max ? pn : max;
960 n_projs = max - translation + 1;
962 foreach_out_edge(node, edge) {
963 proj = get_edge_src_irn(edge);
964 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
966 pn = get_Proj_proj(proj) - translation;
967 set_Proj_proj(proj, pn);
970 const_graph = create_const_graph_value(dbgi, block, translation);
971 sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
972 return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
975 static ir_node *gen_Cmp(ir_node *node)
977 ir_node *block = be_transform_node(get_nodes_block(node));
978 ir_node *op1 = get_Cmp_left(node);
979 ir_node *op2 = get_Cmp_right(node);
980 ir_mode *cmp_mode = get_irn_mode(op1);
981 dbg_info *dbgi = get_irn_dbg_info(node);
986 if (mode_is_float(cmp_mode)) {
987 /* TODO: this is broken... */
988 new_op1 = be_transform_node(op1);
989 new_op2 = be_transform_node(op2);
991 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
993 panic("FloatCmp NIY");
995 ir_node *new_op2 = be_transform_node(op2);
996 /* floating point compare */
997 pn_Cmp pnc = get_Proj_proj(selector);
999 if (pnc & pn_Cmp_Uo) {
1000 /* check for unordered, need cmf */
1001 return new_bd_arm_CmfBra(dbgi, block, new_op1, new_op2, pnc);
1003 /* Hmm: use need cmfe */
1004 return new_bd_arm_CmfeBra(dbgi, block, new_op1, new_op2, pnc);
1008 assert(get_irn_mode(op2) == cmp_mode);
1009 is_unsigned = !mode_is_signed(cmp_mode);
1011 /* compare with 0 can be done with Tst */
1012 if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) {
1013 new_op1 = be_transform_node(op1);
1014 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
1015 return new_bd_arm_Tst_reg(dbgi, block, new_op1, new_op1, false,
1018 if (is_Const(op1) && tarval_is_null(get_Const_tarval(op1))) {
1019 new_op2 = be_transform_node(op2);
1020 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
1021 return new_bd_arm_Tst_reg(dbgi, block, new_op2, new_op2, true,
1025 /* integer compare, TODO: use shifter_op in all its combinations */
1026 new_op1 = be_transform_node(op1);
1027 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
1028 new_op2 = be_transform_node(op2);
1029 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
1030 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
1034 static ir_node *gen_Cond(ir_node *node)
1036 ir_node *selector = get_Cond_selector(node);
1037 ir_mode *mode = get_irn_mode(selector);
1042 if (mode != mode_b) {
1043 return gen_SwitchJmp(node);
1045 assert(is_Proj(selector));
1047 block = be_transform_node(get_nodes_block(node));
1048 dbgi = get_irn_dbg_info(node);
1049 flag_node = be_transform_node(get_Proj_pred(selector));
1051 return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector));
1054 static tarval *fpa_imm[3][fpa_max];
1058 * Check, if a floating point tarval is an fpa immediate, i.e.
1059 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
1061 static int is_fpa_immediate(tarval *tv)
1063 ir_mode *mode = get_tarval_mode(tv);
1066 switch (get_mode_size_bits(mode)) {
1077 if (tarval_is_negative(tv)) {
1078 tv = tarval_neg(tv);
1082 for (j = 0; j < fpa_max; ++j) {
1083 if (tv == fpa_imm[i][j])
1090 static ir_node *gen_Const(ir_node *node)
1092 ir_node *block = be_transform_node(get_nodes_block(node));
1093 ir_mode *mode = get_irn_mode(node);
1094 dbg_info *dbg = get_irn_dbg_info(node);
1096 if (mode_is_float(mode)) {
1097 if (USE_FPA(env_cg->isa)) {
1098 tarval *tv = get_Const_tarval(node);
1099 node = new_bd_arm_fConst(dbg, block, tv);
1100 be_dep_on_frame(node);
1102 } else if (USE_VFP(env_cg->isa)) {
1103 assert(mode != mode_E && "IEEE Extended FP not supported");
1104 panic("VFP not supported yet");
1106 panic("Softfloat not supported yet");
1109 return create_const_graph(node, block);
1112 static ir_node *gen_SymConst(ir_node *node)
1114 ir_node *block = be_transform_node(get_nodes_block(node));
1115 ir_entity *entity = get_SymConst_entity(node);
1116 dbg_info *dbgi = get_irn_dbg_info(node);
1119 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
1120 be_dep_on_frame(new_node);
1124 static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0,
1127 /* the good way to do this would be to use the stm (store multiple)
1128 * instructions, since our input is nearly always 2 consecutive 32bit
1130 ir_graph *irg = current_ir_graph;
1131 ir_node *stack = get_irg_frame(irg);
1132 ir_node *nomem = new_NoMem();
1133 ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp,
1135 ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp,
1137 ir_node *in[2] = { str0, str1 };
1138 ir_node *sync = new_r_Sync(block, 2, in);
1140 set_irn_pinned(str0, op_pin_state_floats);
1141 set_irn_pinned(str1, op_pin_state_floats);
1143 ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true);
1144 set_irn_pinned(ldf, op_pin_state_floats);
1146 return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1149 static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node)
1151 ir_graph *irg = current_ir_graph;
1152 ir_node *stack = get_irg_frame(irg);
1153 ir_node *nomem = new_NoMem();
1154 ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp,
1157 set_irn_pinned(str, op_pin_state_floats);
1159 ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true);
1160 set_irn_pinned(ldf, op_pin_state_floats);
1162 return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1165 static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node)
1167 ir_graph *irg = current_ir_graph;
1168 ir_node *stack = get_irg_frame(irg);
1169 ir_node *nomem = new_NoMem();
1170 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F,
1173 set_irn_pinned(stf, op_pin_state_floats);
1175 ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1176 set_irn_pinned(ldr, op_pin_state_floats);
1178 return new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1181 static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node,
1182 ir_node **out_value0, ir_node **out_value1)
1184 ir_graph *irg = current_ir_graph;
1185 ir_node *stack = get_irg_frame(irg);
1186 ir_node *nomem = new_NoMem();
1187 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D,
1189 ir_node *ldr0, *ldr1;
1190 set_irn_pinned(stf, op_pin_state_floats);
1192 ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1193 set_irn_pinned(ldr0, op_pin_state_floats);
1194 ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true);
1195 set_irn_pinned(ldr1, op_pin_state_floats);
1197 *out_value0 = new_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
1198 *out_value1 = new_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
1201 static ir_node *gen_CopyB(ir_node *node)
1203 ir_node *block = be_transform_node(get_nodes_block(node));
1204 ir_node *src = get_CopyB_src(node);
1205 ir_node *new_src = be_transform_node(src);
1206 ir_node *dst = get_CopyB_dst(node);
1207 ir_node *new_dst = be_transform_node(dst);
1208 ir_node *mem = get_CopyB_mem(node);
1209 ir_node *new_mem = be_transform_node(mem);
1210 dbg_info *dbg = get_irn_dbg_info(node);
1211 int size = get_type_size_bytes(get_CopyB_type(node));
1215 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
1216 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
1218 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1219 new_bd_arm_EmptyReg(dbg, block),
1220 new_bd_arm_EmptyReg(dbg, block),
1221 new_bd_arm_EmptyReg(dbg, block),
1225 static ir_node *gen_Proj_Load(ir_node *node)
1227 ir_node *load = get_Proj_pred(node);
1228 ir_node *new_load = be_transform_node(load);
1229 dbg_info *dbgi = get_irn_dbg_info(node);
1230 long proj = get_Proj_proj(node);
1232 /* renumber the proj */
1233 switch (get_arm_irn_opcode(new_load)) {
1235 /* handle all gp loads equal: they have the same proj numbers. */
1236 if (proj == pn_Load_res) {
1237 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1238 } else if (proj == pn_Load_M) {
1239 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1243 if (proj == pn_Load_res) {
1244 ir_mode *mode = get_Load_mode(load);
1245 return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res);
1246 } else if (proj == pn_Load_M) {
1247 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M);
1253 panic("Unsupported Proj from Load");
1256 static ir_node *gen_Proj_CopyB(ir_node *node)
1258 ir_node *pred = get_Proj_pred(node);
1259 ir_node *new_pred = be_transform_node(pred);
1260 dbg_info *dbgi = get_irn_dbg_info(node);
1261 long proj = get_Proj_proj(node);
1265 if (is_arm_CopyB(new_pred)) {
1266 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1272 panic("Unsupported Proj from CopyB");
1275 static ir_node *gen_Proj_Quot(ir_node *node)
1277 ir_node *pred = get_Proj_pred(node);
1278 ir_node *new_pred = be_transform_node(pred);
1279 dbg_info *dbgi = get_irn_dbg_info(node);
1280 ir_mode *mode = get_irn_mode(node);
1281 long proj = get_Proj_proj(node);
1285 if (is_arm_Dvf(new_pred)) {
1286 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
1290 if (is_arm_Dvf(new_pred)) {
1291 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
1297 panic("Unsupported Proj from Quot");
1301 * Transform the Projs from a Cmp.
1303 static ir_node *gen_Proj_Cmp(ir_node *node)
1306 /* we should only be here in case of a Mux node */
1310 static ir_node *gen_Proj_Start(ir_node *node)
1312 ir_node *block = get_nodes_block(node);
1313 ir_node *new_block = be_transform_node(block);
1314 ir_node *barrier = be_transform_node(get_Proj_pred(node));
1315 long proj = get_Proj_proj(node);
1317 switch ((pn_Start) proj) {
1318 case pn_Start_X_initial_exec:
1319 /* we exchange the ProjX with a jump */
1320 return new_bd_arm_Jmp(NULL, new_block);
1323 return new_r_Proj(barrier, mode_M, 0);
1325 case pn_Start_T_args:
1328 case pn_Start_P_frame_base:
1329 return be_prolog_get_reg_value(abihelper, sp_reg);
1331 case pn_Start_P_tls:
1337 panic("unexpected start proj: %ld\n", proj);
1340 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1342 long pn = get_Proj_proj(node);
1343 ir_node *block = get_nodes_block(node);
1344 ir_node *new_block = be_transform_node(block);
1345 ir_entity *entity = get_irg_entity(current_ir_graph);
1346 ir_type *method_type = get_entity_type(entity);
1347 ir_type *param_type = get_method_param_type(method_type, pn);
1348 const reg_or_stackslot_t *param;
1350 /* Proj->Proj->Start must be a method argument */
1351 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1353 param = &cconv->parameters[pn];
1355 if (param->reg0 != NULL) {
1356 /* argument transmitted in register */
1357 ir_mode *mode = get_type_mode(param_type);
1358 ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0);
1360 if (mode_is_float(mode)) {
1361 ir_node *value1 = NULL;
1363 if (param->reg1 != NULL) {
1364 value1 = be_prolog_get_reg_value(abihelper, param->reg1);
1365 } else if (param->entity != NULL) {
1366 ir_graph *irg = get_irn_irg(node);
1367 ir_node *fp = get_irg_frame(irg);
1368 ir_node *mem = be_prolog_get_memory(abihelper);
1369 ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem,
1370 mode_gp, param->entity,
1372 value1 = new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1375 /* convert integer value to float */
1376 if (value1 == NULL) {
1377 value = int_to_float(NULL, new_block, value);
1379 value = ints_to_double(NULL, new_block, value, value1);
1384 /* argument transmitted on stack */
1385 ir_graph *irg = get_irn_irg(node);
1386 ir_node *fp = get_irg_frame(irg);
1387 ir_node *mem = be_prolog_get_memory(abihelper);
1388 ir_mode *mode = get_type_mode(param->type);
1392 if (mode_is_float(mode)) {
1393 load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode,
1394 param->entity, 0, 0, true);
1395 value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res);
1397 load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1398 param->entity, 0, 0, true);
1399 value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1401 set_irn_pinned(load, op_pin_state_floats);
1408 * Finds number of output value of a mode_T node which is constrained to
1409 * a single specific register.
1411 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1413 int n_outs = arch_irn_get_n_outs(node);
1416 for (o = 0; o < n_outs; ++o) {
1417 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1418 if (req == reg->single_req)
1424 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1426 long pn = get_Proj_proj(node);
1427 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1428 ir_node *new_call = be_transform_node(call);
1429 ir_type *function_type = get_Call_type(call);
1430 calling_convention_t *cconv = arm_decide_calling_convention(function_type);
1431 const reg_or_stackslot_t *res = &cconv->results[pn];
1435 /* TODO 64bit modes */
1436 assert(res->reg0 != NULL && res->reg1 == NULL);
1437 regn = find_out_for_reg(new_call, res->reg0);
1439 panic("Internal error in calling convention for return %+F", node);
1441 mode = res->reg0->reg_class->mode;
1443 arm_free_calling_convention(cconv);
1445 return new_r_Proj(new_call, mode, regn);
1448 static ir_node *gen_Proj_Call(ir_node *node)
1450 long pn = get_Proj_proj(node);
1451 ir_node *call = get_Proj_pred(node);
1452 ir_node *new_call = be_transform_node(call);
1454 switch ((pn_Call) pn) {
1456 return new_r_Proj(new_call, mode_M, 0);
1457 case pn_Call_X_regular:
1458 case pn_Call_X_except:
1459 case pn_Call_T_result:
1460 case pn_Call_P_value_res_base:
1464 panic("Unexpected Call proj %ld\n", pn);
1468 * Transform a Proj node.
1470 static ir_node *gen_Proj(ir_node *node)
1472 ir_node *pred = get_Proj_pred(node);
1473 long proj = get_Proj_proj(node);
1475 switch (get_irn_opcode(pred)) {
1477 if (proj == pn_Store_M) {
1478 return be_transform_node(pred);
1480 panic("Unsupported Proj from Store");
1483 return gen_Proj_Load(node);
1485 return gen_Proj_Call(node);
1487 return gen_Proj_CopyB(node);
1489 return gen_Proj_Quot(node);
1491 return gen_Proj_Cmp(node);
1493 return gen_Proj_Start(node);
1496 return be_duplicate_node(node);
1498 ir_node *pred_pred = get_Proj_pred(pred);
1499 if (is_Call(pred_pred)) {
1500 return gen_Proj_Proj_Call(node);
1501 } else if (is_Start(pred_pred)) {
1502 return gen_Proj_Proj_Start(node);
1507 panic("code selection didn't expect Proj after %+F\n", pred);
1511 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1513 static inline ir_node *create_const(ir_node **place,
1514 create_const_node_func func,
1515 const arch_register_t* reg)
1517 ir_node *block, *res;
1522 block = get_irg_start_block(env_cg->irg);
1523 res = func(NULL, block);
1524 arch_set_irn_register(res, reg);
1529 static ir_node *gen_Unknown(ir_node *node)
1531 ir_node *block = get_nodes_block(node);
1532 ir_node *new_block = be_transform_node(block);
1533 dbg_info *dbgi = get_irn_dbg_info(node);
1535 /* just produce a 0 */
1536 ir_mode *mode = get_irn_mode(node);
1537 if (mode_is_float(mode)) {
1538 tarval *tv = get_mode_null(mode);
1539 ir_node *node = new_bd_arm_fConst(dbgi, new_block, tv);
1540 be_dep_on_frame(node);
1542 } else if (mode_needs_gp_reg(mode)) {
1543 return create_const_graph_value(dbgi, new_block, 0);
1546 panic("Unexpected Unknown mode");
1550 * Produces the type which sits between the stack args and the locals on the
1551 * stack. It will contain the return address and space to store the old base
1553 * @return The Firm type modeling the ABI between type.
1555 static ir_type *arm_get_between_type(void)
1557 static ir_type *between_type = NULL;
1559 if (between_type == NULL) {
1560 between_type = new_type_class(new_id_from_str("arm_between_type"));
1561 set_type_size_bytes(between_type, 0);
1564 return between_type;
1567 static void create_stacklayout(ir_graph *irg)
1569 ir_entity *entity = get_irg_entity(irg);
1570 ir_type *function_type = get_entity_type(entity);
1571 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1576 /* calling conventions must be decided by now */
1577 assert(cconv != NULL);
1579 /* construct argument type */
1580 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1581 n_params = get_method_n_params(function_type);
1582 for (p = 0; p < n_params; ++p) {
1583 reg_or_stackslot_t *param = &cconv->parameters[p];
1587 if (param->type == NULL)
1590 snprintf(buf, sizeof(buf), "param_%d", p);
1591 id = new_id_from_str(buf);
1592 param->entity = new_entity(arg_type, id, param->type);
1593 set_entity_offset(param->entity, param->offset);
1596 /* TODO: what about external functions? we don't know most of the stack
1597 * layout for them. And probably don't need all of this... */
1598 memset(layout, 0, sizeof(*layout));
1600 layout->frame_type = get_irg_frame_type(irg);
1601 layout->between_type = arm_get_between_type();
1602 layout->arg_type = arg_type;
1603 layout->param_map = NULL; /* TODO */
1604 layout->initial_offset = 0;
1605 layout->initial_bias = 0;
1606 layout->stack_dir = -1;
1607 layout->sp_relative = true;
1609 assert(N_FRAME_TYPES == 3);
1610 layout->order[0] = layout->frame_type;
1611 layout->order[1] = layout->between_type;
1612 layout->order[2] = layout->arg_type;
1616 * transform the start node to the prolog code + initial barrier
1618 static ir_node *gen_Start(ir_node *node)
1620 ir_graph *irg = get_irn_irg(node);
1621 ir_entity *entity = get_irg_entity(irg);
1622 ir_type *function_type = get_entity_type(entity);
1623 ir_node *block = get_nodes_block(node);
1624 ir_node *new_block = be_transform_node(block);
1625 dbg_info *dbgi = get_irn_dbg_info(node);
1632 /* stackpointer is important at function prolog */
1633 be_prolog_add_reg(abihelper, sp_reg,
1634 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1635 /* function parameters in registers */
1636 for (i = 0; i < get_method_n_params(function_type); ++i) {
1637 const reg_or_stackslot_t *param = &cconv->parameters[i];
1638 if (param->reg0 != NULL)
1639 be_prolog_add_reg(abihelper, param->reg0, 0);
1640 if (param->reg1 != NULL)
1641 be_prolog_add_reg(abihelper, param->reg1, 0);
1643 /* announce that we need the values of the callee save regs */
1644 for (i = 0; i < (int) (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
1645 be_prolog_add_reg(abihelper, callee_saves[i], 0);
1648 start = be_prolog_create_start(abihelper, dbgi, new_block);
1649 sp = be_prolog_get_reg_value(abihelper, sp_reg);
1650 incsp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
1651 be_prolog_set_reg_value(abihelper, sp_reg, incsp);
1652 barrier = be_prolog_create_barrier(abihelper, new_block);
1657 static ir_node *get_stack_pointer_for(ir_node *node)
1659 /* get predecessor in stack_order list */
1660 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1661 ir_node *stack_pred_transformed;
1664 if (stack_pred == NULL) {
1665 /* first stack user in the current block. We can simply use the
1666 * initial sp_proj for it */
1667 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1671 stack_pred_transformed = be_transform_node(stack_pred);
1672 stack = pmap_get(node_to_stack, stack_pred);
1673 if (stack == NULL) {
1674 return get_stack_pointer_for(stack_pred);
1681 * transform a Return node into epilogue code + return statement
1683 static ir_node *gen_Return(ir_node *node)
1685 ir_node *block = get_nodes_block(node);
1686 ir_node *new_block = be_transform_node(block);
1687 dbg_info *dbgi = get_irn_dbg_info(node);
1688 ir_node *mem = get_Return_mem(node);
1689 ir_node *new_mem = be_transform_node(mem);
1690 int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
1691 ir_node *sp_proj = get_stack_pointer_for(node);
1692 int n_res = get_Return_n_ress(node);
1697 be_epilog_begin(abihelper);
1698 be_epilog_set_memory(abihelper, new_mem);
1699 /* connect stack pointer with initial stack pointer. fix_stack phase
1700 will later serialize all stack pointer adjusting nodes */
1701 be_epilog_add_reg(abihelper, sp_reg,
1702 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1706 for (i = 0; i < n_res; ++i) {
1707 ir_node *res_value = get_Return_res(node, i);
1708 ir_node *new_res_value = be_transform_node(res_value);
1709 const reg_or_stackslot_t *slot = &cconv->results[i];
1710 const arch_register_t *reg = slot->reg0;
1711 assert(slot->reg1 == NULL);
1712 be_epilog_add_reg(abihelper, reg, 0, new_res_value);
1715 /* connect callee saves with their values at the function begin */
1716 for (i = 0; i < n_callee_saves; ++i) {
1717 const arch_register_t *reg = callee_saves[i];
1718 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1719 be_epilog_add_reg(abihelper, reg, 0, value);
1722 /* create the barrier before the epilog code */
1723 be_epilog_create_barrier(abihelper, new_block);
1725 /* epilog code: an incsp */
1726 sp_proj = be_epilog_get_reg_value(abihelper, sp_reg);
1727 incsp = be_new_IncSP(sp_reg, new_block, sp_proj,
1728 BE_STACK_FRAME_SIZE_SHRINK, 0);
1729 be_epilog_set_reg_value(abihelper, sp_reg, incsp);
1731 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1737 static ir_node *gen_Call(ir_node *node)
1739 ir_graph *irg = get_irn_irg(node);
1740 ir_node *callee = get_Call_ptr(node);
1741 ir_node *block = get_nodes_block(node);
1742 ir_node *new_block = be_transform_node(block);
1743 ir_node *mem = get_Call_mem(node);
1744 ir_node *new_mem = be_transform_node(mem);
1745 dbg_info *dbgi = get_irn_dbg_info(node);
1746 ir_type *type = get_Call_type(node);
1747 calling_convention_t *cconv = arm_decide_calling_convention(type);
1748 int n_params = get_Call_n_params(node);
1749 int n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
1750 /* max inputs: memory, callee, register arguments */
1751 int max_inputs = 2 + n_param_regs;
1752 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1753 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1754 struct obstack *obst = be_get_be_obst(irg);
1755 const arch_register_req_t **in_req
1756 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1760 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1761 ir_entity *entity = NULL;
1762 ir_node *incsp = NULL;
1769 assert(n_params == get_method_n_params(type));
1771 /* construct arguments */
1774 in_req[in_arity] = arch_no_register_req;
1778 for (p = 0; p < n_params; ++p) {
1779 ir_node *value = get_Call_param(node, p);
1780 ir_node *new_value = be_transform_node(value);
1781 ir_node *new_value1 = NULL;
1782 const reg_or_stackslot_t *param = &cconv->parameters[p];
1783 ir_type *param_type = get_method_param_type(type, p);
1784 ir_mode *mode = get_type_mode(param_type);
1787 if (mode_is_float(mode) && param->reg0 != NULL) {
1788 unsigned size_bits = get_mode_size_bits(mode);
1789 if (size_bits == 64) {
1790 double_to_ints(dbgi, new_block, new_value, &new_value,
1793 assert(size_bits == 32);
1794 new_value = float_to_int(dbgi, new_block, new_value);
1798 /* put value into registers */
1799 if (param->reg0 != NULL) {
1800 in[in_arity] = new_value;
1801 in_req[in_arity] = param->reg0->single_req;
1803 if (new_value1 == NULL)
1806 if (param->reg1 != NULL) {
1807 assert(new_value1 != NULL);
1808 in[in_arity] = new_value1;
1809 in_req[in_arity] = param->reg1->single_req;
1814 /* we need a store if we're here */
1815 if (new_value1 != NULL) {
1816 new_value = new_value1;
1820 /* create a parameter frame if necessary */
1821 if (incsp == NULL) {
1822 ir_node *new_frame = get_stack_pointer_for(node);
1823 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1824 cconv->param_stack_size, 1);
1826 if (mode_is_float(mode)) {
1827 str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem,
1828 mode, NULL, 0, param->offset, true);
1830 str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem,
1831 mode, NULL, 0, param->offset, true);
1833 sync_ins[sync_arity++] = str;
1835 assert(in_arity <= max_inputs);
1837 /* construct memory input */
1838 if (sync_arity == 0) {
1839 in[mem_pos] = new_mem;
1840 } else if (sync_arity == 1) {
1841 in[mem_pos] = sync_ins[0];
1843 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1846 /* TODO: use a generic symconst matcher here */
1847 if (is_SymConst(callee)) {
1848 entity = get_SymConst_entity(callee);
1850 /* TODO: finish load matcher here */
1853 if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) {
1854 ir_node *load = get_Proj_pred(callee);
1855 ir_node *ptr = get_Load_ptr(load);
1856 ir_node *new_ptr = be_transform_node(ptr);
1857 ir_node *mem = get_Load_mem(load);
1858 ir_node *new_mem = be_transform_node(mem);
1859 ir_mode *mode = get_Load_mode(node);
1863 in[in_arity] = be_transform_node(callee);
1864 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1873 out_arity = 1 + n_caller_saves;
1875 if (entity != NULL) {
1876 /* TODO: use a generic symconst matcher here
1877 * so we can also handle entity+offset, etc. */
1878 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1881 * - use a proper shifter_operand matcher
1882 * - we could also use LinkLdrPC
1884 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1888 if (incsp != NULL) {
1889 /* IncSP to destroy the call stackframe */
1890 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
1892 /* if we are the last IncSP producer in a block then we have to keep
1894 * Note: This here keeps all producers which is more than necessary */
1895 add_irn_dep(incsp, res);
1898 pmap_insert(node_to_stack, node, incsp);
1901 set_arm_in_req_all(res, in_req);
1903 /* create output register reqs */
1904 arch_set_out_register_req(res, 0, arch_no_register_req);
1905 for (o = 0; o < n_caller_saves; ++o) {
1906 const arch_register_t *reg = caller_saves[o];
1907 arch_set_out_register_req(res, o+1, reg->single_req);
1910 /* copy pinned attribute */
1911 set_irn_pinned(res, get_irn_pinned(node));
1913 arm_free_calling_convention(cconv);
1917 static ir_node *gen_Sel(ir_node *node)
1919 dbg_info *dbgi = get_irn_dbg_info(node);
1920 ir_node *block = get_nodes_block(node);
1921 ir_node *new_block = be_transform_node(block);
1922 ir_node *ptr = get_Sel_ptr(node);
1923 ir_node *new_ptr = be_transform_node(ptr);
1924 ir_entity *entity = get_Sel_entity(node);
1926 /* must be the frame pointer all other sels must have been lowered
1928 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1929 /* we should not have value types from parameters anymore - they should be
1931 assert(get_entity_owner(entity) !=
1932 get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
1934 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1938 * Change some phi modes
1940 static ir_node *gen_Phi(ir_node *node)
1942 const arch_register_req_t *req;
1943 ir_node *block = be_transform_node(get_nodes_block(node));
1944 ir_graph *irg = current_ir_graph;
1945 dbg_info *dbgi = get_irn_dbg_info(node);
1946 ir_mode *mode = get_irn_mode(node);
1949 if (mode_needs_gp_reg(mode)) {
1950 /* we shouldn't have any 64bit stuff around anymore */
1951 assert(get_mode_size_bits(mode) <= 32);
1952 /* all integer operations are on 32bit registers now */
1954 req = arm_reg_classes[CLASS_arm_gp].class_req;
1956 req = arch_no_register_req;
1959 /* phi nodes allow loops, so we use the old arguments for now
1960 * and fix this later */
1961 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
1962 get_irn_in(node) + 1);
1963 copy_node_attr(irg, node, phi);
1964 be_duplicate_deps(node, phi);
1966 arch_set_out_register_req(phi, 0, req);
1968 be_enqueue_preds(node);
1975 * Enters all transform functions into the generic pointer
1977 static void arm_register_transformers(void)
1979 be_start_transform_setup();
1981 be_set_transform_function(op_Add, gen_Add);
1982 be_set_transform_function(op_And, gen_And);
1983 be_set_transform_function(op_Call, gen_Call);
1984 be_set_transform_function(op_Cmp, gen_Cmp);
1985 be_set_transform_function(op_Cond, gen_Cond);
1986 be_set_transform_function(op_Const, gen_Const);
1987 be_set_transform_function(op_Conv, gen_Conv);
1988 be_set_transform_function(op_CopyB, gen_CopyB);
1989 be_set_transform_function(op_Eor, gen_Eor);
1990 be_set_transform_function(op_Jmp, gen_Jmp);
1991 be_set_transform_function(op_Load, gen_Load);
1992 be_set_transform_function(op_Minus, gen_Minus);
1993 be_set_transform_function(op_Mul, gen_Mul);
1994 be_set_transform_function(op_Not, gen_Not);
1995 be_set_transform_function(op_Or, gen_Or);
1996 be_set_transform_function(op_Phi, gen_Phi);
1997 be_set_transform_function(op_Proj, gen_Proj);
1998 be_set_transform_function(op_Quot, gen_Quot);
1999 be_set_transform_function(op_Return, gen_Return);
2000 be_set_transform_function(op_Rotl, gen_Rotl);
2001 be_set_transform_function(op_Sel, gen_Sel);
2002 be_set_transform_function(op_Shl, gen_Shl);
2003 be_set_transform_function(op_Shr, gen_Shr);
2004 be_set_transform_function(op_Shrs, gen_Shrs);
2005 be_set_transform_function(op_Start, gen_Start);
2006 be_set_transform_function(op_Store, gen_Store);
2007 be_set_transform_function(op_Sub, gen_Sub);
2008 be_set_transform_function(op_SymConst, gen_SymConst);
2009 be_set_transform_function(op_Unknown, gen_Unknown);
2013 * Initialize fpa Immediate support.
2015 static void arm_init_fpa_immediate(void)
2017 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
2018 fpa_imm[0][fpa_null] = get_mode_null(mode_F);
2019 fpa_imm[0][fpa_one] = get_mode_one(mode_F);
2020 fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
2021 fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
2022 fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
2023 fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
2024 fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
2025 fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
2027 fpa_imm[1][fpa_null] = get_mode_null(mode_D);
2028 fpa_imm[1][fpa_one] = get_mode_one(mode_D);
2029 fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
2030 fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
2031 fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
2032 fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
2033 fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
2034 fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
2036 fpa_imm[2][fpa_null] = get_mode_null(mode_E);
2037 fpa_imm[2][fpa_one] = get_mode_one(mode_E);
2038 fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
2039 fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
2040 fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
2041 fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
2042 fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
2043 fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
2047 * Transform a Firm graph into an ARM graph.
2049 void arm_transform_graph(arm_code_gen_t *cg)
2051 static int imm_initialized = 0;
2052 ir_graph *irg = cg->irg;
2053 ir_entity *entity = get_irg_entity(irg);
2054 ir_type *frame_type;
2059 if (! imm_initialized) {
2060 arm_init_fpa_immediate();
2061 imm_initialized = 1;
2063 arm_register_transformers();
2066 node_to_stack = pmap_create();
2068 assert(abihelper == NULL);
2069 abihelper = be_abihelper_prepare(irg);
2070 be_collect_stacknodes(abihelper);
2071 assert(cconv == NULL);
2072 cconv = arm_decide_calling_convention(get_entity_type(entity));
2073 create_stacklayout(irg);
2075 be_transform_graph(cg->irg, NULL);
2077 be_abihelper_finish(abihelper);
2080 arm_free_calling_convention(cconv);
2083 frame_type = get_irg_frame_type(irg);
2084 if (get_type_state(frame_type) == layout_undefined) {
2085 default_layout_compound_type(frame_type);
2088 pmap_destroy(node_to_stack);
2089 node_to_stack = NULL;
2091 be_add_missing_keeps(irg);
2094 void arm_init_transform(void)
2096 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");