2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
40 #include "../benode.h"
42 #include "../beutil.h"
43 #include "../betranshlp.h"
44 #include "../beabihelper.h"
47 #include "bearch_arm_t.h"
48 #include "arm_nodes_attr.h"
49 #include "arm_transform.h"
50 #include "arm_optimize.h"
51 #include "arm_new_nodes.h"
52 #include "arm_map_regs.h"
53 #include "arm_cconv.h"
55 #include "gen_arm_regalloc_if.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static const arch_register_t *sp_reg = &arm_registers[REG_SP];
62 static ir_mode *mode_gp;
63 static ir_mode *mode_fp;
64 static beabi_helper_env_t *abihelper;
65 static calling_convention_t *cconv = NULL;
66 static arm_isa_t *isa;
68 static pmap *node_to_stack;
70 static const arch_register_t *const callee_saves[] = {
71 &arm_registers[REG_R4],
72 &arm_registers[REG_R5],
73 &arm_registers[REG_R6],
74 &arm_registers[REG_R7],
75 &arm_registers[REG_R8],
76 &arm_registers[REG_R9],
77 &arm_registers[REG_R10],
78 &arm_registers[REG_R11],
79 &arm_registers[REG_LR],
82 static const arch_register_t *const caller_saves[] = {
83 &arm_registers[REG_R0],
84 &arm_registers[REG_R1],
85 &arm_registers[REG_R2],
86 &arm_registers[REG_R3],
87 &arm_registers[REG_LR],
89 &arm_registers[REG_F0],
90 &arm_registers[REG_F1],
91 &arm_registers[REG_F2],
92 &arm_registers[REG_F3],
93 &arm_registers[REG_F4],
94 &arm_registers[REG_F5],
95 &arm_registers[REG_F6],
96 &arm_registers[REG_F7],
99 static bool mode_needs_gp_reg(ir_mode *mode)
101 return mode_is_int(mode) || mode_is_reference(mode);
105 * create firm graph for a constant
107 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
114 /* We only have 8 bit immediates. So we possibly have to combine several
115 * operations to construct the desired value.
117 * we can either create the value by adding bits to 0 or by removing bits
118 * from an register with all bits set. Try which alternative needs fewer
120 arm_gen_vals_from_word(value, &v);
121 arm_gen_vals_from_word(~value, &vn);
123 if (vn.ops < v.ops) {
125 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
127 for (cnt = 1; cnt < vn.ops; ++cnt) {
128 result = new_bd_arm_Bic_imm(dbgi, block, result,
129 vn.values[cnt], vn.rors[cnt]);
133 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
135 for (cnt = 1; cnt < v.ops; ++cnt) {
136 result = new_bd_arm_Or_imm(dbgi, block, result,
137 v.values[cnt], v.rors[cnt]);
144 * Create a DAG constructing a given Const.
146 * @param irn a Firm const
148 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
150 ir_tarval *tv = get_Const_tarval(irn);
151 ir_mode *mode = get_tarval_mode(tv);
154 if (mode_is_reference(mode)) {
155 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
156 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
157 tv = tarval_convert_to(tv, mode_Iu);
159 value = get_tarval_long(tv);
160 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
164 * Create an And that will zero out upper bits.
166 * @param dbgi debug info
167 * @param block the basic block
168 * @param op the original node
169 * param src_bits number of lower bits that will remain
171 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
175 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
176 } else if (src_bits == 16) {
177 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
178 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
181 panic("zero extension only supported for 8 and 16 bits");
186 * Generate code for a sign extension.
188 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
191 int shift_width = 32 - src_bits;
192 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
193 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
197 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
200 int bits = get_mode_size_bits(orig_mode);
204 if (mode_is_signed(orig_mode)) {
205 return gen_sign_extension(dbgi, block, op, bits);
207 return gen_zero_extension(dbgi, block, op, bits);
212 * returns true if it is assured, that the upper bits of a node are "clean"
213 * which means for a 16 or 8 bit value, that the upper bits in the register
214 * are 0 for unsigned and a copy of the last significant bit for signed
217 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
219 (void) transformed_node;
226 * Transforms a Conv node.
228 * @return The created ia32 Conv node
230 static ir_node *gen_Conv(ir_node *node)
232 ir_node *block = be_transform_node(get_nodes_block(node));
233 ir_node *op = get_Conv_op(node);
234 ir_node *new_op = be_transform_node(op);
235 ir_mode *src_mode = get_irn_mode(op);
236 ir_mode *dst_mode = get_irn_mode(node);
237 dbg_info *dbg = get_irn_dbg_info(node);
239 if (src_mode == dst_mode)
242 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
244 if (mode_is_float(src_mode)) {
245 if (mode_is_float(dst_mode)) {
246 /* from float to float */
247 return new_bd_arm_Mvf(dbg, block, new_op, dst_mode);
249 /* from float to int */
253 /* from int to float */
254 if (!mode_is_signed(src_mode)) {
257 return new_bd_arm_FltX(dbg, block, new_op, dst_mode);
260 } else if (USE_VFP(isa)) {
261 panic("VFP not supported yet");
263 panic("Softfloat not supported yet");
265 } else { /* complete in gp registers */
266 int src_bits = get_mode_size_bits(src_mode);
267 int dst_bits = get_mode_size_bits(dst_mode);
271 if (src_bits == dst_bits) {
272 /* kill unnecessary conv */
276 if (src_bits < dst_bits) {
284 if (upper_bits_clean(new_op, min_mode)) {
288 if (mode_is_signed(min_mode)) {
289 return gen_sign_extension(dbg, block, new_op, min_bits);
291 return gen_zero_extension(dbg, block, new_op, min_bits);
301 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
303 unsigned val, low_pos, high_pos;
308 val = get_tarval_long(get_Const_tarval(node));
320 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
322 So we determine the smallest even position with a bit set
323 and the highest even position with no bit set anymore.
324 If the difference between these 2 is <= 8, then we can encode the value
327 low_pos = ntz(val) & ~1u;
328 high_pos = (32-nlz(val)+1) & ~1u;
330 if (high_pos - low_pos <= 8) {
331 res->imm_8 = val >> low_pos;
332 res->rot = 32 - low_pos;
337 res->rot = 34 - high_pos;
338 val = val >> (32-res->rot) | val << (res->rot);
348 static bool is_downconv(const ir_node *node)
356 /* we only want to skip the conv when we're the only user
357 * (not optimal but for now...)
359 if (get_irn_n_edges(node) > 1)
362 src_mode = get_irn_mode(get_Conv_op(node));
363 dest_mode = get_irn_mode(node);
365 mode_needs_gp_reg(src_mode) &&
366 mode_needs_gp_reg(dest_mode) &&
367 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
370 static ir_node *arm_skip_downconv(ir_node *node)
372 while (is_downconv(node))
373 node = get_Conv_op(node);
379 MATCH_COMMUTATIVE = 1 << 0, /**< commutative node */
380 MATCH_REVERSE = 1 << 1, /**< support reverse opcode */
381 MATCH_SIZE_NEUTRAL = 1 << 2,
382 MATCH_SKIP_NOT = 1 << 3, /**< skip Not on ONE input */
384 ENUM_BITSET(match_flags_t)
387 * possible binop constructors.
389 typedef struct arm_binop_factory_t {
390 /** normal reg op reg operation. */
391 ir_node *(*new_binop_reg)(dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
392 /** normal reg op imm operation. */
393 ir_node *(*new_binop_imm)(dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
394 /** barrel shifter reg op (reg shift reg operation. */
395 ir_node *(*new_binop_reg_shift_reg)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *shift, arm_shift_modifier_t shift_modifier);
396 /** barrel shifter reg op (reg shift imm operation. */
397 ir_node *(*new_binop_reg_shift_imm)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, arm_shift_modifier_t shift_modifier, unsigned shift_immediate);
398 } arm_binop_factory_t;
400 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
401 const arm_binop_factory_t *factory)
403 ir_node *block = be_transform_node(get_nodes_block(node));
404 ir_node *op1 = get_binop_left(node);
406 ir_node *op2 = get_binop_right(node);
408 dbg_info *dbgi = get_irn_dbg_info(node);
411 if (flags & MATCH_SKIP_NOT) {
413 op1 = get_Not_op(op1);
414 else if (is_Not(op2))
415 op2 = get_Not_op(op2);
417 panic("cannot execute MATCH_SKIP_NOT");
419 if (flags & MATCH_SIZE_NEUTRAL) {
420 op1 = arm_skip_downconv(op1);
421 op2 = arm_skip_downconv(op2);
423 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
426 if (try_encode_as_immediate(op2, &imm)) {
427 new_op1 = be_transform_node(op1);
428 return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
430 new_op2 = be_transform_node(op2);
431 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && try_encode_as_immediate(op1, &imm)) {
432 if (flags & MATCH_REVERSE)
433 return factory[1].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
435 return factory[0].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
437 new_op1 = be_transform_node(op1);
439 /* check if we can fold in a Mov */
440 if (is_arm_Mov(new_op2)) {
441 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op2);
443 switch (attr->shift_modifier) {
445 case ARM_SHF_ASR_IMM:
446 case ARM_SHF_LSL_IMM:
447 case ARM_SHF_LSR_IMM:
448 case ARM_SHF_ROR_IMM:
449 if (factory->new_binop_reg_shift_imm) {
450 ir_node *mov_op = get_irn_n(new_op2, 0);
451 return factory->new_binop_reg_shift_imm(dbgi, block, new_op1, mov_op,
452 attr->shift_modifier, attr->shift_immediate);
456 case ARM_SHF_ASR_REG:
457 case ARM_SHF_LSL_REG:
458 case ARM_SHF_LSR_REG:
459 case ARM_SHF_ROR_REG:
460 if (factory->new_binop_reg_shift_reg) {
461 ir_node *mov_op = get_irn_n(new_op2, 0);
462 ir_node *mov_sft = get_irn_n(new_op2, 1);
463 return factory->new_binop_reg_shift_reg(dbgi, block, new_op1, mov_op, mov_sft,
464 attr->shift_modifier);
470 case ARM_SHF_INVALID:
471 panic("invalid shift");
474 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && is_arm_Mov(new_op1)) {
475 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op1);
476 int idx = flags & MATCH_REVERSE ? 1 : 0;
478 switch (attr->shift_modifier) {
479 ir_node *mov_op, *mov_sft;
482 case ARM_SHF_ASR_IMM:
483 case ARM_SHF_LSL_IMM:
484 case ARM_SHF_LSR_IMM:
485 case ARM_SHF_ROR_IMM:
486 if (factory[idx].new_binop_reg_shift_imm) {
487 mov_op = get_irn_n(new_op1, 0);
488 return factory[idx].new_binop_reg_shift_imm(dbgi, block, new_op2, mov_op,
489 attr->shift_modifier, attr->shift_immediate);
493 case ARM_SHF_ASR_REG:
494 case ARM_SHF_LSL_REG:
495 case ARM_SHF_LSR_REG:
496 case ARM_SHF_ROR_REG:
497 if (factory[idx].new_binop_reg_shift_reg) {
498 mov_op = get_irn_n(new_op1, 0);
499 mov_sft = get_irn_n(new_op1, 1);
500 return factory[idx].new_binop_reg_shift_reg(dbgi, block, new_op2, mov_op, mov_sft,
501 attr->shift_modifier);
508 case ARM_SHF_INVALID:
509 panic("invalid shift");
512 return factory->new_binop_reg(dbgi, block, new_op1, new_op2);
516 * Creates an ARM Add.
518 * @return the created arm Add node
520 static ir_node *gen_Add(ir_node *node)
522 static const arm_binop_factory_t add_factory = {
525 new_bd_arm_Add_reg_shift_reg,
526 new_bd_arm_Add_reg_shift_imm
529 ir_mode *mode = get_irn_mode(node);
531 if (mode_is_float(mode)) {
532 ir_node *block = be_transform_node(get_nodes_block(node));
533 ir_node *op1 = get_Add_left(node);
534 ir_node *op2 = get_Add_right(node);
535 dbg_info *dbgi = get_irn_dbg_info(node);
536 ir_node *new_op1 = be_transform_node(op1);
537 ir_node *new_op2 = be_transform_node(op2);
539 return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
540 } else if (USE_VFP(isa)) {
541 assert(mode != mode_E && "IEEE Extended FP not supported");
542 panic("VFP not supported yet");
544 panic("Softfloat not supported yet");
549 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
551 new_op2 = get_irn_n(new_op1, 1);
552 new_op1 = get_irn_n(new_op1, 0);
554 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
556 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
558 new_op1 = get_irn_n(new_op2, 0);
559 new_op2 = get_irn_n(new_op2, 1);
561 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
565 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &add_factory);
570 * Creates an ARM Mul.
572 * @return the created arm Mul node
574 static ir_node *gen_Mul(ir_node *node)
576 ir_node *block = be_transform_node(get_nodes_block(node));
577 ir_node *op1 = get_Mul_left(node);
578 ir_node *new_op1 = be_transform_node(op1);
579 ir_node *op2 = get_Mul_right(node);
580 ir_node *new_op2 = be_transform_node(op2);
581 ir_mode *mode = get_irn_mode(node);
582 dbg_info *dbg = get_irn_dbg_info(node);
584 if (mode_is_float(mode)) {
586 return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
587 } else if (USE_VFP(isa)) {
588 assert(mode != mode_E && "IEEE Extended FP not supported");
589 panic("VFP not supported yet");
591 panic("Softfloat not supported yet");
594 assert(mode_is_data(mode));
595 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
598 static ir_node *gen_Div(ir_node *node)
600 ir_node *block = be_transform_node(get_nodes_block(node));
601 ir_node *op1 = get_Div_left(node);
602 ir_node *new_op1 = be_transform_node(op1);
603 ir_node *op2 = get_Div_right(node);
604 ir_node *new_op2 = be_transform_node(op2);
605 ir_mode *mode = get_Div_resmode(node);
606 dbg_info *dbg = get_irn_dbg_info(node);
608 assert(mode != mode_E && "IEEE Extended FP not supported");
609 /* integer division should be replaced by builtin call */
610 assert(mode_is_float(mode));
613 return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
614 } else if (USE_VFP(isa)) {
615 assert(mode != mode_E && "IEEE Extended FP not supported");
616 panic("VFP not supported yet");
618 panic("Softfloat not supported yet");
622 static ir_node *gen_And(ir_node *node)
624 static const arm_binop_factory_t and_factory = {
627 new_bd_arm_And_reg_shift_reg,
628 new_bd_arm_And_reg_shift_imm
630 static const arm_binop_factory_t bic_factory = {
633 new_bd_arm_Bic_reg_shift_reg,
634 new_bd_arm_Bic_reg_shift_imm
637 /* check for and not */
638 ir_node *left = get_And_left(node);
639 ir_node *right = get_And_right(node);
641 if (is_Not(left) || is_Not(right)) {
642 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL | MATCH_SKIP_NOT,
646 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &and_factory);
649 static ir_node *gen_Or(ir_node *node)
651 static const arm_binop_factory_t or_factory = {
654 new_bd_arm_Or_reg_shift_reg,
655 new_bd_arm_Or_reg_shift_imm
658 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &or_factory);
661 static ir_node *gen_Eor(ir_node *node)
663 static const arm_binop_factory_t eor_factory = {
666 new_bd_arm_Eor_reg_shift_reg,
667 new_bd_arm_Eor_reg_shift_imm
670 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &eor_factory);
673 static ir_node *gen_Sub(ir_node *node)
675 static const arm_binop_factory_t sub_rsb_factory[2] = {
679 new_bd_arm_Sub_reg_shift_reg,
680 new_bd_arm_Sub_reg_shift_imm
685 new_bd_arm_Rsb_reg_shift_reg,
686 new_bd_arm_Rsb_reg_shift_imm
690 ir_node *block = be_transform_node(get_nodes_block(node));
691 ir_node *op1 = get_Sub_left(node);
692 ir_node *new_op1 = be_transform_node(op1);
693 ir_node *op2 = get_Sub_right(node);
694 ir_node *new_op2 = be_transform_node(op2);
695 ir_mode *mode = get_irn_mode(node);
696 dbg_info *dbgi = get_irn_dbg_info(node);
698 if (mode_is_float(mode)) {
700 return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
701 } else if (USE_VFP(isa)) {
702 assert(mode != mode_E && "IEEE Extended FP not supported");
703 panic("VFP not supported yet");
705 panic("Softfloat not supported yet");
708 return gen_int_binop(node, MATCH_SIZE_NEUTRAL | MATCH_REVERSE, sub_rsb_factory);
713 * Checks if a given value can be used as an immediate for the given
716 static bool can_use_shift_constant(unsigned int val,
717 arm_shift_modifier_t modifier)
721 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
727 * generate an ARM shift instruction.
729 * @param node the node
730 * @param flags matching flags
731 * @param shift_modifier initial encoding of the desired shift operation
733 static ir_node *make_shift(ir_node *node, match_flags_t flags,
734 arm_shift_modifier_t shift_modifier)
736 ir_node *block = be_transform_node(get_nodes_block(node));
737 ir_node *op1 = get_binop_left(node);
738 ir_node *op2 = get_binop_right(node);
739 dbg_info *dbgi = get_irn_dbg_info(node);
743 if (flags & MATCH_SIZE_NEUTRAL) {
744 op1 = arm_skip_downconv(op1);
745 op2 = arm_skip_downconv(op2);
748 new_op1 = be_transform_node(op1);
750 ir_tarval *tv = get_Const_tarval(op2);
751 unsigned int val = get_tarval_long(tv);
752 assert(tarval_is_long(tv));
753 if (can_use_shift_constant(val, shift_modifier)) {
754 switch (shift_modifier) {
755 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
756 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
757 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
758 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
759 default: panic("unexpected shift modifier");
761 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
762 shift_modifier, val);
766 new_op2 = be_transform_node(op2);
767 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
771 static ir_node *gen_Shl(ir_node *node)
773 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
776 static ir_node *gen_Shr(ir_node *node)
778 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
781 static ir_node *gen_Shrs(ir_node *node)
783 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
786 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
788 ir_node *block = be_transform_node(get_nodes_block(node));
789 ir_node *new_op1 = be_transform_node(op1);
790 dbg_info *dbgi = get_irn_dbg_info(node);
791 ir_node *new_op2 = be_transform_node(op2);
793 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
797 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
799 ir_node *block = be_transform_node(get_nodes_block(node));
800 ir_node *new_op1 = be_transform_node(op1);
801 dbg_info *dbgi = get_irn_dbg_info(node);
802 ir_node *new_op2 = be_transform_node(op2);
804 /* Note: there is no Rol on arm, we have to use Ror */
805 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
806 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
810 static ir_node *gen_Rotl(ir_node *node)
812 ir_node *rotate = NULL;
813 ir_node *op1 = get_Rotl_left(node);
814 ir_node *op2 = get_Rotl_right(node);
816 /* Firm has only RotL, so we are looking for a right (op2)
817 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
818 that means we can create a RotR. */
821 ir_node *right = get_Add_right(op2);
822 if (is_Const(right)) {
823 ir_tarval *tv = get_Const_tarval(right);
824 ir_mode *mode = get_irn_mode(node);
825 long bits = get_mode_size_bits(mode);
826 ir_node *left = get_Add_left(op2);
828 if (is_Minus(left) &&
829 tarval_is_long(tv) &&
830 get_tarval_long(tv) == bits &&
832 rotate = gen_Ror(node, op1, get_Minus_op(left));
834 } else if (is_Sub(op2)) {
835 ir_node *left = get_Sub_left(op2);
836 if (is_Const(left)) {
837 ir_tarval *tv = get_Const_tarval(left);
838 ir_mode *mode = get_irn_mode(node);
839 long bits = get_mode_size_bits(mode);
840 ir_node *right = get_Sub_right(op2);
842 if (tarval_is_long(tv) &&
843 get_tarval_long(tv) == bits &&
845 rotate = gen_Ror(node, op1, right);
847 } else if (is_Const(op2)) {
848 ir_tarval *tv = get_Const_tarval(op2);
849 ir_mode *mode = get_irn_mode(node);
850 long bits = get_mode_size_bits(mode);
852 if (tarval_is_long(tv) && bits == 32) {
853 ir_node *block = be_transform_node(get_nodes_block(node));
854 ir_node *new_op1 = be_transform_node(op1);
855 dbg_info *dbgi = get_irn_dbg_info(node);
857 bits = (bits - get_tarval_long(tv)) & 31;
858 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
862 if (rotate == NULL) {
863 rotate = gen_Rol(node, op1, op2);
869 static ir_node *gen_Not(ir_node *node)
871 ir_node *block = be_transform_node(get_nodes_block(node));
872 ir_node *op = get_Not_op(node);
873 ir_node *new_op = be_transform_node(op);
874 dbg_info *dbgi = get_irn_dbg_info(node);
876 /* check if we can fold in a Mov */
877 if (is_arm_Mov(new_op)) {
878 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op);
880 switch (attr->shift_modifier) {
881 ir_node *mov_op, *mov_sft;
884 case ARM_SHF_ASR_IMM:
885 case ARM_SHF_LSL_IMM:
886 case ARM_SHF_LSR_IMM:
887 case ARM_SHF_ROR_IMM:
888 mov_op = get_irn_n(new_op, 0);
889 return new_bd_arm_Mvn_reg_shift_imm(dbgi, block, mov_op,
890 attr->shift_modifier, attr->shift_immediate);
892 case ARM_SHF_ASR_REG:
893 case ARM_SHF_LSL_REG:
894 case ARM_SHF_LSR_REG:
895 case ARM_SHF_ROR_REG:
896 mov_op = get_irn_n(new_op, 0);
897 mov_sft = get_irn_n(new_op, 1);
898 return new_bd_arm_Mvn_reg_shift_reg(dbgi, block, mov_op, mov_sft,
899 attr->shift_modifier);
904 case ARM_SHF_INVALID:
905 panic("invalid shift");
909 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
912 static ir_node *gen_Minus(ir_node *node)
914 ir_node *block = be_transform_node(get_nodes_block(node));
915 ir_node *op = get_Minus_op(node);
916 ir_node *new_op = be_transform_node(op);
917 dbg_info *dbgi = get_irn_dbg_info(node);
918 ir_mode *mode = get_irn_mode(node);
920 if (mode_is_float(mode)) {
922 return new_bd_arm_Mvf(dbgi, block, op, mode);
923 } else if (USE_VFP(isa)) {
924 assert(mode != mode_E && "IEEE Extended FP not supported");
925 panic("VFP not supported yet");
927 panic("Softfloat not supported yet");
930 assert(mode_is_data(mode));
931 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
934 static ir_node *gen_Load(ir_node *node)
936 ir_node *block = be_transform_node(get_nodes_block(node));
937 ir_node *ptr = get_Load_ptr(node);
938 ir_node *new_ptr = be_transform_node(ptr);
939 ir_node *mem = get_Load_mem(node);
940 ir_node *new_mem = be_transform_node(mem);
941 ir_mode *mode = get_Load_mode(node);
942 dbg_info *dbgi = get_irn_dbg_info(node);
943 ir_node *new_load = NULL;
945 if (get_Load_unaligned(node) == align_non_aligned)
946 panic("arm: unaligned Loads not supported yet");
948 if (mode_is_float(mode)) {
950 new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
952 } else if (USE_VFP(isa)) {
953 assert(mode != mode_E && "IEEE Extended FP not supported");
954 panic("VFP not supported yet");
956 panic("Softfloat not supported yet");
959 assert(mode_is_data(mode) && "unsupported mode for Load");
961 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
963 set_irn_pinned(new_load, get_irn_pinned(node));
965 /* check for special case: the loaded value might not be used */
966 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
967 /* add a result proj and a Keep to produce a pseudo use */
968 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
969 be_new_Keep(block, 1, &proj);
975 static ir_node *gen_Store(ir_node *node)
977 ir_node *block = be_transform_node(get_nodes_block(node));
978 ir_node *ptr = get_Store_ptr(node);
979 ir_node *new_ptr = be_transform_node(ptr);
980 ir_node *mem = get_Store_mem(node);
981 ir_node *new_mem = be_transform_node(mem);
982 ir_node *val = get_Store_value(node);
983 ir_node *new_val = be_transform_node(val);
984 ir_mode *mode = get_irn_mode(val);
985 dbg_info *dbgi = get_irn_dbg_info(node);
986 ir_node *new_store = NULL;
988 if (get_Store_unaligned(node) == align_non_aligned)
989 panic("arm: unaligned Stores not supported yet");
991 if (mode_is_float(mode)) {
993 new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
994 new_mem, mode, NULL, 0, 0, false);
995 } else if (USE_VFP(isa)) {
996 assert(mode != mode_E && "IEEE Extended FP not supported");
997 panic("VFP not supported yet");
999 panic("Softfloat not supported yet");
1002 assert(mode_is_data(mode) && "unsupported mode for Store");
1003 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
1006 set_irn_pinned(new_store, get_irn_pinned(node));
1010 static ir_node *gen_Jmp(ir_node *node)
1012 ir_node *block = get_nodes_block(node);
1013 ir_node *new_block = be_transform_node(block);
1014 dbg_info *dbgi = get_irn_dbg_info(node);
1016 return new_bd_arm_Jmp(dbgi, new_block);
1019 static ir_node *gen_SwitchJmp(ir_node *node)
1021 ir_node *block = be_transform_node(get_nodes_block(node));
1022 ir_node *selector = get_Cond_selector(node);
1023 dbg_info *dbgi = get_irn_dbg_info(node);
1024 ir_node *new_op = be_transform_node(selector);
1025 ir_node *const_graph;
1029 const ir_edge_t *edge;
1036 foreach_out_edge(node, edge) {
1037 proj = get_edge_src_irn(edge);
1038 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1040 pn = get_Proj_proj(proj);
1042 min = pn<min ? pn : min;
1043 max = pn>max ? pn : max;
1046 n_projs = max - translation + 1;
1048 foreach_out_edge(node, edge) {
1049 proj = get_edge_src_irn(edge);
1050 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1052 pn = get_Proj_proj(proj) - translation;
1053 set_Proj_proj(proj, pn);
1056 const_graph = create_const_graph_value(dbgi, block, translation);
1057 sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
1058 return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
1061 static ir_node *gen_Cmp(ir_node *node)
1063 ir_node *block = be_transform_node(get_nodes_block(node));
1064 ir_node *op1 = get_Cmp_left(node);
1065 ir_node *op2 = get_Cmp_right(node);
1066 ir_mode *cmp_mode = get_irn_mode(op1);
1067 dbg_info *dbgi = get_irn_dbg_info(node);
1072 if (mode_is_float(cmp_mode)) {
1073 /* TODO: this is broken... */
1074 new_op1 = be_transform_node(op1);
1075 new_op2 = be_transform_node(op2);
1077 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
1080 assert(get_irn_mode(op2) == cmp_mode);
1081 is_unsigned = !mode_is_signed(cmp_mode);
1083 /* integer compare, TODO: use shifter_op in all its combinations */
1084 new_op1 = be_transform_node(op1);
1085 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
1086 new_op2 = be_transform_node(op2);
1087 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
1088 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
1092 static ir_node *gen_Cond(ir_node *node)
1094 ir_node *selector = get_Cond_selector(node);
1095 ir_mode *mode = get_irn_mode(selector);
1096 ir_relation relation;
1101 if (mode != mode_b) {
1102 return gen_SwitchJmp(node);
1104 assert(is_Cmp(selector));
1106 block = be_transform_node(get_nodes_block(node));
1107 dbgi = get_irn_dbg_info(node);
1108 flag_node = be_transform_node(selector);
1109 relation = get_Cmp_relation(selector);
1111 return new_bd_arm_B(dbgi, block, flag_node, relation);
1117 FPA_IMM_EXTENDED = 2,
1118 FPA_IMM_MAX = FPA_IMM_EXTENDED
1121 static ir_tarval *fpa_imm[FPA_IMM_MAX + 1][fpa_max];
1125 * Check, if a floating point tarval is an fpa immediate, i.e.
1126 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
1128 static int is_fpa_immediate(tarval *tv)
1130 ir_mode *mode = get_tarval_mode(tv);
1133 switch (get_mode_size_bits(mode)) {
1141 i = FPA_IMM_EXTENDED;
1144 if (tarval_is_negative(tv)) {
1145 tv = tarval_neg(tv);
1149 for (j = 0; j < fpa_max; ++j) {
1150 if (tv == fpa_imm[i][j])
1157 static ir_node *gen_Const(ir_node *node)
1159 ir_node *block = be_transform_node(get_nodes_block(node));
1160 ir_mode *mode = get_irn_mode(node);
1161 dbg_info *dbg = get_irn_dbg_info(node);
1163 if (mode_is_float(mode)) {
1165 ir_tarval *tv = get_Const_tarval(node);
1166 node = new_bd_arm_fConst(dbg, block, tv);
1168 } else if (USE_VFP(isa)) {
1169 assert(mode != mode_E && "IEEE Extended FP not supported");
1170 panic("VFP not supported yet");
1172 panic("Softfloat not supported yet");
1175 return create_const_graph(node, block);
1178 static ir_node *gen_SymConst(ir_node *node)
1180 ir_node *block = be_transform_node(get_nodes_block(node));
1181 ir_entity *entity = get_SymConst_entity(node);
1182 dbg_info *dbgi = get_irn_dbg_info(node);
1185 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
1189 static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0,
1192 /* the good way to do this would be to use the stm (store multiple)
1193 * instructions, since our input is nearly always 2 consecutive 32bit
1195 ir_graph *irg = current_ir_graph;
1196 ir_node *stack = get_irg_frame(irg);
1197 ir_node *nomem = get_irg_no_mem(irg);
1198 ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp,
1200 ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp,
1202 ir_node *in[2] = { str0, str1 };
1203 ir_node *sync = new_r_Sync(block, 2, in);
1205 set_irn_pinned(str0, op_pin_state_floats);
1206 set_irn_pinned(str1, op_pin_state_floats);
1208 ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true);
1209 set_irn_pinned(ldf, op_pin_state_floats);
1211 return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1214 static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node)
1216 ir_graph *irg = current_ir_graph;
1217 ir_node *stack = get_irg_frame(irg);
1218 ir_node *nomem = get_irg_no_mem(irg);
1219 ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp,
1222 set_irn_pinned(str, op_pin_state_floats);
1224 ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true);
1225 set_irn_pinned(ldf, op_pin_state_floats);
1227 return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1230 static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node)
1232 ir_graph *irg = current_ir_graph;
1233 ir_node *stack = get_irg_frame(irg);
1234 ir_node *nomem = get_irg_no_mem(irg);
1235 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F,
1238 set_irn_pinned(stf, op_pin_state_floats);
1240 ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1241 set_irn_pinned(ldr, op_pin_state_floats);
1243 return new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1246 static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node,
1247 ir_node **out_value0, ir_node **out_value1)
1249 ir_graph *irg = current_ir_graph;
1250 ir_node *stack = get_irg_frame(irg);
1251 ir_node *nomem = get_irg_no_mem(irg);
1252 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D,
1254 ir_node *ldr0, *ldr1;
1255 set_irn_pinned(stf, op_pin_state_floats);
1257 ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1258 set_irn_pinned(ldr0, op_pin_state_floats);
1259 ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true);
1260 set_irn_pinned(ldr1, op_pin_state_floats);
1262 *out_value0 = new_r_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
1263 *out_value1 = new_r_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
1266 static ir_node *gen_CopyB(ir_node *node)
1268 ir_node *block = be_transform_node(get_nodes_block(node));
1269 ir_node *src = get_CopyB_src(node);
1270 ir_node *new_src = be_transform_node(src);
1271 ir_node *dst = get_CopyB_dst(node);
1272 ir_node *new_dst = be_transform_node(dst);
1273 ir_node *mem = get_CopyB_mem(node);
1274 ir_node *new_mem = be_transform_node(mem);
1275 dbg_info *dbg = get_irn_dbg_info(node);
1276 int size = get_type_size_bytes(get_CopyB_type(node));
1280 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
1281 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
1283 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1284 new_bd_arm_EmptyReg(dbg, block),
1285 new_bd_arm_EmptyReg(dbg, block),
1286 new_bd_arm_EmptyReg(dbg, block),
1291 * Transform builtin clz.
1293 static ir_node *gen_clz(ir_node *node)
1295 ir_node *block = be_transform_node(get_nodes_block(node));
1296 dbg_info *dbg = get_irn_dbg_info(node);
1297 ir_node *op = get_irn_n(node, 1);
1298 ir_node *new_op = be_transform_node(op);
1300 /* TODO armv5 instruction, otherwise create a call */
1301 return new_bd_arm_Clz(dbg, block, new_op);
1305 * Transform Builtin node.
1307 static ir_node *gen_Builtin(ir_node *node)
1309 ir_builtin_kind kind = get_Builtin_kind(node);
1313 case ir_bk_debugbreak:
1314 case ir_bk_return_address:
1315 case ir_bk_frame_address:
1316 case ir_bk_prefetch:
1320 return gen_clz(node);
1323 case ir_bk_popcount:
1327 case ir_bk_inner_trampoline:
1330 panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
1334 * Transform Proj(Builtin) node.
1336 static ir_node *gen_Proj_Builtin(ir_node *proj)
1338 ir_node *node = get_Proj_pred(proj);
1339 ir_node *new_node = be_transform_node(node);
1340 ir_builtin_kind kind = get_Builtin_kind(node);
1343 case ir_bk_return_address:
1344 case ir_bk_frame_address:
1349 case ir_bk_popcount:
1351 assert(get_Proj_proj(proj) == pn_Builtin_1_result);
1354 case ir_bk_debugbreak:
1355 case ir_bk_prefetch:
1357 assert(get_Proj_proj(proj) == pn_Builtin_M);
1360 case ir_bk_inner_trampoline:
1363 panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
1366 static ir_node *gen_Proj_Load(ir_node *node)
1368 ir_node *load = get_Proj_pred(node);
1369 ir_node *new_load = be_transform_node(load);
1370 dbg_info *dbgi = get_irn_dbg_info(node);
1371 long proj = get_Proj_proj(node);
1373 /* renumber the proj */
1374 switch (get_arm_irn_opcode(new_load)) {
1376 /* handle all gp loads equal: they have the same proj numbers. */
1377 if (proj == pn_Load_res) {
1378 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1379 } else if (proj == pn_Load_M) {
1380 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1384 if (proj == pn_Load_res) {
1385 ir_mode *mode = get_Load_mode(load);
1386 return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res);
1387 } else if (proj == pn_Load_M) {
1388 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M);
1394 panic("Unsupported Proj from Load");
1397 static ir_node *gen_Proj_CopyB(ir_node *node)
1399 ir_node *pred = get_Proj_pred(node);
1400 ir_node *new_pred = be_transform_node(pred);
1401 dbg_info *dbgi = get_irn_dbg_info(node);
1402 long proj = get_Proj_proj(node);
1406 if (is_arm_CopyB(new_pred)) {
1407 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1413 panic("Unsupported Proj from CopyB");
1416 static ir_node *gen_Proj_Div(ir_node *node)
1418 ir_node *pred = get_Proj_pred(node);
1419 ir_node *new_pred = be_transform_node(pred);
1420 dbg_info *dbgi = get_irn_dbg_info(node);
1421 ir_mode *mode = get_irn_mode(node);
1422 long proj = get_Proj_proj(node);
1426 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
1428 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
1432 panic("Unsupported Proj from Div");
1436 * Transform the Projs from a Cmp.
1438 static ir_node *gen_Proj_Cmp(ir_node *node)
1441 /* we should only be here in case of a Mux node */
1445 static ir_node *gen_Proj_Start(ir_node *node)
1447 ir_node *block = get_nodes_block(node);
1448 ir_node *new_block = be_transform_node(block);
1449 long proj = get_Proj_proj(node);
1451 switch ((pn_Start) proj) {
1452 case pn_Start_X_initial_exec:
1453 /* we exchange the ProjX with a jump */
1454 return new_bd_arm_Jmp(NULL, new_block);
1457 return be_prolog_get_memory(abihelper);
1459 case pn_Start_T_args:
1460 return new_r_Bad(get_irn_irg(block), mode_T);
1462 case pn_Start_P_frame_base:
1463 return be_prolog_get_reg_value(abihelper, sp_reg);
1465 panic("unexpected start proj: %ld\n", proj);
1468 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1470 long pn = get_Proj_proj(node);
1471 ir_node *block = get_nodes_block(node);
1472 ir_node *new_block = be_transform_node(block);
1473 ir_entity *entity = get_irg_entity(current_ir_graph);
1474 ir_type *method_type = get_entity_type(entity);
1475 ir_type *param_type = get_method_param_type(method_type, pn);
1476 const reg_or_stackslot_t *param;
1478 /* Proj->Proj->Start must be a method argument */
1479 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1481 param = &cconv->parameters[pn];
1483 if (param->reg0 != NULL) {
1484 /* argument transmitted in register */
1485 ir_mode *mode = get_type_mode(param_type);
1486 ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0);
1488 if (mode_is_float(mode)) {
1489 ir_node *value1 = NULL;
1491 if (param->reg1 != NULL) {
1492 value1 = be_prolog_get_reg_value(abihelper, param->reg1);
1493 } else if (param->entity != NULL) {
1494 ir_graph *irg = get_irn_irg(node);
1495 ir_node *fp = get_irg_frame(irg);
1496 ir_node *mem = be_prolog_get_memory(abihelper);
1497 ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem,
1498 mode_gp, param->entity,
1500 value1 = new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1503 /* convert integer value to float */
1504 if (value1 == NULL) {
1505 value = int_to_float(NULL, new_block, value);
1507 value = ints_to_double(NULL, new_block, value, value1);
1512 /* argument transmitted on stack */
1513 ir_graph *irg = get_irn_irg(node);
1514 ir_node *fp = get_irg_frame(irg);
1515 ir_node *mem = be_prolog_get_memory(abihelper);
1516 ir_mode *mode = get_type_mode(param->type);
1520 if (mode_is_float(mode)) {
1521 load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode,
1522 param->entity, 0, 0, true);
1523 value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res);
1525 load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1526 param->entity, 0, 0, true);
1527 value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1529 set_irn_pinned(load, op_pin_state_floats);
1536 * Finds number of output value of a mode_T node which is constrained to
1537 * a single specific register.
1539 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1541 int n_outs = arch_irn_get_n_outs(node);
1544 for (o = 0; o < n_outs; ++o) {
1545 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1546 if (req == reg->single_req)
1552 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1554 long pn = get_Proj_proj(node);
1555 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1556 ir_node *new_call = be_transform_node(call);
1557 ir_type *function_type = get_Call_type(call);
1558 calling_convention_t *cconv
1559 = arm_decide_calling_convention(NULL, function_type);
1560 const reg_or_stackslot_t *res = &cconv->results[pn];
1564 /* TODO 64bit modes */
1565 assert(res->reg0 != NULL && res->reg1 == NULL);
1566 regn = find_out_for_reg(new_call, res->reg0);
1568 panic("Internal error in calling convention for return %+F", node);
1570 mode = res->reg0->reg_class->mode;
1572 arm_free_calling_convention(cconv);
1574 return new_r_Proj(new_call, mode, regn);
1577 static ir_node *gen_Proj_Call(ir_node *node)
1579 long pn = get_Proj_proj(node);
1580 ir_node *call = get_Proj_pred(node);
1581 ir_node *new_call = be_transform_node(call);
1583 switch ((pn_Call) pn) {
1585 return new_r_Proj(new_call, mode_M, 0);
1586 case pn_Call_X_regular:
1587 case pn_Call_X_except:
1588 case pn_Call_T_result:
1591 panic("Unexpected Call proj %ld\n", pn);
1595 * Transform a Proj node.
1597 static ir_node *gen_Proj(ir_node *node)
1599 ir_node *pred = get_Proj_pred(node);
1600 long proj = get_Proj_proj(node);
1602 switch (get_irn_opcode(pred)) {
1604 if (proj == pn_Store_M) {
1605 return be_transform_node(pred);
1607 panic("Unsupported Proj from Store");
1610 return gen_Proj_Load(node);
1612 return gen_Proj_Call(node);
1614 return gen_Proj_CopyB(node);
1616 return gen_Proj_Div(node);
1618 return gen_Proj_Cmp(node);
1620 return gen_Proj_Start(node);
1623 return be_duplicate_node(node);
1625 ir_node *pred_pred = get_Proj_pred(pred);
1626 if (is_Call(pred_pred)) {
1627 return gen_Proj_Proj_Call(node);
1628 } else if (is_Start(pred_pred)) {
1629 return gen_Proj_Proj_Start(node);
1634 return gen_Proj_Builtin(node);
1636 panic("code selection didn't expect Proj after %+F\n", pred);
1640 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1642 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
1643 create_const_node_func func,
1644 const arch_register_t* reg)
1646 ir_node *block, *res;
1651 block = get_irg_start_block(irg);
1652 res = func(NULL, block);
1653 arch_set_irn_register(res, reg);
1658 static ir_node *gen_Unknown(ir_node *node)
1660 ir_node *block = get_nodes_block(node);
1661 ir_node *new_block = be_transform_node(block);
1662 dbg_info *dbgi = get_irn_dbg_info(node);
1664 /* just produce a 0 */
1665 ir_mode *mode = get_irn_mode(node);
1666 if (mode_is_float(mode)) {
1667 ir_tarval *tv = get_mode_null(mode);
1668 ir_node *fconst = new_bd_arm_fConst(dbgi, new_block, tv);
1670 } else if (mode_needs_gp_reg(mode)) {
1671 return create_const_graph_value(dbgi, new_block, 0);
1674 panic("Unexpected Unknown mode");
1678 * Produces the type which sits between the stack args and the locals on the
1679 * stack. It will contain the return address and space to store the old base
1681 * @return The Firm type modeling the ABI between type.
1683 static ir_type *arm_get_between_type(void)
1685 static ir_type *between_type = NULL;
1687 if (between_type == NULL) {
1688 between_type = new_type_class(new_id_from_str("arm_between_type"));
1689 set_type_size_bytes(between_type, 0);
1692 return between_type;
1695 static void create_stacklayout(ir_graph *irg)
1697 ir_entity *entity = get_irg_entity(irg);
1698 ir_type *function_type = get_entity_type(entity);
1699 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1704 /* calling conventions must be decided by now */
1705 assert(cconv != NULL);
1707 /* construct argument type */
1708 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1709 n_params = get_method_n_params(function_type);
1710 for (p = 0; p < n_params; ++p) {
1711 reg_or_stackslot_t *param = &cconv->parameters[p];
1715 if (param->type == NULL)
1718 snprintf(buf, sizeof(buf), "param_%d", p);
1719 id = new_id_from_str(buf);
1720 param->entity = new_entity(arg_type, id, param->type);
1721 set_entity_offset(param->entity, param->offset);
1724 /* TODO: what about external functions? we don't know most of the stack
1725 * layout for them. And probably don't need all of this... */
1726 memset(layout, 0, sizeof(*layout));
1728 layout->frame_type = get_irg_frame_type(irg);
1729 layout->between_type = arm_get_between_type();
1730 layout->arg_type = arg_type;
1731 layout->param_map = NULL; /* TODO */
1732 layout->initial_offset = 0;
1733 layout->initial_bias = 0;
1734 layout->sp_relative = true;
1736 assert(N_FRAME_TYPES == 3);
1737 layout->order[0] = layout->frame_type;
1738 layout->order[1] = layout->between_type;
1739 layout->order[2] = layout->arg_type;
1743 * transform the start node to the prolog code
1745 static ir_node *gen_Start(ir_node *node)
1747 ir_graph *irg = get_irn_irg(node);
1748 ir_entity *entity = get_irg_entity(irg);
1749 ir_type *function_type = get_entity_type(entity);
1750 ir_node *block = get_nodes_block(node);
1751 ir_node *new_block = be_transform_node(block);
1752 dbg_info *dbgi = get_irn_dbg_info(node);
1756 /* stackpointer is important at function prolog */
1757 be_prolog_add_reg(abihelper, sp_reg,
1758 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1759 /* function parameters in registers */
1760 for (i = 0; i < get_method_n_params(function_type); ++i) {
1761 const reg_or_stackslot_t *param = &cconv->parameters[i];
1762 if (param->reg0 != NULL)
1763 be_prolog_add_reg(abihelper, param->reg0, arch_register_req_type_none);
1764 if (param->reg1 != NULL)
1765 be_prolog_add_reg(abihelper, param->reg1, arch_register_req_type_none);
1767 /* announce that we need the values of the callee save regs */
1768 for (i = 0; i < (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
1769 be_prolog_add_reg(abihelper, callee_saves[i], arch_register_req_type_none);
1772 start = be_prolog_create_start(abihelper, dbgi, new_block);
1776 static ir_node *get_stack_pointer_for(ir_node *node)
1778 /* get predecessor in stack_order list */
1779 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1782 if (stack_pred == NULL) {
1783 /* first stack user in the current block. We can simply use the
1784 * initial sp_proj for it */
1785 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1789 be_transform_node(stack_pred);
1790 stack = (ir_node*)pmap_get(node_to_stack, stack_pred);
1791 if (stack == NULL) {
1792 return get_stack_pointer_for(stack_pred);
1799 * transform a Return node into epilogue code + return statement
1801 static ir_node *gen_Return(ir_node *node)
1803 ir_node *block = get_nodes_block(node);
1804 ir_node *new_block = be_transform_node(block);
1805 dbg_info *dbgi = get_irn_dbg_info(node);
1806 ir_node *mem = get_Return_mem(node);
1807 ir_node *new_mem = be_transform_node(mem);
1808 int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
1809 ir_node *sp_proj = get_stack_pointer_for(node);
1810 int n_res = get_Return_n_ress(node);
1814 be_epilog_begin(abihelper);
1815 be_epilog_set_memory(abihelper, new_mem);
1816 /* connect stack pointer with initial stack pointer. fix_stack phase
1817 will later serialize all stack pointer adjusting nodes */
1818 be_epilog_add_reg(abihelper, sp_reg,
1819 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1823 for (i = 0; i < n_res; ++i) {
1824 ir_node *res_value = get_Return_res(node, i);
1825 ir_node *new_res_value = be_transform_node(res_value);
1826 const reg_or_stackslot_t *slot = &cconv->results[i];
1827 const arch_register_t *reg = slot->reg0;
1828 assert(slot->reg1 == NULL);
1829 be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, new_res_value);
1832 /* connect callee saves with their values at the function begin */
1833 for (i = 0; i < n_callee_saves; ++i) {
1834 const arch_register_t *reg = callee_saves[i];
1835 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1836 be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, value);
1839 /* epilog code: an incsp */
1840 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1845 static ir_node *gen_Call(ir_node *node)
1847 ir_graph *irg = get_irn_irg(node);
1848 ir_node *callee = get_Call_ptr(node);
1849 ir_node *block = get_nodes_block(node);
1850 ir_node *new_block = be_transform_node(block);
1851 ir_node *mem = get_Call_mem(node);
1852 ir_node *new_mem = be_transform_node(mem);
1853 dbg_info *dbgi = get_irn_dbg_info(node);
1854 ir_type *type = get_Call_type(node);
1855 calling_convention_t *cconv = arm_decide_calling_convention(NULL, type);
1856 size_t n_params = get_Call_n_params(node);
1857 size_t n_param_regs = cconv->n_reg_params;
1858 /* max inputs: memory, callee, register arguments */
1859 int max_inputs = 2 + n_param_regs;
1860 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1861 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1862 struct obstack *obst = be_get_be_obst(irg);
1863 const arch_register_req_t **in_req
1864 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1868 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1869 ir_entity *entity = NULL;
1870 ir_node *incsp = NULL;
1877 assert(n_params == get_method_n_params(type));
1879 /* construct arguments */
1882 in_req[in_arity] = arch_no_register_req;
1886 for (p = 0; p < n_params; ++p) {
1887 ir_node *value = get_Call_param(node, p);
1888 ir_node *new_value = be_transform_node(value);
1889 ir_node *new_value1 = NULL;
1890 const reg_or_stackslot_t *param = &cconv->parameters[p];
1891 ir_type *param_type = get_method_param_type(type, p);
1892 ir_mode *mode = get_type_mode(param_type);
1895 if (mode_is_float(mode) && param->reg0 != NULL) {
1896 unsigned size_bits = get_mode_size_bits(mode);
1897 if (size_bits == 64) {
1898 double_to_ints(dbgi, new_block, new_value, &new_value,
1901 assert(size_bits == 32);
1902 new_value = float_to_int(dbgi, new_block, new_value);
1906 /* put value into registers */
1907 if (param->reg0 != NULL) {
1908 in[in_arity] = new_value;
1909 in_req[in_arity] = param->reg0->single_req;
1911 if (new_value1 == NULL)
1914 if (param->reg1 != NULL) {
1915 assert(new_value1 != NULL);
1916 in[in_arity] = new_value1;
1917 in_req[in_arity] = param->reg1->single_req;
1922 /* we need a store if we're here */
1923 if (new_value1 != NULL) {
1924 new_value = new_value1;
1928 /* create a parameter frame if necessary */
1929 if (incsp == NULL) {
1930 ir_node *new_frame = get_stack_pointer_for(node);
1931 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1932 cconv->param_stack_size, 1);
1934 if (mode_is_float(mode)) {
1935 str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem,
1936 mode, NULL, 0, param->offset, true);
1938 str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem,
1939 mode, NULL, 0, param->offset, true);
1941 sync_ins[sync_arity++] = str;
1943 assert(in_arity <= max_inputs);
1945 /* construct memory input */
1946 if (sync_arity == 0) {
1947 in[mem_pos] = new_mem;
1948 } else if (sync_arity == 1) {
1949 in[mem_pos] = sync_ins[0];
1951 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1954 /* TODO: use a generic symconst matcher here */
1955 if (is_SymConst(callee)) {
1956 entity = get_SymConst_entity(callee);
1958 /* TODO: finish load matcher here */
1961 if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) {
1962 ir_node *load = get_Proj_pred(callee);
1963 ir_node *ptr = get_Load_ptr(load);
1964 ir_node *new_ptr = be_transform_node(ptr);
1965 ir_node *mem = get_Load_mem(load);
1966 ir_node *new_mem = be_transform_node(mem);
1967 ir_mode *mode = get_Load_mode(node);
1971 in[in_arity] = be_transform_node(callee);
1972 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1981 out_arity = 1 + n_caller_saves;
1983 if (entity != NULL) {
1984 /* TODO: use a generic symconst matcher here
1985 * so we can also handle entity+offset, etc. */
1986 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1989 * - use a proper shifter_operand matcher
1990 * - we could also use LinkLdrPC
1992 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1996 if (incsp != NULL) {
1997 /* IncSP to destroy the call stackframe */
1998 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
2000 /* if we are the last IncSP producer in a block then we have to keep
2002 * Note: This here keeps all producers which is more than necessary */
2003 add_irn_dep(incsp, res);
2006 pmap_insert(node_to_stack, node, incsp);
2009 arch_set_in_register_reqs(res, in_req);
2011 /* create output register reqs */
2012 arch_set_out_register_req(res, 0, arch_no_register_req);
2013 for (o = 0; o < n_caller_saves; ++o) {
2014 const arch_register_t *reg = caller_saves[o];
2015 arch_set_out_register_req(res, o+1, reg->single_req);
2018 /* copy pinned attribute */
2019 set_irn_pinned(res, get_irn_pinned(node));
2021 arm_free_calling_convention(cconv);
2025 static ir_node *gen_Sel(ir_node *node)
2027 dbg_info *dbgi = get_irn_dbg_info(node);
2028 ir_node *block = get_nodes_block(node);
2029 ir_node *new_block = be_transform_node(block);
2030 ir_node *ptr = get_Sel_ptr(node);
2031 ir_node *new_ptr = be_transform_node(ptr);
2032 ir_entity *entity = get_Sel_entity(node);
2034 /* must be the frame pointer all other sels must have been lowered
2036 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
2038 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
2042 * Change some phi modes
2044 static ir_node *gen_Phi(ir_node *node)
2046 const arch_register_req_t *req;
2047 ir_node *block = be_transform_node(get_nodes_block(node));
2048 ir_graph *irg = current_ir_graph;
2049 dbg_info *dbgi = get_irn_dbg_info(node);
2050 ir_mode *mode = get_irn_mode(node);
2053 if (mode_needs_gp_reg(mode)) {
2054 /* we shouldn't have any 64bit stuff around anymore */
2055 assert(get_mode_size_bits(mode) <= 32);
2056 /* all integer operations are on 32bit registers now */
2058 req = arm_reg_classes[CLASS_arm_gp].class_req;
2060 req = arch_no_register_req;
2063 /* phi nodes allow loops, so we use the old arguments for now
2064 * and fix this later */
2065 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
2066 get_irn_in(node) + 1);
2067 copy_node_attr(irg, node, phi);
2068 be_duplicate_deps(node, phi);
2070 arch_set_out_register_req(phi, 0, req);
2072 be_enqueue_preds(node);
2079 * Enters all transform functions into the generic pointer
2081 static void arm_register_transformers(void)
2083 be_start_transform_setup();
2085 be_set_transform_function(op_Add, gen_Add);
2086 be_set_transform_function(op_And, gen_And);
2087 be_set_transform_function(op_Call, gen_Call);
2088 be_set_transform_function(op_Cmp, gen_Cmp);
2089 be_set_transform_function(op_Cond, gen_Cond);
2090 be_set_transform_function(op_Const, gen_Const);
2091 be_set_transform_function(op_Conv, gen_Conv);
2092 be_set_transform_function(op_CopyB, gen_CopyB);
2093 be_set_transform_function(op_Div, gen_Div);
2094 be_set_transform_function(op_Eor, gen_Eor);
2095 be_set_transform_function(op_Jmp, gen_Jmp);
2096 be_set_transform_function(op_Load, gen_Load);
2097 be_set_transform_function(op_Minus, gen_Minus);
2098 be_set_transform_function(op_Mul, gen_Mul);
2099 be_set_transform_function(op_Not, gen_Not);
2100 be_set_transform_function(op_Or, gen_Or);
2101 be_set_transform_function(op_Phi, gen_Phi);
2102 be_set_transform_function(op_Proj, gen_Proj);
2103 be_set_transform_function(op_Return, gen_Return);
2104 be_set_transform_function(op_Rotl, gen_Rotl);
2105 be_set_transform_function(op_Sel, gen_Sel);
2106 be_set_transform_function(op_Shl, gen_Shl);
2107 be_set_transform_function(op_Shr, gen_Shr);
2108 be_set_transform_function(op_Shrs, gen_Shrs);
2109 be_set_transform_function(op_Start, gen_Start);
2110 be_set_transform_function(op_Store, gen_Store);
2111 be_set_transform_function(op_Sub, gen_Sub);
2112 be_set_transform_function(op_SymConst, gen_SymConst);
2113 be_set_transform_function(op_Unknown, gen_Unknown);
2114 be_set_transform_function(op_Builtin, gen_Builtin);
2118 * Initialize fpa Immediate support.
2120 static void arm_init_fpa_immediate(void)
2122 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
2123 fpa_imm[FPA_IMM_FLOAT][fpa_null] = get_mode_null(mode_F);
2124 fpa_imm[FPA_IMM_FLOAT][fpa_one] = get_mode_one(mode_F);
2125 fpa_imm[FPA_IMM_FLOAT][fpa_two] = new_tarval_from_str("2", 1, mode_F);
2126 fpa_imm[FPA_IMM_FLOAT][fpa_three] = new_tarval_from_str("3", 1, mode_F);
2127 fpa_imm[FPA_IMM_FLOAT][fpa_four] = new_tarval_from_str("4", 1, mode_F);
2128 fpa_imm[FPA_IMM_FLOAT][fpa_five] = new_tarval_from_str("5", 1, mode_F);
2129 fpa_imm[FPA_IMM_FLOAT][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
2130 fpa_imm[FPA_IMM_FLOAT][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
2132 fpa_imm[FPA_IMM_DOUBLE][fpa_null] = get_mode_null(mode_D);
2133 fpa_imm[FPA_IMM_DOUBLE][fpa_one] = get_mode_one(mode_D);
2134 fpa_imm[FPA_IMM_DOUBLE][fpa_two] = new_tarval_from_str("2", 1, mode_D);
2135 fpa_imm[FPA_IMM_DOUBLE][fpa_three] = new_tarval_from_str("3", 1, mode_D);
2136 fpa_imm[FPA_IMM_DOUBLE][fpa_four] = new_tarval_from_str("4", 1, mode_D);
2137 fpa_imm[FPA_IMM_DOUBLE][fpa_five] = new_tarval_from_str("5", 1, mode_D);
2138 fpa_imm[FPA_IMM_DOUBLE][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
2139 fpa_imm[FPA_IMM_DOUBLE][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
2141 fpa_imm[FPA_IMM_EXTENDED][fpa_null] = get_mode_null(mode_E);
2142 fpa_imm[FPA_IMM_EXTENDED][fpa_one] = get_mode_one(mode_E);
2143 fpa_imm[FPA_IMM_EXTENDED][fpa_two] = new_tarval_from_str("2", 1, mode_E);
2144 fpa_imm[FPA_IMM_EXTENDED][fpa_three] = new_tarval_from_str("3", 1, mode_E);
2145 fpa_imm[FPA_IMM_EXTENDED][fpa_four] = new_tarval_from_str("4", 1, mode_E);
2146 fpa_imm[FPA_IMM_EXTENDED][fpa_five] = new_tarval_from_str("5", 1, mode_E);
2147 fpa_imm[FPA_IMM_EXTENDED][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
2148 fpa_imm[FPA_IMM_EXTENDED][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
2152 * Transform a Firm graph into an ARM graph.
2154 void arm_transform_graph(ir_graph *irg)
2156 static int imm_initialized = 0;
2157 ir_entity *entity = get_irg_entity(irg);
2158 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
2159 ir_type *frame_type;
2164 if (! imm_initialized) {
2165 arm_init_fpa_immediate();
2166 imm_initialized = 1;
2168 arm_register_transformers();
2170 isa = (arm_isa_t*) arch_env;
2172 node_to_stack = pmap_create();
2174 assert(abihelper == NULL);
2175 abihelper = be_abihelper_prepare(irg);
2176 be_collect_stacknodes(abihelper);
2177 assert(cconv == NULL);
2178 cconv = arm_decide_calling_convention(irg, get_entity_type(entity));
2179 create_stacklayout(irg);
2181 be_transform_graph(irg, NULL);
2183 be_abihelper_finish(abihelper);
2186 arm_free_calling_convention(cconv);
2189 frame_type = get_irg_frame_type(irg);
2190 if (get_type_state(frame_type) == layout_undefined) {
2191 default_layout_compound_type(frame_type);
2194 pmap_destroy(node_to_stack);
2195 node_to_stack = NULL;
2197 be_add_missing_keeps(irg);
2200 void arm_init_transform(void)
2202 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");