2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
31 #include "irgraph_t.h"
43 #include "../benode_t.h"
44 #include "../beirg_t.h"
45 #include "../beutil.h"
46 #include "../betranshlp.h"
47 #include "bearch_arm_t.h"
49 #include "arm_nodes_attr.h"
51 #include "arm_transform.h"
52 #include "arm_optimize.h"
53 #include "arm_new_nodes.h"
54 #include "arm_map_regs.h"
56 #include "gen_arm_regalloc_if.h"
61 /** hold the current code generator during transformation */
62 static arm_code_gen_t *env_cg;
64 extern ir_op *get_op_Mulh(void);
67 /****************************************************************************************************
69 * | | | | / _| | | (_)
70 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
71 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
72 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
73 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
75 ****************************************************************************************************/
77 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
78 return mode_is_int(mode) || mode_is_reference(mode);
82 * Creates a arm_Const node.
84 static ir_node *create_mov_node(dbg_info *dbg, ir_node *block, long value) {
85 ir_mode *mode = mode_Iu;
86 ir_graph *irg = current_ir_graph;
89 if (mode_needs_gp_reg(mode))
91 res = new_rd_arm_Mov_i(dbg, irg, block, mode, value);
92 /* ensure the const is scheduled AFTER the stack frame */
93 add_irn_dep(res, get_irg_frame(irg));
98 * Creates a arm_Const_Neg node.
100 static ir_node *create_mvn_node(dbg_info *dbg, ir_node *block, long value) {
101 ir_mode *mode = mode_Iu;
102 ir_graph *irg = current_ir_graph;
105 if (mode_needs_gp_reg(mode))
107 res = new_rd_arm_Mvn_i(dbg, irg, block, mode, value);
108 /* ensure the const is scheduled AFTER the stack frame */
109 add_irn_dep(res, get_irg_frame(irg));
113 #define NEW_BINOP_NODE(opname, env, op1, op2) new_rd_arm_##opname(env->dbg, current_ir_graph, env->block, op1, op2, env->mode)
116 * Creates a possible DAG for an constant.
118 static ir_node *create_const_graph_value(dbg_info *dbg, ir_node *block, unsigned int value) {
122 ir_mode *mode = mode_Iu;
124 arm_gen_vals_from_word(value, &v);
125 arm_gen_vals_from_word(~value, &vn);
127 if (vn.ops < v.ops) {
129 result = create_mvn_node(dbg, block, arm_encode_imm_w_shift(vn.shifts[0], vn.values[0]));
131 for (cnt = 1; cnt < vn.ops; ++cnt) {
132 long value = arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]);
133 ir_node *bic_i_node = new_rd_arm_Bic_i(dbg, current_ir_graph, block, result, mode, value);
139 result = create_mov_node(dbg, block, arm_encode_imm_w_shift(v.shifts[0], v.values[0]));
141 for (cnt = 1; cnt < v.ops; ++cnt) {
142 long value = arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]);
143 ir_node *orr_i_node = new_rd_arm_Or_i(dbg, current_ir_graph, block, result, mode, value);
151 * Create a DAG constructing a given Const.
153 * @param irn a Firm const
155 static ir_node *create_const_graph(ir_node *irn, ir_node *block) {
156 tarval *tv = get_Const_tarval(irn);
157 ir_mode *mode = get_tarval_mode(tv);
160 if (mode_is_reference(mode)) {
161 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
162 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
163 tv = tarval_convert_to(tv, mode_Iu);
165 value = get_tarval_long(tv);
166 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
170 * Create an And that will mask all upper bits
172 static ir_node *gen_zero_extension(dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) {
173 unsigned mask_bits = (1 << result_bits) - 1;
174 ir_node *mask_node = create_const_graph_value(dbg, block, mask_bits);
175 return new_rd_arm_And(dbg, current_ir_graph, block, op, mask_node, mode_Iu, ARM_SHF_NONE, 0);
179 * Generate code for a sign extension.
181 static ir_node *gen_sign_extension(dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) {
182 ir_graph *irg = current_ir_graph;
183 int shift_width = 32 - result_bits;
184 ir_node *shift_const_node = create_const_graph_value(dbg, block, shift_width);
185 ir_node *lshift_node = new_rd_arm_Shl(dbg, irg, block, op, shift_const_node, mode_Iu);
186 ir_node *rshift_node = new_rd_arm_Shrs(dbg, irg, block, lshift_node, shift_const_node, mode_Iu);
191 * Transforms a Conv node.
193 * @return The created ia32 Conv node
195 static ir_node *gen_Conv(ir_node *node) {
196 ir_node *block = be_transform_node(get_nodes_block(node));
197 ir_node *op = get_Conv_op(node);
198 ir_node *new_op = be_transform_node(op);
199 ir_graph *irg = current_ir_graph;
200 ir_mode *src_mode = get_irn_mode(op);
201 ir_mode *dst_mode = get_irn_mode(node);
202 dbg_info *dbg = get_irn_dbg_info(node);
204 if (src_mode == dst_mode)
207 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
208 env_cg->have_fp_insn = 1;
210 if (USE_FPA(env_cg->isa)) {
211 if (mode_is_float(src_mode)) {
212 if (mode_is_float(dst_mode)) {
213 /* from float to float */
214 return new_rd_arm_fpaMvf(dbg, irg, block, new_op, dst_mode);
217 /* from float to int */
218 return new_rd_arm_fpaFix(dbg, irg, block, new_op, dst_mode);
222 /* from int to float */
223 return new_rd_arm_fpaFlt(dbg, irg, block, new_op, dst_mode);
226 else if (USE_VFP(env_cg->isa)) {
227 panic("VFP not supported yet\n");
231 panic("Softfloat not supported yet\n");
235 else { /* complete in gp registers */
236 int src_bits = get_mode_size_bits(src_mode);
237 int dst_bits = get_mode_size_bits(dst_mode);
241 if (is_Load(skip_Proj(op))) {
242 if (src_bits == dst_bits) {
243 /* kill unneccessary conv */
246 /* after a load, the bit size is already converted */
250 if (src_bits == dst_bits) {
251 /* kill unneccessary conv */
253 } else if (dst_bits <= 32 && src_bits <= 32) {
254 if (src_bits < dst_bits) {
261 if (mode_is_signed(min_mode)) {
262 return gen_sign_extension(dbg, block, new_op, min_bits);
264 return gen_zero_extension(dbg, block, new_op, min_bits);
267 panic("Cannot handle Conv %+F->%+F with %d->%d bits\n", src_mode, dst_mode,
275 * Return true if an operand is a shifter operand
277 static int is_shifter_operand(ir_node *n, arm_shift_modifier *pmod) {
278 arm_shift_modifier mod = ARM_SHF_NONE;
281 mod = get_arm_shift_modifier(n);
284 if (mod != ARM_SHF_NONE) {
285 long v = get_arm_imm_value(n);
293 * Creates an ARM Add.
295 * @return the created arm Add node
297 static ir_node *gen_Add(ir_node *node) {
298 ir_node *block = be_transform_node(get_nodes_block(node));
299 ir_node *op1 = get_Add_left(node);
300 ir_node *new_op1 = be_transform_node(op1);
301 ir_node *op2 = get_Add_right(node);
302 ir_node *new_op2 = be_transform_node(op2);
303 ir_mode *mode = get_irn_mode(node);
304 ir_graph *irg = current_ir_graph;
307 arm_shift_modifier mod;
308 dbg_info *dbg = get_irn_dbg_info(node);
310 if (mode_is_float(mode)) {
311 env_cg->have_fp_insn = 1;
312 if (USE_FPA(env_cg->isa)) {
313 if (is_arm_fpaMvf_i(new_op1))
314 return new_rd_arm_fpaAdf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1));
315 if (is_arm_fpaMvf_i(new_op2))
316 return new_rd_arm_fpaAdf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2));
317 return new_rd_arm_fpaAdf(dbg, irg, block, new_op1, new_op2, mode);
318 } else if (USE_VFP(env_cg->isa)) {
319 assert(mode != mode_E && "IEEE Extended FP not supported");
320 panic("VFP not supported yet\n");
324 panic("Softfloat not supported yet\n");
328 assert(mode_is_data(mode));
331 if (is_arm_Mov_i(new_op1))
332 return new_rd_arm_Add_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1));
333 if (is_arm_Mov_i(new_op2))
334 return new_rd_arm_Add_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2));
337 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
339 new_op2 = get_irn_n(new_op1, 1);
340 new_op1 = get_irn_n(new_op1, 0);
342 return new_rd_arm_Mla(dbg, irg, block, new_op1, new_op2, new_op3, mode);
344 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
346 new_op1 = get_irn_n(new_op2, 0);
347 new_op2 = get_irn_n(new_op2, 1);
349 return new_rd_arm_Mla(dbg, irg, block, new_op1, new_op2, new_op3, mode);
352 /* is the first a shifter */
353 v = is_shifter_operand(new_op1, &mod);
355 new_op1 = get_irn_n(new_op1, 0);
356 return new_rd_arm_Add(dbg, irg, block, new_op2, new_op1, mode, mod, v);
358 /* is the second a shifter */
359 v = is_shifter_operand(new_op2, &mod);
361 new_op2 = get_irn_n(new_op2, 0);
362 return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, mod, v);
366 return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0);
371 * Creates an ARM Mul.
373 * @return the created arm Mul node
375 static ir_node *gen_Mul(ir_node *node) {
376 ir_node *block = be_transform_node(get_nodes_block(node));
377 ir_node *op1 = get_Mul_left(node);
378 ir_node *new_op1 = be_transform_node(op1);
379 ir_node *op2 = get_Mul_right(node);
380 ir_node *new_op2 = be_transform_node(op2);
381 ir_mode *mode = get_irn_mode(node);
382 ir_graph *irg = current_ir_graph;
383 dbg_info *dbg = get_irn_dbg_info(node);
385 if (mode_is_float(mode)) {
386 env_cg->have_fp_insn = 1;
387 if (USE_FPA(env_cg->isa)) {
388 if (is_arm_Mov_i(new_op1))
389 return new_rd_arm_fpaMuf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1));
390 if (is_arm_Mov_i(new_op2))
391 return new_rd_arm_fpaMuf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2));
392 return new_rd_arm_fpaMuf(dbg, irg, block, new_op1, new_op2, mode);
394 else if (USE_VFP(env_cg->isa)) {
395 assert(mode != mode_E && "IEEE Extended FP not supported");
396 panic("VFP not supported yet\n");
400 panic("Softfloat not supported yet\n");
404 assert(mode_is_data(mode));
406 return new_rd_arm_Mul(dbg, irg, block, new_op1, new_op2, mode);
410 * Creates an ARM floating point Div.
412 * @param env The transformation environment
413 * @return the created arm fDiv node
415 static ir_node *gen_Quot(ir_node *node) {
416 ir_node *block = be_transform_node(get_nodes_block(node));
417 ir_node *op1 = get_Quot_left(node);
418 ir_node *new_op1 = be_transform_node(op1);
419 ir_node *op2 = get_Quot_right(node);
420 ir_node *new_op2 = be_transform_node(op2);
421 ir_mode *mode = get_irn_mode(node);
422 dbg_info *dbg = get_irn_dbg_info(node);
424 assert(mode != mode_E && "IEEE Extended FP not supported");
426 env_cg->have_fp_insn = 1;
427 if (USE_FPA(env_cg->isa)) {
428 if (is_arm_Mov_i(new_op1))
429 return new_rd_arm_fpaRdf_i(dbg, current_ir_graph, block, new_op2, mode, get_arm_imm_value(new_op1));
430 if (is_arm_Mov_i(new_op2))
431 return new_rd_arm_fpaDvf_i(dbg, current_ir_graph, block, new_op1, mode, get_arm_imm_value(new_op2));
432 return new_rd_arm_fpaDvf(dbg, current_ir_graph, block, new_op1, new_op2, mode);
433 } else if (USE_VFP(env_cg->isa)) {
434 assert(mode != mode_E && "IEEE Extended FP not supported");
435 panic("VFP not supported yet\n");
438 panic("Softfloat not supported yet\n");
443 #define GEN_INT_OP(op) \
444 ir_node *block = be_transform_node(get_nodes_block(node)); \
445 ir_node *op1 = get_ ## op ## _left(node); \
446 ir_node *new_op1 = be_transform_node(op1); \
447 ir_node *op2 = get_ ## op ## _right(node); \
448 ir_node *new_op2 = be_transform_node(op2); \
449 ir_graph *irg = current_ir_graph; \
450 ir_mode *mode = mode_Iu; \
451 dbg_info *dbg = get_irn_dbg_info(node); \
453 arm_shift_modifier mod; \
455 if (is_arm_Mov_i(new_op1)) \
456 return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); \
457 if (is_arm_Mov_i(new_op2)) \
458 return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); \
459 /* is the first a shifter */ \
460 v = is_shifter_operand(new_op1, &mod); \
462 new_op1 = get_irn_n(new_op1, 0); \
463 return new_rd_arm_ ## op(dbg, irg, block, new_op2, new_op1, mode, mod, v); \
465 /* is the second a shifter */ \
466 v = is_shifter_operand(new_op2, &mod); \
468 new_op2 = get_irn_n(new_op2, 0); \
469 return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, mod, v); \
472 return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0) \
475 * Creates an ARM And.
477 * @return the created arm And node
479 static ir_node *gen_And(ir_node *node) {
484 * Creates an ARM Orr.
486 * @param env The transformation environment
487 * @return the created arm Or node
489 static ir_node *gen_Or(ir_node *node) {
494 * Creates an ARM Eor.
496 * @return the created arm Eor node
498 static ir_node *gen_Eor(ir_node *node) {
503 * Creates an ARM Sub.
505 * @return the created arm Sub node
507 static ir_node *gen_Sub(ir_node *node) {
508 ir_node *block = be_transform_node(get_nodes_block(node));
509 ir_node *op1 = get_Sub_left(node);
510 ir_node *new_op1 = be_transform_node(op1);
511 ir_node *op2 = get_Sub_right(node);
512 ir_node *new_op2 = be_transform_node(op2);
513 ir_mode *mode = get_irn_mode(node);
514 ir_graph *irg = current_ir_graph;
515 dbg_info *dbg = get_irn_dbg_info(node);
517 arm_shift_modifier mod;
519 if (mode_is_float(mode)) {
520 env_cg->have_fp_insn = 1;
521 if (USE_FPA(env_cg->isa)) {
522 if (is_arm_Mov_i(new_op1))
523 return new_rd_arm_fpaRsf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1));
524 if (is_arm_Mov_i(new_op2))
525 return new_rd_arm_fpaSuf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2));
526 return new_rd_arm_fpaSuf(dbg, irg, block, new_op1, new_op2, mode);
527 } else if (USE_VFP(env_cg->isa)) {
528 assert(mode != mode_E && "IEEE Extended FP not supported");
529 panic("VFP not supported yet\n");
533 panic("Softfloat not supported yet\n");
538 assert(mode_is_data(mode) && "unknown mode for Sub");
541 if (is_arm_Mov_i(new_op1))
542 return new_rd_arm_Rsb_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1));
543 if (is_arm_Mov_i(new_op2))
544 return new_rd_arm_Sub_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2));
546 /* is the first a shifter */
547 v = is_shifter_operand(new_op1, &mod);
549 new_op1 = get_irn_n(new_op1, 0);
550 return new_rd_arm_Rsb(dbg, irg, block, new_op2, new_op1, mode, mod, v);
552 /* is the second a shifter */
553 v = is_shifter_operand(new_op2, &mod);
555 new_op2 = get_irn_n(new_op2, 0);
556 return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, mod, v);
559 return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0);
564 * Creates an ARM Shl.
566 * @return the created ARM Shl node
568 static ir_node *gen_Shl(ir_node *node) {
569 ir_node *block = be_transform_node(get_nodes_block(node));
570 ir_node *op1 = get_Shl_left(node);
571 ir_node *new_op1 = be_transform_node(op1);
572 ir_node *op2 = get_Shl_right(node);
573 ir_node *new_op2 = be_transform_node(op2);
574 ir_mode *mode = mode_Iu;
575 dbg_info *dbg = get_irn_dbg_info(node);
577 if (is_arm_Mov_i(new_op2)) {
578 return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSL, get_arm_imm_value(new_op2));
580 return new_rd_arm_Shl(dbg, current_ir_graph, block, new_op1, new_op2, mode);
584 * Creates an ARM Shr.
586 * @return the created ARM Shr node
588 static ir_node *gen_Shr(ir_node *node) {
589 ir_node *block = be_transform_node(get_nodes_block(node));
590 ir_node *op1 = get_Shr_left(node);
591 ir_node *new_op1 = be_transform_node(op1);
592 ir_node *op2 = get_Shr_right(node);
593 ir_node *new_op2 = be_transform_node(op2);
594 ir_mode *mode = mode_Iu;
595 dbg_info *dbg = get_irn_dbg_info(node);
597 if (is_arm_Mov_i(new_op2)) {
598 return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSR, get_arm_imm_value(new_op2));
600 return new_rd_arm_Shr(dbg, current_ir_graph, block, new_op1, new_op2, mode);
604 * Creates an ARM Shrs.
606 * @return the created ARM Shrs node
608 static ir_node *gen_Shrs(ir_node *node) {
609 ir_node *block = be_transform_node(get_nodes_block(node));
610 ir_node *op1 = get_Shrs_left(node);
611 ir_node *new_op1 = be_transform_node(op1);
612 ir_node *op2 = get_Shrs_right(node);
613 ir_node *new_op2 = be_transform_node(op2);
614 ir_mode *mode = mode_Iu;
615 dbg_info *dbg = get_irn_dbg_info(node);
617 if (is_arm_Mov_i(new_op2)) {
618 return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_ASR, get_arm_imm_value(new_op2));
620 return new_rd_arm_Shrs(dbg, current_ir_graph, block, new_op1, new_op2, mode);
624 * Transforms a Not node.
626 * @return the created ARM Not node
628 static ir_node *gen_Not(ir_node *node) {
629 ir_node *block = be_transform_node(get_nodes_block(node));
630 ir_node *op = get_Not_op(node);
631 ir_node *new_op = be_transform_node(op);
632 dbg_info *dbg = get_irn_dbg_info(node);
633 ir_mode *mode = mode_Iu;
634 arm_shift_modifier mod = ARM_SHF_NONE;
635 int v = is_shifter_operand(new_op, &mod);
638 new_op = get_irn_n(new_op, 0);
640 return new_rd_arm_Mvn(dbg, current_ir_graph, block, new_op, mode, mod, v);
644 * Transforms an Abs node.
646 * @param env The transformation environment
647 * @return the created ARM Abs node
649 static ir_node *gen_Abs(ir_node *node) {
650 ir_node *block = be_transform_node(get_nodes_block(node));
651 ir_node *op = get_Abs_op(node);
652 ir_node *new_op = be_transform_node(op);
653 dbg_info *dbg = get_irn_dbg_info(node);
654 ir_mode *mode = get_irn_mode(node);
656 if (mode_is_float(mode)) {
657 env_cg->have_fp_insn = 1;
658 if (USE_FPA(env_cg->isa))
659 return new_rd_arm_fpaAbs(dbg, current_ir_graph, block, new_op, mode);
660 else if (USE_VFP(env_cg->isa)) {
661 assert(mode != mode_E && "IEEE Extended FP not supported");
662 panic("VFP not supported yet\n");
665 panic("Softfloat not supported yet\n");
668 assert(mode_is_data(mode));
670 return new_rd_arm_Abs(dbg, current_ir_graph, block, new_op, mode);
674 * Transforms a Minus node.
676 * @return the created ARM Minus node
678 static ir_node *gen_Minus(ir_node *node) {
679 ir_node *block = be_transform_node(get_nodes_block(node));
680 ir_node *op = get_Minus_op(node);
681 ir_node *new_op = be_transform_node(op);
682 dbg_info *dbg = get_irn_dbg_info(node);
683 ir_mode *mode = get_irn_mode(node);
685 if (mode_is_float(mode)) {
686 env_cg->have_fp_insn = 1;
687 if (USE_FPA(env_cg->isa))
688 return new_rd_arm_fpaMvf(dbg, current_ir_graph, block, op, mode);
689 else if (USE_VFP(env_cg->isa)) {
690 assert(mode != mode_E && "IEEE Extended FP not supported");
691 panic("VFP not supported yet\n");
694 panic("Softfloat not supported yet\n");
697 assert(mode_is_data(mode));
699 return new_rd_arm_Rsb_i(dbg, current_ir_graph, block, new_op, mode, 0);
705 * @return the created ARM Load node
707 static ir_node *gen_Load(ir_node *node) {
708 ir_node *block = be_transform_node(get_nodes_block(node));
709 ir_node *ptr = get_Load_ptr(node);
710 ir_node *new_ptr = be_transform_node(ptr);
711 ir_node *mem = get_Load_mem(node);
712 ir_node *new_mem = be_transform_node(mem);
713 ir_mode *mode = get_Load_mode(node);
714 ir_graph *irg = current_ir_graph;
715 dbg_info *dbg = get_irn_dbg_info(node);
716 ir_node *new_load = NULL;
718 if (mode_is_float(mode)) {
719 env_cg->have_fp_insn = 1;
720 if (USE_FPA(env_cg->isa))
721 new_load = new_rd_arm_fpaLdf(dbg, irg, block, new_ptr, new_mem, mode);
722 else if (USE_VFP(env_cg->isa)) {
723 assert(mode != mode_E && "IEEE Extended FP not supported");
724 panic("VFP not supported yet\n");
727 panic("Softfloat not supported yet\n");
731 assert(mode_is_data(mode) && "unsupported mode for Load");
733 if (mode_is_signed(mode)) {
734 /* sign extended loads */
735 switch (get_mode_size_bits(mode)) {
737 new_load = new_rd_arm_Loadbs(dbg, irg, block, new_ptr, new_mem);
740 new_load = new_rd_arm_Loadhs(dbg, irg, block, new_ptr, new_mem);
743 new_load = new_rd_arm_Load(dbg, irg, block, new_ptr, new_mem);
746 panic("mode size not supported\n");
749 /* zero extended loads */
750 switch (get_mode_size_bits(mode)) {
752 new_load = new_rd_arm_Loadb(dbg, irg, block, new_ptr, new_mem);
755 new_load = new_rd_arm_Loadh(dbg, irg, block, new_ptr, new_mem);
758 new_load = new_rd_arm_Load(dbg, irg, block, new_ptr, new_mem);
761 panic("mode size not supported\n");
765 set_irn_pinned(new_load, get_irn_pinned(node));
767 /* check for special case: the loaded value might not be used */
768 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
769 /* add a result proj and a Keep to produce a pseudo use */
770 ir_node *proj = new_r_Proj(irg, block, new_load, mode_Iu, pn_arm_Load_res);
771 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
778 * Transforms a Store.
780 * @return the created ARM Store node
782 static ir_node *gen_Store(ir_node *node) {
783 ir_node *block = be_transform_node(get_nodes_block(node));
784 ir_node *ptr = get_Store_ptr(node);
785 ir_node *new_ptr = be_transform_node(ptr);
786 ir_node *mem = get_Store_mem(node);
787 ir_node *new_mem = be_transform_node(mem);
788 ir_node *val = get_Store_value(node);
789 ir_node *new_val = be_transform_node(val);
790 ir_mode *mode = get_irn_mode(val);
791 ir_graph *irg = current_ir_graph;
792 dbg_info *dbg = get_irn_dbg_info(node);
793 ir_node *new_store = NULL;
795 if (mode_is_float(mode)) {
796 env_cg->have_fp_insn = 1;
797 if (USE_FPA(env_cg->isa))
798 new_store = new_rd_arm_fpaStf(dbg, irg, block, new_ptr, new_val, new_mem, mode);
799 else if (USE_VFP(env_cg->isa)) {
800 assert(mode != mode_E && "IEEE Extended FP not supported");
801 panic("VFP not supported yet\n");
803 panic("Softfloat not supported yet\n");
806 assert(mode_is_data(mode) && "unsupported mode for Store");
807 switch (get_mode_size_bits(mode)) {
809 new_store = new_rd_arm_Storeb(dbg, irg, block, new_ptr, new_val, new_mem);
811 new_store = new_rd_arm_Storeh(dbg, irg, block, new_ptr, new_val, new_mem);
813 new_store = new_rd_arm_Store(dbg, irg, block, new_ptr, new_val, new_mem);
816 set_irn_pinned(new_store, get_irn_pinned(node));
823 * @return the created ARM Cond node
825 static ir_node *gen_Cond(ir_node *node) {
826 ir_node *block = be_transform_node(get_nodes_block(node));
827 ir_node *selector = get_Cond_selector(node);
828 ir_graph *irg = current_ir_graph;
829 dbg_info *dbg = get_irn_dbg_info(node);
830 ir_mode *mode = get_irn_mode(selector);
832 if (mode == mode_b) {
833 /* an conditional jump */
834 ir_node *cmp_node = get_Proj_pred(selector);
835 ir_node *op1 = get_Cmp_left(cmp_node);
836 ir_node *new_op1 = be_transform_node(op1);
837 ir_node *op2 = get_Cmp_right(cmp_node);
838 ir_node *new_op2 = be_transform_node(op2);
840 if (mode_is_float(get_irn_mode(op1))) {
841 /* floating point compare */
842 pn_Cmp pnc = get_Proj_proj(selector);
844 if (pnc & pn_Cmp_Uo) {
845 /* check for unordered, need cmf */
846 return new_rd_arm_fpaCmfBra(dbg, irg, block, new_op1, new_op2, pnc);
848 /* Hmm: use need cmfe */
849 return new_rd_arm_fpaCmfeBra(dbg, irg, block, new_op1, new_op2, pnc);
851 /* integer compare */
852 return new_rd_arm_CmpBra(dbg, irg, block, new_op1, new_op2, get_Proj_proj(selector));
856 ir_node *new_op = be_transform_node(selector);
857 ir_node *const_graph;
861 const ir_edge_t *edge;
868 foreach_out_edge(node, edge) {
869 proj = get_edge_src_irn(edge);
870 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
872 pn = get_Proj_proj(proj);
874 min = pn<min ? pn : min;
875 max = pn>max ? pn : max;
878 n_projs = max - translation + 1;
880 foreach_out_edge(node, edge) {
881 proj = get_edge_src_irn(edge);
882 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
884 pn = get_Proj_proj(proj) - translation;
885 set_Proj_proj(proj, pn);
888 const_graph = create_const_graph_value(dbg, block, translation);
889 sub = new_rd_arm_Sub(dbg, irg, block, new_op, const_graph, mode, ARM_SHF_NONE, 0);
890 return new_rd_arm_SwitchJmp(dbg, irg, block, sub, n_projs, get_Cond_defaultProj(node) - translation);
895 * Returns the name of a SymConst.
896 * @param symc the SymConst
897 * @return name of the SymConst
899 static ident *get_sc_ident(ir_node *symc) {
902 switch (get_SymConst_kind(symc)) {
903 case symconst_addr_name:
904 return get_SymConst_name(symc);
906 case symconst_addr_ent:
907 ent = get_SymConst_entity(symc);
908 set_entity_backend_marked(ent, 1);
909 return get_entity_ld_ident(ent);
912 assert(0 && "Unsupported SymConst");
918 static tarval *fpa_imm[3][fpa_max];
921 * Check, if a floating point tarval is an fpa immediate, i.e.
922 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
924 static int is_fpa_immediate(tarval *tv) {
925 ir_mode *mode = get_tarval_mode(tv);
928 switch (get_mode_size_bits(mode)) {
939 if (tarval_cmp(tv, get_tarval_null(mode)) & pn_Cmp_Lt) {
944 for (j = 0; j < fpa_max; ++j) {
945 if (tv == fpa_imm[i][j])
952 * Transforms a Const node.
954 * @return The transformed ARM node.
956 static ir_node *gen_Const(ir_node *node) {
957 ir_node *block = be_transform_node(get_nodes_block(node));
958 ir_graph *irg = current_ir_graph;
959 ir_mode *mode = get_irn_mode(node);
960 dbg_info *dbg = get_irn_dbg_info(node);
962 if (mode_is_float(mode)) {
963 env_cg->have_fp_insn = 1;
964 if (USE_FPA(env_cg->isa)) {
965 tarval *tv = get_Const_tarval(node);
966 int imm = is_fpa_immediate(tv);
968 if (imm != fpa_max) {
970 node = new_rd_arm_fpaMvf_i(dbg, irg, block, mode, imm);
972 node = new_rd_arm_fpaMnf_i(dbg, irg, block, mode, -imm);
974 node = new_rd_arm_fpaConst(dbg, irg, block, tv);
976 /* ensure the const is scheduled AFTER the stack frame */
977 add_irn_dep(node, get_irg_frame(irg));
980 else if (USE_VFP(env_cg->isa)) {
981 assert(mode != mode_E && "IEEE Extended FP not supported");
982 panic("VFP not supported yet\n");
985 panic("Softfloat not supported yet\n");
988 return create_const_graph(node, block);
992 * Transforms a SymConst node.
994 * @return The transformed ARM node.
996 static ir_node *gen_SymConst(ir_node *node) {
997 ir_node *block = be_transform_node(get_nodes_block(node));
998 ir_mode *mode = mode_Iu;
999 dbg_info *dbg = get_irn_dbg_info(node);
1000 ir_graph *irg = current_ir_graph;
1003 res = new_rd_arm_SymConst(dbg, irg, block, mode, get_sc_ident(node));
1004 /* ensure the const is scheduled AFTER the stack frame */
1005 add_irn_dep(res, get_irg_frame(irg));
1010 * Transforms a CopyB node.
1012 * @return The transformed ARM node.
1014 static ir_node *gen_CopyB(ir_node *node) {
1015 ir_node *block = be_transform_node(get_nodes_block(node));
1016 ir_node *src = get_CopyB_src(node);
1017 ir_node *new_src = be_transform_node(src);
1018 ir_node *dst = get_CopyB_dst(node);
1019 ir_node *new_dst = be_transform_node(dst);
1020 ir_node *mem = get_CopyB_mem(node);
1021 ir_node *new_mem = be_transform_node(mem);
1022 ir_graph *irg = current_ir_graph;
1023 dbg_info *dbg = get_irn_dbg_info(node);
1024 int size = get_type_size_bytes(get_CopyB_type(node));
1028 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, new_src);
1029 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, new_dst);
1031 return new_rd_arm_CopyB(dbg, irg, block, dst_copy, src_copy,
1032 new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu),
1033 new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu),
1034 new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu),
1039 /********************************************
1042 * | |__ ___ _ __ ___ __| | ___ ___
1043 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1044 * | |_) | __/ | | | (_) | (_| | __/\__ \
1045 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1047 ********************************************/
1050 * Return an expanding stack offset.
1051 * Note that function is called in the transform phase
1052 * where the stack offsets are still relative regarding
1053 * the first (frame allocating) IncSP.
1054 * However this is exactly what we want because frame
1055 * access must be done relative the the fist IncSP ...
1057 static int get_sp_expand_offset(ir_node *inc_sp) {
1058 int offset = be_get_IncSP_offset(inc_sp);
1060 if (offset == BE_STACK_FRAME_SIZE_EXPAND)
1067 static ir_node *gen_StackParam(ir_node *irn) {
1068 ir_node *block = be_transform_node(get_nodes_block(node));
1069 ir_node *new_op = NULL;
1070 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1071 ir_node *mem = new_rd_NoMem(env->irg);
1072 ir_node *ptr = get_irn_n(irn, 0);
1073 ir_entity *ent = be_get_frame_entity(irn);
1074 ir_mode *mode = env->mode;
1076 // /* If the StackParam has only one user -> */
1077 // /* put it in the Block where the user resides */
1078 // if (get_irn_n_edges(node) == 1) {
1079 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1082 if (mode_is_float(mode)) {
1083 if (USE_SSE2(env->cg))
1084 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1086 env->cg->used_x87 = 1;
1087 new_op = new_rd_ia32_vfld(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1091 new_op = new_rd_ia32_Load(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1094 set_ia32_frame_ent(new_op, ent);
1095 set_ia32_use_frame(new_op);
1097 set_ia32_am_support(new_op, ia32_am_Source);
1098 set_ia32_op_type(new_op, ia32_AddrModeS);
1099 set_ia32_am_flavour(new_op, ia32_B);
1100 set_ia32_ls_mode(new_op, mode);
1102 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1104 return new_rd_Proj(env->dbg, env->irg, block, new_op, mode, 0);
1109 * Transforms a FrameAddr into an ARM Add.
1111 static ir_node *gen_be_FrameAddr(ir_node *node) {
1112 ir_node *block = be_transform_node(get_nodes_block(node));
1113 ir_entity *ent = be_get_frame_entity(node);
1114 int offset = get_entity_offset(ent);
1115 ir_node *op = be_get_FrameAddr_frame(node);
1116 ir_node *new_op = be_transform_node(op);
1117 dbg_info *dbg = get_irn_dbg_info(node);
1118 ir_mode *mode = mode_Iu;
1121 if (be_is_IncSP(op)) {
1122 /* BEWARE: we get an offset which is absolute from an offset that
1123 is relative. Both must be merged */
1124 offset += get_sp_expand_offset(op);
1126 cnst = create_const_graph_value(dbg, block, (unsigned)offset);
1127 if (is_arm_Mov_i(cnst))
1128 return new_rd_arm_Add_i(dbg, current_ir_graph, block, new_op, mode, get_arm_imm_value(cnst));
1129 return new_rd_arm_Add(dbg, current_ir_graph, block, new_op, cnst, mode, ARM_SHF_NONE, 0);
1133 * Transform a be_AddSP into an arm_AddSP. Eat up const sizes.
1135 static ir_node *gen_be_AddSP(ir_node *node) {
1136 ir_node *block = be_transform_node(get_nodes_block(node));
1137 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
1138 ir_node *new_sz = be_transform_node(sz);
1139 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
1140 ir_node *new_sp = be_transform_node(sp);
1141 ir_graph *irg = current_ir_graph;
1142 dbg_info *dbgi = get_irn_dbg_info(node);
1143 ir_node *nomem = new_NoMem();
1146 /* ARM stack grows in reverse direction, make a SubSPandCopy */
1147 new_op = new_rd_arm_SubSPandCopy(dbgi, irg, block, new_sp, new_sz, nomem);
1153 * Transform a be_SubSP into an arm_SubSP. Eat up const sizes.
1155 static ir_node *gen_be_SubSP(ir_node *node) {
1156 ir_node *block = be_transform_node(get_nodes_block(node));
1157 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
1158 ir_node *new_sz = be_transform_node(sz);
1159 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
1160 ir_node *new_sp = be_transform_node(sp);
1161 ir_graph *irg = current_ir_graph;
1162 dbg_info *dbgi = get_irn_dbg_info(node);
1163 ir_node *nomem = new_NoMem();
1166 /* ARM stack grows in reverse direction, make an AddSP */
1167 new_op = new_rd_arm_AddSP(dbgi, irg, block, new_sp, new_sz, nomem);
1173 * Transform a be_Copy.
1175 static ir_node *gen_be_Copy(ir_node *node) {
1176 ir_node *result = be_duplicate_node(node);
1177 ir_mode *mode = get_irn_mode(result);
1179 if (mode_needs_gp_reg(mode)) {
1180 set_irn_mode(node, mode_Iu);
1187 * Transform a Proj from a Load.
1189 static ir_node *gen_Proj_Load(ir_node *node) {
1190 ir_node *block = be_transform_node(get_nodes_block(node));
1191 ir_node *load = get_Proj_pred(node);
1192 ir_node *new_load = be_transform_node(load);
1193 ir_graph *irg = current_ir_graph;
1194 dbg_info *dbgi = get_irn_dbg_info(node);
1195 long proj = get_Proj_proj(node);
1197 /* renumber the proj */
1198 switch (get_arm_irn_opcode(new_load)) {
1201 case iro_arm_Loadbs:
1203 case iro_arm_Loadhs:
1204 /* handle all gp loads equal: they have the same proj numbers. */
1205 if (proj == pn_Load_res) {
1206 return new_rd_Proj(dbgi, irg, block, new_load, mode_Iu, pn_arm_Load_res);
1207 } else if (proj == pn_Load_M) {
1208 return new_rd_Proj(dbgi, irg, block, new_load, mode_M, pn_arm_Load_M);
1211 case iro_arm_fpaLdf:
1212 if (proj == pn_Load_res) {
1213 ir_mode *mode = get_Load_mode(load);
1214 return new_rd_Proj(dbgi, irg, block, new_load, mode, pn_arm_fpaLdf_res);
1215 } else if (proj == pn_Load_M) {
1216 return new_rd_Proj(dbgi, irg, block, new_load, mode_M, pn_arm_fpaLdf_M);
1223 return new_rd_Unknown(irg, get_irn_mode(node));
1227 * Transform and renumber the Projs from a CopyB.
1229 static ir_node *gen_Proj_CopyB(ir_node *node) {
1230 ir_node *block = be_transform_node(get_nodes_block(node));
1231 ir_node *pred = get_Proj_pred(node);
1232 ir_node *new_pred = be_transform_node(pred);
1233 ir_graph *irg = current_ir_graph;
1234 dbg_info *dbgi = get_irn_dbg_info(node);
1235 ir_mode *mode = get_irn_mode(node);
1236 long proj = get_Proj_proj(node);
1239 case pn_CopyB_M_regular:
1240 if (is_arm_CopyB(new_pred)) {
1241 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_CopyB_M);
1248 return new_rd_Unknown(irg, mode);
1252 * Transform and renumber the Projs from a Quot.
1254 static ir_node *gen_Proj_Quot(ir_node *node) {
1255 ir_node *block = be_transform_node(get_nodes_block(node));
1256 ir_node *pred = get_Proj_pred(node);
1257 ir_node *new_pred = be_transform_node(pred);
1258 ir_graph *irg = current_ir_graph;
1259 dbg_info *dbgi = get_irn_dbg_info(node);
1260 ir_mode *mode = get_irn_mode(node);
1261 long proj = get_Proj_proj(node);
1265 if (is_arm_fpaDvf(new_pred) || is_arm_fpaDvf_i(new_pred)) {
1266 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaDvf_M);
1267 } else if (is_arm_fpaRdf(new_pred) || is_arm_fpaRdf_i(new_pred)) {
1268 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaRdf_M);
1269 } else if (is_arm_fpaFdv(new_pred) || is_arm_fpaFdv_i(new_pred)) {
1270 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaFdv_M);
1271 } else if (is_arm_fpaFrd(new_pred) || is_arm_fpaFrd_i(new_pred)) {
1272 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaFrd_M);
1276 if (is_arm_fpaDvf(new_pred) || is_arm_fpaDvf_i(new_pred)) {
1277 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaDvf_res);
1278 } else if (is_arm_fpaRdf(new_pred) || is_arm_fpaRdf_i(new_pred)) {
1279 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaRdf_res);
1280 } else if (is_arm_fpaFdv(new_pred) || is_arm_fpaFdv_i(new_pred)) {
1281 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaFdv_res);
1282 } else if (is_arm_fpaFrd(new_pred) || is_arm_fpaFrd_i(new_pred)) {
1283 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaFrd_res);
1290 return new_rd_Unknown(irg, mode);
1294 * Transform the Projs of a be_AddSP.
1296 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
1297 ir_node *block = be_transform_node(get_nodes_block(node));
1298 ir_node *pred = get_Proj_pred(node);
1299 ir_node *new_pred = be_transform_node(pred);
1300 ir_graph *irg = current_ir_graph;
1301 dbg_info *dbgi = get_irn_dbg_info(node);
1302 long proj = get_Proj_proj(node);
1304 if (proj == pn_be_AddSP_sp) {
1305 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
1306 pn_arm_SubSPandCopy_stack);
1307 arch_set_irn_register(env_cg->arch_env, res, &arm_gp_regs[REG_SP]);
1309 } else if(proj == pn_be_AddSP_res) {
1310 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
1311 pn_arm_SubSPandCopy_addr);
1312 } else if (proj == pn_be_AddSP_M) {
1313 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_SubSPandCopy_M);
1317 return new_rd_Unknown(irg, get_irn_mode(node));
1321 * Transform the Projs of a be_SubSP.
1323 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
1324 ir_node *block = be_transform_node(get_nodes_block(node));
1325 ir_node *pred = get_Proj_pred(node);
1326 ir_node *new_pred = be_transform_node(pred);
1327 ir_graph *irg = current_ir_graph;
1328 dbg_info *dbgi = get_irn_dbg_info(node);
1329 long proj = get_Proj_proj(node);
1331 if (proj == pn_be_SubSP_sp) {
1332 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
1333 pn_arm_AddSP_stack);
1334 arch_set_irn_register(env_cg->arch_env, res, &arm_gp_regs[REG_SP]);
1336 } else if (proj == pn_be_SubSP_M) {
1337 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_AddSP_M);
1341 return new_rd_Unknown(irg, get_irn_mode(node));
1345 * Transform the Projs from a Cmp.
1347 static ir_node *gen_Proj_Cmp(ir_node *node) {
1354 * Transform the Thread Local Storage Proj.
1356 static ir_node *gen_Proj_tls(ir_node *node) {
1357 ir_node *block = be_transform_node(get_nodes_block(node));
1358 ir_graph *irg = current_ir_graph;
1359 dbg_info *dbgi = NULL;
1361 return new_rd_arm_LdTls(dbgi, irg, block, mode_Iu);
1365 * Transform a Proj node.
1367 static ir_node *gen_Proj(ir_node *node) {
1368 ir_graph *irg = current_ir_graph;
1369 dbg_info *dbgi = get_irn_dbg_info(node);
1370 ir_node *pred = get_Proj_pred(node);
1371 long proj = get_Proj_proj(node);
1373 if (is_Store(pred)) {
1374 if (proj == pn_Store_M) {
1375 return be_transform_node(pred);
1378 return new_r_Bad(irg);
1380 } else if (is_Load(pred)) {
1381 return gen_Proj_Load(node);
1382 } else if (is_CopyB(pred)) {
1383 return gen_Proj_CopyB(node);
1384 } else if (is_Quot(pred)) {
1385 return gen_Proj_Quot(node);
1386 } else if (be_is_SubSP(pred)) {
1387 return gen_Proj_be_SubSP(node);
1388 } else if (be_is_AddSP(pred)) {
1389 return gen_Proj_be_AddSP(node);
1390 } else if (is_Cmp(pred)) {
1391 return gen_Proj_Cmp(node);
1392 } else if (get_irn_op(pred) == op_Start) {
1393 if (proj == pn_Start_X_initial_exec) {
1394 ir_node *block = get_nodes_block(pred);
1397 /* we exchange the ProjX with a jump */
1398 block = be_transform_node(block);
1399 jump = new_rd_Jmp(dbgi, irg, block);
1400 ir_fprintf(stderr, "created jump: %+F\n", jump);
1403 if (node == get_irg_anchor(irg, anchor_tls)) {
1404 return gen_Proj_tls(node);
1407 ir_node *new_pred = be_transform_node(pred);
1408 ir_mode *mode = get_irn_mode(node);
1409 if (mode_needs_gp_reg(mode)) {
1410 ir_node *block = be_transform_node(get_nodes_block(node));
1411 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
1412 get_Proj_proj(node));
1413 #ifdef DEBUG_libfirm
1414 new_proj->node_nr = node->node_nr;
1420 return be_duplicate_node(node);
1423 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_graph *irg, ir_node *block);
1425 static INLINE ir_node *create_const(ir_node **place,
1426 create_const_node_func func,
1427 const arch_register_t* reg)
1429 ir_node *block, *res;
1434 block = get_irg_start_block(env_cg->irg);
1435 res = func(NULL, env_cg->irg, block);
1436 arch_set_irn_register(env_cg->arch_env, res, reg);
1439 add_irn_dep(get_irg_end(env_cg->irg), res);
1443 static ir_node *arm_new_Unknown_gp(void) {
1444 return create_const(&env_cg->unknown_gp, new_rd_arm_Unknown_GP,
1445 &arm_gp_regs[REG_GP_UKNWN]);
1448 static ir_node *arm_new_Unknown_fpa(void) {
1449 return create_const(&env_cg->unknown_fpa, new_rd_arm_Unknown_FPA,
1450 &arm_fpa_regs[REG_FPA_UKNWN]);
1454 * This function just sets the register for the Unknown node
1455 * as this is not done during register allocation because Unknown
1456 * is an "ignore" node.
1458 static ir_node *gen_Unknown(ir_node *node) {
1459 ir_mode *mode = get_irn_mode(node);
1460 if (mode_is_float(mode)) {
1461 if (USE_FPA(env_cg->isa))
1462 return arm_new_Unknown_fpa();
1463 else if (USE_VFP(env_cg->isa))
1464 panic("VFP not supported yet");
1466 panic("Softfloat not supported yet");
1467 } else if (mode_needs_gp_reg(mode)) {
1468 return arm_new_Unknown_gp();
1470 assert(0 && "unsupported Unknown-Mode");
1477 * Change some phi modes
1479 static ir_node *gen_Phi(ir_node *node) {
1480 ir_node *block = be_transform_node(get_nodes_block(node));
1481 ir_graph *irg = current_ir_graph;
1482 dbg_info *dbgi = get_irn_dbg_info(node);
1483 ir_mode *mode = get_irn_mode(node);
1486 if (mode_needs_gp_reg(mode)) {
1487 /* we shouldn't have any 64bit stuff around anymore */
1488 assert(get_mode_size_bits(mode) <= 32);
1489 /* all integer operations are on 32bit registers now */
1493 /* phi nodes allow loops, so we use the old arguments for now
1494 * and fix this later */
1495 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
1496 copy_node_attr(node, phi);
1497 be_duplicate_deps(node, phi);
1499 be_set_transformed_node(node, phi);
1500 be_enqueue_preds(node);
1505 /*********************************************************
1508 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1509 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1510 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1511 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1513 *********************************************************/
1516 * the BAD transformer.
1518 static ir_node *bad_transform(ir_node *irn) {
1519 panic("ARM backend: Not implemented: %+F\n", irn);
1524 * Set a node emitter. Make it a bit more type safe.
1526 static INLINE void set_transformer(ir_op *op, be_transform_func arm_transform_func) {
1527 op->ops.generic = (op_func)arm_transform_func;
1531 * Enters all transform functions into the generic pointer
1533 static void arm_register_transformers(void) {
1534 ir_op *op_Max, *op_Min, *op_Mulh;
1536 /* first clear the generic function pointer for all ops */
1537 clear_irp_opcodes_generic_func();
1539 #define GEN(a) set_transformer(op_##a, gen_##a)
1540 #define BAD(a) set_transformer(op_##a, bad_transform)
1552 BAD(Rot); /* unsupported yet */
1556 /* should be lowered */
1570 BAD(ASM); /* unsupported yet */
1573 BAD(Psi); /* unsupported yet */
1580 /* we should never see these nodes */
1595 /* handle generic backend nodes */
1603 /* set the register for all Unknown nodes */
1606 op_Max = get_op_Max();
1608 BAD(Max); /* unsupported yet */
1609 op_Min = get_op_Min();
1611 BAD(Min); /* unsupported yet */
1612 op_Mulh = get_op_Mulh();
1614 BAD(Mulh); /* unsupported yet */
1621 * Pre-transform all unknown nodes.
1623 static void arm_pretransform_node(void *arch_cg) {
1624 arm_code_gen_t *cg = arch_cg;
1626 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
1627 cg->unknown_fpa = be_pre_transform_node(cg->unknown_fpa);
1631 * Initialize fpa Immediate support.
1633 static void arm_init_fpa_immediate(void) {
1634 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
1635 fpa_imm[0][fpa_null] = get_tarval_null(mode_F);
1636 fpa_imm[0][fpa_one] = get_tarval_one(mode_F);
1637 fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
1638 fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
1639 fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
1640 fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
1641 fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
1642 fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
1644 fpa_imm[1][fpa_null] = get_tarval_null(mode_D);
1645 fpa_imm[1][fpa_one] = get_tarval_one(mode_D);
1646 fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
1647 fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
1648 fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
1649 fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
1650 fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
1651 fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
1653 fpa_imm[2][fpa_null] = get_tarval_null(mode_E);
1654 fpa_imm[2][fpa_one] = get_tarval_one(mode_E);
1655 fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
1656 fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
1657 fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
1658 fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
1659 fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
1660 fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
1664 * Transform a Firm graph into an ARM graph.
1666 void arm_transform_graph(arm_code_gen_t *cg) {
1667 static int imm_initialized = 0;
1669 if (! imm_initialized) {
1670 arm_init_fpa_immediate();
1671 imm_initialized = 1;
1673 arm_register_transformers();
1675 be_transform_graph(cg->birg, arm_pretransform_node, cg);
1678 void arm_init_transform(void) {
1679 // FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");