2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
41 #include "../benode.h"
43 #include "../beutil.h"
44 #include "../betranshlp.h"
45 #include "../beabihelper.h"
48 #include "bearch_arm_t.h"
49 #include "arm_nodes_attr.h"
50 #include "arm_transform.h"
51 #include "arm_optimize.h"
52 #include "arm_new_nodes.h"
53 #include "arm_map_regs.h"
54 #include "arm_cconv.h"
56 #include "gen_arm_regalloc_if.h"
60 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 /** hold the current code generator during transformation */
63 static arm_code_gen_t *env_cg;
65 static const arch_register_t *sp_reg = &arm_gp_regs[REG_SP];
66 static ir_mode *mode_gp;
67 static ir_mode *mode_fp;
68 static beabi_helper_env_t *abihelper;
69 static calling_convention_t *cconv = NULL;
71 static pmap *node_to_stack;
73 static bool mode_needs_gp_reg(ir_mode *mode)
75 return mode_is_int(mode) || mode_is_reference(mode);
79 * create firm graph for a constant
81 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
88 /* We only have 8 bit immediates. So we possibly have to combine several
89 * operations to construct the desired value.
91 * we can either create the value by adding bits to 0 or by removing bits
92 * from an register with all bits set. Try which alternative needs fewer
94 arm_gen_vals_from_word(value, &v);
95 arm_gen_vals_from_word(~value, &vn);
99 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
100 be_dep_on_frame(result);
102 for (cnt = 1; cnt < vn.ops; ++cnt) {
103 result = new_bd_arm_Bic_imm(dbgi, block, result,
104 vn.values[cnt], vn.rors[cnt]);
108 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
109 be_dep_on_frame(result);
111 for (cnt = 1; cnt < v.ops; ++cnt) {
112 result = new_bd_arm_Or_imm(dbgi, block, result,
113 v.values[cnt], v.rors[cnt]);
120 * Create a DAG constructing a given Const.
122 * @param irn a Firm const
124 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
126 tarval *tv = get_Const_tarval(irn);
127 ir_mode *mode = get_tarval_mode(tv);
130 if (mode_is_reference(mode)) {
131 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
132 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
133 tv = tarval_convert_to(tv, mode_Iu);
135 value = get_tarval_long(tv);
136 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
140 * Create an And that will zero out upper bits.
142 * @param dbgi debug info
143 * @param block the basic block
144 * @param op the original node
145 * param src_bits number of lower bits that will remain
147 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
151 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
152 } else if (src_bits == 16) {
153 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
154 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
157 panic("zero extension only supported for 8 and 16 bits");
162 * Generate code for a sign extension.
164 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
167 int shift_width = 32 - src_bits;
168 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
169 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
173 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
176 int bits = get_mode_size_bits(orig_mode);
180 if (mode_is_signed(orig_mode)) {
181 return gen_sign_extension(dbgi, block, op, bits);
183 return gen_zero_extension(dbgi, block, op, bits);
188 * returns true if it is assured, that the upper bits of a node are "clean"
189 * which means for a 16 or 8 bit value, that the upper bits in the register
190 * are 0 for unsigned and a copy of the last significant bit for signed
193 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
195 (void) transformed_node;
202 * Transforms a Conv node.
204 * @return The created ia32 Conv node
206 static ir_node *gen_Conv(ir_node *node)
208 ir_node *block = be_transform_node(get_nodes_block(node));
209 ir_node *op = get_Conv_op(node);
210 ir_node *new_op = be_transform_node(op);
211 ir_mode *src_mode = get_irn_mode(op);
212 ir_mode *dst_mode = get_irn_mode(node);
213 dbg_info *dbg = get_irn_dbg_info(node);
215 if (src_mode == dst_mode)
218 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
219 if (USE_FPA(env_cg->isa)) {
220 if (mode_is_float(src_mode)) {
221 if (mode_is_float(dst_mode)) {
222 /* from float to float */
223 return new_bd_arm_Mvf(dbg, block, new_op, dst_mode);
225 /* from float to int */
229 /* from int to float */
230 if (!mode_is_signed(src_mode)) {
233 return new_bd_arm_FltX(dbg, block, new_op, dst_mode);
236 } else if (USE_VFP(env_cg->isa)) {
237 panic("VFP not supported yet");
239 panic("Softfloat not supported yet");
241 } else { /* complete in gp registers */
242 int src_bits = get_mode_size_bits(src_mode);
243 int dst_bits = get_mode_size_bits(dst_mode);
247 if (src_bits == dst_bits) {
248 /* kill unnecessary conv */
252 if (src_bits < dst_bits) {
260 if (upper_bits_clean(new_op, min_mode)) {
264 if (mode_is_signed(min_mode)) {
265 return gen_sign_extension(dbg, block, new_op, min_bits);
267 return gen_zero_extension(dbg, block, new_op, min_bits);
277 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
279 unsigned val, low_pos, high_pos;
284 val = get_tarval_long(get_Const_tarval(node));
296 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
298 So we determine the smallest even position with a bit set
299 and the highest even position with no bit set anymore.
300 If the difference between these 2 is <= 8, then we can encode the value
303 low_pos = ntz(val) & ~1u;
304 high_pos = (32-nlz(val)+1) & ~1u;
306 if (high_pos - low_pos <= 8) {
307 res->imm_8 = val >> low_pos;
308 res->rot = 32 - low_pos;
313 res->rot = 34 - high_pos;
314 val = val >> (32-res->rot) | val << (res->rot);
324 static bool is_downconv(const ir_node *node)
332 /* we only want to skip the conv when we're the only user
333 * (not optimal but for now...)
335 if (get_irn_n_edges(node) > 1)
338 src_mode = get_irn_mode(get_Conv_op(node));
339 dest_mode = get_irn_mode(node);
341 mode_needs_gp_reg(src_mode) &&
342 mode_needs_gp_reg(dest_mode) &&
343 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
346 static ir_node *arm_skip_downconv(ir_node *node)
348 while (is_downconv(node))
349 node = get_Conv_op(node);
355 MATCH_COMMUTATIVE = 1 << 0, /**< commutative node */
356 MATCH_SIZE_NEUTRAL = 1 << 1,
357 MATCH_SKIP_NOT = 1 << 2, /**< skip Not on ONE input */
361 * possible binop constructors.
363 typedef struct arm_binop_factory_t {
364 /** normal reg op reg operation. */
365 ir_node *(*new_binop_reg)(dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
366 /** normal reg op imm operation. */
367 ir_node *(*new_binop_imm)(dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
368 /** barrel shifter reg op (reg shift reg operation. */
369 ir_node *(*new_binop_reg_shift_reg)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *shift, arm_shift_modifier_t shift_modifier);
370 /** barrel shifter reg op (reg shift imm operation. */
371 ir_node *(*new_binop_reg_shift_imm)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, arm_shift_modifier_t shift_modifier, unsigned shift_immediate);
372 } arm_binop_factory_t;
374 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
375 const arm_binop_factory_t *factory)
377 ir_node *block = be_transform_node(get_nodes_block(node));
378 ir_node *op1 = get_binop_left(node);
380 ir_node *op2 = get_binop_right(node);
382 dbg_info *dbgi = get_irn_dbg_info(node);
385 if (flags & MATCH_SKIP_NOT) {
387 op1 = get_Not_op(op1);
388 else if (is_Not(op2))
389 op2 = get_Not_op(op2);
391 panic("cannot execute MATCH_SKIP_NOT");
393 if (flags & MATCH_SIZE_NEUTRAL) {
394 op1 = arm_skip_downconv(op1);
395 op2 = arm_skip_downconv(op2);
397 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
400 if (try_encode_as_immediate(op2, &imm)) {
401 ir_node *new_op1 = be_transform_node(op1);
402 return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
404 new_op2 = be_transform_node(op2);
405 if ((flags & MATCH_COMMUTATIVE) && try_encode_as_immediate(op1, &imm)) {
406 return factory->new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
408 new_op1 = be_transform_node(op1);
410 /* check if we can fold in a Mov */
411 if (is_arm_Mov(new_op2)) {
412 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op2);
414 switch (attr->shift_modifier) {
416 case ARM_SHF_ASR_IMM:
417 case ARM_SHF_LSL_IMM:
418 case ARM_SHF_LSR_IMM:
419 case ARM_SHF_ROR_IMM:
420 if (factory->new_binop_reg_shift_imm) {
421 ir_node *mov_op = get_irn_n(new_op2, 0);
422 return factory->new_binop_reg_shift_imm(dbgi, block, new_op1, mov_op,
423 attr->shift_modifier, attr->shift_immediate);
427 case ARM_SHF_ASR_REG:
428 case ARM_SHF_LSL_REG:
429 case ARM_SHF_LSR_REG:
430 case ARM_SHF_ROR_REG:
431 if (factory->new_binop_reg_shift_reg) {
432 ir_node *mov_op = get_irn_n(new_op2, 0);
433 ir_node *mov_sft = get_irn_n(new_op2, 1);
434 return factory->new_binop_reg_shift_reg(dbgi, block, new_op1, mov_op, mov_sft,
435 attr->shift_modifier);
440 if ((flags & MATCH_COMMUTATIVE) && is_arm_Mov(new_op1)) {
441 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op1);
443 switch (attr->shift_modifier) {
444 ir_node *mov_op, *mov_sft;
447 case ARM_SHF_ASR_IMM:
448 case ARM_SHF_LSL_IMM:
449 case ARM_SHF_LSR_IMM:
450 case ARM_SHF_ROR_IMM:
451 if (factory->new_binop_reg_shift_imm) {
452 mov_op = get_irn_n(new_op1, 0);
453 return factory->new_binop_reg_shift_imm(dbgi, block, new_op2, mov_op,
454 attr->shift_modifier, attr->shift_immediate);
458 case ARM_SHF_ASR_REG:
459 case ARM_SHF_LSL_REG:
460 case ARM_SHF_LSR_REG:
461 case ARM_SHF_ROR_REG:
462 if (factory->new_binop_reg_shift_reg) {
463 mov_op = get_irn_n(new_op1, 0);
464 mov_sft = get_irn_n(new_op1, 1);
465 return factory->new_binop_reg_shift_reg(dbgi, block, new_op2, mov_op, mov_sft,
466 attr->shift_modifier);
471 return factory->new_binop_reg(dbgi, block, new_op1, new_op2);
475 * Creates an ARM Add.
477 * @return the created arm Add node
479 static ir_node *gen_Add(ir_node *node)
481 static const arm_binop_factory_t add_factory = {
484 new_bd_arm_Add_reg_shift_reg,
485 new_bd_arm_Add_reg_shift_imm
488 ir_mode *mode = get_irn_mode(node);
490 if (mode_is_float(mode)) {
491 ir_node *block = be_transform_node(get_nodes_block(node));
492 ir_node *op1 = get_Add_left(node);
493 ir_node *op2 = get_Add_right(node);
494 dbg_info *dbgi = get_irn_dbg_info(node);
495 ir_node *new_op1 = be_transform_node(op1);
496 ir_node *new_op2 = be_transform_node(op2);
497 if (USE_FPA(env_cg->isa)) {
498 return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
499 } else if (USE_VFP(env_cg->isa)) {
500 assert(mode != mode_E && "IEEE Extended FP not supported");
501 panic("VFP not supported yet");
503 panic("Softfloat not supported yet");
508 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
510 new_op2 = get_irn_n(new_op1, 1);
511 new_op1 = get_irn_n(new_op1, 0);
513 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
515 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
517 new_op1 = get_irn_n(new_op2, 0);
518 new_op2 = get_irn_n(new_op2, 1);
520 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
524 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &add_factory);
529 * Creates an ARM Mul.
531 * @return the created arm Mul node
533 static ir_node *gen_Mul(ir_node *node)
535 ir_node *block = be_transform_node(get_nodes_block(node));
536 ir_node *op1 = get_Mul_left(node);
537 ir_node *new_op1 = be_transform_node(op1);
538 ir_node *op2 = get_Mul_right(node);
539 ir_node *new_op2 = be_transform_node(op2);
540 ir_mode *mode = get_irn_mode(node);
541 dbg_info *dbg = get_irn_dbg_info(node);
543 if (mode_is_float(mode)) {
544 if (USE_FPA(env_cg->isa)) {
545 return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
546 } else if (USE_VFP(env_cg->isa)) {
547 assert(mode != mode_E && "IEEE Extended FP not supported");
548 panic("VFP not supported yet");
550 panic("Softfloat not supported yet");
553 assert(mode_is_data(mode));
554 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
557 static ir_node *gen_Quot(ir_node *node)
559 ir_node *block = be_transform_node(get_nodes_block(node));
560 ir_node *op1 = get_Quot_left(node);
561 ir_node *new_op1 = be_transform_node(op1);
562 ir_node *op2 = get_Quot_right(node);
563 ir_node *new_op2 = be_transform_node(op2);
564 ir_mode *mode = get_irn_mode(node);
565 dbg_info *dbg = get_irn_dbg_info(node);
567 assert(mode != mode_E && "IEEE Extended FP not supported");
569 if (USE_FPA(env_cg->isa)) {
570 return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
571 } else if (USE_VFP(env_cg->isa)) {
572 assert(mode != mode_E && "IEEE Extended FP not supported");
573 panic("VFP not supported yet");
575 panic("Softfloat not supported yet");
579 static ir_node *gen_And(ir_node *node)
581 static const arm_binop_factory_t and_factory = {
584 new_bd_arm_And_reg_shift_reg,
585 new_bd_arm_And_reg_shift_imm
587 static const arm_binop_factory_t bic_factory = {
590 new_bd_arm_Bic_reg_shift_reg,
591 new_bd_arm_Bic_reg_shift_imm
594 /* check for and not */
595 ir_node *left = get_And_left(node);
596 ir_node *right = get_And_right(node);
598 if (is_Not(left) || is_Not(right)) {
599 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL | MATCH_SKIP_NOT,
603 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &and_factory);
606 static ir_node *gen_Or(ir_node *node)
608 static const arm_binop_factory_t or_factory = {
611 new_bd_arm_Or_reg_shift_reg,
612 new_bd_arm_Or_reg_shift_imm
615 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &or_factory);
618 static ir_node *gen_Eor(ir_node *node)
620 static const arm_binop_factory_t eor_factory = {
623 new_bd_arm_Eor_reg_shift_reg,
624 new_bd_arm_Eor_reg_shift_imm
627 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &eor_factory);
630 static ir_node *gen_Sub(ir_node *node)
632 static const arm_binop_factory_t sub_factory = {
635 new_bd_arm_Sub_reg_shift_reg,
636 new_bd_arm_Sub_reg_shift_imm
639 ir_node *block = be_transform_node(get_nodes_block(node));
640 ir_node *op1 = get_Sub_left(node);
641 ir_node *new_op1 = be_transform_node(op1);
642 ir_node *op2 = get_Sub_right(node);
643 ir_node *new_op2 = be_transform_node(op2);
644 ir_mode *mode = get_irn_mode(node);
645 dbg_info *dbgi = get_irn_dbg_info(node);
647 if (mode_is_float(mode)) {
648 if (USE_FPA(env_cg->isa)) {
649 return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
650 } else if (USE_VFP(env_cg->isa)) {
651 assert(mode != mode_E && "IEEE Extended FP not supported");
652 panic("VFP not supported yet");
654 panic("Softfloat not supported yet");
657 return gen_int_binop(node, MATCH_SIZE_NEUTRAL, &sub_factory);
662 * Checks if a given value can be used as an immediate for the given
665 static bool can_use_shift_constant(unsigned int val,
666 arm_shift_modifier_t modifier)
670 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
676 * generate an ARM shift instruction.
678 * @param node the node
679 * @param flags matching flags
680 * @param shift_modifier initial encoding of the desired shift operation
682 static ir_node *make_shift(ir_node *node, match_flags_t flags,
683 arm_shift_modifier_t shift_modifier)
685 ir_node *block = be_transform_node(get_nodes_block(node));
686 ir_node *op1 = get_binop_left(node);
687 ir_node *op2 = get_binop_right(node);
688 dbg_info *dbgi = get_irn_dbg_info(node);
692 if (flags & MATCH_SIZE_NEUTRAL) {
693 op1 = arm_skip_downconv(op1);
694 op2 = arm_skip_downconv(op2);
697 new_op1 = be_transform_node(op1);
699 tarval *tv = get_Const_tarval(op2);
700 unsigned int val = get_tarval_long(tv);
701 assert(tarval_is_long(tv));
702 if (can_use_shift_constant(val, shift_modifier)) {
703 switch (shift_modifier) {
704 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
705 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
706 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
707 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
708 default: panic("unexpected shift modifier");
710 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
711 shift_modifier, val);
715 new_op2 = be_transform_node(op2);
716 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
720 static ir_node *gen_Shl(ir_node *node)
722 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
725 static ir_node *gen_Shr(ir_node *node)
727 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
730 static ir_node *gen_Shrs(ir_node *node)
732 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
735 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
737 ir_node *block = be_transform_node(get_nodes_block(node));
738 ir_node *new_op1 = be_transform_node(op1);
739 dbg_info *dbgi = get_irn_dbg_info(node);
740 ir_node *new_op2 = be_transform_node(op2);
742 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
746 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
748 ir_node *block = be_transform_node(get_nodes_block(node));
749 ir_node *new_op1 = be_transform_node(op1);
750 dbg_info *dbgi = get_irn_dbg_info(node);
751 ir_node *new_op2 = be_transform_node(op2);
753 /* Note: there is no Rol on arm, we have to use Ror */
754 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
755 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
759 static ir_node *gen_Rotl(ir_node *node)
761 ir_node *rotate = NULL;
762 ir_node *op1 = get_Rotl_left(node);
763 ir_node *op2 = get_Rotl_right(node);
765 /* Firm has only RotL, so we are looking for a right (op2)
766 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
767 that means we can create a RotR. */
770 ir_node *right = get_Add_right(op2);
771 if (is_Const(right)) {
772 tarval *tv = get_Const_tarval(right);
773 ir_mode *mode = get_irn_mode(node);
774 long bits = get_mode_size_bits(mode);
775 ir_node *left = get_Add_left(op2);
777 if (is_Minus(left) &&
778 tarval_is_long(tv) &&
779 get_tarval_long(tv) == bits &&
781 rotate = gen_Ror(node, op1, get_Minus_op(left));
783 } else if (is_Sub(op2)) {
784 ir_node *left = get_Sub_left(op2);
785 if (is_Const(left)) {
786 tarval *tv = get_Const_tarval(left);
787 ir_mode *mode = get_irn_mode(node);
788 long bits = get_mode_size_bits(mode);
789 ir_node *right = get_Sub_right(op2);
791 if (tarval_is_long(tv) &&
792 get_tarval_long(tv) == bits &&
794 rotate = gen_Ror(node, op1, right);
796 } else if (is_Const(op2)) {
797 tarval *tv = get_Const_tarval(op2);
798 ir_mode *mode = get_irn_mode(node);
799 long bits = get_mode_size_bits(mode);
801 if (tarval_is_long(tv) && bits == 32) {
802 ir_node *block = be_transform_node(get_nodes_block(node));
803 ir_node *new_op1 = be_transform_node(op1);
804 dbg_info *dbgi = get_irn_dbg_info(node);
806 bits = (bits - get_tarval_long(tv)) & 31;
807 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
811 if (rotate == NULL) {
812 rotate = gen_Rol(node, op1, op2);
818 static ir_node *gen_Not(ir_node *node)
820 ir_node *block = be_transform_node(get_nodes_block(node));
821 ir_node *op = get_Not_op(node);
822 ir_node *new_op = be_transform_node(op);
823 dbg_info *dbgi = get_irn_dbg_info(node);
825 /* check if we can fold in a Mov */
826 if (is_arm_Mov(new_op)) {
827 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op);
829 switch (attr->shift_modifier) {
830 ir_node *mov_op, *mov_sft;
833 case ARM_SHF_ASR_IMM:
834 case ARM_SHF_LSL_IMM:
835 case ARM_SHF_LSR_IMM:
836 case ARM_SHF_ROR_IMM:
837 mov_op = get_irn_n(new_op, 0);
838 return new_bd_arm_Mvn_reg_shift_imm(dbgi, block, mov_op,
839 attr->shift_modifier, attr->shift_immediate);
841 case ARM_SHF_ASR_REG:
842 case ARM_SHF_LSL_REG:
843 case ARM_SHF_LSR_REG:
844 case ARM_SHF_ROR_REG:
845 mov_op = get_irn_n(new_op, 0);
846 mov_sft = get_irn_n(new_op, 1);
847 return new_bd_arm_Mvn_reg_shift_reg(dbgi, block, mov_op, mov_sft,
848 attr->shift_modifier);
852 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
855 static ir_node *gen_Minus(ir_node *node)
857 ir_node *block = be_transform_node(get_nodes_block(node));
858 ir_node *op = get_Minus_op(node);
859 ir_node *new_op = be_transform_node(op);
860 dbg_info *dbgi = get_irn_dbg_info(node);
861 ir_mode *mode = get_irn_mode(node);
863 if (mode_is_float(mode)) {
864 if (USE_FPA(env_cg->isa)) {
865 return new_bd_arm_Mvf(dbgi, block, op, mode);
866 } else if (USE_VFP(env_cg->isa)) {
867 assert(mode != mode_E && "IEEE Extended FP not supported");
868 panic("VFP not supported yet");
870 panic("Softfloat not supported yet");
873 assert(mode_is_data(mode));
874 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
877 static ir_node *gen_Load(ir_node *node)
879 ir_node *block = be_transform_node(get_nodes_block(node));
880 ir_node *ptr = get_Load_ptr(node);
881 ir_node *new_ptr = be_transform_node(ptr);
882 ir_node *mem = get_Load_mem(node);
883 ir_node *new_mem = be_transform_node(mem);
884 ir_mode *mode = get_Load_mode(node);
885 dbg_info *dbgi = get_irn_dbg_info(node);
886 ir_node *new_load = NULL;
888 if (mode_is_float(mode)) {
889 if (USE_FPA(env_cg->isa)) {
890 new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
892 } else if (USE_VFP(env_cg->isa)) {
893 assert(mode != mode_E && "IEEE Extended FP not supported");
894 panic("VFP not supported yet");
896 panic("Softfloat not supported yet");
899 assert(mode_is_data(mode) && "unsupported mode for Load");
901 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
903 set_irn_pinned(new_load, get_irn_pinned(node));
905 /* check for special case: the loaded value might not be used */
906 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
907 /* add a result proj and a Keep to produce a pseudo use */
908 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
909 be_new_Keep(block, 1, &proj);
915 static ir_node *gen_Store(ir_node *node)
917 ir_node *block = be_transform_node(get_nodes_block(node));
918 ir_node *ptr = get_Store_ptr(node);
919 ir_node *new_ptr = be_transform_node(ptr);
920 ir_node *mem = get_Store_mem(node);
921 ir_node *new_mem = be_transform_node(mem);
922 ir_node *val = get_Store_value(node);
923 ir_node *new_val = be_transform_node(val);
924 ir_mode *mode = get_irn_mode(val);
925 dbg_info *dbgi = get_irn_dbg_info(node);
926 ir_node *new_store = NULL;
928 if (mode_is_float(mode)) {
929 if (USE_FPA(env_cg->isa)) {
930 new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
931 new_mem, mode, NULL, 0, 0, false);
932 } else if (USE_VFP(env_cg->isa)) {
933 assert(mode != mode_E && "IEEE Extended FP not supported");
934 panic("VFP not supported yet");
936 panic("Softfloat not supported yet");
939 assert(mode_is_data(mode) && "unsupported mode for Store");
940 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
943 set_irn_pinned(new_store, get_irn_pinned(node));
947 static ir_node *gen_Jmp(ir_node *node)
949 ir_node *block = get_nodes_block(node);
950 ir_node *new_block = be_transform_node(block);
951 dbg_info *dbgi = get_irn_dbg_info(node);
953 return new_bd_arm_Jmp(dbgi, new_block);
956 static ir_node *gen_SwitchJmp(ir_node *node)
958 ir_node *block = be_transform_node(get_nodes_block(node));
959 ir_node *selector = get_Cond_selector(node);
960 dbg_info *dbgi = get_irn_dbg_info(node);
961 ir_node *new_op = be_transform_node(selector);
962 ir_node *const_graph;
966 const ir_edge_t *edge;
973 foreach_out_edge(node, edge) {
974 proj = get_edge_src_irn(edge);
975 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
977 pn = get_Proj_proj(proj);
979 min = pn<min ? pn : min;
980 max = pn>max ? pn : max;
983 n_projs = max - translation + 1;
985 foreach_out_edge(node, edge) {
986 proj = get_edge_src_irn(edge);
987 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
989 pn = get_Proj_proj(proj) - translation;
990 set_Proj_proj(proj, pn);
993 const_graph = create_const_graph_value(dbgi, block, translation);
994 sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
995 return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
998 static ir_node *gen_Cmp(ir_node *node)
1000 ir_node *block = be_transform_node(get_nodes_block(node));
1001 ir_node *op1 = get_Cmp_left(node);
1002 ir_node *op2 = get_Cmp_right(node);
1003 ir_mode *cmp_mode = get_irn_mode(op1);
1004 dbg_info *dbgi = get_irn_dbg_info(node);
1009 if (mode_is_float(cmp_mode)) {
1010 /* TODO: this is broken... */
1011 new_op1 = be_transform_node(op1);
1012 new_op2 = be_transform_node(op2);
1014 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
1016 panic("FloatCmp NIY");
1018 ir_node *new_op2 = be_transform_node(op2);
1019 /* floating point compare */
1020 pn_Cmp pnc = get_Proj_proj(selector);
1022 if (pnc & pn_Cmp_Uo) {
1023 /* check for unordered, need cmf */
1024 return new_bd_arm_CmfBra(dbgi, block, new_op1, new_op2, pnc);
1026 /* Hmm: use need cmfe */
1027 return new_bd_arm_CmfeBra(dbgi, block, new_op1, new_op2, pnc);
1031 assert(get_irn_mode(op2) == cmp_mode);
1032 is_unsigned = !mode_is_signed(cmp_mode);
1034 /* compare with 0 can be done with Tst */
1035 if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) {
1036 new_op1 = be_transform_node(op1);
1037 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
1038 return new_bd_arm_Tst_reg(dbgi, block, new_op1, new_op1, false,
1041 if (is_Const(op1) && tarval_is_null(get_Const_tarval(op1))) {
1042 new_op2 = be_transform_node(op2);
1043 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
1044 return new_bd_arm_Tst_reg(dbgi, block, new_op2, new_op2, true,
1048 /* integer compare, TODO: use shifter_op in all its combinations */
1049 new_op1 = be_transform_node(op1);
1050 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
1051 new_op2 = be_transform_node(op2);
1052 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
1053 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
1057 static ir_node *gen_Cond(ir_node *node)
1059 ir_node *selector = get_Cond_selector(node);
1060 ir_mode *mode = get_irn_mode(selector);
1065 if (mode != mode_b) {
1066 return gen_SwitchJmp(node);
1068 assert(is_Proj(selector));
1070 block = be_transform_node(get_nodes_block(node));
1071 dbgi = get_irn_dbg_info(node);
1072 flag_node = be_transform_node(get_Proj_pred(selector));
1074 return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector));
1077 static tarval *fpa_imm[3][fpa_max];
1081 * Check, if a floating point tarval is an fpa immediate, i.e.
1082 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
1084 static int is_fpa_immediate(tarval *tv)
1086 ir_mode *mode = get_tarval_mode(tv);
1089 switch (get_mode_size_bits(mode)) {
1100 if (tarval_is_negative(tv)) {
1101 tv = tarval_neg(tv);
1105 for (j = 0; j < fpa_max; ++j) {
1106 if (tv == fpa_imm[i][j])
1113 static ir_node *gen_Const(ir_node *node)
1115 ir_node *block = be_transform_node(get_nodes_block(node));
1116 ir_mode *mode = get_irn_mode(node);
1117 dbg_info *dbg = get_irn_dbg_info(node);
1119 if (mode_is_float(mode)) {
1120 if (USE_FPA(env_cg->isa)) {
1121 tarval *tv = get_Const_tarval(node);
1122 node = new_bd_arm_fConst(dbg, block, tv);
1123 be_dep_on_frame(node);
1125 } else if (USE_VFP(env_cg->isa)) {
1126 assert(mode != mode_E && "IEEE Extended FP not supported");
1127 panic("VFP not supported yet");
1129 panic("Softfloat not supported yet");
1132 return create_const_graph(node, block);
1135 static ir_node *gen_SymConst(ir_node *node)
1137 ir_node *block = be_transform_node(get_nodes_block(node));
1138 ir_entity *entity = get_SymConst_entity(node);
1139 dbg_info *dbgi = get_irn_dbg_info(node);
1142 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
1143 be_dep_on_frame(new_node);
1147 static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0,
1150 /* the good way to do this would be to use the stm (store multiple)
1151 * instructions, since our input is nearly always 2 consecutive 32bit
1153 ir_graph *irg = current_ir_graph;
1154 ir_node *stack = get_irg_frame(irg);
1155 ir_node *nomem = new_NoMem();
1156 ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp,
1158 ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp,
1160 ir_node *in[2] = { str0, str1 };
1161 ir_node *sync = new_r_Sync(block, 2, in);
1163 set_irn_pinned(str0, op_pin_state_floats);
1164 set_irn_pinned(str1, op_pin_state_floats);
1166 ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true);
1167 set_irn_pinned(ldf, op_pin_state_floats);
1169 return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1172 static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node)
1174 ir_graph *irg = current_ir_graph;
1175 ir_node *stack = get_irg_frame(irg);
1176 ir_node *nomem = new_NoMem();
1177 ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp,
1180 set_irn_pinned(str, op_pin_state_floats);
1182 ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true);
1183 set_irn_pinned(ldf, op_pin_state_floats);
1185 return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1188 static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node)
1190 ir_graph *irg = current_ir_graph;
1191 ir_node *stack = get_irg_frame(irg);
1192 ir_node *nomem = new_NoMem();
1193 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F,
1196 set_irn_pinned(stf, op_pin_state_floats);
1198 ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1199 set_irn_pinned(ldr, op_pin_state_floats);
1201 return new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1204 static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node,
1205 ir_node **out_value0, ir_node **out_value1)
1207 ir_graph *irg = current_ir_graph;
1208 ir_node *stack = get_irg_frame(irg);
1209 ir_node *nomem = new_NoMem();
1210 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D,
1212 ir_node *ldr0, *ldr1;
1213 set_irn_pinned(stf, op_pin_state_floats);
1215 ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1216 set_irn_pinned(ldr0, op_pin_state_floats);
1217 ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true);
1218 set_irn_pinned(ldr1, op_pin_state_floats);
1220 *out_value0 = new_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
1221 *out_value1 = new_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
1224 static ir_node *gen_CopyB(ir_node *node)
1226 ir_node *block = be_transform_node(get_nodes_block(node));
1227 ir_node *src = get_CopyB_src(node);
1228 ir_node *new_src = be_transform_node(src);
1229 ir_node *dst = get_CopyB_dst(node);
1230 ir_node *new_dst = be_transform_node(dst);
1231 ir_node *mem = get_CopyB_mem(node);
1232 ir_node *new_mem = be_transform_node(mem);
1233 dbg_info *dbg = get_irn_dbg_info(node);
1234 int size = get_type_size_bytes(get_CopyB_type(node));
1238 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
1239 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
1241 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1242 new_bd_arm_EmptyReg(dbg, block),
1243 new_bd_arm_EmptyReg(dbg, block),
1244 new_bd_arm_EmptyReg(dbg, block),
1248 static ir_node *gen_Proj_Load(ir_node *node)
1250 ir_node *load = get_Proj_pred(node);
1251 ir_node *new_load = be_transform_node(load);
1252 dbg_info *dbgi = get_irn_dbg_info(node);
1253 long proj = get_Proj_proj(node);
1255 /* renumber the proj */
1256 switch (get_arm_irn_opcode(new_load)) {
1258 /* handle all gp loads equal: they have the same proj numbers. */
1259 if (proj == pn_Load_res) {
1260 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1261 } else if (proj == pn_Load_M) {
1262 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1266 if (proj == pn_Load_res) {
1267 ir_mode *mode = get_Load_mode(load);
1268 return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res);
1269 } else if (proj == pn_Load_M) {
1270 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M);
1276 panic("Unsupported Proj from Load");
1279 static ir_node *gen_Proj_CopyB(ir_node *node)
1281 ir_node *pred = get_Proj_pred(node);
1282 ir_node *new_pred = be_transform_node(pred);
1283 dbg_info *dbgi = get_irn_dbg_info(node);
1284 long proj = get_Proj_proj(node);
1288 if (is_arm_CopyB(new_pred)) {
1289 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1295 panic("Unsupported Proj from CopyB");
1298 static ir_node *gen_Proj_Quot(ir_node *node)
1300 ir_node *pred = get_Proj_pred(node);
1301 ir_node *new_pred = be_transform_node(pred);
1302 dbg_info *dbgi = get_irn_dbg_info(node);
1303 ir_mode *mode = get_irn_mode(node);
1304 long proj = get_Proj_proj(node);
1308 if (is_arm_Dvf(new_pred)) {
1309 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
1313 if (is_arm_Dvf(new_pred)) {
1314 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
1320 panic("Unsupported Proj from Quot");
1324 * Transform the Projs from a Cmp.
1326 static ir_node *gen_Proj_Cmp(ir_node *node)
1329 /* we should only be here in case of a Mux node */
1333 static ir_node *gen_Proj_Start(ir_node *node)
1335 ir_node *block = get_nodes_block(node);
1336 ir_node *new_block = be_transform_node(block);
1337 ir_node *barrier = be_transform_node(get_Proj_pred(node));
1338 long proj = get_Proj_proj(node);
1340 switch ((pn_Start) proj) {
1341 case pn_Start_X_initial_exec:
1342 /* we exchange the ProjX with a jump */
1343 return new_bd_arm_Jmp(NULL, new_block);
1346 return new_r_Proj(barrier, mode_M, 0);
1348 case pn_Start_T_args:
1351 case pn_Start_P_frame_base:
1352 return be_prolog_get_reg_value(abihelper, sp_reg);
1354 case pn_Start_P_tls:
1360 panic("unexpected start proj: %ld\n", proj);
1363 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1365 long pn = get_Proj_proj(node);
1366 ir_node *block = get_nodes_block(node);
1367 ir_node *new_block = be_transform_node(block);
1368 ir_entity *entity = get_irg_entity(current_ir_graph);
1369 ir_type *method_type = get_entity_type(entity);
1370 ir_type *param_type = get_method_param_type(method_type, pn);
1371 const reg_or_stackslot_t *param;
1373 /* Proj->Proj->Start must be a method argument */
1374 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1376 param = &cconv->parameters[pn];
1378 if (param->reg0 != NULL) {
1379 /* argument transmitted in register */
1380 ir_mode *mode = get_type_mode(param_type);
1381 ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0);
1383 if (mode_is_float(mode)) {
1384 ir_node *value1 = NULL;
1386 if (param->reg1 != NULL) {
1387 value1 = be_prolog_get_reg_value(abihelper, param->reg1);
1388 } else if (param->entity != NULL) {
1389 ir_graph *irg = get_irn_irg(node);
1390 ir_node *fp = get_irg_frame(irg);
1391 ir_node *mem = be_prolog_get_memory(abihelper);
1392 ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem,
1393 mode_gp, param->entity,
1395 value1 = new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1398 /* convert integer value to float */
1399 if (value1 == NULL) {
1400 value = int_to_float(NULL, new_block, value);
1402 value = ints_to_double(NULL, new_block, value, value1);
1407 /* argument transmitted on stack */
1408 ir_graph *irg = get_irn_irg(node);
1409 ir_node *fp = get_irg_frame(irg);
1410 ir_node *mem = be_prolog_get_memory(abihelper);
1411 ir_mode *mode = get_type_mode(param->type);
1415 if (mode_is_float(mode)) {
1416 load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode,
1417 param->entity, 0, 0, true);
1418 value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res);
1420 load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1421 param->entity, 0, 0, true);
1422 value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1424 set_irn_pinned(load, op_pin_state_floats);
1431 * Finds number of output value of a mode_T node which is constrained to
1432 * a single specific register.
1434 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1436 int n_outs = arch_irn_get_n_outs(node);
1439 for (o = 0; o < n_outs; ++o) {
1440 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1441 if (req == reg->single_req)
1447 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1449 long pn = get_Proj_proj(node);
1450 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1451 ir_node *new_call = be_transform_node(call);
1452 ir_type *function_type = get_Call_type(call);
1453 calling_convention_t *cconv = arm_decide_calling_convention(function_type);
1454 const reg_or_stackslot_t *res = &cconv->results[pn];
1458 /* TODO 64bit modes */
1459 assert(res->reg0 != NULL && res->reg1 == NULL);
1460 regn = find_out_for_reg(new_call, res->reg0);
1462 panic("Internal error in calling convention for return %+F", node);
1464 mode = res->reg0->reg_class->mode;
1466 arm_free_calling_convention(cconv);
1468 return new_r_Proj(new_call, mode, regn);
1471 static ir_node *gen_Proj_Call(ir_node *node)
1473 long pn = get_Proj_proj(node);
1474 ir_node *call = get_Proj_pred(node);
1475 ir_node *new_call = be_transform_node(call);
1477 switch ((pn_Call) pn) {
1479 return new_r_Proj(new_call, mode_M, 0);
1480 case pn_Call_X_regular:
1481 case pn_Call_X_except:
1482 case pn_Call_T_result:
1483 case pn_Call_P_value_res_base:
1487 panic("Unexpected Call proj %ld\n", pn);
1491 * Transform a Proj node.
1493 static ir_node *gen_Proj(ir_node *node)
1495 ir_node *pred = get_Proj_pred(node);
1496 long proj = get_Proj_proj(node);
1498 switch (get_irn_opcode(pred)) {
1500 if (proj == pn_Store_M) {
1501 return be_transform_node(pred);
1503 panic("Unsupported Proj from Store");
1506 return gen_Proj_Load(node);
1508 return gen_Proj_Call(node);
1510 return gen_Proj_CopyB(node);
1512 return gen_Proj_Quot(node);
1514 return gen_Proj_Cmp(node);
1516 return gen_Proj_Start(node);
1519 return be_duplicate_node(node);
1521 ir_node *pred_pred = get_Proj_pred(pred);
1522 if (is_Call(pred_pred)) {
1523 return gen_Proj_Proj_Call(node);
1524 } else if (is_Start(pred_pred)) {
1525 return gen_Proj_Proj_Start(node);
1530 panic("code selection didn't expect Proj after %+F\n", pred);
1534 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1536 static inline ir_node *create_const(ir_node **place,
1537 create_const_node_func func,
1538 const arch_register_t* reg)
1540 ir_node *block, *res;
1545 block = get_irg_start_block(env_cg->irg);
1546 res = func(NULL, block);
1547 arch_set_irn_register(res, reg);
1552 static ir_node *gen_Unknown(ir_node *node)
1554 ir_node *block = get_nodes_block(node);
1555 ir_node *new_block = be_transform_node(block);
1556 dbg_info *dbgi = get_irn_dbg_info(node);
1558 /* just produce a 0 */
1559 ir_mode *mode = get_irn_mode(node);
1560 if (mode_is_float(mode)) {
1561 tarval *tv = get_mode_null(mode);
1562 ir_node *node = new_bd_arm_fConst(dbgi, new_block, tv);
1563 be_dep_on_frame(node);
1565 } else if (mode_needs_gp_reg(mode)) {
1566 return create_const_graph_value(dbgi, new_block, 0);
1569 panic("Unexpected Unknown mode");
1573 * Produces the type which sits between the stack args and the locals on the
1574 * stack. It will contain the return address and space to store the old base
1576 * @return The Firm type modeling the ABI between type.
1578 static ir_type *arm_get_between_type(void)
1580 static ir_type *between_type = NULL;
1582 if (between_type == NULL) {
1583 between_type = new_type_class(new_id_from_str("arm_between_type"));
1584 set_type_size_bytes(between_type, 0);
1587 return between_type;
1590 static void create_stacklayout(ir_graph *irg)
1592 ir_entity *entity = get_irg_entity(irg);
1593 ir_type *function_type = get_entity_type(entity);
1594 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1599 /* calling conventions must be decided by now */
1600 assert(cconv != NULL);
1602 /* construct argument type */
1603 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1604 n_params = get_method_n_params(function_type);
1605 for (p = 0; p < n_params; ++p) {
1606 reg_or_stackslot_t *param = &cconv->parameters[p];
1610 if (param->type == NULL)
1613 snprintf(buf, sizeof(buf), "param_%d", p);
1614 id = new_id_from_str(buf);
1615 param->entity = new_entity(arg_type, id, param->type);
1616 set_entity_offset(param->entity, param->offset);
1619 /* TODO: what about external functions? we don't know most of the stack
1620 * layout for them. And probably don't need all of this... */
1621 memset(layout, 0, sizeof(*layout));
1623 layout->frame_type = get_irg_frame_type(irg);
1624 layout->between_type = arm_get_between_type();
1625 layout->arg_type = arg_type;
1626 layout->param_map = NULL; /* TODO */
1627 layout->initial_offset = 0;
1628 layout->initial_bias = 0;
1629 layout->stack_dir = -1;
1630 layout->sp_relative = true;
1632 assert(N_FRAME_TYPES == 3);
1633 layout->order[0] = layout->frame_type;
1634 layout->order[1] = layout->between_type;
1635 layout->order[2] = layout->arg_type;
1639 * transform the start node to the prolog code + initial barrier
1641 static ir_node *gen_Start(ir_node *node)
1643 ir_graph *irg = get_irn_irg(node);
1644 ir_entity *entity = get_irg_entity(irg);
1645 ir_type *function_type = get_entity_type(entity);
1646 ir_node *block = get_nodes_block(node);
1647 ir_node *new_block = be_transform_node(block);
1648 dbg_info *dbgi = get_irn_dbg_info(node);
1655 /* stackpointer is important at function prolog */
1656 be_prolog_add_reg(abihelper, sp_reg,
1657 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1658 /* function parameters in registers */
1659 for (i = 0; i < get_method_n_params(function_type); ++i) {
1660 const reg_or_stackslot_t *param = &cconv->parameters[i];
1661 if (param->reg0 != NULL)
1662 be_prolog_add_reg(abihelper, param->reg0, 0);
1663 if (param->reg1 != NULL)
1664 be_prolog_add_reg(abihelper, param->reg1, 0);
1666 /* announce that we need the values of the callee save regs */
1667 for (i = 0; i < (int) (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
1668 be_prolog_add_reg(abihelper, callee_saves[i], 0);
1671 start = be_prolog_create_start(abihelper, dbgi, new_block);
1672 sp = be_prolog_get_reg_value(abihelper, sp_reg);
1673 incsp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
1674 be_prolog_set_reg_value(abihelper, sp_reg, incsp);
1675 barrier = be_prolog_create_barrier(abihelper, new_block);
1680 static ir_node *get_stack_pointer_for(ir_node *node)
1682 /* get predecessor in stack_order list */
1683 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1684 ir_node *stack_pred_transformed;
1687 if (stack_pred == NULL) {
1688 /* first stack user in the current block. We can simply use the
1689 * initial sp_proj for it */
1690 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1694 stack_pred_transformed = be_transform_node(stack_pred);
1695 stack = pmap_get(node_to_stack, stack_pred);
1696 if (stack == NULL) {
1697 return get_stack_pointer_for(stack_pred);
1704 * transform a Return node into epilogue code + return statement
1706 static ir_node *gen_Return(ir_node *node)
1708 ir_node *block = get_nodes_block(node);
1709 ir_node *new_block = be_transform_node(block);
1710 dbg_info *dbgi = get_irn_dbg_info(node);
1711 ir_node *mem = get_Return_mem(node);
1712 ir_node *new_mem = be_transform_node(mem);
1713 int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
1714 ir_node *sp_proj = get_stack_pointer_for(node);
1715 int n_res = get_Return_n_ress(node);
1720 be_epilog_begin(abihelper);
1721 be_epilog_set_memory(abihelper, new_mem);
1722 /* connect stack pointer with initial stack pointer. fix_stack phase
1723 will later serialize all stack pointer adjusting nodes */
1724 be_epilog_add_reg(abihelper, sp_reg,
1725 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1729 for (i = 0; i < n_res; ++i) {
1730 ir_node *res_value = get_Return_res(node, i);
1731 ir_node *new_res_value = be_transform_node(res_value);
1732 const reg_or_stackslot_t *slot = &cconv->results[i];
1733 const arch_register_t *reg = slot->reg0;
1734 assert(slot->reg1 == NULL);
1735 be_epilog_add_reg(abihelper, reg, 0, new_res_value);
1738 /* connect callee saves with their values at the function begin */
1739 for (i = 0; i < n_callee_saves; ++i) {
1740 const arch_register_t *reg = callee_saves[i];
1741 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1742 be_epilog_add_reg(abihelper, reg, 0, value);
1745 /* create the barrier before the epilog code */
1746 be_epilog_create_barrier(abihelper, new_block);
1748 /* epilog code: an incsp */
1749 sp_proj = be_epilog_get_reg_value(abihelper, sp_reg);
1750 incsp = be_new_IncSP(sp_reg, new_block, sp_proj,
1751 BE_STACK_FRAME_SIZE_SHRINK, 0);
1752 be_epilog_set_reg_value(abihelper, sp_reg, incsp);
1754 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1760 static ir_node *gen_Call(ir_node *node)
1762 ir_graph *irg = get_irn_irg(node);
1763 ir_node *callee = get_Call_ptr(node);
1764 ir_node *block = get_nodes_block(node);
1765 ir_node *new_block = be_transform_node(block);
1766 ir_node *mem = get_Call_mem(node);
1767 ir_node *new_mem = be_transform_node(mem);
1768 dbg_info *dbgi = get_irn_dbg_info(node);
1769 ir_type *type = get_Call_type(node);
1770 calling_convention_t *cconv = arm_decide_calling_convention(type);
1771 int n_params = get_Call_n_params(node);
1772 int n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
1773 /* max inputs: memory, callee, register arguments */
1774 int max_inputs = 2 + n_param_regs;
1775 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1776 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1777 struct obstack *obst = be_get_be_obst(irg);
1778 const arch_register_req_t **in_req
1779 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1783 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1784 ir_entity *entity = NULL;
1785 ir_node *incsp = NULL;
1792 assert(n_params == get_method_n_params(type));
1794 /* construct arguments */
1797 in_req[in_arity] = arch_no_register_req;
1801 for (p = 0; p < n_params; ++p) {
1802 ir_node *value = get_Call_param(node, p);
1803 ir_node *new_value = be_transform_node(value);
1804 ir_node *new_value1 = NULL;
1805 const reg_or_stackslot_t *param = &cconv->parameters[p];
1806 ir_type *param_type = get_method_param_type(type, p);
1807 ir_mode *mode = get_type_mode(param_type);
1810 if (mode_is_float(mode) && param->reg0 != NULL) {
1811 unsigned size_bits = get_mode_size_bits(mode);
1812 if (size_bits == 64) {
1813 double_to_ints(dbgi, new_block, new_value, &new_value,
1816 assert(size_bits == 32);
1817 new_value = float_to_int(dbgi, new_block, new_value);
1821 /* put value into registers */
1822 if (param->reg0 != NULL) {
1823 in[in_arity] = new_value;
1824 in_req[in_arity] = param->reg0->single_req;
1826 if (new_value1 == NULL)
1829 if (param->reg1 != NULL) {
1830 assert(new_value1 != NULL);
1831 in[in_arity] = new_value1;
1832 in_req[in_arity] = param->reg1->single_req;
1837 /* we need a store if we're here */
1838 if (new_value1 != NULL) {
1839 new_value = new_value1;
1843 /* create a parameter frame if necessary */
1844 if (incsp == NULL) {
1845 ir_node *new_frame = get_stack_pointer_for(node);
1846 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1847 cconv->param_stack_size, 1);
1849 if (mode_is_float(mode)) {
1850 str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem,
1851 mode, NULL, 0, param->offset, true);
1853 str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem,
1854 mode, NULL, 0, param->offset, true);
1856 sync_ins[sync_arity++] = str;
1858 assert(in_arity <= max_inputs);
1860 /* construct memory input */
1861 if (sync_arity == 0) {
1862 in[mem_pos] = new_mem;
1863 } else if (sync_arity == 1) {
1864 in[mem_pos] = sync_ins[0];
1866 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1869 /* TODO: use a generic symconst matcher here */
1870 if (is_SymConst(callee)) {
1871 entity = get_SymConst_entity(callee);
1873 /* TODO: finish load matcher here */
1876 if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) {
1877 ir_node *load = get_Proj_pred(callee);
1878 ir_node *ptr = get_Load_ptr(load);
1879 ir_node *new_ptr = be_transform_node(ptr);
1880 ir_node *mem = get_Load_mem(load);
1881 ir_node *new_mem = be_transform_node(mem);
1882 ir_mode *mode = get_Load_mode(node);
1886 in[in_arity] = be_transform_node(callee);
1887 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1896 out_arity = 1 + n_caller_saves;
1898 if (entity != NULL) {
1899 /* TODO: use a generic symconst matcher here
1900 * so we can also handle entity+offset, etc. */
1901 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1904 * - use a proper shifter_operand matcher
1905 * - we could also use LinkLdrPC
1907 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1911 if (incsp != NULL) {
1912 /* IncSP to destroy the call stackframe */
1913 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
1915 /* if we are the last IncSP producer in a block then we have to keep
1917 * Note: This here keeps all producers which is more than necessary */
1918 add_irn_dep(incsp, res);
1921 pmap_insert(node_to_stack, node, incsp);
1924 set_arm_in_req_all(res, in_req);
1926 /* create output register reqs */
1927 arch_set_out_register_req(res, 0, arch_no_register_req);
1928 for (o = 0; o < n_caller_saves; ++o) {
1929 const arch_register_t *reg = caller_saves[o];
1930 arch_set_out_register_req(res, o+1, reg->single_req);
1933 /* copy pinned attribute */
1934 set_irn_pinned(res, get_irn_pinned(node));
1936 arm_free_calling_convention(cconv);
1940 static ir_node *gen_Sel(ir_node *node)
1942 dbg_info *dbgi = get_irn_dbg_info(node);
1943 ir_node *block = get_nodes_block(node);
1944 ir_node *new_block = be_transform_node(block);
1945 ir_node *ptr = get_Sel_ptr(node);
1946 ir_node *new_ptr = be_transform_node(ptr);
1947 ir_entity *entity = get_Sel_entity(node);
1949 /* must be the frame pointer all other sels must have been lowered
1951 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1952 /* we should not have value types from parameters anymore - they should be
1954 assert(get_entity_owner(entity) !=
1955 get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
1957 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1961 * Change some phi modes
1963 static ir_node *gen_Phi(ir_node *node)
1965 const arch_register_req_t *req;
1966 ir_node *block = be_transform_node(get_nodes_block(node));
1967 ir_graph *irg = current_ir_graph;
1968 dbg_info *dbgi = get_irn_dbg_info(node);
1969 ir_mode *mode = get_irn_mode(node);
1972 if (mode_needs_gp_reg(mode)) {
1973 /* we shouldn't have any 64bit stuff around anymore */
1974 assert(get_mode_size_bits(mode) <= 32);
1975 /* all integer operations are on 32bit registers now */
1977 req = arm_reg_classes[CLASS_arm_gp].class_req;
1979 req = arch_no_register_req;
1982 /* phi nodes allow loops, so we use the old arguments for now
1983 * and fix this later */
1984 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
1985 get_irn_in(node) + 1);
1986 copy_node_attr(irg, node, phi);
1987 be_duplicate_deps(node, phi);
1989 arch_set_out_register_req(phi, 0, req);
1991 be_enqueue_preds(node);
1998 * Enters all transform functions into the generic pointer
2000 static void arm_register_transformers(void)
2002 be_start_transform_setup();
2004 be_set_transform_function(op_Add, gen_Add);
2005 be_set_transform_function(op_And, gen_And);
2006 be_set_transform_function(op_Call, gen_Call);
2007 be_set_transform_function(op_Cmp, gen_Cmp);
2008 be_set_transform_function(op_Cond, gen_Cond);
2009 be_set_transform_function(op_Const, gen_Const);
2010 be_set_transform_function(op_Conv, gen_Conv);
2011 be_set_transform_function(op_CopyB, gen_CopyB);
2012 be_set_transform_function(op_Eor, gen_Eor);
2013 be_set_transform_function(op_Jmp, gen_Jmp);
2014 be_set_transform_function(op_Load, gen_Load);
2015 be_set_transform_function(op_Minus, gen_Minus);
2016 be_set_transform_function(op_Mul, gen_Mul);
2017 be_set_transform_function(op_Not, gen_Not);
2018 be_set_transform_function(op_Or, gen_Or);
2019 be_set_transform_function(op_Phi, gen_Phi);
2020 be_set_transform_function(op_Proj, gen_Proj);
2021 be_set_transform_function(op_Quot, gen_Quot);
2022 be_set_transform_function(op_Return, gen_Return);
2023 be_set_transform_function(op_Rotl, gen_Rotl);
2024 be_set_transform_function(op_Sel, gen_Sel);
2025 be_set_transform_function(op_Shl, gen_Shl);
2026 be_set_transform_function(op_Shr, gen_Shr);
2027 be_set_transform_function(op_Shrs, gen_Shrs);
2028 be_set_transform_function(op_Start, gen_Start);
2029 be_set_transform_function(op_Store, gen_Store);
2030 be_set_transform_function(op_Sub, gen_Sub);
2031 be_set_transform_function(op_SymConst, gen_SymConst);
2032 be_set_transform_function(op_Unknown, gen_Unknown);
2036 * Initialize fpa Immediate support.
2038 static void arm_init_fpa_immediate(void)
2040 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
2041 fpa_imm[0][fpa_null] = get_mode_null(mode_F);
2042 fpa_imm[0][fpa_one] = get_mode_one(mode_F);
2043 fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
2044 fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
2045 fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
2046 fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
2047 fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
2048 fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
2050 fpa_imm[1][fpa_null] = get_mode_null(mode_D);
2051 fpa_imm[1][fpa_one] = get_mode_one(mode_D);
2052 fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
2053 fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
2054 fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
2055 fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
2056 fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
2057 fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
2059 fpa_imm[2][fpa_null] = get_mode_null(mode_E);
2060 fpa_imm[2][fpa_one] = get_mode_one(mode_E);
2061 fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
2062 fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
2063 fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
2064 fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
2065 fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
2066 fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
2070 * Transform a Firm graph into an ARM graph.
2072 void arm_transform_graph(arm_code_gen_t *cg)
2074 static int imm_initialized = 0;
2075 ir_graph *irg = cg->irg;
2076 ir_entity *entity = get_irg_entity(irg);
2077 ir_type *frame_type;
2082 if (! imm_initialized) {
2083 arm_init_fpa_immediate();
2084 imm_initialized = 1;
2086 arm_register_transformers();
2089 node_to_stack = pmap_create();
2091 assert(abihelper == NULL);
2092 abihelper = be_abihelper_prepare(irg);
2093 be_collect_stacknodes(abihelper);
2094 assert(cconv == NULL);
2095 cconv = arm_decide_calling_convention(get_entity_type(entity));
2096 create_stacklayout(irg);
2098 be_transform_graph(cg->irg, NULL);
2100 be_abihelper_finish(abihelper);
2103 arm_free_calling_convention(cconv);
2106 frame_type = get_irg_frame_type(irg);
2107 if (get_type_state(frame_type) == layout_undefined) {
2108 default_layout_compound_type(frame_type);
2111 pmap_destroy(node_to_stack);
2112 node_to_stack = NULL;
2114 be_add_missing_keeps(irg);
2117 void arm_init_transform(void)
2119 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");