2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
31 #include "irgraph_t.h"
43 #include "../benode_t.h"
44 #include "../beirg_t.h"
45 #include "../beutil.h"
46 #include "../betranshlp.h"
47 #include "bearch_arm_t.h"
49 #include "arm_nodes_attr.h"
51 #include "arm_transform.h"
52 #include "arm_optimize.h"
53 #include "arm_new_nodes.h"
54 #include "arm_map_regs.h"
56 #include "gen_arm_regalloc_if.h"
61 /** hold the current code generator during transformation */
62 static arm_code_gen_t *env_cg;
64 extern ir_op *get_op_Mulh(void);
67 /****************************************************************************************************
69 * | | | | / _| | | (_)
70 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
71 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
72 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
73 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
75 ****************************************************************************************************/
77 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
78 return mode_is_int(mode) || mode_is_reference(mode);
82 * Creates a arm_Const node.
84 static ir_node *create_mov_node(dbg_info *dbg, ir_node *block, long value) {
85 ir_mode *mode = mode_Iu;
86 ir_graph *irg = current_ir_graph;
89 if (mode_needs_gp_reg(mode))
91 res = new_rd_arm_Mov_i(dbg, irg, block, mode, value);
97 * Creates a arm_Const_Neg node.
99 static ir_node *create_mvn_node(dbg_info *dbg, ir_node *block, long value) {
100 ir_mode *mode = mode_Iu;
101 ir_graph *irg = current_ir_graph;
104 if (mode_needs_gp_reg(mode))
106 res = new_rd_arm_Mvn_i(dbg, irg, block, mode, value);
107 be_dep_on_frame(res);
111 #define NEW_BINOP_NODE(opname, env, op1, op2) new_rd_arm_##opname(env->dbg, current_ir_graph, env->block, op1, op2, env->mode)
114 * Creates a possible DAG for an constant.
116 static ir_node *create_const_graph_value(dbg_info *dbg, ir_node *block, unsigned int value) {
120 ir_mode *mode = mode_Iu;
122 arm_gen_vals_from_word(value, &v);
123 arm_gen_vals_from_word(~value, &vn);
125 if (vn.ops < v.ops) {
127 result = create_mvn_node(dbg, block, arm_encode_imm_w_shift(vn.shifts[0], vn.values[0]));
129 for (cnt = 1; cnt < vn.ops; ++cnt) {
130 long value = arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]);
131 ir_node *bic_i_node = new_rd_arm_Bic_i(dbg, current_ir_graph, block, result, mode, value);
137 result = create_mov_node(dbg, block, arm_encode_imm_w_shift(v.shifts[0], v.values[0]));
139 for (cnt = 1; cnt < v.ops; ++cnt) {
140 long value = arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]);
141 ir_node *orr_i_node = new_rd_arm_Or_i(dbg, current_ir_graph, block, result, mode, value);
149 * Create a DAG constructing a given Const.
151 * @param irn a Firm const
153 static ir_node *create_const_graph(ir_node *irn, ir_node *block) {
154 tarval *tv = get_Const_tarval(irn);
155 ir_mode *mode = get_tarval_mode(tv);
158 if (mode_is_reference(mode)) {
159 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
160 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
161 tv = tarval_convert_to(tv, mode_Iu);
163 value = get_tarval_long(tv);
164 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
168 * Create an And that will mask all upper bits
170 static ir_node *gen_zero_extension(dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) {
171 unsigned mask_bits = (1 << result_bits) - 1;
172 ir_node *mask_node = create_const_graph_value(dbg, block, mask_bits);
173 return new_rd_arm_And(dbg, current_ir_graph, block, op, mask_node, mode_Iu, ARM_SHF_NONE, 0);
177 * Generate code for a sign extension.
179 static ir_node *gen_sign_extension(dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) {
180 ir_graph *irg = current_ir_graph;
181 int shift_width = 32 - result_bits;
182 ir_node *shift_const_node = create_const_graph_value(dbg, block, shift_width);
183 ir_node *lshift_node = new_rd_arm_Shl(dbg, irg, block, op, shift_const_node, mode_Iu);
184 ir_node *rshift_node = new_rd_arm_Shrs(dbg, irg, block, lshift_node, shift_const_node, mode_Iu);
189 * Transforms a Conv node.
191 * @return The created ia32 Conv node
193 static ir_node *gen_Conv(ir_node *node) {
194 ir_node *block = be_transform_node(get_nodes_block(node));
195 ir_node *op = get_Conv_op(node);
196 ir_node *new_op = be_transform_node(op);
197 ir_graph *irg = current_ir_graph;
198 ir_mode *src_mode = get_irn_mode(op);
199 ir_mode *dst_mode = get_irn_mode(node);
200 dbg_info *dbg = get_irn_dbg_info(node);
202 if (src_mode == dst_mode)
205 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
206 env_cg->have_fp_insn = 1;
208 if (USE_FPA(env_cg->isa)) {
209 if (mode_is_float(src_mode)) {
210 if (mode_is_float(dst_mode)) {
211 /* from float to float */
212 return new_rd_arm_fpaMvf(dbg, irg, block, new_op, dst_mode);
215 /* from float to int */
216 return new_rd_arm_fpaFix(dbg, irg, block, new_op, dst_mode);
220 /* from int to float */
221 return new_rd_arm_fpaFlt(dbg, irg, block, new_op, dst_mode);
224 else if (USE_VFP(env_cg->isa)) {
225 panic("VFP not supported yet");
229 panic("Softfloat not supported yet");
233 else { /* complete in gp registers */
234 int src_bits = get_mode_size_bits(src_mode);
235 int dst_bits = get_mode_size_bits(dst_mode);
239 if (is_Load(skip_Proj(op))) {
240 if (src_bits == dst_bits) {
241 /* kill unneccessary conv */
244 /* after a load, the bit size is already converted */
248 if (src_bits == dst_bits) {
249 /* kill unneccessary conv */
251 } else if (dst_bits <= 32 && src_bits <= 32) {
252 if (src_bits < dst_bits) {
259 if (mode_is_signed(min_mode)) {
260 return gen_sign_extension(dbg, block, new_op, min_bits);
262 return gen_zero_extension(dbg, block, new_op, min_bits);
265 panic("Cannot handle Conv %+F->%+F with %d->%d bits", src_mode, dst_mode,
273 * Return true if an operand is a shifter operand
275 static int is_shifter_operand(ir_node *n, arm_shift_modifier *pmod) {
276 arm_shift_modifier mod = ARM_SHF_NONE;
279 mod = get_arm_shift_modifier(n);
282 if (mod != ARM_SHF_NONE) {
283 long v = get_arm_imm_value(n);
291 * Creates an ARM Add.
293 * @return the created arm Add node
295 static ir_node *gen_Add(ir_node *node) {
296 ir_node *block = be_transform_node(get_nodes_block(node));
297 ir_node *op1 = get_Add_left(node);
298 ir_node *new_op1 = be_transform_node(op1);
299 ir_node *op2 = get_Add_right(node);
300 ir_node *new_op2 = be_transform_node(op2);
301 ir_mode *mode = get_irn_mode(node);
302 ir_graph *irg = current_ir_graph;
305 arm_shift_modifier mod;
306 dbg_info *dbg = get_irn_dbg_info(node);
308 if (mode_is_float(mode)) {
309 env_cg->have_fp_insn = 1;
310 if (USE_FPA(env_cg->isa)) {
311 if (is_arm_fpaMvf_i(new_op1))
312 return new_rd_arm_fpaAdf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1));
313 if (is_arm_fpaMvf_i(new_op2))
314 return new_rd_arm_fpaAdf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2));
315 return new_rd_arm_fpaAdf(dbg, irg, block, new_op1, new_op2, mode);
316 } else if (USE_VFP(env_cg->isa)) {
317 assert(mode != mode_E && "IEEE Extended FP not supported");
318 panic("VFP not supported yet");
322 panic("Softfloat not supported yet");
326 assert(mode_is_data(mode));
329 if (is_arm_Mov_i(new_op1))
330 return new_rd_arm_Add_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1));
331 if (is_arm_Mov_i(new_op2))
332 return new_rd_arm_Add_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2));
335 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
337 new_op2 = get_irn_n(new_op1, 1);
338 new_op1 = get_irn_n(new_op1, 0);
340 return new_rd_arm_Mla(dbg, irg, block, new_op1, new_op2, new_op3, mode);
342 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
344 new_op1 = get_irn_n(new_op2, 0);
345 new_op2 = get_irn_n(new_op2, 1);
347 return new_rd_arm_Mla(dbg, irg, block, new_op1, new_op2, new_op3, mode);
350 /* is the first a shifter */
351 v = is_shifter_operand(new_op1, &mod);
353 new_op1 = get_irn_n(new_op1, 0);
354 return new_rd_arm_Add(dbg, irg, block, new_op2, new_op1, mode, mod, v);
356 /* is the second a shifter */
357 v = is_shifter_operand(new_op2, &mod);
359 new_op2 = get_irn_n(new_op2, 0);
360 return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, mod, v);
364 return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0);
369 * Creates an ARM Mul.
371 * @return the created arm Mul node
373 static ir_node *gen_Mul(ir_node *node) {
374 ir_node *block = be_transform_node(get_nodes_block(node));
375 ir_node *op1 = get_Mul_left(node);
376 ir_node *new_op1 = be_transform_node(op1);
377 ir_node *op2 = get_Mul_right(node);
378 ir_node *new_op2 = be_transform_node(op2);
379 ir_mode *mode = get_irn_mode(node);
380 ir_graph *irg = current_ir_graph;
381 dbg_info *dbg = get_irn_dbg_info(node);
383 if (mode_is_float(mode)) {
384 env_cg->have_fp_insn = 1;
385 if (USE_FPA(env_cg->isa)) {
386 if (is_arm_Mov_i(new_op1))
387 return new_rd_arm_fpaMuf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1));
388 if (is_arm_Mov_i(new_op2))
389 return new_rd_arm_fpaMuf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2));
390 return new_rd_arm_fpaMuf(dbg, irg, block, new_op1, new_op2, mode);
392 else if (USE_VFP(env_cg->isa)) {
393 assert(mode != mode_E && "IEEE Extended FP not supported");
394 panic("VFP not supported yet");
398 panic("Softfloat not supported yet");
402 assert(mode_is_data(mode));
404 return new_rd_arm_Mul(dbg, irg, block, new_op1, new_op2, mode);
408 * Creates an ARM floating point Div.
410 * @param env The transformation environment
411 * @return the created arm fDiv node
413 static ir_node *gen_Quot(ir_node *node) {
414 ir_node *block = be_transform_node(get_nodes_block(node));
415 ir_node *op1 = get_Quot_left(node);
416 ir_node *new_op1 = be_transform_node(op1);
417 ir_node *op2 = get_Quot_right(node);
418 ir_node *new_op2 = be_transform_node(op2);
419 ir_mode *mode = get_irn_mode(node);
420 dbg_info *dbg = get_irn_dbg_info(node);
422 assert(mode != mode_E && "IEEE Extended FP not supported");
424 env_cg->have_fp_insn = 1;
425 if (USE_FPA(env_cg->isa)) {
426 if (is_arm_Mov_i(new_op1))
427 return new_rd_arm_fpaRdf_i(dbg, current_ir_graph, block, new_op2, mode, get_arm_imm_value(new_op1));
428 if (is_arm_Mov_i(new_op2))
429 return new_rd_arm_fpaDvf_i(dbg, current_ir_graph, block, new_op1, mode, get_arm_imm_value(new_op2));
430 return new_rd_arm_fpaDvf(dbg, current_ir_graph, block, new_op1, new_op2, mode);
431 } else if (USE_VFP(env_cg->isa)) {
432 assert(mode != mode_E && "IEEE Extended FP not supported");
433 panic("VFP not supported yet");
436 panic("Softfloat not supported yet");
441 #define GEN_INT_OP(op) \
442 ir_node *block = be_transform_node(get_nodes_block(node)); \
443 ir_node *op1 = get_ ## op ## _left(node); \
444 ir_node *new_op1 = be_transform_node(op1); \
445 ir_node *op2 = get_ ## op ## _right(node); \
446 ir_node *new_op2 = be_transform_node(op2); \
447 ir_graph *irg = current_ir_graph; \
448 ir_mode *mode = mode_Iu; \
449 dbg_info *dbg = get_irn_dbg_info(node); \
451 arm_shift_modifier mod; \
453 if (is_arm_Mov_i(new_op1)) \
454 return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); \
455 if (is_arm_Mov_i(new_op2)) \
456 return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); \
457 /* is the first a shifter */ \
458 v = is_shifter_operand(new_op1, &mod); \
460 new_op1 = get_irn_n(new_op1, 0); \
461 return new_rd_arm_ ## op(dbg, irg, block, new_op2, new_op1, mode, mod, v); \
463 /* is the second a shifter */ \
464 v = is_shifter_operand(new_op2, &mod); \
466 new_op2 = get_irn_n(new_op2, 0); \
467 return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, mod, v); \
470 return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0) \
473 * Creates an ARM And.
475 * @return the created arm And node
477 static ir_node *gen_And(ir_node *node) {
482 * Creates an ARM Orr.
484 * @param env The transformation environment
485 * @return the created arm Or node
487 static ir_node *gen_Or(ir_node *node) {
492 * Creates an ARM Eor.
494 * @return the created arm Eor node
496 static ir_node *gen_Eor(ir_node *node) {
501 * Creates an ARM Sub.
503 * @return the created arm Sub node
505 static ir_node *gen_Sub(ir_node *node) {
506 ir_node *block = be_transform_node(get_nodes_block(node));
507 ir_node *op1 = get_Sub_left(node);
508 ir_node *new_op1 = be_transform_node(op1);
509 ir_node *op2 = get_Sub_right(node);
510 ir_node *new_op2 = be_transform_node(op2);
511 ir_mode *mode = get_irn_mode(node);
512 ir_graph *irg = current_ir_graph;
513 dbg_info *dbg = get_irn_dbg_info(node);
515 arm_shift_modifier mod;
517 if (mode_is_float(mode)) {
518 env_cg->have_fp_insn = 1;
519 if (USE_FPA(env_cg->isa)) {
520 if (is_arm_Mov_i(new_op1))
521 return new_rd_arm_fpaRsf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1));
522 if (is_arm_Mov_i(new_op2))
523 return new_rd_arm_fpaSuf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2));
524 return new_rd_arm_fpaSuf(dbg, irg, block, new_op1, new_op2, mode);
525 } else if (USE_VFP(env_cg->isa)) {
526 assert(mode != mode_E && "IEEE Extended FP not supported");
527 panic("VFP not supported yet");
531 panic("Softfloat not supported yet");
536 assert(mode_is_data(mode) && "unknown mode for Sub");
539 if (is_arm_Mov_i(new_op1))
540 return new_rd_arm_Rsb_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1));
541 if (is_arm_Mov_i(new_op2))
542 return new_rd_arm_Sub_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2));
544 /* is the first a shifter */
545 v = is_shifter_operand(new_op1, &mod);
547 new_op1 = get_irn_n(new_op1, 0);
548 return new_rd_arm_Rsb(dbg, irg, block, new_op2, new_op1, mode, mod, v);
550 /* is the second a shifter */
551 v = is_shifter_operand(new_op2, &mod);
553 new_op2 = get_irn_n(new_op2, 0);
554 return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, mod, v);
557 return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0);
562 * Creates an ARM Shl.
564 * @return the created ARM Shl node
566 static ir_node *gen_Shl(ir_node *node) {
567 ir_node *block = be_transform_node(get_nodes_block(node));
568 ir_node *op1 = get_Shl_left(node);
569 ir_node *new_op1 = be_transform_node(op1);
570 ir_node *op2 = get_Shl_right(node);
571 ir_node *new_op2 = be_transform_node(op2);
572 ir_mode *mode = mode_Iu;
573 dbg_info *dbg = get_irn_dbg_info(node);
575 if (is_arm_Mov_i(new_op2)) {
576 return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSL, get_arm_imm_value(new_op2));
578 return new_rd_arm_Shl(dbg, current_ir_graph, block, new_op1, new_op2, mode);
582 * Creates an ARM Shr.
584 * @return the created ARM Shr node
586 static ir_node *gen_Shr(ir_node *node) {
587 ir_node *block = be_transform_node(get_nodes_block(node));
588 ir_node *op1 = get_Shr_left(node);
589 ir_node *new_op1 = be_transform_node(op1);
590 ir_node *op2 = get_Shr_right(node);
591 ir_node *new_op2 = be_transform_node(op2);
592 ir_mode *mode = mode_Iu;
593 dbg_info *dbg = get_irn_dbg_info(node);
595 if (is_arm_Mov_i(new_op2)) {
596 return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSR, get_arm_imm_value(new_op2));
598 return new_rd_arm_Shr(dbg, current_ir_graph, block, new_op1, new_op2, mode);
602 * Creates an ARM Shrs.
604 * @return the created ARM Shrs node
606 static ir_node *gen_Shrs(ir_node *node) {
607 ir_node *block = be_transform_node(get_nodes_block(node));
608 ir_node *op1 = get_Shrs_left(node);
609 ir_node *new_op1 = be_transform_node(op1);
610 ir_node *op2 = get_Shrs_right(node);
611 ir_node *new_op2 = be_transform_node(op2);
612 ir_mode *mode = mode_Iu;
613 dbg_info *dbg = get_irn_dbg_info(node);
615 if (is_arm_Mov_i(new_op2)) {
616 return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_ASR, get_arm_imm_value(new_op2));
618 return new_rd_arm_Shrs(dbg, current_ir_graph, block, new_op1, new_op2, mode);
622 * Creates an ARM Ror.
624 * @return the created ARM Ror node
626 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2) {
627 ir_node *block = be_transform_node(get_nodes_block(node));
628 ir_node *new_op1 = be_transform_node(op1);
629 ir_node *new_op2 = be_transform_node(op2);
630 ir_mode *mode = mode_Iu;
631 dbg_info *dbg = get_irn_dbg_info(node);
633 if (is_arm_Mov_i(new_op2)) {
634 return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_ROR, get_arm_imm_value(new_op2));
636 return new_rd_arm_Ror(dbg, current_ir_graph, block, new_op1, new_op2, mode);
640 * Creates an ARM Rol.
642 * @return the created ARM Rol node
644 * Note: there is no Rol on arm, we have to use Ror
646 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2) {
647 ir_node *block = be_transform_node(get_nodes_block(node));
648 ir_node *new_op1 = be_transform_node(op1);
649 ir_mode *mode = mode_Iu;
650 dbg_info *dbg = get_irn_dbg_info(node);
651 ir_node *new_op2 = be_transform_node(op2);
653 new_op2 = new_rd_arm_Rsb_i(dbg, current_ir_graph, block, new_op2, mode, 32);
654 return new_rd_arm_Ror(dbg, current_ir_graph, block, new_op1, new_op2, mode);
658 * Creates an ARM ROR from a Firm Rotl.
660 * @return the created ARM Ror node
662 static ir_node *gen_Rotl(ir_node *node) {
663 ir_node *rotate = NULL;
664 ir_node *op1 = get_Rotl_left(node);
665 ir_node *op2 = get_Rotl_right(node);
667 /* Firm has only RotL, so we are looking for a right (op2)
668 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
669 that means we can create a RotR. */
672 ir_node *right = get_Add_right(op2);
673 if (is_Const(right)) {
674 tarval *tv = get_Const_tarval(right);
675 ir_mode *mode = get_irn_mode(node);
676 long bits = get_mode_size_bits(mode);
677 ir_node *left = get_Add_left(op2);
679 if (is_Minus(left) &&
680 tarval_is_long(tv) &&
681 get_tarval_long(tv) == bits &&
683 rotate = gen_Ror(node, op1, get_Minus_op(left));
685 } else if (is_Sub(op2)) {
686 ir_node *left = get_Sub_left(op2);
687 if (is_Const(left)) {
688 tarval *tv = get_Const_tarval(left);
689 ir_mode *mode = get_irn_mode(node);
690 long bits = get_mode_size_bits(mode);
691 ir_node *right = get_Sub_right(op2);
693 if (tarval_is_long(tv) &&
694 get_tarval_long(tv) == bits &&
696 rotate = gen_Ror(node, op1, right);
698 } else if (is_Const(op2)) {
699 tarval *tv = get_Const_tarval(op2);
700 ir_mode *mode = get_irn_mode(node);
701 long bits = get_mode_size_bits(mode);
703 if (tarval_is_long(tv) && bits == 32) {
704 ir_node *block = be_transform_node(get_nodes_block(node));
705 ir_node *new_op1 = be_transform_node(op1);
706 ir_mode *mode = mode_Iu;
707 dbg_info *dbg = get_irn_dbg_info(node);
709 bits = (bits - get_tarval_long(tv)) & 31;
710 rotate = new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_ROR, bits);
714 if (rotate == NULL) {
715 rotate = gen_Rol(node, op1, op2);
722 * Transforms a Not node.
724 * @return the created ARM Not node
726 static ir_node *gen_Not(ir_node *node) {
727 ir_node *block = be_transform_node(get_nodes_block(node));
728 ir_node *op = get_Not_op(node);
729 ir_node *new_op = be_transform_node(op);
730 dbg_info *dbg = get_irn_dbg_info(node);
731 ir_mode *mode = mode_Iu;
732 arm_shift_modifier mod = ARM_SHF_NONE;
733 int v = is_shifter_operand(new_op, &mod);
736 new_op = get_irn_n(new_op, 0);
738 return new_rd_arm_Mvn(dbg, current_ir_graph, block, new_op, mode, mod, v);
742 * Transforms an Abs node.
744 * @param env The transformation environment
745 * @return the created ARM Abs node
747 static ir_node *gen_Abs(ir_node *node) {
748 ir_node *block = be_transform_node(get_nodes_block(node));
749 ir_node *op = get_Abs_op(node);
750 ir_node *new_op = be_transform_node(op);
751 dbg_info *dbg = get_irn_dbg_info(node);
752 ir_mode *mode = get_irn_mode(node);
754 if (mode_is_float(mode)) {
755 env_cg->have_fp_insn = 1;
756 if (USE_FPA(env_cg->isa))
757 return new_rd_arm_fpaAbs(dbg, current_ir_graph, block, new_op, mode);
758 else if (USE_VFP(env_cg->isa)) {
759 assert(mode != mode_E && "IEEE Extended FP not supported");
760 panic("VFP not supported yet");
763 panic("Softfloat not supported yet");
766 assert(mode_is_data(mode));
768 return new_rd_arm_Abs(dbg, current_ir_graph, block, new_op, mode);
772 * Transforms a Minus node.
774 * @return the created ARM Minus node
776 static ir_node *gen_Minus(ir_node *node) {
777 ir_node *block = be_transform_node(get_nodes_block(node));
778 ir_node *op = get_Minus_op(node);
779 ir_node *new_op = be_transform_node(op);
780 dbg_info *dbg = get_irn_dbg_info(node);
781 ir_mode *mode = get_irn_mode(node);
783 if (mode_is_float(mode)) {
784 env_cg->have_fp_insn = 1;
785 if (USE_FPA(env_cg->isa))
786 return new_rd_arm_fpaMvf(dbg, current_ir_graph, block, op, mode);
787 else if (USE_VFP(env_cg->isa)) {
788 assert(mode != mode_E && "IEEE Extended FP not supported");
789 panic("VFP not supported yet");
792 panic("Softfloat not supported yet");
795 assert(mode_is_data(mode));
797 return new_rd_arm_Rsb_i(dbg, current_ir_graph, block, new_op, mode, 0);
803 * @return the created ARM Load node
805 static ir_node *gen_Load(ir_node *node) {
806 ir_node *block = be_transform_node(get_nodes_block(node));
807 ir_node *ptr = get_Load_ptr(node);
808 ir_node *new_ptr = be_transform_node(ptr);
809 ir_node *mem = get_Load_mem(node);
810 ir_node *new_mem = be_transform_node(mem);
811 ir_mode *mode = get_Load_mode(node);
812 ir_graph *irg = current_ir_graph;
813 dbg_info *dbg = get_irn_dbg_info(node);
814 ir_node *new_load = NULL;
816 if (mode_is_float(mode)) {
817 env_cg->have_fp_insn = 1;
818 if (USE_FPA(env_cg->isa))
819 new_load = new_rd_arm_fpaLdf(dbg, irg, block, new_ptr, new_mem, mode);
820 else if (USE_VFP(env_cg->isa)) {
821 assert(mode != mode_E && "IEEE Extended FP not supported");
822 panic("VFP not supported yet");
825 panic("Softfloat not supported yet");
829 assert(mode_is_data(mode) && "unsupported mode for Load");
831 if (mode_is_signed(mode)) {
832 /* sign extended loads */
833 switch (get_mode_size_bits(mode)) {
835 new_load = new_rd_arm_Loadbs(dbg, irg, block, new_ptr, new_mem);
838 new_load = new_rd_arm_Loadhs(dbg, irg, block, new_ptr, new_mem);
841 new_load = new_rd_arm_Load(dbg, irg, block, new_ptr, new_mem);
844 panic("mode size not supported");
847 /* zero extended loads */
848 switch (get_mode_size_bits(mode)) {
850 new_load = new_rd_arm_Loadb(dbg, irg, block, new_ptr, new_mem);
853 new_load = new_rd_arm_Loadh(dbg, irg, block, new_ptr, new_mem);
856 new_load = new_rd_arm_Load(dbg, irg, block, new_ptr, new_mem);
859 panic("mode size not supported");
863 set_irn_pinned(new_load, get_irn_pinned(node));
865 /* check for special case: the loaded value might not be used */
866 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
867 /* add a result proj and a Keep to produce a pseudo use */
868 ir_node *proj = new_r_Proj(irg, block, new_load, mode_Iu, pn_arm_Load_res);
869 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
876 * Transforms a Store.
878 * @return the created ARM Store node
880 static ir_node *gen_Store(ir_node *node) {
881 ir_node *block = be_transform_node(get_nodes_block(node));
882 ir_node *ptr = get_Store_ptr(node);
883 ir_node *new_ptr = be_transform_node(ptr);
884 ir_node *mem = get_Store_mem(node);
885 ir_node *new_mem = be_transform_node(mem);
886 ir_node *val = get_Store_value(node);
887 ir_node *new_val = be_transform_node(val);
888 ir_mode *mode = get_irn_mode(val);
889 ir_graph *irg = current_ir_graph;
890 dbg_info *dbg = get_irn_dbg_info(node);
891 ir_node *new_store = NULL;
893 if (mode_is_float(mode)) {
894 env_cg->have_fp_insn = 1;
895 if (USE_FPA(env_cg->isa))
896 new_store = new_rd_arm_fpaStf(dbg, irg, block, new_ptr, new_val, new_mem, mode);
897 else if (USE_VFP(env_cg->isa)) {
898 assert(mode != mode_E && "IEEE Extended FP not supported");
899 panic("VFP not supported yet");
901 panic("Softfloat not supported yet");
904 assert(mode_is_data(mode) && "unsupported mode for Store");
905 switch (get_mode_size_bits(mode)) {
907 new_store = new_rd_arm_Storeb(dbg, irg, block, new_ptr, new_val, new_mem);
909 new_store = new_rd_arm_Storeh(dbg, irg, block, new_ptr, new_val, new_mem);
911 new_store = new_rd_arm_Store(dbg, irg, block, new_ptr, new_val, new_mem);
914 set_irn_pinned(new_store, get_irn_pinned(node));
921 * @return the created ARM Cond node
923 static ir_node *gen_Cond(ir_node *node) {
924 ir_node *block = be_transform_node(get_nodes_block(node));
925 ir_node *selector = get_Cond_selector(node);
926 ir_graph *irg = current_ir_graph;
927 dbg_info *dbg = get_irn_dbg_info(node);
928 ir_mode *mode = get_irn_mode(selector);
930 if (mode == mode_b) {
931 /* an conditional jump */
932 ir_node *cmp_node = get_Proj_pred(selector);
933 ir_node *op1 = get_Cmp_left(cmp_node);
934 ir_node *new_op1 = be_transform_node(op1);
935 ir_node *op2 = get_Cmp_right(cmp_node);
937 if (mode_is_float(get_irn_mode(op1))) {
938 ir_node *new_op2 = be_transform_node(op2);
939 /* floating point compare */
940 pn_Cmp pnc = get_Proj_proj(selector);
942 if (pnc & pn_Cmp_Uo) {
943 /* check for unordered, need cmf */
944 return new_rd_arm_fpaCmfBra(dbg, irg, block, new_op1, new_op2, pnc);
946 /* Hmm: use need cmfe */
947 return new_rd_arm_fpaCmfeBra(dbg, irg, block, new_op1, new_op2, pnc);
948 } else if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) {
950 return new_rd_arm_TstBra(dbg, irg, block, new_op1, new_op1, get_Proj_proj(selector));
952 /* integer compare */
953 ir_node *new_op2 = be_transform_node(op2);
954 return new_rd_arm_CmpBra(dbg, irg, block, new_op1, new_op2, get_Proj_proj(selector));
958 ir_node *new_op = be_transform_node(selector);
959 ir_node *const_graph;
963 const ir_edge_t *edge;
970 foreach_out_edge(node, edge) {
971 proj = get_edge_src_irn(edge);
972 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
974 pn = get_Proj_proj(proj);
976 min = pn<min ? pn : min;
977 max = pn>max ? pn : max;
980 n_projs = max - translation + 1;
982 foreach_out_edge(node, edge) {
983 proj = get_edge_src_irn(edge);
984 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
986 pn = get_Proj_proj(proj) - translation;
987 set_Proj_proj(proj, pn);
990 const_graph = create_const_graph_value(dbg, block, translation);
991 sub = new_rd_arm_Sub(dbg, irg, block, new_op, const_graph, mode, ARM_SHF_NONE, 0);
992 return new_rd_arm_SwitchJmp(dbg, irg, block, sub, n_projs, get_Cond_defaultProj(node) - translation);
997 * Returns the name of a SymConst.
998 * @param symc the SymConst
999 * @return name of the SymConst
1001 static ident *get_sc_ident(ir_node *symc) {
1004 switch (get_SymConst_kind(symc)) {
1005 case symconst_addr_name:
1006 return get_SymConst_name(symc);
1008 case symconst_addr_ent:
1009 ent = get_SymConst_entity(symc);
1010 set_entity_backend_marked(ent, 1);
1011 return get_entity_ld_ident(ent);
1014 assert(0 && "Unsupported SymConst");
1020 static tarval *fpa_imm[3][fpa_max];
1023 * Check, if a floating point tarval is an fpa immediate, i.e.
1024 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
1026 static int is_fpa_immediate(tarval *tv) {
1027 ir_mode *mode = get_tarval_mode(tv);
1030 switch (get_mode_size_bits(mode)) {
1041 if (tarval_cmp(tv, get_tarval_null(mode)) & pn_Cmp_Lt) {
1042 tv = tarval_neg(tv);
1046 for (j = 0; j < fpa_max; ++j) {
1047 if (tv == fpa_imm[i][j])
1054 * Transforms a Const node.
1056 * @return The transformed ARM node.
1058 static ir_node *gen_Const(ir_node *node) {
1059 ir_node *block = be_transform_node(get_nodes_block(node));
1060 ir_graph *irg = current_ir_graph;
1061 ir_mode *mode = get_irn_mode(node);
1062 dbg_info *dbg = get_irn_dbg_info(node);
1064 if (mode_is_float(mode)) {
1065 env_cg->have_fp_insn = 1;
1066 if (USE_FPA(env_cg->isa)) {
1067 tarval *tv = get_Const_tarval(node);
1068 int imm = is_fpa_immediate(tv);
1070 if (imm != fpa_max) {
1072 node = new_rd_arm_fpaMvf_i(dbg, irg, block, mode, imm);
1074 node = new_rd_arm_fpaMnf_i(dbg, irg, block, mode, -imm);
1076 node = new_rd_arm_fpaConst(dbg, irg, block, tv);
1078 be_dep_on_frame(node);
1081 else if (USE_VFP(env_cg->isa)) {
1082 assert(mode != mode_E && "IEEE Extended FP not supported");
1083 panic("VFP not supported yet");
1086 panic("Softfloat not supported yet");
1089 return create_const_graph(node, block);
1093 * Transforms a SymConst node.
1095 * @return The transformed ARM node.
1097 static ir_node *gen_SymConst(ir_node *node) {
1098 ir_node *block = be_transform_node(get_nodes_block(node));
1099 ir_mode *mode = mode_Iu;
1100 dbg_info *dbg = get_irn_dbg_info(node);
1101 ir_graph *irg = current_ir_graph;
1104 res = new_rd_arm_SymConst(dbg, irg, block, mode, get_sc_ident(node));
1105 be_dep_on_frame(res);
1110 * Transforms a CopyB node.
1112 * @return The transformed ARM node.
1114 static ir_node *gen_CopyB(ir_node *node) {
1115 ir_node *block = be_transform_node(get_nodes_block(node));
1116 ir_node *src = get_CopyB_src(node);
1117 ir_node *new_src = be_transform_node(src);
1118 ir_node *dst = get_CopyB_dst(node);
1119 ir_node *new_dst = be_transform_node(dst);
1120 ir_node *mem = get_CopyB_mem(node);
1121 ir_node *new_mem = be_transform_node(mem);
1122 ir_graph *irg = current_ir_graph;
1123 dbg_info *dbg = get_irn_dbg_info(node);
1124 int size = get_type_size_bytes(get_CopyB_type(node));
1128 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, new_src);
1129 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, new_dst);
1131 return new_rd_arm_CopyB(dbg, irg, block, dst_copy, src_copy,
1132 new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu),
1133 new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu),
1134 new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu),
1139 /********************************************
1142 * | |__ ___ _ __ ___ __| | ___ ___
1143 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1144 * | |_) | __/ | | | (_) | (_| | __/\__ \
1145 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1147 ********************************************/
1150 * Return an expanding stack offset.
1151 * Note that function is called in the transform phase
1152 * where the stack offsets are still relative regarding
1153 * the first (frame allocating) IncSP.
1154 * However this is exactly what we want because frame
1155 * access must be done relative the the fist IncSP ...
1157 static int get_sp_expand_offset(ir_node *inc_sp) {
1158 int offset = be_get_IncSP_offset(inc_sp);
1160 if (offset == BE_STACK_FRAME_SIZE_EXPAND)
1167 static ir_node *gen_StackParam(ir_node *irn) {
1168 ir_node *block = be_transform_node(get_nodes_block(node));
1169 ir_node *new_op = NULL;
1170 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1171 ir_node *mem = new_rd_NoMem(env->irg);
1172 ir_node *ptr = get_irn_n(irn, 0);
1173 ir_entity *ent = be_get_frame_entity(irn);
1174 ir_mode *mode = env->mode;
1176 // /* If the StackParam has only one user -> */
1177 // /* put it in the Block where the user resides */
1178 // if (get_irn_n_edges(node) == 1) {
1179 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1182 if (mode_is_float(mode)) {
1183 if (USE_SSE2(env->cg))
1184 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1186 env->cg->used_x87 = 1;
1187 new_op = new_rd_ia32_vfld(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1191 new_op = new_rd_ia32_Load(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1194 set_ia32_frame_ent(new_op, ent);
1195 set_ia32_use_frame(new_op);
1197 set_ia32_am_support(new_op, ia32_am_Source);
1198 set_ia32_op_type(new_op, ia32_AddrModeS);
1199 set_ia32_am_flavour(new_op, ia32_B);
1200 set_ia32_ls_mode(new_op, mode);
1202 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1204 return new_rd_Proj(env->dbg, env->irg, block, new_op, mode, 0);
1209 * Transforms a FrameAddr into an ARM Add.
1211 static ir_node *gen_be_FrameAddr(ir_node *node) {
1212 ir_node *block = be_transform_node(get_nodes_block(node));
1213 ir_entity *ent = be_get_frame_entity(node);
1214 int offset = get_entity_offset(ent);
1215 ir_node *op = be_get_FrameAddr_frame(node);
1216 ir_node *new_op = be_transform_node(op);
1217 dbg_info *dbg = get_irn_dbg_info(node);
1218 ir_mode *mode = mode_Iu;
1221 if (be_is_IncSP(op)) {
1222 /* BEWARE: we get an offset which is absolute from an offset that
1223 is relative. Both must be merged */
1224 offset += get_sp_expand_offset(op);
1226 cnst = create_const_graph_value(dbg, block, (unsigned)offset);
1227 if (is_arm_Mov_i(cnst))
1228 return new_rd_arm_Add_i(dbg, current_ir_graph, block, new_op, mode, get_arm_imm_value(cnst));
1229 return new_rd_arm_Add(dbg, current_ir_graph, block, new_op, cnst, mode, ARM_SHF_NONE, 0);
1233 * Transform a be_AddSP into an arm_AddSP. Eat up const sizes.
1235 static ir_node *gen_be_AddSP(ir_node *node) {
1236 ir_node *block = be_transform_node(get_nodes_block(node));
1237 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
1238 ir_node *new_sz = be_transform_node(sz);
1239 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
1240 ir_node *new_sp = be_transform_node(sp);
1241 ir_graph *irg = current_ir_graph;
1242 dbg_info *dbgi = get_irn_dbg_info(node);
1243 ir_node *nomem = new_NoMem();
1246 /* ARM stack grows in reverse direction, make a SubSPandCopy */
1247 new_op = new_rd_arm_SubSPandCopy(dbgi, irg, block, new_sp, new_sz, nomem);
1253 * Transform a be_SubSP into an arm_SubSP. Eat up const sizes.
1255 static ir_node *gen_be_SubSP(ir_node *node) {
1256 ir_node *block = be_transform_node(get_nodes_block(node));
1257 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
1258 ir_node *new_sz = be_transform_node(sz);
1259 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
1260 ir_node *new_sp = be_transform_node(sp);
1261 ir_graph *irg = current_ir_graph;
1262 dbg_info *dbgi = get_irn_dbg_info(node);
1263 ir_node *nomem = new_NoMem();
1266 /* ARM stack grows in reverse direction, make an AddSP */
1267 new_op = new_rd_arm_AddSP(dbgi, irg, block, new_sp, new_sz, nomem);
1273 * Transform a be_Copy.
1275 static ir_node *gen_be_Copy(ir_node *node) {
1276 ir_node *result = be_duplicate_node(node);
1277 ir_mode *mode = get_irn_mode(result);
1279 if (mode_needs_gp_reg(mode)) {
1280 set_irn_mode(node, mode_Iu);
1287 * Transform a Proj from a Load.
1289 static ir_node *gen_Proj_Load(ir_node *node) {
1290 ir_node *block = be_transform_node(get_nodes_block(node));
1291 ir_node *load = get_Proj_pred(node);
1292 ir_node *new_load = be_transform_node(load);
1293 ir_graph *irg = current_ir_graph;
1294 dbg_info *dbgi = get_irn_dbg_info(node);
1295 long proj = get_Proj_proj(node);
1297 /* renumber the proj */
1298 switch (get_arm_irn_opcode(new_load)) {
1301 case iro_arm_Loadbs:
1303 case iro_arm_Loadhs:
1304 /* handle all gp loads equal: they have the same proj numbers. */
1305 if (proj == pn_Load_res) {
1306 return new_rd_Proj(dbgi, irg, block, new_load, mode_Iu, pn_arm_Load_res);
1307 } else if (proj == pn_Load_M) {
1308 return new_rd_Proj(dbgi, irg, block, new_load, mode_M, pn_arm_Load_M);
1311 case iro_arm_fpaLdf:
1312 if (proj == pn_Load_res) {
1313 ir_mode *mode = get_Load_mode(load);
1314 return new_rd_Proj(dbgi, irg, block, new_load, mode, pn_arm_fpaLdf_res);
1315 } else if (proj == pn_Load_M) {
1316 return new_rd_Proj(dbgi, irg, block, new_load, mode_M, pn_arm_fpaLdf_M);
1322 panic("Unsupported Proj from Load");
1326 * Transform and renumber the Projs from a CopyB.
1328 static ir_node *gen_Proj_CopyB(ir_node *node) {
1329 ir_node *block = be_transform_node(get_nodes_block(node));
1330 ir_node *pred = get_Proj_pred(node);
1331 ir_node *new_pred = be_transform_node(pred);
1332 ir_graph *irg = current_ir_graph;
1333 dbg_info *dbgi = get_irn_dbg_info(node);
1334 long proj = get_Proj_proj(node);
1337 case pn_CopyB_M_regular:
1338 if (is_arm_CopyB(new_pred)) {
1339 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_CopyB_M);
1345 panic("Unsupported Proj from CopyB");
1349 * Transform and renumber the Projs from a Quot.
1351 static ir_node *gen_Proj_Quot(ir_node *node) {
1352 ir_node *block = be_transform_node(get_nodes_block(node));
1353 ir_node *pred = get_Proj_pred(node);
1354 ir_node *new_pred = be_transform_node(pred);
1355 ir_graph *irg = current_ir_graph;
1356 dbg_info *dbgi = get_irn_dbg_info(node);
1357 ir_mode *mode = get_irn_mode(node);
1358 long proj = get_Proj_proj(node);
1362 if (is_arm_fpaDvf(new_pred) || is_arm_fpaDvf_i(new_pred)) {
1363 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaDvf_M);
1364 } else if (is_arm_fpaRdf(new_pred) || is_arm_fpaRdf_i(new_pred)) {
1365 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaRdf_M);
1366 } else if (is_arm_fpaFdv(new_pred) || is_arm_fpaFdv_i(new_pred)) {
1367 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaFdv_M);
1368 } else if (is_arm_fpaFrd(new_pred) || is_arm_fpaFrd_i(new_pred)) {
1369 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaFrd_M);
1373 if (is_arm_fpaDvf(new_pred) || is_arm_fpaDvf_i(new_pred)) {
1374 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaDvf_res);
1375 } else if (is_arm_fpaRdf(new_pred) || is_arm_fpaRdf_i(new_pred)) {
1376 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaRdf_res);
1377 } else if (is_arm_fpaFdv(new_pred) || is_arm_fpaFdv_i(new_pred)) {
1378 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaFdv_res);
1379 } else if (is_arm_fpaFrd(new_pred) || is_arm_fpaFrd_i(new_pred)) {
1380 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaFrd_res);
1386 panic("Unsupported Proj from Quot");
1390 * Transform the Projs of a be_AddSP.
1392 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
1393 ir_node *block = be_transform_node(get_nodes_block(node));
1394 ir_node *pred = get_Proj_pred(node);
1395 ir_node *new_pred = be_transform_node(pred);
1396 ir_graph *irg = current_ir_graph;
1397 dbg_info *dbgi = get_irn_dbg_info(node);
1398 long proj = get_Proj_proj(node);
1400 if (proj == pn_be_AddSP_sp) {
1401 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
1402 pn_arm_SubSPandCopy_stack);
1403 arch_set_irn_register(env_cg->arch_env, res, &arm_gp_regs[REG_SP]);
1405 } else if(proj == pn_be_AddSP_res) {
1406 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
1407 pn_arm_SubSPandCopy_addr);
1408 } else if (proj == pn_be_AddSP_M) {
1409 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_SubSPandCopy_M);
1411 panic("Unsupported Proj from AddSP");
1415 * Transform the Projs of a be_SubSP.
1417 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
1418 ir_node *block = be_transform_node(get_nodes_block(node));
1419 ir_node *pred = get_Proj_pred(node);
1420 ir_node *new_pred = be_transform_node(pred);
1421 ir_graph *irg = current_ir_graph;
1422 dbg_info *dbgi = get_irn_dbg_info(node);
1423 long proj = get_Proj_proj(node);
1425 if (proj == pn_be_SubSP_sp) {
1426 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
1427 pn_arm_AddSP_stack);
1428 arch_set_irn_register(env_cg->arch_env, res, &arm_gp_regs[REG_SP]);
1430 } else if (proj == pn_be_SubSP_M) {
1431 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_AddSP_M);
1433 panic("Unsupported Proj from SubSP");
1437 * Transform the Projs from a Cmp.
1439 static ir_node *gen_Proj_Cmp(ir_node *node) {
1446 * Transform the Thread Local Storage Proj.
1448 static ir_node *gen_Proj_tls(ir_node *node) {
1449 ir_node *block = be_transform_node(get_nodes_block(node));
1450 ir_graph *irg = current_ir_graph;
1451 dbg_info *dbgi = NULL;
1453 return new_rd_arm_LdTls(dbgi, irg, block, mode_Iu);
1457 * Transform a Proj node.
1459 static ir_node *gen_Proj(ir_node *node) {
1460 ir_graph *irg = current_ir_graph;
1461 dbg_info *dbgi = get_irn_dbg_info(node);
1462 ir_node *pred = get_Proj_pred(node);
1463 long proj = get_Proj_proj(node);
1465 if (is_Store(pred)) {
1466 if (proj == pn_Store_M) {
1467 return be_transform_node(pred);
1469 panic("Unsupported Proj from Store");
1471 } else if (is_Load(pred)) {
1472 return gen_Proj_Load(node);
1473 } else if (is_CopyB(pred)) {
1474 return gen_Proj_CopyB(node);
1475 } else if (is_Quot(pred)) {
1476 return gen_Proj_Quot(node);
1477 } else if (be_is_SubSP(pred)) {
1478 return gen_Proj_be_SubSP(node);
1479 } else if (be_is_AddSP(pred)) {
1480 return gen_Proj_be_AddSP(node);
1481 } else if (is_Cmp(pred)) {
1482 return gen_Proj_Cmp(node);
1483 } else if (is_Start(pred)) {
1484 if (proj == pn_Start_X_initial_exec) {
1485 ir_node *block = get_nodes_block(pred);
1488 /* we exchange the ProjX with a jump */
1489 block = be_transform_node(block);
1490 jump = new_rd_Jmp(dbgi, irg, block);
1493 if (node == get_irg_anchor(irg, anchor_tls)) {
1494 return gen_Proj_tls(node);
1497 ir_node *new_pred = be_transform_node(pred);
1498 ir_mode *mode = get_irn_mode(node);
1499 if (mode_needs_gp_reg(mode)) {
1500 ir_node *block = be_transform_node(get_nodes_block(node));
1501 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
1502 get_Proj_proj(node));
1503 #ifdef DEBUG_libfirm
1504 new_proj->node_nr = node->node_nr;
1510 return be_duplicate_node(node);
1513 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_graph *irg, ir_node *block);
1515 static INLINE ir_node *create_const(ir_node **place,
1516 create_const_node_func func,
1517 const arch_register_t* reg)
1519 ir_node *block, *res;
1524 block = get_irg_start_block(env_cg->irg);
1525 res = func(NULL, env_cg->irg, block);
1526 arch_set_irn_register(env_cg->arch_env, res, reg);
1529 add_irn_dep(get_irg_end(env_cg->irg), res);
1533 static ir_node *arm_new_Unknown_gp(void) {
1534 return create_const(&env_cg->unknown_gp, new_rd_arm_Unknown_GP,
1535 &arm_gp_regs[REG_GP_UKNWN]);
1538 static ir_node *arm_new_Unknown_fpa(void) {
1539 return create_const(&env_cg->unknown_fpa, new_rd_arm_Unknown_FPA,
1540 &arm_fpa_regs[REG_FPA_UKNWN]);
1544 * This function just sets the register for the Unknown node
1545 * as this is not done during register allocation because Unknown
1546 * is an "ignore" node.
1548 static ir_node *gen_Unknown(ir_node *node) {
1549 ir_mode *mode = get_irn_mode(node);
1550 if (mode_is_float(mode)) {
1551 if (USE_FPA(env_cg->isa))
1552 return arm_new_Unknown_fpa();
1553 else if (USE_VFP(env_cg->isa))
1554 panic("VFP not supported yet");
1556 panic("Softfloat not supported yet");
1557 } else if (mode_needs_gp_reg(mode)) {
1558 return arm_new_Unknown_gp();
1560 assert(0 && "unsupported Unknown-Mode");
1567 * Change some phi modes
1569 static ir_node *gen_Phi(ir_node *node) {
1570 ir_node *block = be_transform_node(get_nodes_block(node));
1571 ir_graph *irg = current_ir_graph;
1572 dbg_info *dbgi = get_irn_dbg_info(node);
1573 ir_mode *mode = get_irn_mode(node);
1576 if (mode_needs_gp_reg(mode)) {
1577 /* we shouldn't have any 64bit stuff around anymore */
1578 assert(get_mode_size_bits(mode) <= 32);
1579 /* all integer operations are on 32bit registers now */
1583 /* phi nodes allow loops, so we use the old arguments for now
1584 * and fix this later */
1585 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
1586 copy_node_attr(node, phi);
1587 be_duplicate_deps(node, phi);
1589 be_enqueue_preds(node);
1594 /*********************************************************
1597 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1598 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1599 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1600 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1602 *********************************************************/
1605 * the BAD transformer.
1607 static ir_node *bad_transform(ir_node *irn) {
1608 panic("ARM backend: Not implemented: %+F", irn);
1613 * Set a node emitter. Make it a bit more type safe.
1615 static INLINE void set_transformer(ir_op *op, be_transform_func arm_transform_func) {
1616 op->ops.generic = (op_func)arm_transform_func;
1620 * Enters all transform functions into the generic pointer
1622 static void arm_register_transformers(void) {
1623 ir_op *op_Max, *op_Min, *op_Mulh;
1625 /* first clear the generic function pointer for all ops */
1626 clear_irp_opcodes_generic_func();
1628 #define GEN(a) set_transformer(op_##a, gen_##a)
1629 #define BAD(a) set_transformer(op_##a, bad_transform)
1645 /* should be lowered */
1659 BAD(ASM); /* unsupported yet */
1661 BAD(Mux); /* unsupported yet */
1668 /* we should never see these nodes */
1683 /* handle generic backend nodes */
1691 /* set the register for all Unknown nodes */
1694 op_Max = get_op_Max();
1696 BAD(Max); /* unsupported yet */
1697 op_Min = get_op_Min();
1699 BAD(Min); /* unsupported yet */
1700 op_Mulh = get_op_Mulh();
1702 BAD(Mulh); /* unsupported yet */
1709 * Pre-transform all unknown nodes.
1711 static void arm_pretransform_node(void)
1713 arm_code_gen_t *cg = env_cg;
1715 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
1716 cg->unknown_fpa = be_pre_transform_node(cg->unknown_fpa);
1720 * Initialize fpa Immediate support.
1722 static void arm_init_fpa_immediate(void) {
1723 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
1724 fpa_imm[0][fpa_null] = get_tarval_null(mode_F);
1725 fpa_imm[0][fpa_one] = get_tarval_one(mode_F);
1726 fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
1727 fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
1728 fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
1729 fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
1730 fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
1731 fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
1733 fpa_imm[1][fpa_null] = get_tarval_null(mode_D);
1734 fpa_imm[1][fpa_one] = get_tarval_one(mode_D);
1735 fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
1736 fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
1737 fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
1738 fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
1739 fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
1740 fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
1742 fpa_imm[2][fpa_null] = get_tarval_null(mode_E);
1743 fpa_imm[2][fpa_one] = get_tarval_one(mode_E);
1744 fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
1745 fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
1746 fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
1747 fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
1748 fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
1749 fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
1753 * Transform a Firm graph into an ARM graph.
1755 void arm_transform_graph(arm_code_gen_t *cg) {
1756 static int imm_initialized = 0;
1758 if (! imm_initialized) {
1759 arm_init_fpa_immediate();
1760 imm_initialized = 1;
1762 arm_register_transformers();
1764 be_transform_graph(cg->birg, arm_pretransform_node);
1767 void arm_init_transform(void) {
1768 // FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");