2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
28 #include "irgraph_t.h"
42 #include "betranshlp.h"
43 #include "beabihelper.h"
46 #include "bearch_arm_t.h"
47 #include "arm_nodes_attr.h"
48 #include "arm_transform.h"
49 #include "arm_optimize.h"
50 #include "arm_new_nodes.h"
51 #include "arm_map_regs.h"
52 #include "arm_cconv.h"
54 #include "gen_arm_regalloc_if.h"
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 static const arch_register_t *sp_reg = &arm_registers[REG_SP];
61 static ir_mode *mode_gp;
62 static ir_mode *mode_fp;
63 static beabi_helper_env_t *abihelper;
64 static be_stackorder_t *stackorder;
65 static calling_convention_t *cconv = NULL;
66 static arm_isa_t *isa;
68 static pmap *node_to_stack;
70 static const arch_register_t *const callee_saves[] = {
71 &arm_registers[REG_R4],
72 &arm_registers[REG_R5],
73 &arm_registers[REG_R6],
74 &arm_registers[REG_R7],
75 &arm_registers[REG_R8],
76 &arm_registers[REG_R9],
77 &arm_registers[REG_R10],
78 &arm_registers[REG_R11],
79 &arm_registers[REG_LR],
82 static const arch_register_t *const caller_saves[] = {
83 &arm_registers[REG_R0],
84 &arm_registers[REG_R1],
85 &arm_registers[REG_R2],
86 &arm_registers[REG_R3],
87 &arm_registers[REG_LR],
89 &arm_registers[REG_F0],
90 &arm_registers[REG_F1],
91 &arm_registers[REG_F2],
92 &arm_registers[REG_F3],
93 &arm_registers[REG_F4],
94 &arm_registers[REG_F5],
95 &arm_registers[REG_F6],
96 &arm_registers[REG_F7],
99 static bool mode_needs_gp_reg(ir_mode *mode)
101 return mode_is_int(mode) || mode_is_reference(mode);
105 * create firm graph for a constant
107 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
114 /* We only have 8 bit immediates. So we possibly have to combine several
115 * operations to construct the desired value.
117 * we can either create the value by adding bits to 0 or by removing bits
118 * from an register with all bits set. Try which alternative needs fewer
120 arm_gen_vals_from_word(value, &v);
121 arm_gen_vals_from_word(~value, &vn);
123 if (vn.ops < v.ops) {
125 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
127 for (cnt = 1; cnt < vn.ops; ++cnt) {
128 result = new_bd_arm_Bic_imm(dbgi, block, result,
129 vn.values[cnt], vn.rors[cnt]);
133 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
135 for (cnt = 1; cnt < v.ops; ++cnt) {
136 result = new_bd_arm_Or_imm(dbgi, block, result,
137 v.values[cnt], v.rors[cnt]);
144 * Create a DAG constructing a given Const.
146 * @param irn a Firm const
148 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
150 ir_tarval *tv = get_Const_tarval(irn);
151 ir_mode *mode = get_tarval_mode(tv);
154 if (mode_is_reference(mode)) {
155 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
156 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
157 tv = tarval_convert_to(tv, mode_Iu);
159 value = get_tarval_long(tv);
160 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
164 * Create an And that will zero out upper bits.
166 * @param dbgi debug info
167 * @param block the basic block
168 * @param op the original node
169 * param src_bits number of lower bits that will remain
171 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
175 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
176 } else if (src_bits == 16) {
177 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
178 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
181 panic("zero extension only supported for 8 and 16 bits");
186 * Generate code for a sign extension.
188 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
191 int shift_width = 32 - src_bits;
192 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
193 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
197 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
200 int bits = get_mode_size_bits(orig_mode);
204 if (mode_is_signed(orig_mode)) {
205 return gen_sign_extension(dbgi, block, op, bits);
207 return gen_zero_extension(dbgi, block, op, bits);
212 * returns true if it is assured, that the upper bits of a node are "clean"
213 * which means for a 16 or 8 bit value, that the upper bits in the register
214 * are 0 for unsigned and a copy of the last significant bit for signed
217 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
219 (void) transformed_node;
226 * Transforms a Conv node.
228 * @return The created ia32 Conv node
230 static ir_node *gen_Conv(ir_node *node)
232 ir_node *block = be_transform_node(get_nodes_block(node));
233 ir_node *op = get_Conv_op(node);
234 ir_node *new_op = be_transform_node(op);
235 ir_mode *src_mode = get_irn_mode(op);
236 ir_mode *dst_mode = get_irn_mode(node);
237 dbg_info *dbg = get_irn_dbg_info(node);
239 if (src_mode == dst_mode)
242 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
244 if (mode_is_float(src_mode)) {
245 if (mode_is_float(dst_mode)) {
246 /* from float to float */
247 return new_bd_arm_Mvf(dbg, block, new_op, dst_mode);
249 /* from float to int */
253 /* from int to float */
254 if (!mode_is_signed(src_mode)) {
257 return new_bd_arm_FltX(dbg, block, new_op, dst_mode);
260 } else if (USE_VFP(isa)) {
261 panic("VFP not supported yet");
263 panic("Softfloat not supported yet");
265 } else { /* complete in gp registers */
266 int src_bits = get_mode_size_bits(src_mode);
267 int dst_bits = get_mode_size_bits(dst_mode);
271 if (src_bits == dst_bits) {
272 /* kill unnecessary conv */
276 if (src_bits < dst_bits) {
284 if (upper_bits_clean(new_op, min_mode)) {
288 if (mode_is_signed(min_mode)) {
289 return gen_sign_extension(dbg, block, new_op, min_bits);
291 return gen_zero_extension(dbg, block, new_op, min_bits);
301 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
303 unsigned val, low_pos, high_pos;
308 val = get_tarval_long(get_Const_tarval(node));
320 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
322 So we determine the smallest even position with a bit set
323 and the highest even position with no bit set anymore.
324 If the difference between these 2 is <= 8, then we can encode the value
327 low_pos = ntz(val) & ~1u;
328 high_pos = (32-nlz(val)+1) & ~1u;
330 if (high_pos - low_pos <= 8) {
331 res->imm_8 = val >> low_pos;
332 res->rot = 32 - low_pos;
337 res->rot = 34 - high_pos;
338 val = val >> (32-res->rot) | val << (res->rot);
348 static bool is_downconv(const ir_node *node)
356 /* we only want to skip the conv when we're the only user
357 * (not optimal but for now...)
359 if (get_irn_n_edges(node) > 1)
362 src_mode = get_irn_mode(get_Conv_op(node));
363 dest_mode = get_irn_mode(node);
365 mode_needs_gp_reg(src_mode) &&
366 mode_needs_gp_reg(dest_mode) &&
367 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
370 static ir_node *arm_skip_downconv(ir_node *node)
372 while (is_downconv(node))
373 node = get_Conv_op(node);
379 MATCH_COMMUTATIVE = 1 << 0, /**< commutative node */
380 MATCH_REVERSE = 1 << 1, /**< support reverse opcode */
381 MATCH_SIZE_NEUTRAL = 1 << 2,
382 MATCH_SKIP_NOT = 1 << 3, /**< skip Not on ONE input */
384 ENUM_BITSET(match_flags_t)
387 * possible binop constructors.
389 typedef struct arm_binop_factory_t {
390 /** normal reg op reg operation. */
391 ir_node *(*new_binop_reg)(dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
392 /** normal reg op imm operation. */
393 ir_node *(*new_binop_imm)(dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
394 /** barrel shifter reg op (reg shift reg operation. */
395 ir_node *(*new_binop_reg_shift_reg)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *shift, arm_shift_modifier_t shift_modifier);
396 /** barrel shifter reg op (reg shift imm operation. */
397 ir_node *(*new_binop_reg_shift_imm)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, arm_shift_modifier_t shift_modifier, unsigned shift_immediate);
398 } arm_binop_factory_t;
400 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
401 const arm_binop_factory_t *factory)
403 ir_node *block = be_transform_node(get_nodes_block(node));
404 ir_node *op1 = get_binop_left(node);
406 ir_node *op2 = get_binop_right(node);
408 dbg_info *dbgi = get_irn_dbg_info(node);
411 if (flags & MATCH_SKIP_NOT) {
413 op1 = get_Not_op(op1);
414 else if (is_Not(op2))
415 op2 = get_Not_op(op2);
417 panic("cannot execute MATCH_SKIP_NOT");
419 if (flags & MATCH_SIZE_NEUTRAL) {
420 op1 = arm_skip_downconv(op1);
421 op2 = arm_skip_downconv(op2);
423 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
426 if (try_encode_as_immediate(op2, &imm)) {
427 new_op1 = be_transform_node(op1);
428 return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
430 new_op2 = be_transform_node(op2);
431 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && try_encode_as_immediate(op1, &imm)) {
432 if (flags & MATCH_REVERSE)
433 return factory[1].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
435 return factory[0].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
437 new_op1 = be_transform_node(op1);
439 /* check if we can fold in a Mov */
440 if (is_arm_Mov(new_op2)) {
441 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op2);
443 switch (attr->shift_modifier) {
445 case ARM_SHF_ASR_IMM:
446 case ARM_SHF_LSL_IMM:
447 case ARM_SHF_LSR_IMM:
448 case ARM_SHF_ROR_IMM:
449 if (factory->new_binop_reg_shift_imm) {
450 ir_node *mov_op = get_irn_n(new_op2, 0);
451 return factory->new_binop_reg_shift_imm(dbgi, block, new_op1, mov_op,
452 attr->shift_modifier, attr->shift_immediate);
456 case ARM_SHF_ASR_REG:
457 case ARM_SHF_LSL_REG:
458 case ARM_SHF_LSR_REG:
459 case ARM_SHF_ROR_REG:
460 if (factory->new_binop_reg_shift_reg) {
461 ir_node *mov_op = get_irn_n(new_op2, 0);
462 ir_node *mov_sft = get_irn_n(new_op2, 1);
463 return factory->new_binop_reg_shift_reg(dbgi, block, new_op1, mov_op, mov_sft,
464 attr->shift_modifier);
470 case ARM_SHF_INVALID:
471 panic("invalid shift");
474 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && is_arm_Mov(new_op1)) {
475 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op1);
476 int idx = flags & MATCH_REVERSE ? 1 : 0;
478 switch (attr->shift_modifier) {
479 ir_node *mov_op, *mov_sft;
482 case ARM_SHF_ASR_IMM:
483 case ARM_SHF_LSL_IMM:
484 case ARM_SHF_LSR_IMM:
485 case ARM_SHF_ROR_IMM:
486 if (factory[idx].new_binop_reg_shift_imm) {
487 mov_op = get_irn_n(new_op1, 0);
488 return factory[idx].new_binop_reg_shift_imm(dbgi, block, new_op2, mov_op,
489 attr->shift_modifier, attr->shift_immediate);
493 case ARM_SHF_ASR_REG:
494 case ARM_SHF_LSL_REG:
495 case ARM_SHF_LSR_REG:
496 case ARM_SHF_ROR_REG:
497 if (factory[idx].new_binop_reg_shift_reg) {
498 mov_op = get_irn_n(new_op1, 0);
499 mov_sft = get_irn_n(new_op1, 1);
500 return factory[idx].new_binop_reg_shift_reg(dbgi, block, new_op2, mov_op, mov_sft,
501 attr->shift_modifier);
508 case ARM_SHF_INVALID:
509 panic("invalid shift");
512 return factory->new_binop_reg(dbgi, block, new_op1, new_op2);
516 * Creates an ARM Add.
518 * @return the created arm Add node
520 static ir_node *gen_Add(ir_node *node)
522 static const arm_binop_factory_t add_factory = {
525 new_bd_arm_Add_reg_shift_reg,
526 new_bd_arm_Add_reg_shift_imm
529 ir_mode *mode = get_irn_mode(node);
531 if (mode_is_float(mode)) {
532 ir_node *block = be_transform_node(get_nodes_block(node));
533 ir_node *op1 = get_Add_left(node);
534 ir_node *op2 = get_Add_right(node);
535 dbg_info *dbgi = get_irn_dbg_info(node);
536 ir_node *new_op1 = be_transform_node(op1);
537 ir_node *new_op2 = be_transform_node(op2);
539 return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
540 } else if (USE_VFP(isa)) {
541 panic("VFP not supported yet");
543 panic("Softfloat not supported yet");
548 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
550 new_op2 = get_irn_n(new_op1, 1);
551 new_op1 = get_irn_n(new_op1, 0);
553 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
555 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
557 new_op1 = get_irn_n(new_op2, 0);
558 new_op2 = get_irn_n(new_op2, 1);
560 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
564 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &add_factory);
569 * Creates an ARM Mul.
571 * @return the created arm Mul node
573 static ir_node *gen_Mul(ir_node *node)
575 ir_node *block = be_transform_node(get_nodes_block(node));
576 ir_node *op1 = get_Mul_left(node);
577 ir_node *new_op1 = be_transform_node(op1);
578 ir_node *op2 = get_Mul_right(node);
579 ir_node *new_op2 = be_transform_node(op2);
580 ir_mode *mode = get_irn_mode(node);
581 dbg_info *dbg = get_irn_dbg_info(node);
583 if (mode_is_float(mode)) {
585 return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
586 } else if (USE_VFP(isa)) {
587 panic("VFP not supported yet");
589 panic("Softfloat not supported yet");
592 assert(mode_is_data(mode));
593 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
596 static ir_node *gen_Div(ir_node *node)
598 ir_node *block = be_transform_node(get_nodes_block(node));
599 ir_node *op1 = get_Div_left(node);
600 ir_node *new_op1 = be_transform_node(op1);
601 ir_node *op2 = get_Div_right(node);
602 ir_node *new_op2 = be_transform_node(op2);
603 ir_mode *mode = get_Div_resmode(node);
604 dbg_info *dbg = get_irn_dbg_info(node);
606 /* integer division should be replaced by builtin call */
607 assert(mode_is_float(mode));
610 return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
611 } else if (USE_VFP(isa)) {
612 panic("VFP not supported yet");
614 panic("Softfloat not supported yet");
618 static ir_node *gen_And(ir_node *node)
620 static const arm_binop_factory_t and_factory = {
623 new_bd_arm_And_reg_shift_reg,
624 new_bd_arm_And_reg_shift_imm
626 static const arm_binop_factory_t bic_factory = {
629 new_bd_arm_Bic_reg_shift_reg,
630 new_bd_arm_Bic_reg_shift_imm
633 /* check for and not */
634 ir_node *left = get_And_left(node);
635 ir_node *right = get_And_right(node);
637 if (is_Not(left) || is_Not(right)) {
638 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL | MATCH_SKIP_NOT,
642 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &and_factory);
645 static ir_node *gen_Or(ir_node *node)
647 static const arm_binop_factory_t or_factory = {
650 new_bd_arm_Or_reg_shift_reg,
651 new_bd_arm_Or_reg_shift_imm
654 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &or_factory);
657 static ir_node *gen_Eor(ir_node *node)
659 static const arm_binop_factory_t eor_factory = {
662 new_bd_arm_Eor_reg_shift_reg,
663 new_bd_arm_Eor_reg_shift_imm
666 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &eor_factory);
669 static ir_node *gen_Sub(ir_node *node)
671 static const arm_binop_factory_t sub_rsb_factory[2] = {
675 new_bd_arm_Sub_reg_shift_reg,
676 new_bd_arm_Sub_reg_shift_imm
681 new_bd_arm_Rsb_reg_shift_reg,
682 new_bd_arm_Rsb_reg_shift_imm
686 ir_node *block = be_transform_node(get_nodes_block(node));
687 ir_node *op1 = get_Sub_left(node);
688 ir_node *new_op1 = be_transform_node(op1);
689 ir_node *op2 = get_Sub_right(node);
690 ir_node *new_op2 = be_transform_node(op2);
691 ir_mode *mode = get_irn_mode(node);
692 dbg_info *dbgi = get_irn_dbg_info(node);
694 if (mode_is_float(mode)) {
696 return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
697 } else if (USE_VFP(isa)) {
698 panic("VFP not supported yet");
700 panic("Softfloat not supported yet");
703 return gen_int_binop(node, MATCH_SIZE_NEUTRAL | MATCH_REVERSE, sub_rsb_factory);
708 * Checks if a given value can be used as an immediate for the given
711 static bool can_use_shift_constant(unsigned int val,
712 arm_shift_modifier_t modifier)
716 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
722 * generate an ARM shift instruction.
724 * @param node the node
725 * @param flags matching flags
726 * @param shift_modifier initial encoding of the desired shift operation
728 static ir_node *make_shift(ir_node *node, match_flags_t flags,
729 arm_shift_modifier_t shift_modifier)
731 ir_node *block = be_transform_node(get_nodes_block(node));
732 ir_node *op1 = get_binop_left(node);
733 ir_node *op2 = get_binop_right(node);
734 dbg_info *dbgi = get_irn_dbg_info(node);
735 ir_mode *mode = get_irn_mode(node);
739 if (get_mode_modulo_shift(mode) != 32)
740 panic("modulo shift!=32 not supported by arm backend");
742 if (flags & MATCH_SIZE_NEUTRAL) {
743 op1 = arm_skip_downconv(op1);
744 op2 = arm_skip_downconv(op2);
747 new_op1 = be_transform_node(op1);
749 ir_tarval *tv = get_Const_tarval(op2);
750 unsigned int val = get_tarval_long(tv);
751 assert(tarval_is_long(tv));
752 if (can_use_shift_constant(val, shift_modifier)) {
753 switch (shift_modifier) {
754 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
755 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
756 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
757 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
758 default: panic("unexpected shift modifier");
760 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
761 shift_modifier, val);
765 new_op2 = be_transform_node(op2);
766 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
770 static ir_node *gen_Shl(ir_node *node)
772 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
775 static ir_node *gen_Shr(ir_node *node)
777 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
780 static ir_node *gen_Shrs(ir_node *node)
782 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
785 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
787 ir_node *block = be_transform_node(get_nodes_block(node));
788 ir_node *new_op1 = be_transform_node(op1);
789 dbg_info *dbgi = get_irn_dbg_info(node);
790 ir_node *new_op2 = be_transform_node(op2);
792 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
796 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
798 ir_node *block = be_transform_node(get_nodes_block(node));
799 ir_node *new_op1 = be_transform_node(op1);
800 dbg_info *dbgi = get_irn_dbg_info(node);
801 ir_node *new_op2 = be_transform_node(op2);
803 /* Note: there is no Rol on arm, we have to use Ror */
804 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
805 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
809 static ir_node *gen_Rotl(ir_node *node)
811 ir_node *rotate = NULL;
812 ir_node *op1 = get_Rotl_left(node);
813 ir_node *op2 = get_Rotl_right(node);
815 /* Firm has only RotL, so we are looking for a right (op2)
816 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
817 that means we can create a RotR. */
820 ir_node *right = get_Add_right(op2);
821 if (is_Const(right)) {
822 ir_tarval *tv = get_Const_tarval(right);
823 ir_mode *mode = get_irn_mode(node);
824 long bits = get_mode_size_bits(mode);
825 ir_node *left = get_Add_left(op2);
827 if (is_Minus(left) &&
828 tarval_is_long(tv) &&
829 get_tarval_long(tv) == bits &&
831 rotate = gen_Ror(node, op1, get_Minus_op(left));
833 } else if (is_Sub(op2)) {
834 ir_node *left = get_Sub_left(op2);
835 if (is_Const(left)) {
836 ir_tarval *tv = get_Const_tarval(left);
837 ir_mode *mode = get_irn_mode(node);
838 long bits = get_mode_size_bits(mode);
839 ir_node *right = get_Sub_right(op2);
841 if (tarval_is_long(tv) &&
842 get_tarval_long(tv) == bits &&
844 rotate = gen_Ror(node, op1, right);
846 } else if (is_Const(op2)) {
847 ir_tarval *tv = get_Const_tarval(op2);
848 ir_mode *mode = get_irn_mode(node);
849 long bits = get_mode_size_bits(mode);
851 if (tarval_is_long(tv) && bits == 32) {
852 ir_node *block = be_transform_node(get_nodes_block(node));
853 ir_node *new_op1 = be_transform_node(op1);
854 dbg_info *dbgi = get_irn_dbg_info(node);
856 bits = (bits - get_tarval_long(tv)) & 31;
857 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
861 if (rotate == NULL) {
862 rotate = gen_Rol(node, op1, op2);
868 static ir_node *gen_Not(ir_node *node)
870 ir_node *block = be_transform_node(get_nodes_block(node));
871 ir_node *op = get_Not_op(node);
872 ir_node *new_op = be_transform_node(op);
873 dbg_info *dbgi = get_irn_dbg_info(node);
875 /* check if we can fold in a Mov */
876 if (is_arm_Mov(new_op)) {
877 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op);
879 switch (attr->shift_modifier) {
880 ir_node *mov_op, *mov_sft;
883 case ARM_SHF_ASR_IMM:
884 case ARM_SHF_LSL_IMM:
885 case ARM_SHF_LSR_IMM:
886 case ARM_SHF_ROR_IMM:
887 mov_op = get_irn_n(new_op, 0);
888 return new_bd_arm_Mvn_reg_shift_imm(dbgi, block, mov_op,
889 attr->shift_modifier, attr->shift_immediate);
891 case ARM_SHF_ASR_REG:
892 case ARM_SHF_LSL_REG:
893 case ARM_SHF_LSR_REG:
894 case ARM_SHF_ROR_REG:
895 mov_op = get_irn_n(new_op, 0);
896 mov_sft = get_irn_n(new_op, 1);
897 return new_bd_arm_Mvn_reg_shift_reg(dbgi, block, mov_op, mov_sft,
898 attr->shift_modifier);
903 case ARM_SHF_INVALID:
904 panic("invalid shift");
908 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
911 static ir_node *gen_Minus(ir_node *node)
913 ir_node *block = be_transform_node(get_nodes_block(node));
914 ir_node *op = get_Minus_op(node);
915 ir_node *new_op = be_transform_node(op);
916 dbg_info *dbgi = get_irn_dbg_info(node);
917 ir_mode *mode = get_irn_mode(node);
919 if (mode_is_float(mode)) {
921 return new_bd_arm_Mvf(dbgi, block, op, mode);
922 } else if (USE_VFP(isa)) {
923 panic("VFP not supported yet");
925 panic("Softfloat not supported yet");
928 assert(mode_is_data(mode));
929 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
932 static ir_node *gen_Load(ir_node *node)
934 ir_node *block = be_transform_node(get_nodes_block(node));
935 ir_node *ptr = get_Load_ptr(node);
936 ir_node *new_ptr = be_transform_node(ptr);
937 ir_node *mem = get_Load_mem(node);
938 ir_node *new_mem = be_transform_node(mem);
939 ir_mode *mode = get_Load_mode(node);
940 dbg_info *dbgi = get_irn_dbg_info(node);
941 ir_node *new_load = NULL;
943 if (get_Load_unaligned(node) == align_non_aligned)
944 panic("arm: unaligned Loads not supported yet");
946 if (mode_is_float(mode)) {
948 new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
950 } else if (USE_VFP(isa)) {
951 panic("VFP not supported yet");
953 panic("Softfloat not supported yet");
956 assert(mode_is_data(mode) && "unsupported mode for Load");
958 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
960 set_irn_pinned(new_load, get_irn_pinned(node));
962 /* check for special case: the loaded value might not be used */
963 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
964 /* add a result proj and a Keep to produce a pseudo use */
965 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
966 be_new_Keep(block, 1, &proj);
972 static ir_node *gen_Store(ir_node *node)
974 ir_node *block = be_transform_node(get_nodes_block(node));
975 ir_node *ptr = get_Store_ptr(node);
976 ir_node *new_ptr = be_transform_node(ptr);
977 ir_node *mem = get_Store_mem(node);
978 ir_node *new_mem = be_transform_node(mem);
979 ir_node *val = get_Store_value(node);
980 ir_node *new_val = be_transform_node(val);
981 ir_mode *mode = get_irn_mode(val);
982 dbg_info *dbgi = get_irn_dbg_info(node);
983 ir_node *new_store = NULL;
985 if (get_Store_unaligned(node) == align_non_aligned)
986 panic("arm: unaligned Stores not supported yet");
988 if (mode_is_float(mode)) {
990 new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
991 new_mem, mode, NULL, 0, 0, false);
992 } else if (USE_VFP(isa)) {
993 panic("VFP not supported yet");
995 panic("Softfloat not supported yet");
998 assert(mode_is_data(mode) && "unsupported mode for Store");
999 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
1002 set_irn_pinned(new_store, get_irn_pinned(node));
1006 static ir_node *gen_Jmp(ir_node *node)
1008 ir_node *block = get_nodes_block(node);
1009 ir_node *new_block = be_transform_node(block);
1010 dbg_info *dbgi = get_irn_dbg_info(node);
1012 return new_bd_arm_Jmp(dbgi, new_block);
1015 static ir_node *gen_Switch(ir_node *node)
1017 ir_graph *irg = get_irn_irg(node);
1018 ir_node *block = be_transform_node(get_nodes_block(node));
1019 ir_node *selector = get_Switch_selector(node);
1020 dbg_info *dbgi = get_irn_dbg_info(node);
1021 ir_node *new_op = be_transform_node(selector);
1022 ir_mode *mode = get_irn_mode(selector);
1023 const ir_switch_table *table = get_Switch_table(node);
1024 unsigned n_outs = get_Switch_n_outs(node);
1026 table = ir_switch_table_duplicate(irg, table);
1028 /* switch with smaller modes not implemented yet */
1029 assert(get_mode_size_bits(mode) == 32);
1031 return new_bd_arm_SwitchJmp(dbgi, block, new_op, n_outs, table);
1034 static ir_node *gen_Cmp(ir_node *node)
1036 ir_node *block = be_transform_node(get_nodes_block(node));
1037 ir_node *op1 = get_Cmp_left(node);
1038 ir_node *op2 = get_Cmp_right(node);
1039 ir_mode *cmp_mode = get_irn_mode(op1);
1040 dbg_info *dbgi = get_irn_dbg_info(node);
1045 if (mode_is_float(cmp_mode)) {
1046 /* TODO: this is broken... */
1047 new_op1 = be_transform_node(op1);
1048 new_op2 = be_transform_node(op2);
1050 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
1053 assert(get_irn_mode(op2) == cmp_mode);
1054 is_unsigned = !mode_is_signed(cmp_mode);
1056 /* integer compare, TODO: use shifter_op in all its combinations */
1057 new_op1 = be_transform_node(op1);
1058 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
1059 new_op2 = be_transform_node(op2);
1060 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
1061 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
1065 static ir_node *gen_Cond(ir_node *node)
1067 ir_node *selector = get_Cond_selector(node);
1068 ir_relation relation;
1073 assert(is_Cmp(selector));
1075 block = be_transform_node(get_nodes_block(node));
1076 dbgi = get_irn_dbg_info(node);
1077 flag_node = be_transform_node(selector);
1078 relation = get_Cmp_relation(selector);
1080 return new_bd_arm_B(dbgi, block, flag_node, relation);
1086 FPA_IMM_MAX = FPA_IMM_DOUBLE
1089 static ir_tarval *fpa_imm[FPA_IMM_MAX + 1][fpa_max];
1093 * Check, if a floating point tarval is an fpa immediate, i.e.
1094 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
1096 static int is_fpa_immediate(tarval *tv)
1098 ir_mode *mode = get_tarval_mode(tv);
1101 switch (get_mode_size_bits(mode)) {
1110 if (tarval_is_negative(tv)) {
1111 tv = tarval_neg(tv);
1115 for (j = 0; j < fpa_max; ++j) {
1116 if (tv == fpa_imm[i][j])
1123 static ir_node *gen_Const(ir_node *node)
1125 ir_node *block = be_transform_node(get_nodes_block(node));
1126 ir_mode *mode = get_irn_mode(node);
1127 dbg_info *dbg = get_irn_dbg_info(node);
1129 if (mode_is_float(mode)) {
1131 ir_tarval *tv = get_Const_tarval(node);
1132 node = new_bd_arm_fConst(dbg, block, tv);
1134 } else if (USE_VFP(isa)) {
1135 panic("VFP not supported yet");
1137 panic("Softfloat not supported yet");
1140 return create_const_graph(node, block);
1143 static ir_node *gen_SymConst(ir_node *node)
1145 ir_node *block = be_transform_node(get_nodes_block(node));
1146 ir_entity *entity = get_SymConst_entity(node);
1147 dbg_info *dbgi = get_irn_dbg_info(node);
1150 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
1154 static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0,
1157 /* the good way to do this would be to use the stm (store multiple)
1158 * instructions, since our input is nearly always 2 consecutive 32bit
1160 ir_graph *irg = current_ir_graph;
1161 ir_node *stack = get_irg_frame(irg);
1162 ir_node *nomem = get_irg_no_mem(irg);
1163 ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp,
1165 ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp,
1167 ir_node *in[2] = { str0, str1 };
1168 ir_node *sync = new_r_Sync(block, 2, in);
1170 set_irn_pinned(str0, op_pin_state_floats);
1171 set_irn_pinned(str1, op_pin_state_floats);
1173 ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true);
1174 set_irn_pinned(ldf, op_pin_state_floats);
1176 return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1179 static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node)
1181 ir_graph *irg = current_ir_graph;
1182 ir_node *stack = get_irg_frame(irg);
1183 ir_node *nomem = get_irg_no_mem(irg);
1184 ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp,
1187 set_irn_pinned(str, op_pin_state_floats);
1189 ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true);
1190 set_irn_pinned(ldf, op_pin_state_floats);
1192 return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1195 static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node)
1197 ir_graph *irg = current_ir_graph;
1198 ir_node *stack = get_irg_frame(irg);
1199 ir_node *nomem = get_irg_no_mem(irg);
1200 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F,
1203 set_irn_pinned(stf, op_pin_state_floats);
1205 ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1206 set_irn_pinned(ldr, op_pin_state_floats);
1208 return new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1211 static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node,
1212 ir_node **out_value0, ir_node **out_value1)
1214 ir_graph *irg = current_ir_graph;
1215 ir_node *stack = get_irg_frame(irg);
1216 ir_node *nomem = get_irg_no_mem(irg);
1217 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D,
1219 ir_node *ldr0, *ldr1;
1220 set_irn_pinned(stf, op_pin_state_floats);
1222 ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1223 set_irn_pinned(ldr0, op_pin_state_floats);
1224 ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true);
1225 set_irn_pinned(ldr1, op_pin_state_floats);
1227 *out_value0 = new_r_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
1228 *out_value1 = new_r_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
1231 static ir_node *gen_CopyB(ir_node *node)
1233 ir_node *block = be_transform_node(get_nodes_block(node));
1234 ir_node *src = get_CopyB_src(node);
1235 ir_node *new_src = be_transform_node(src);
1236 ir_node *dst = get_CopyB_dst(node);
1237 ir_node *new_dst = be_transform_node(dst);
1238 ir_node *mem = get_CopyB_mem(node);
1239 ir_node *new_mem = be_transform_node(mem);
1240 dbg_info *dbg = get_irn_dbg_info(node);
1241 int size = get_type_size_bytes(get_CopyB_type(node));
1245 src_copy = be_new_Copy(block, new_src);
1246 dst_copy = be_new_Copy(block, new_dst);
1248 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1249 new_bd_arm_EmptyReg(dbg, block),
1250 new_bd_arm_EmptyReg(dbg, block),
1251 new_bd_arm_EmptyReg(dbg, block),
1256 * Transform builtin clz.
1258 static ir_node *gen_clz(ir_node *node)
1260 ir_node *block = be_transform_node(get_nodes_block(node));
1261 dbg_info *dbg = get_irn_dbg_info(node);
1262 ir_node *op = get_irn_n(node, 1);
1263 ir_node *new_op = be_transform_node(op);
1265 /* TODO armv5 instruction, otherwise create a call */
1266 return new_bd_arm_Clz(dbg, block, new_op);
1270 * Transform Builtin node.
1272 static ir_node *gen_Builtin(ir_node *node)
1274 ir_builtin_kind kind = get_Builtin_kind(node);
1278 case ir_bk_debugbreak:
1279 case ir_bk_return_address:
1280 case ir_bk_frame_address:
1281 case ir_bk_prefetch:
1285 return gen_clz(node);
1288 case ir_bk_popcount:
1292 case ir_bk_inner_trampoline:
1295 panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
1299 * Transform Proj(Builtin) node.
1301 static ir_node *gen_Proj_Builtin(ir_node *proj)
1303 ir_node *node = get_Proj_pred(proj);
1304 ir_node *new_node = be_transform_node(node);
1305 ir_builtin_kind kind = get_Builtin_kind(node);
1308 case ir_bk_return_address:
1309 case ir_bk_frame_address:
1314 case ir_bk_popcount:
1316 assert(get_Proj_proj(proj) == pn_Builtin_max+1);
1319 case ir_bk_debugbreak:
1320 case ir_bk_prefetch:
1322 assert(get_Proj_proj(proj) == pn_Builtin_M);
1325 case ir_bk_inner_trampoline:
1328 panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
1331 static ir_node *gen_Proj_Load(ir_node *node)
1333 ir_node *load = get_Proj_pred(node);
1334 ir_node *new_load = be_transform_node(load);
1335 dbg_info *dbgi = get_irn_dbg_info(node);
1336 long proj = get_Proj_proj(node);
1338 /* renumber the proj */
1339 switch (get_arm_irn_opcode(new_load)) {
1341 /* handle all gp loads equal: they have the same proj numbers. */
1342 if (proj == pn_Load_res) {
1343 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1344 } else if (proj == pn_Load_M) {
1345 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1349 if (proj == pn_Load_res) {
1350 ir_mode *mode = get_Load_mode(load);
1351 return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res);
1352 } else if (proj == pn_Load_M) {
1353 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M);
1359 panic("Unsupported Proj from Load");
1362 static ir_node *gen_Proj_CopyB(ir_node *node)
1364 ir_node *pred = get_Proj_pred(node);
1365 ir_node *new_pred = be_transform_node(pred);
1366 dbg_info *dbgi = get_irn_dbg_info(node);
1367 long proj = get_Proj_proj(node);
1371 if (is_arm_CopyB(new_pred)) {
1372 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1378 panic("Unsupported Proj from CopyB");
1381 static ir_node *gen_Proj_Div(ir_node *node)
1383 ir_node *pred = get_Proj_pred(node);
1384 ir_node *new_pred = be_transform_node(pred);
1385 dbg_info *dbgi = get_irn_dbg_info(node);
1386 ir_mode *mode = get_irn_mode(node);
1387 long proj = get_Proj_proj(node);
1391 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
1393 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
1397 panic("Unsupported Proj from Div");
1401 * Transform the Projs from a Cmp.
1403 static ir_node *gen_Proj_Cmp(ir_node *node)
1406 /* we should only be here in case of a Mux node */
1410 static ir_node *gen_Proj_Start(ir_node *node)
1412 ir_node *block = get_nodes_block(node);
1413 ir_node *new_block = be_transform_node(block);
1414 long proj = get_Proj_proj(node);
1416 switch ((pn_Start) proj) {
1417 case pn_Start_X_initial_exec:
1418 /* we exchange the ProjX with a jump */
1419 return new_bd_arm_Jmp(NULL, new_block);
1422 return be_prolog_get_memory(abihelper);
1424 case pn_Start_T_args:
1425 return new_r_Bad(get_irn_irg(block), mode_T);
1427 case pn_Start_P_frame_base:
1428 return be_prolog_get_reg_value(abihelper, sp_reg);
1430 panic("unexpected start proj: %ld\n", proj);
1433 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1435 long pn = get_Proj_proj(node);
1436 ir_node *block = get_nodes_block(node);
1437 ir_node *new_block = be_transform_node(block);
1438 ir_entity *entity = get_irg_entity(current_ir_graph);
1439 ir_type *method_type = get_entity_type(entity);
1440 ir_type *param_type = get_method_param_type(method_type, pn);
1441 const reg_or_stackslot_t *param;
1443 /* Proj->Proj->Start must be a method argument */
1444 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1446 param = &cconv->parameters[pn];
1448 if (param->reg0 != NULL) {
1449 /* argument transmitted in register */
1450 ir_mode *mode = get_type_mode(param_type);
1451 ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0);
1453 if (mode_is_float(mode)) {
1454 ir_node *value1 = NULL;
1456 if (param->reg1 != NULL) {
1457 value1 = be_prolog_get_reg_value(abihelper, param->reg1);
1458 } else if (param->entity != NULL) {
1459 ir_graph *irg = get_irn_irg(node);
1460 ir_node *fp = get_irg_frame(irg);
1461 ir_node *mem = be_prolog_get_memory(abihelper);
1462 ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem,
1463 mode_gp, param->entity,
1465 value1 = new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1468 /* convert integer value to float */
1469 if (value1 == NULL) {
1470 value = int_to_float(NULL, new_block, value);
1472 value = ints_to_double(NULL, new_block, value, value1);
1477 /* argument transmitted on stack */
1478 ir_graph *irg = get_irn_irg(node);
1479 ir_node *fp = get_irg_frame(irg);
1480 ir_node *mem = be_prolog_get_memory(abihelper);
1481 ir_mode *mode = get_type_mode(param->type);
1485 if (mode_is_float(mode)) {
1486 load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode,
1487 param->entity, 0, 0, true);
1488 value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res);
1490 load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1491 param->entity, 0, 0, true);
1492 value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1494 set_irn_pinned(load, op_pin_state_floats);
1501 * Finds number of output value of a mode_T node which is constrained to
1502 * a single specific register.
1504 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1506 int n_outs = arch_get_irn_n_outs(node);
1509 for (o = 0; o < n_outs; ++o) {
1510 const arch_register_req_t *req = arch_get_irn_register_req_out(node, o);
1511 if (req == reg->single_req)
1517 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1519 long pn = get_Proj_proj(node);
1520 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1521 ir_node *new_call = be_transform_node(call);
1522 ir_type *function_type = get_Call_type(call);
1523 calling_convention_t *cconv
1524 = arm_decide_calling_convention(NULL, function_type);
1525 const reg_or_stackslot_t *res = &cconv->results[pn];
1529 /* TODO 64bit modes */
1530 assert(res->reg0 != NULL && res->reg1 == NULL);
1531 regn = find_out_for_reg(new_call, res->reg0);
1533 panic("Internal error in calling convention for return %+F", node);
1535 mode = res->reg0->reg_class->mode;
1537 arm_free_calling_convention(cconv);
1539 return new_r_Proj(new_call, mode, regn);
1542 static ir_node *gen_Proj_Call(ir_node *node)
1544 long pn = get_Proj_proj(node);
1545 ir_node *call = get_Proj_pred(node);
1546 ir_node *new_call = be_transform_node(call);
1548 switch ((pn_Call) pn) {
1550 return new_r_Proj(new_call, mode_M, 0);
1551 case pn_Call_X_regular:
1552 case pn_Call_X_except:
1553 case pn_Call_T_result:
1556 panic("Unexpected Call proj %ld\n", pn);
1560 * Transform a Proj node.
1562 static ir_node *gen_Proj(ir_node *node)
1564 ir_node *pred = get_Proj_pred(node);
1565 long proj = get_Proj_proj(node);
1567 switch (get_irn_opcode(pred)) {
1569 if (proj == pn_Store_M) {
1570 return be_transform_node(pred);
1572 panic("Unsupported Proj from Store");
1575 return gen_Proj_Load(node);
1577 return gen_Proj_Call(node);
1579 return gen_Proj_CopyB(node);
1581 return gen_Proj_Div(node);
1583 return gen_Proj_Cmp(node);
1585 return gen_Proj_Start(node);
1589 return be_duplicate_node(node);
1591 ir_node *pred_pred = get_Proj_pred(pred);
1592 if (is_Call(pred_pred)) {
1593 return gen_Proj_Proj_Call(node);
1594 } else if (is_Start(pred_pred)) {
1595 return gen_Proj_Proj_Start(node);
1600 return gen_Proj_Builtin(node);
1602 panic("code selection didn't expect Proj after %+F\n", pred);
1606 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1608 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
1609 create_const_node_func func,
1610 const arch_register_t* reg)
1612 ir_node *block, *res;
1617 block = get_irg_start_block(irg);
1618 res = func(NULL, block);
1619 arch_set_irn_register(res, reg);
1624 static ir_node *gen_Unknown(ir_node *node)
1626 ir_node *block = get_nodes_block(node);
1627 ir_node *new_block = be_transform_node(block);
1628 dbg_info *dbgi = get_irn_dbg_info(node);
1630 /* just produce a 0 */
1631 ir_mode *mode = get_irn_mode(node);
1632 if (mode_is_float(mode)) {
1633 ir_tarval *tv = get_mode_null(mode);
1634 ir_node *fconst = new_bd_arm_fConst(dbgi, new_block, tv);
1636 } else if (mode_needs_gp_reg(mode)) {
1637 return create_const_graph_value(dbgi, new_block, 0);
1640 panic("Unexpected Unknown mode");
1644 * Produces the type which sits between the stack args and the locals on the
1645 * stack. It will contain the return address and space to store the old base
1647 * @return The Firm type modeling the ABI between type.
1649 static ir_type *arm_get_between_type(void)
1651 static ir_type *between_type = NULL;
1653 if (between_type == NULL) {
1654 between_type = new_type_class(new_id_from_str("arm_between_type"));
1655 set_type_size_bytes(between_type, 0);
1658 return between_type;
1661 static void create_stacklayout(ir_graph *irg)
1663 ir_entity *entity = get_irg_entity(irg);
1664 ir_type *function_type = get_entity_type(entity);
1665 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1670 /* calling conventions must be decided by now */
1671 assert(cconv != NULL);
1673 /* construct argument type */
1674 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1675 n_params = get_method_n_params(function_type);
1676 for (p = 0; p < n_params; ++p) {
1677 reg_or_stackslot_t *param = &cconv->parameters[p];
1681 if (param->type == NULL)
1684 snprintf(buf, sizeof(buf), "param_%d", p);
1685 id = new_id_from_str(buf);
1686 param->entity = new_entity(arg_type, id, param->type);
1687 set_entity_offset(param->entity, param->offset);
1690 /* TODO: what about external functions? we don't know most of the stack
1691 * layout for them. And probably don't need all of this... */
1692 memset(layout, 0, sizeof(*layout));
1694 layout->frame_type = get_irg_frame_type(irg);
1695 layout->between_type = arm_get_between_type();
1696 layout->arg_type = arg_type;
1697 layout->param_map = NULL; /* TODO */
1698 layout->initial_offset = 0;
1699 layout->initial_bias = 0;
1700 layout->sp_relative = true;
1702 assert(N_FRAME_TYPES == 3);
1703 layout->order[0] = layout->frame_type;
1704 layout->order[1] = layout->between_type;
1705 layout->order[2] = layout->arg_type;
1709 * transform the start node to the prolog code
1711 static ir_node *gen_Start(ir_node *node)
1713 ir_graph *irg = get_irn_irg(node);
1714 ir_entity *entity = get_irg_entity(irg);
1715 ir_type *function_type = get_entity_type(entity);
1716 ir_node *block = get_nodes_block(node);
1717 ir_node *new_block = be_transform_node(block);
1718 dbg_info *dbgi = get_irn_dbg_info(node);
1722 /* stackpointer is important at function prolog */
1723 be_prolog_add_reg(abihelper, sp_reg,
1724 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1725 /* function parameters in registers */
1726 for (i = 0; i < get_method_n_params(function_type); ++i) {
1727 const reg_or_stackslot_t *param = &cconv->parameters[i];
1728 if (param->reg0 != NULL)
1729 be_prolog_add_reg(abihelper, param->reg0, arch_register_req_type_none);
1730 if (param->reg1 != NULL)
1731 be_prolog_add_reg(abihelper, param->reg1, arch_register_req_type_none);
1733 /* announce that we need the values of the callee save regs */
1734 for (i = 0; i < (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
1735 be_prolog_add_reg(abihelper, callee_saves[i], arch_register_req_type_none);
1738 start = be_prolog_create_start(abihelper, dbgi, new_block);
1742 static ir_node *get_stack_pointer_for(ir_node *node)
1744 /* get predecessor in stack_order list */
1745 ir_node *stack_pred = be_get_stack_pred(stackorder, node);
1748 if (stack_pred == NULL) {
1749 /* first stack user in the current block. We can simply use the
1750 * initial sp_proj for it */
1751 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1755 be_transform_node(stack_pred);
1756 stack = (ir_node*)pmap_get(node_to_stack, stack_pred);
1757 if (stack == NULL) {
1758 return get_stack_pointer_for(stack_pred);
1765 * transform a Return node into epilogue code + return statement
1767 static ir_node *gen_Return(ir_node *node)
1769 ir_node *block = get_nodes_block(node);
1770 ir_node *new_block = be_transform_node(block);
1771 dbg_info *dbgi = get_irn_dbg_info(node);
1772 ir_node *mem = get_Return_mem(node);
1773 ir_node *new_mem = be_transform_node(mem);
1774 int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
1775 ir_node *sp_proj = get_stack_pointer_for(node);
1776 int n_res = get_Return_n_ress(node);
1780 be_epilog_begin(abihelper);
1781 be_epilog_set_memory(abihelper, new_mem);
1782 /* connect stack pointer with initial stack pointer. fix_stack phase
1783 will later serialize all stack pointer adjusting nodes */
1784 be_epilog_add_reg(abihelper, sp_reg,
1785 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1789 for (i = 0; i < n_res; ++i) {
1790 ir_node *res_value = get_Return_res(node, i);
1791 ir_node *new_res_value = be_transform_node(res_value);
1792 const reg_or_stackslot_t *slot = &cconv->results[i];
1793 const arch_register_t *reg = slot->reg0;
1794 assert(slot->reg1 == NULL);
1795 be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, new_res_value);
1798 /* connect callee saves with their values at the function begin */
1799 for (i = 0; i < n_callee_saves; ++i) {
1800 const arch_register_t *reg = callee_saves[i];
1801 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1802 be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, value);
1805 /* epilog code: an incsp */
1806 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1811 static ir_node *gen_Call(ir_node *node)
1813 ir_graph *irg = get_irn_irg(node);
1814 ir_node *callee = get_Call_ptr(node);
1815 ir_node *block = get_nodes_block(node);
1816 ir_node *new_block = be_transform_node(block);
1817 ir_node *mem = get_Call_mem(node);
1818 ir_node *new_mem = be_transform_node(mem);
1819 dbg_info *dbgi = get_irn_dbg_info(node);
1820 ir_type *type = get_Call_type(node);
1821 calling_convention_t *cconv = arm_decide_calling_convention(NULL, type);
1822 size_t n_params = get_Call_n_params(node);
1823 size_t n_param_regs = cconv->n_reg_params;
1824 /* max inputs: memory, callee, register arguments */
1825 int max_inputs = 2 + n_param_regs;
1826 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1827 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1828 struct obstack *obst = be_get_be_obst(irg);
1829 const arch_register_req_t **in_req
1830 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1834 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1835 ir_entity *entity = NULL;
1836 ir_node *incsp = NULL;
1843 assert(n_params == get_method_n_params(type));
1845 /* construct arguments */
1848 in_req[in_arity] = arch_no_register_req;
1852 for (p = 0; p < n_params; ++p) {
1853 ir_node *value = get_Call_param(node, p);
1854 ir_node *new_value = be_transform_node(value);
1855 ir_node *new_value1 = NULL;
1856 const reg_or_stackslot_t *param = &cconv->parameters[p];
1857 ir_type *param_type = get_method_param_type(type, p);
1858 ir_mode *mode = get_type_mode(param_type);
1861 if (mode_is_float(mode) && param->reg0 != NULL) {
1862 unsigned size_bits = get_mode_size_bits(mode);
1863 if (size_bits == 64) {
1864 double_to_ints(dbgi, new_block, new_value, &new_value,
1867 assert(size_bits == 32);
1868 new_value = float_to_int(dbgi, new_block, new_value);
1872 /* put value into registers */
1873 if (param->reg0 != NULL) {
1874 in[in_arity] = new_value;
1875 in_req[in_arity] = param->reg0->single_req;
1877 if (new_value1 == NULL)
1880 if (param->reg1 != NULL) {
1881 assert(new_value1 != NULL);
1882 in[in_arity] = new_value1;
1883 in_req[in_arity] = param->reg1->single_req;
1888 /* we need a store if we're here */
1889 if (new_value1 != NULL) {
1890 new_value = new_value1;
1894 /* create a parameter frame if necessary */
1895 if (incsp == NULL) {
1896 ir_node *new_frame = get_stack_pointer_for(node);
1897 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1898 cconv->param_stack_size, 1);
1900 if (mode_is_float(mode)) {
1901 str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem,
1902 mode, NULL, 0, param->offset, true);
1904 str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem,
1905 mode, NULL, 0, param->offset, true);
1907 sync_ins[sync_arity++] = str;
1909 assert(in_arity <= max_inputs);
1911 /* construct memory input */
1912 if (sync_arity == 0) {
1913 in[mem_pos] = new_mem;
1914 } else if (sync_arity == 1) {
1915 in[mem_pos] = sync_ins[0];
1917 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1920 /* TODO: use a generic symconst matcher here */
1921 if (is_SymConst(callee)) {
1922 entity = get_SymConst_entity(callee);
1924 /* TODO: finish load matcher here */
1927 if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) {
1928 ir_node *load = get_Proj_pred(callee);
1929 ir_node *ptr = get_Load_ptr(load);
1930 ir_node *new_ptr = be_transform_node(ptr);
1931 ir_node *mem = get_Load_mem(load);
1932 ir_node *new_mem = be_transform_node(mem);
1933 ir_mode *mode = get_Load_mode(node);
1937 in[in_arity] = be_transform_node(callee);
1938 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1947 out_arity = 1 + n_caller_saves;
1949 if (entity != NULL) {
1950 /* TODO: use a generic symconst matcher here
1951 * so we can also handle entity+offset, etc. */
1952 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1955 * - use a proper shifter_operand matcher
1956 * - we could also use LinkLdrPC
1958 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1962 if (incsp != NULL) {
1963 /* IncSP to destroy the call stackframe */
1964 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
1966 /* if we are the last IncSP producer in a block then we have to keep
1968 * Note: This here keeps all producers which is more than necessary */
1969 add_irn_dep(incsp, res);
1972 pmap_insert(node_to_stack, node, incsp);
1975 arch_set_irn_register_reqs_in(res, in_req);
1977 /* create output register reqs */
1978 arch_set_irn_register_req_out(res, 0, arch_no_register_req);
1979 for (o = 0; o < n_caller_saves; ++o) {
1980 const arch_register_t *reg = caller_saves[o];
1981 arch_set_irn_register_req_out(res, o+1, reg->single_req);
1984 /* copy pinned attribute */
1985 set_irn_pinned(res, get_irn_pinned(node));
1987 arm_free_calling_convention(cconv);
1991 static ir_node *gen_Sel(ir_node *node)
1993 dbg_info *dbgi = get_irn_dbg_info(node);
1994 ir_node *block = get_nodes_block(node);
1995 ir_node *new_block = be_transform_node(block);
1996 ir_node *ptr = get_Sel_ptr(node);
1997 ir_node *new_ptr = be_transform_node(ptr);
1998 ir_entity *entity = get_Sel_entity(node);
2000 /* must be the frame pointer all other sels must have been lowered
2002 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
2004 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
2008 * Change some phi modes
2010 static ir_node *gen_Phi(ir_node *node)
2012 const arch_register_req_t *req;
2013 ir_node *block = be_transform_node(get_nodes_block(node));
2014 ir_graph *irg = current_ir_graph;
2015 dbg_info *dbgi = get_irn_dbg_info(node);
2016 ir_mode *mode = get_irn_mode(node);
2019 if (mode_needs_gp_reg(mode)) {
2020 /* we shouldn't have any 64bit stuff around anymore */
2021 assert(get_mode_size_bits(mode) <= 32);
2022 /* all integer operations are on 32bit registers now */
2024 req = arm_reg_classes[CLASS_arm_gp].class_req;
2026 req = arch_no_register_req;
2029 /* phi nodes allow loops, so we use the old arguments for now
2030 * and fix this later */
2031 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
2032 get_irn_in(node) + 1);
2033 copy_node_attr(irg, node, phi);
2034 be_duplicate_deps(node, phi);
2036 arch_set_irn_register_req_out(phi, 0, req);
2038 be_enqueue_preds(node);
2045 * Enters all transform functions into the generic pointer
2047 static void arm_register_transformers(void)
2049 be_start_transform_setup();
2051 be_set_transform_function(op_Add, gen_Add);
2052 be_set_transform_function(op_And, gen_And);
2053 be_set_transform_function(op_Call, gen_Call);
2054 be_set_transform_function(op_Cmp, gen_Cmp);
2055 be_set_transform_function(op_Cond, gen_Cond);
2056 be_set_transform_function(op_Const, gen_Const);
2057 be_set_transform_function(op_Conv, gen_Conv);
2058 be_set_transform_function(op_CopyB, gen_CopyB);
2059 be_set_transform_function(op_Div, gen_Div);
2060 be_set_transform_function(op_Eor, gen_Eor);
2061 be_set_transform_function(op_Jmp, gen_Jmp);
2062 be_set_transform_function(op_Load, gen_Load);
2063 be_set_transform_function(op_Minus, gen_Minus);
2064 be_set_transform_function(op_Mul, gen_Mul);
2065 be_set_transform_function(op_Not, gen_Not);
2066 be_set_transform_function(op_Or, gen_Or);
2067 be_set_transform_function(op_Phi, gen_Phi);
2068 be_set_transform_function(op_Proj, gen_Proj);
2069 be_set_transform_function(op_Return, gen_Return);
2070 be_set_transform_function(op_Rotl, gen_Rotl);
2071 be_set_transform_function(op_Sel, gen_Sel);
2072 be_set_transform_function(op_Shl, gen_Shl);
2073 be_set_transform_function(op_Shr, gen_Shr);
2074 be_set_transform_function(op_Shrs, gen_Shrs);
2075 be_set_transform_function(op_Start, gen_Start);
2076 be_set_transform_function(op_Store, gen_Store);
2077 be_set_transform_function(op_Sub, gen_Sub);
2078 be_set_transform_function(op_Switch, gen_Switch);
2079 be_set_transform_function(op_SymConst, gen_SymConst);
2080 be_set_transform_function(op_Unknown, gen_Unknown);
2081 be_set_transform_function(op_Builtin, gen_Builtin);
2085 * Initialize fpa Immediate support.
2087 static void arm_init_fpa_immediate(void)
2089 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
2090 fpa_imm[FPA_IMM_FLOAT][fpa_null] = get_mode_null(mode_F);
2091 fpa_imm[FPA_IMM_FLOAT][fpa_one] = get_mode_one(mode_F);
2092 fpa_imm[FPA_IMM_FLOAT][fpa_two] = new_tarval_from_str("2", 1, mode_F);
2093 fpa_imm[FPA_IMM_FLOAT][fpa_three] = new_tarval_from_str("3", 1, mode_F);
2094 fpa_imm[FPA_IMM_FLOAT][fpa_four] = new_tarval_from_str("4", 1, mode_F);
2095 fpa_imm[FPA_IMM_FLOAT][fpa_five] = new_tarval_from_str("5", 1, mode_F);
2096 fpa_imm[FPA_IMM_FLOAT][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
2097 fpa_imm[FPA_IMM_FLOAT][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
2099 fpa_imm[FPA_IMM_DOUBLE][fpa_null] = get_mode_null(mode_D);
2100 fpa_imm[FPA_IMM_DOUBLE][fpa_one] = get_mode_one(mode_D);
2101 fpa_imm[FPA_IMM_DOUBLE][fpa_two] = new_tarval_from_str("2", 1, mode_D);
2102 fpa_imm[FPA_IMM_DOUBLE][fpa_three] = new_tarval_from_str("3", 1, mode_D);
2103 fpa_imm[FPA_IMM_DOUBLE][fpa_four] = new_tarval_from_str("4", 1, mode_D);
2104 fpa_imm[FPA_IMM_DOUBLE][fpa_five] = new_tarval_from_str("5", 1, mode_D);
2105 fpa_imm[FPA_IMM_DOUBLE][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
2106 fpa_imm[FPA_IMM_DOUBLE][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
2110 * Transform a Firm graph into an ARM graph.
2112 void arm_transform_graph(ir_graph *irg)
2114 static int imm_initialized = 0;
2115 ir_entity *entity = get_irg_entity(irg);
2116 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
2117 ir_type *frame_type;
2122 if (! imm_initialized) {
2123 arm_init_fpa_immediate();
2124 imm_initialized = 1;
2126 arm_register_transformers();
2128 isa = (arm_isa_t*) arch_env;
2130 node_to_stack = pmap_create();
2132 assert(abihelper == NULL);
2133 abihelper = be_abihelper_prepare(irg);
2134 stackorder = be_collect_stacknodes(irg);
2135 assert(cconv == NULL);
2136 cconv = arm_decide_calling_convention(irg, get_entity_type(entity));
2137 create_stacklayout(irg);
2139 be_transform_graph(irg, NULL);
2141 be_abihelper_finish(abihelper);
2143 be_free_stackorder(stackorder);
2146 arm_free_calling_convention(cconv);
2149 frame_type = get_irg_frame_type(irg);
2150 if (get_type_state(frame_type) == layout_undefined) {
2151 default_layout_compound_type(frame_type);
2154 pmap_destroy(node_to_stack);
2155 node_to_stack = NULL;
2157 be_add_missing_keeps(irg);
2160 void arm_init_transform(void)
2162 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");