2 * This file is part of libFirm.
3 * Copyright (C) 2012 University of Karlsruhe.
8 * @brief The codegenerator (transform FIRM into arm FIRM)
9 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
14 #include "irgraph_t.h"
29 #include "betranshlp.h"
30 #include "beabihelper.h"
33 #include "bearch_arm_t.h"
34 #include "arm_nodes_attr.h"
35 #include "arm_transform.h"
36 #include "arm_optimize.h"
37 #include "arm_new_nodes.h"
38 #include "arm_map_regs.h"
39 #include "arm_cconv.h"
41 #include "gen_arm_regalloc_if.h"
45 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
47 static const arch_register_t *sp_reg = &arm_registers[REG_SP];
48 static ir_mode *mode_gp;
49 static ir_mode *mode_fp;
50 static beabi_helper_env_t *abihelper;
51 static be_stackorder_t *stackorder;
52 static calling_convention_t *cconv = NULL;
53 static arm_isa_t *isa;
55 static pmap *node_to_stack;
57 static const arch_register_t *const callee_saves[] = {
58 &arm_registers[REG_R4],
59 &arm_registers[REG_R5],
60 &arm_registers[REG_R6],
61 &arm_registers[REG_R7],
62 &arm_registers[REG_R8],
63 &arm_registers[REG_R9],
64 &arm_registers[REG_R10],
65 &arm_registers[REG_R11],
66 &arm_registers[REG_LR],
69 static const arch_register_t *const caller_saves[] = {
70 &arm_registers[REG_R0],
71 &arm_registers[REG_R1],
72 &arm_registers[REG_R2],
73 &arm_registers[REG_R3],
74 &arm_registers[REG_LR],
76 &arm_registers[REG_F0],
77 &arm_registers[REG_F1],
78 &arm_registers[REG_F2],
79 &arm_registers[REG_F3],
80 &arm_registers[REG_F4],
81 &arm_registers[REG_F5],
82 &arm_registers[REG_F6],
83 &arm_registers[REG_F7],
86 static bool mode_needs_gp_reg(ir_mode *mode)
88 return mode_is_int(mode) || mode_is_reference(mode);
92 * create firm graph for a constant
94 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
101 /* We only have 8 bit immediates. So we possibly have to combine several
102 * operations to construct the desired value.
104 * we can either create the value by adding bits to 0 or by removing bits
105 * from an register with all bits set. Try which alternative needs fewer
107 arm_gen_vals_from_word(value, &v);
108 arm_gen_vals_from_word(~value, &vn);
110 if (vn.ops < v.ops) {
112 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
114 for (cnt = 1; cnt < vn.ops; ++cnt) {
115 result = new_bd_arm_Bic_imm(dbgi, block, result,
116 vn.values[cnt], vn.rors[cnt]);
120 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
122 for (cnt = 1; cnt < v.ops; ++cnt) {
123 result = new_bd_arm_Or_imm(dbgi, block, result,
124 v.values[cnt], v.rors[cnt]);
131 * Create a DAG constructing a given Const.
133 * @param irn a Firm const
135 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
137 ir_tarval *tv = get_Const_tarval(irn);
138 ir_mode *mode = get_tarval_mode(tv);
141 if (mode_is_reference(mode)) {
142 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
143 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
144 tv = tarval_convert_to(tv, mode_Iu);
146 value = get_tarval_long(tv);
147 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
151 * Create an And that will zero out upper bits.
153 * @param dbgi debug info
154 * @param block the basic block
155 * @param op the original node
156 * param src_bits number of lower bits that will remain
158 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
162 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
163 } else if (src_bits == 16) {
164 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
165 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
168 panic("zero extension only supported for 8 and 16 bits");
173 * Generate code for a sign extension.
175 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
178 int shift_width = 32 - src_bits;
179 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
180 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
184 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
187 int bits = get_mode_size_bits(orig_mode);
191 if (mode_is_signed(orig_mode)) {
192 return gen_sign_extension(dbgi, block, op, bits);
194 return gen_zero_extension(dbgi, block, op, bits);
199 * returns true if it is assured, that the upper bits of a node are "clean"
200 * which means for a 16 or 8 bit value, that the upper bits in the register
201 * are 0 for unsigned and a copy of the last significant bit for signed
204 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
206 (void) transformed_node;
213 * Transforms a Conv node.
215 * @return The created ia32 Conv node
217 static ir_node *gen_Conv(ir_node *node)
219 ir_node *block = be_transform_node(get_nodes_block(node));
220 ir_node *op = get_Conv_op(node);
221 ir_node *new_op = be_transform_node(op);
222 ir_mode *src_mode = get_irn_mode(op);
223 ir_mode *dst_mode = get_irn_mode(node);
224 dbg_info *dbg = get_irn_dbg_info(node);
226 if (src_mode == dst_mode)
229 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
231 if (mode_is_float(src_mode)) {
232 if (mode_is_float(dst_mode)) {
233 /* from float to float */
234 return new_bd_arm_Mvf(dbg, block, new_op, dst_mode);
236 /* from float to int */
240 /* from int to float */
241 if (!mode_is_signed(src_mode)) {
244 return new_bd_arm_FltX(dbg, block, new_op, dst_mode);
247 } else if (USE_VFP(isa)) {
248 panic("VFP not supported yet");
250 panic("Softfloat not supported yet");
252 } else { /* complete in gp registers */
253 int src_bits = get_mode_size_bits(src_mode);
254 int dst_bits = get_mode_size_bits(dst_mode);
258 if (src_bits == dst_bits) {
259 /* kill unnecessary conv */
263 if (src_bits < dst_bits) {
271 if (upper_bits_clean(new_op, min_mode)) {
275 if (mode_is_signed(min_mode)) {
276 return gen_sign_extension(dbg, block, new_op, min_bits);
278 return gen_zero_extension(dbg, block, new_op, min_bits);
288 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
290 unsigned val, low_pos, high_pos;
295 val = get_tarval_long(get_Const_tarval(node));
307 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
309 So we determine the smallest even position with a bit set
310 and the highest even position with no bit set anymore.
311 If the difference between these 2 is <= 8, then we can encode the value
314 low_pos = ntz(val) & ~1u;
315 high_pos = (32-nlz(val)+1) & ~1u;
317 if (high_pos - low_pos <= 8) {
318 res->imm_8 = val >> low_pos;
319 res->rot = 32 - low_pos;
324 res->rot = 34 - high_pos;
325 val = val >> (32-res->rot) | val << (res->rot);
335 static bool is_downconv(const ir_node *node)
343 /* we only want to skip the conv when we're the only user
344 * (not optimal but for now...)
346 if (get_irn_n_edges(node) > 1)
349 src_mode = get_irn_mode(get_Conv_op(node));
350 dest_mode = get_irn_mode(node);
352 mode_needs_gp_reg(src_mode) &&
353 mode_needs_gp_reg(dest_mode) &&
354 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
357 static ir_node *arm_skip_downconv(ir_node *node)
359 while (is_downconv(node))
360 node = get_Conv_op(node);
366 MATCH_COMMUTATIVE = 1 << 0, /**< commutative node */
367 MATCH_REVERSE = 1 << 1, /**< support reverse opcode */
368 MATCH_SIZE_NEUTRAL = 1 << 2,
369 MATCH_SKIP_NOT = 1 << 3, /**< skip Not on ONE input */
371 ENUM_BITSET(match_flags_t)
374 * possible binop constructors.
376 typedef struct arm_binop_factory_t {
377 /** normal reg op reg operation. */
378 ir_node *(*new_binop_reg)(dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
379 /** normal reg op imm operation. */
380 ir_node *(*new_binop_imm)(dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
381 /** barrel shifter reg op (reg shift reg operation. */
382 ir_node *(*new_binop_reg_shift_reg)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *shift, arm_shift_modifier_t shift_modifier);
383 /** barrel shifter reg op (reg shift imm operation. */
384 ir_node *(*new_binop_reg_shift_imm)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, arm_shift_modifier_t shift_modifier, unsigned shift_immediate);
385 } arm_binop_factory_t;
387 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
388 const arm_binop_factory_t *factory)
390 ir_node *block = be_transform_node(get_nodes_block(node));
391 ir_node *op1 = get_binop_left(node);
393 ir_node *op2 = get_binop_right(node);
395 dbg_info *dbgi = get_irn_dbg_info(node);
398 if (flags & MATCH_SKIP_NOT) {
400 op1 = get_Not_op(op1);
401 else if (is_Not(op2))
402 op2 = get_Not_op(op2);
404 panic("cannot execute MATCH_SKIP_NOT");
406 if (flags & MATCH_SIZE_NEUTRAL) {
407 op1 = arm_skip_downconv(op1);
408 op2 = arm_skip_downconv(op2);
410 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
413 if (try_encode_as_immediate(op2, &imm)) {
414 new_op1 = be_transform_node(op1);
415 return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
417 new_op2 = be_transform_node(op2);
418 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && try_encode_as_immediate(op1, &imm)) {
419 if (flags & MATCH_REVERSE)
420 return factory[1].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
422 return factory[0].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
424 new_op1 = be_transform_node(op1);
426 /* check if we can fold in a Mov */
427 if (is_arm_Mov(new_op2)) {
428 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op2);
430 switch (attr->shift_modifier) {
432 case ARM_SHF_ASR_IMM:
433 case ARM_SHF_LSL_IMM:
434 case ARM_SHF_LSR_IMM:
435 case ARM_SHF_ROR_IMM:
436 if (factory->new_binop_reg_shift_imm) {
437 ir_node *mov_op = get_irn_n(new_op2, 0);
438 return factory->new_binop_reg_shift_imm(dbgi, block, new_op1, mov_op,
439 attr->shift_modifier, attr->shift_immediate);
443 case ARM_SHF_ASR_REG:
444 case ARM_SHF_LSL_REG:
445 case ARM_SHF_LSR_REG:
446 case ARM_SHF_ROR_REG:
447 if (factory->new_binop_reg_shift_reg) {
448 ir_node *mov_op = get_irn_n(new_op2, 0);
449 ir_node *mov_sft = get_irn_n(new_op2, 1);
450 return factory->new_binop_reg_shift_reg(dbgi, block, new_op1, mov_op, mov_sft,
451 attr->shift_modifier);
457 case ARM_SHF_INVALID:
458 panic("invalid shift");
461 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && is_arm_Mov(new_op1)) {
462 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op1);
463 int idx = flags & MATCH_REVERSE ? 1 : 0;
465 switch (attr->shift_modifier) {
466 ir_node *mov_op, *mov_sft;
469 case ARM_SHF_ASR_IMM:
470 case ARM_SHF_LSL_IMM:
471 case ARM_SHF_LSR_IMM:
472 case ARM_SHF_ROR_IMM:
473 if (factory[idx].new_binop_reg_shift_imm) {
474 mov_op = get_irn_n(new_op1, 0);
475 return factory[idx].new_binop_reg_shift_imm(dbgi, block, new_op2, mov_op,
476 attr->shift_modifier, attr->shift_immediate);
480 case ARM_SHF_ASR_REG:
481 case ARM_SHF_LSL_REG:
482 case ARM_SHF_LSR_REG:
483 case ARM_SHF_ROR_REG:
484 if (factory[idx].new_binop_reg_shift_reg) {
485 mov_op = get_irn_n(new_op1, 0);
486 mov_sft = get_irn_n(new_op1, 1);
487 return factory[idx].new_binop_reg_shift_reg(dbgi, block, new_op2, mov_op, mov_sft,
488 attr->shift_modifier);
495 case ARM_SHF_INVALID:
496 panic("invalid shift");
499 return factory->new_binop_reg(dbgi, block, new_op1, new_op2);
503 * Creates an ARM Add.
505 * @return the created arm Add node
507 static ir_node *gen_Add(ir_node *node)
509 static const arm_binop_factory_t add_factory = {
512 new_bd_arm_Add_reg_shift_reg,
513 new_bd_arm_Add_reg_shift_imm
516 ir_mode *mode = get_irn_mode(node);
518 if (mode_is_float(mode)) {
519 ir_node *block = be_transform_node(get_nodes_block(node));
520 ir_node *op1 = get_Add_left(node);
521 ir_node *op2 = get_Add_right(node);
522 dbg_info *dbgi = get_irn_dbg_info(node);
523 ir_node *new_op1 = be_transform_node(op1);
524 ir_node *new_op2 = be_transform_node(op2);
526 return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
527 } else if (USE_VFP(isa)) {
528 panic("VFP not supported yet");
530 panic("Softfloat not supported yet");
533 /* TODO: check for MLA */
534 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &add_factory);
539 * Creates an ARM Mul.
541 * @return the created arm Mul node
543 static ir_node *gen_Mul(ir_node *node)
545 ir_node *block = be_transform_node(get_nodes_block(node));
546 ir_node *op1 = get_Mul_left(node);
547 ir_node *new_op1 = be_transform_node(op1);
548 ir_node *op2 = get_Mul_right(node);
549 ir_node *new_op2 = be_transform_node(op2);
550 ir_mode *mode = get_irn_mode(node);
551 dbg_info *dbg = get_irn_dbg_info(node);
553 if (mode_is_float(mode)) {
555 return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
556 } else if (USE_VFP(isa)) {
557 panic("VFP not supported yet");
559 panic("Softfloat not supported yet");
562 assert(mode_is_data(mode));
563 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
566 static ir_node *gen_Div(ir_node *node)
568 ir_node *block = be_transform_node(get_nodes_block(node));
569 ir_node *op1 = get_Div_left(node);
570 ir_node *new_op1 = be_transform_node(op1);
571 ir_node *op2 = get_Div_right(node);
572 ir_node *new_op2 = be_transform_node(op2);
573 ir_mode *mode = get_Div_resmode(node);
574 dbg_info *dbg = get_irn_dbg_info(node);
576 /* integer division should be replaced by builtin call */
577 assert(mode_is_float(mode));
580 return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
581 } else if (USE_VFP(isa)) {
582 panic("VFP not supported yet");
584 panic("Softfloat not supported yet");
588 static ir_node *gen_And(ir_node *node)
590 static const arm_binop_factory_t and_factory = {
593 new_bd_arm_And_reg_shift_reg,
594 new_bd_arm_And_reg_shift_imm
596 static const arm_binop_factory_t bic_factory = {
599 new_bd_arm_Bic_reg_shift_reg,
600 new_bd_arm_Bic_reg_shift_imm
603 /* check for and not */
604 ir_node *left = get_And_left(node);
605 ir_node *right = get_And_right(node);
607 if (is_Not(left) || is_Not(right)) {
608 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL | MATCH_SKIP_NOT,
612 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &and_factory);
615 static ir_node *gen_Or(ir_node *node)
617 static const arm_binop_factory_t or_factory = {
620 new_bd_arm_Or_reg_shift_reg,
621 new_bd_arm_Or_reg_shift_imm
624 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &or_factory);
627 static ir_node *gen_Eor(ir_node *node)
629 static const arm_binop_factory_t eor_factory = {
632 new_bd_arm_Eor_reg_shift_reg,
633 new_bd_arm_Eor_reg_shift_imm
636 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &eor_factory);
639 static ir_node *gen_Sub(ir_node *node)
641 static const arm_binop_factory_t sub_rsb_factory[2] = {
645 new_bd_arm_Sub_reg_shift_reg,
646 new_bd_arm_Sub_reg_shift_imm
651 new_bd_arm_Rsb_reg_shift_reg,
652 new_bd_arm_Rsb_reg_shift_imm
656 ir_node *block = be_transform_node(get_nodes_block(node));
657 ir_node *op1 = get_Sub_left(node);
658 ir_node *new_op1 = be_transform_node(op1);
659 ir_node *op2 = get_Sub_right(node);
660 ir_node *new_op2 = be_transform_node(op2);
661 ir_mode *mode = get_irn_mode(node);
662 dbg_info *dbgi = get_irn_dbg_info(node);
664 if (mode_is_float(mode)) {
666 return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
667 } else if (USE_VFP(isa)) {
668 panic("VFP not supported yet");
670 panic("Softfloat not supported yet");
673 return gen_int_binop(node, MATCH_SIZE_NEUTRAL | MATCH_REVERSE, sub_rsb_factory);
678 * Checks if a given value can be used as an immediate for the given
681 static bool can_use_shift_constant(unsigned int val,
682 arm_shift_modifier_t modifier)
686 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
692 * generate an ARM shift instruction.
694 * @param node the node
695 * @param flags matching flags
696 * @param shift_modifier initial encoding of the desired shift operation
698 static ir_node *make_shift(ir_node *node, match_flags_t flags,
699 arm_shift_modifier_t shift_modifier)
701 ir_node *block = be_transform_node(get_nodes_block(node));
702 ir_node *op1 = get_binop_left(node);
703 ir_node *op2 = get_binop_right(node);
704 dbg_info *dbgi = get_irn_dbg_info(node);
705 ir_mode *mode = get_irn_mode(node);
709 if (get_mode_modulo_shift(mode) != 32)
710 panic("modulo shift!=32 not supported");
712 if (flags & MATCH_SIZE_NEUTRAL) {
713 op1 = arm_skip_downconv(op1);
714 op2 = arm_skip_downconv(op2);
717 new_op1 = be_transform_node(op1);
719 ir_tarval *tv = get_Const_tarval(op2);
720 unsigned int val = get_tarval_long(tv);
721 assert(tarval_is_long(tv));
722 if (can_use_shift_constant(val, shift_modifier)) {
723 switch (shift_modifier) {
724 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
725 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
726 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
727 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
728 default: panic("unexpected shift modifier");
730 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
731 shift_modifier, val);
735 new_op2 = be_transform_node(op2);
736 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
740 static ir_node *gen_Shl(ir_node *node)
742 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
745 static ir_node *gen_Shr(ir_node *node)
747 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
750 static ir_node *gen_Shrs(ir_node *node)
752 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
755 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
757 ir_node *block = be_transform_node(get_nodes_block(node));
758 ir_node *new_op1 = be_transform_node(op1);
759 dbg_info *dbgi = get_irn_dbg_info(node);
760 ir_node *new_op2 = be_transform_node(op2);
762 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
766 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
768 ir_node *block = be_transform_node(get_nodes_block(node));
769 ir_node *new_op1 = be_transform_node(op1);
770 dbg_info *dbgi = get_irn_dbg_info(node);
771 ir_node *new_op2 = be_transform_node(op2);
773 /* Note: there is no Rol on arm, we have to use Ror */
774 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
775 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
779 static ir_node *gen_Rotl(ir_node *node)
781 ir_node *rotate = NULL;
782 ir_node *op1 = get_Rotl_left(node);
783 ir_node *op2 = get_Rotl_right(node);
785 /* Firm has only RotL, so we are looking for a right (op2)
786 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
787 that means we can create a RotR. */
790 ir_node *right = get_Add_right(op2);
791 if (is_Const(right)) {
792 ir_tarval *tv = get_Const_tarval(right);
793 ir_mode *mode = get_irn_mode(node);
794 long bits = get_mode_size_bits(mode);
795 ir_node *left = get_Add_left(op2);
797 if (is_Minus(left) &&
798 tarval_is_long(tv) &&
799 get_tarval_long(tv) == bits &&
801 rotate = gen_Ror(node, op1, get_Minus_op(left));
803 } else if (is_Sub(op2)) {
804 ir_node *left = get_Sub_left(op2);
805 if (is_Const(left)) {
806 ir_tarval *tv = get_Const_tarval(left);
807 ir_mode *mode = get_irn_mode(node);
808 long bits = get_mode_size_bits(mode);
809 ir_node *right = get_Sub_right(op2);
811 if (tarval_is_long(tv) &&
812 get_tarval_long(tv) == bits &&
814 rotate = gen_Ror(node, op1, right);
816 } else if (is_Const(op2)) {
817 ir_tarval *tv = get_Const_tarval(op2);
818 ir_mode *mode = get_irn_mode(node);
819 long bits = get_mode_size_bits(mode);
821 if (tarval_is_long(tv) && bits == 32) {
822 ir_node *block = be_transform_node(get_nodes_block(node));
823 ir_node *new_op1 = be_transform_node(op1);
824 dbg_info *dbgi = get_irn_dbg_info(node);
826 bits = (bits - get_tarval_long(tv)) & 31;
827 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
831 if (rotate == NULL) {
832 rotate = gen_Rol(node, op1, op2);
838 static ir_node *gen_Not(ir_node *node)
840 ir_node *block = be_transform_node(get_nodes_block(node));
841 ir_node *op = get_Not_op(node);
842 ir_node *new_op = be_transform_node(op);
843 dbg_info *dbgi = get_irn_dbg_info(node);
845 /* check if we can fold in a Mov */
846 if (is_arm_Mov(new_op)) {
847 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op);
849 switch (attr->shift_modifier) {
850 ir_node *mov_op, *mov_sft;
853 case ARM_SHF_ASR_IMM:
854 case ARM_SHF_LSL_IMM:
855 case ARM_SHF_LSR_IMM:
856 case ARM_SHF_ROR_IMM:
857 mov_op = get_irn_n(new_op, 0);
858 return new_bd_arm_Mvn_reg_shift_imm(dbgi, block, mov_op,
859 attr->shift_modifier, attr->shift_immediate);
861 case ARM_SHF_ASR_REG:
862 case ARM_SHF_LSL_REG:
863 case ARM_SHF_LSR_REG:
864 case ARM_SHF_ROR_REG:
865 mov_op = get_irn_n(new_op, 0);
866 mov_sft = get_irn_n(new_op, 1);
867 return new_bd_arm_Mvn_reg_shift_reg(dbgi, block, mov_op, mov_sft,
868 attr->shift_modifier);
873 case ARM_SHF_INVALID:
874 panic("invalid shift");
878 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
881 static ir_node *gen_Minus(ir_node *node)
883 ir_node *block = be_transform_node(get_nodes_block(node));
884 ir_node *op = get_Minus_op(node);
885 ir_node *new_op = be_transform_node(op);
886 dbg_info *dbgi = get_irn_dbg_info(node);
887 ir_mode *mode = get_irn_mode(node);
889 if (mode_is_float(mode)) {
891 return new_bd_arm_Mvf(dbgi, block, op, mode);
892 } else if (USE_VFP(isa)) {
893 panic("VFP not supported yet");
895 panic("Softfloat not supported yet");
898 assert(mode_is_data(mode));
899 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
902 static ir_node *gen_Load(ir_node *node)
904 ir_node *block = be_transform_node(get_nodes_block(node));
905 ir_node *ptr = get_Load_ptr(node);
906 ir_node *new_ptr = be_transform_node(ptr);
907 ir_node *mem = get_Load_mem(node);
908 ir_node *new_mem = be_transform_node(mem);
909 ir_mode *mode = get_Load_mode(node);
910 dbg_info *dbgi = get_irn_dbg_info(node);
911 ir_node *new_load = NULL;
913 if (get_Load_unaligned(node) == align_non_aligned)
914 panic("unaligned Loads not supported yet");
916 if (mode_is_float(mode)) {
918 new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
920 } else if (USE_VFP(isa)) {
921 panic("VFP not supported yet");
923 panic("Softfloat not supported yet");
926 assert(mode_is_data(mode) && "unsupported mode for Load");
928 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
930 set_irn_pinned(new_load, get_irn_pinned(node));
932 /* check for special case: the loaded value might not be used */
933 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
934 /* add a result proj and a Keep to produce a pseudo use */
935 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
936 be_new_Keep(block, 1, &proj);
942 static ir_node *gen_Store(ir_node *node)
944 ir_node *block = be_transform_node(get_nodes_block(node));
945 ir_node *ptr = get_Store_ptr(node);
946 ir_node *new_ptr = be_transform_node(ptr);
947 ir_node *mem = get_Store_mem(node);
948 ir_node *new_mem = be_transform_node(mem);
949 ir_node *val = get_Store_value(node);
950 ir_node *new_val = be_transform_node(val);
951 ir_mode *mode = get_irn_mode(val);
952 dbg_info *dbgi = get_irn_dbg_info(node);
953 ir_node *new_store = NULL;
955 if (get_Store_unaligned(node) == align_non_aligned)
956 panic("unaligned Stores not supported yet");
958 if (mode_is_float(mode)) {
960 new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
961 new_mem, mode, NULL, 0, 0, false);
962 } else if (USE_VFP(isa)) {
963 panic("VFP not supported yet");
965 panic("Softfloat not supported yet");
968 assert(mode_is_data(mode) && "unsupported mode for Store");
969 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
972 set_irn_pinned(new_store, get_irn_pinned(node));
976 static ir_node *gen_Jmp(ir_node *node)
978 ir_node *block = get_nodes_block(node);
979 ir_node *new_block = be_transform_node(block);
980 dbg_info *dbgi = get_irn_dbg_info(node);
982 return new_bd_arm_Jmp(dbgi, new_block);
985 static ir_node *gen_Switch(ir_node *node)
987 ir_graph *irg = get_irn_irg(node);
988 ir_node *block = be_transform_node(get_nodes_block(node));
989 ir_node *selector = get_Switch_selector(node);
990 dbg_info *dbgi = get_irn_dbg_info(node);
991 ir_node *new_op = be_transform_node(selector);
992 ir_mode *mode = get_irn_mode(selector);
993 const ir_switch_table *table = get_Switch_table(node);
994 unsigned n_outs = get_Switch_n_outs(node);
996 table = ir_switch_table_duplicate(irg, table);
998 /* switch with smaller modes not implemented yet */
999 assert(get_mode_size_bits(mode) == 32);
1001 return new_bd_arm_SwitchJmp(dbgi, block, new_op, n_outs, table);
1004 static ir_node *gen_Cmp(ir_node *node)
1006 ir_node *block = be_transform_node(get_nodes_block(node));
1007 ir_node *op1 = get_Cmp_left(node);
1008 ir_node *op2 = get_Cmp_right(node);
1009 ir_mode *cmp_mode = get_irn_mode(op1);
1010 dbg_info *dbgi = get_irn_dbg_info(node);
1015 if (mode_is_float(cmp_mode)) {
1016 /* TODO: this is broken... */
1017 new_op1 = be_transform_node(op1);
1018 new_op2 = be_transform_node(op2);
1020 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
1023 assert(get_irn_mode(op2) == cmp_mode);
1024 is_unsigned = !mode_is_signed(cmp_mode);
1026 /* integer compare, TODO: use shifter_op in all its combinations */
1027 new_op1 = be_transform_node(op1);
1028 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
1029 new_op2 = be_transform_node(op2);
1030 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
1031 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
1035 static ir_node *gen_Cond(ir_node *node)
1037 ir_node *const block = be_transform_node(get_nodes_block(node));
1038 dbg_info *const dbgi = get_irn_dbg_info(node);
1039 ir_node *const selector = get_Cond_selector(node);
1040 ir_node *const flag_node = be_transform_node(selector);
1041 ir_relation const relation = get_Cmp_relation(selector);
1042 return new_bd_arm_B(dbgi, block, flag_node, relation);
1048 FPA_IMM_MAX = FPA_IMM_DOUBLE
1051 static ir_tarval *fpa_imm[FPA_IMM_MAX + 1][fpa_max];
1053 static ir_node *gen_Const(ir_node *node)
1055 ir_node *block = be_transform_node(get_nodes_block(node));
1056 ir_mode *mode = get_irn_mode(node);
1057 dbg_info *dbg = get_irn_dbg_info(node);
1059 if (mode_is_float(mode)) {
1061 ir_tarval *tv = get_Const_tarval(node);
1062 node = new_bd_arm_fConst(dbg, block, tv);
1064 } else if (USE_VFP(isa)) {
1065 panic("VFP not supported yet");
1067 panic("Softfloat not supported yet");
1070 return create_const_graph(node, block);
1073 static ir_node *gen_SymConst(ir_node *node)
1075 ir_node *block = be_transform_node(get_nodes_block(node));
1076 ir_entity *entity = get_SymConst_entity(node);
1077 dbg_info *dbgi = get_irn_dbg_info(node);
1080 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
1084 static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0,
1087 /* the good way to do this would be to use the stm (store multiple)
1088 * instructions, since our input is nearly always 2 consecutive 32bit
1090 ir_graph *irg = get_Block_irg(block);
1091 ir_node *stack = get_irg_frame(irg);
1092 ir_node *nomem = get_irg_no_mem(irg);
1093 ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp,
1095 ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp,
1097 ir_node *in[2] = { str0, str1 };
1098 ir_node *sync = new_r_Sync(block, 2, in);
1100 set_irn_pinned(str0, op_pin_state_floats);
1101 set_irn_pinned(str1, op_pin_state_floats);
1103 ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true);
1104 set_irn_pinned(ldf, op_pin_state_floats);
1106 return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1109 static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node)
1111 ir_graph *irg = get_Block_irg(block);
1112 ir_node *stack = get_irg_frame(irg);
1113 ir_node *nomem = get_irg_no_mem(irg);
1114 ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp,
1117 set_irn_pinned(str, op_pin_state_floats);
1119 ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true);
1120 set_irn_pinned(ldf, op_pin_state_floats);
1122 return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1125 static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node)
1127 ir_graph *irg = get_Block_irg(block);
1128 ir_node *stack = get_irg_frame(irg);
1129 ir_node *nomem = get_irg_no_mem(irg);
1130 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F,
1133 set_irn_pinned(stf, op_pin_state_floats);
1135 ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1136 set_irn_pinned(ldr, op_pin_state_floats);
1138 return new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1141 static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node,
1142 ir_node **out_value0, ir_node **out_value1)
1144 ir_graph *irg = get_Block_irg(block);
1145 ir_node *stack = get_irg_frame(irg);
1146 ir_node *nomem = get_irg_no_mem(irg);
1147 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D,
1149 ir_node *ldr0, *ldr1;
1150 set_irn_pinned(stf, op_pin_state_floats);
1152 ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1153 set_irn_pinned(ldr0, op_pin_state_floats);
1154 ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true);
1155 set_irn_pinned(ldr1, op_pin_state_floats);
1157 *out_value0 = new_r_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
1158 *out_value1 = new_r_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
1161 static ir_node *gen_CopyB(ir_node *node)
1163 ir_node *block = be_transform_node(get_nodes_block(node));
1164 ir_node *src = get_CopyB_src(node);
1165 ir_node *new_src = be_transform_node(src);
1166 ir_node *dst = get_CopyB_dst(node);
1167 ir_node *new_dst = be_transform_node(dst);
1168 ir_node *mem = get_CopyB_mem(node);
1169 ir_node *new_mem = be_transform_node(mem);
1170 dbg_info *dbg = get_irn_dbg_info(node);
1171 int size = get_type_size_bytes(get_CopyB_type(node));
1175 src_copy = be_new_Copy(block, new_src);
1176 dst_copy = be_new_Copy(block, new_dst);
1178 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1179 new_bd_arm_EmptyReg(dbg, block),
1180 new_bd_arm_EmptyReg(dbg, block),
1181 new_bd_arm_EmptyReg(dbg, block),
1186 * Transform builtin clz.
1188 static ir_node *gen_clz(ir_node *node)
1190 ir_node *block = be_transform_node(get_nodes_block(node));
1191 dbg_info *dbg = get_irn_dbg_info(node);
1192 ir_node *op = get_irn_n(node, 1);
1193 ir_node *new_op = be_transform_node(op);
1195 /* TODO armv5 instruction, otherwise create a call */
1196 return new_bd_arm_Clz(dbg, block, new_op);
1200 * Transform Builtin node.
1202 static ir_node *gen_Builtin(ir_node *node)
1204 ir_builtin_kind kind = get_Builtin_kind(node);
1208 case ir_bk_debugbreak:
1209 case ir_bk_return_address:
1210 case ir_bk_frame_address:
1211 case ir_bk_prefetch:
1215 return gen_clz(node);
1218 case ir_bk_popcount:
1222 case ir_bk_inner_trampoline:
1225 panic("Builtin %s not implemented", get_builtin_kind_name(kind));
1229 * Transform Proj(Builtin) node.
1231 static ir_node *gen_Proj_Builtin(ir_node *proj)
1233 ir_node *node = get_Proj_pred(proj);
1234 ir_node *new_node = be_transform_node(node);
1235 ir_builtin_kind kind = get_Builtin_kind(node);
1238 case ir_bk_return_address:
1239 case ir_bk_frame_address:
1244 case ir_bk_popcount:
1246 assert(get_Proj_proj(proj) == pn_Builtin_max+1);
1249 case ir_bk_debugbreak:
1250 case ir_bk_prefetch:
1252 assert(get_Proj_proj(proj) == pn_Builtin_M);
1255 case ir_bk_inner_trampoline:
1258 panic("Builtin %s not implemented", get_builtin_kind_name(kind));
1261 static ir_node *gen_Proj_Load(ir_node *node)
1263 ir_node *load = get_Proj_pred(node);
1264 ir_node *new_load = be_transform_node(load);
1265 dbg_info *dbgi = get_irn_dbg_info(node);
1266 long proj = get_Proj_proj(node);
1268 /* renumber the proj */
1269 switch (get_arm_irn_opcode(new_load)) {
1271 /* handle all gp loads equal: they have the same proj numbers. */
1272 if (proj == pn_Load_res) {
1273 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1274 } else if (proj == pn_Load_M) {
1275 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1279 if (proj == pn_Load_res) {
1280 ir_mode *mode = get_Load_mode(load);
1281 return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res);
1282 } else if (proj == pn_Load_M) {
1283 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M);
1289 panic("Unsupported Proj from Load");
1292 static ir_node *gen_Proj_CopyB(ir_node *node)
1294 ir_node *pred = get_Proj_pred(node);
1295 ir_node *new_pred = be_transform_node(pred);
1296 dbg_info *dbgi = get_irn_dbg_info(node);
1297 long proj = get_Proj_proj(node);
1301 if (is_arm_CopyB(new_pred)) {
1302 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1308 panic("Unsupported Proj from CopyB");
1311 static ir_node *gen_Proj_Div(ir_node *node)
1313 ir_node *pred = get_Proj_pred(node);
1314 ir_node *new_pred = be_transform_node(pred);
1315 dbg_info *dbgi = get_irn_dbg_info(node);
1316 ir_mode *mode = get_irn_mode(node);
1317 long proj = get_Proj_proj(node);
1321 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
1323 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
1327 panic("Unsupported Proj from Div");
1330 static ir_node *gen_Proj_Start(ir_node *node)
1332 ir_node *block = get_nodes_block(node);
1333 ir_node *new_block = be_transform_node(block);
1334 long proj = get_Proj_proj(node);
1336 switch ((pn_Start) proj) {
1337 case pn_Start_X_initial_exec:
1338 /* we exchange the ProjX with a jump */
1339 return new_bd_arm_Jmp(NULL, new_block);
1342 return be_prolog_get_memory(abihelper);
1344 case pn_Start_T_args:
1345 return new_r_Bad(get_irn_irg(block), mode_T);
1347 case pn_Start_P_frame_base:
1348 return be_prolog_get_reg_value(abihelper, sp_reg);
1350 panic("unexpected start proj: %ld\n", proj);
1353 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1355 long pn = get_Proj_proj(node);
1356 ir_node *block = get_nodes_block(node);
1357 ir_node *new_block = be_transform_node(block);
1358 ir_graph *irg = get_Block_irg(new_block);
1359 ir_entity *entity = get_irg_entity(irg);
1360 ir_type *method_type = get_entity_type(entity);
1361 ir_type *param_type = get_method_param_type(method_type, pn);
1362 const reg_or_stackslot_t *param;
1364 /* Proj->Proj->Start must be a method argument */
1365 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1367 param = &cconv->parameters[pn];
1369 if (param->reg0 != NULL) {
1370 /* argument transmitted in register */
1371 ir_mode *mode = get_type_mode(param_type);
1372 ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0);
1374 if (mode_is_float(mode)) {
1375 ir_node *value1 = NULL;
1377 if (param->reg1 != NULL) {
1378 value1 = be_prolog_get_reg_value(abihelper, param->reg1);
1379 } else if (param->entity != NULL) {
1380 ir_node *const fp = get_irg_frame(irg);
1381 ir_node *const mem = be_prolog_get_memory(abihelper);
1382 ir_node *const ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode_gp, param->entity, 0, 0, true);
1383 value1 = new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1386 /* convert integer value to float */
1387 if (value1 == NULL) {
1388 value = int_to_float(NULL, new_block, value);
1390 value = ints_to_double(NULL, new_block, value, value1);
1395 /* argument transmitted on stack */
1396 ir_node *const fp = get_irg_frame(irg);
1397 ir_node *const mem = be_prolog_get_memory(abihelper);
1398 ir_mode *const mode = get_type_mode(param->type);
1402 if (mode_is_float(mode)) {
1403 load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode,
1404 param->entity, 0, 0, true);
1405 value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res);
1407 load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1408 param->entity, 0, 0, true);
1409 value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1411 set_irn_pinned(load, op_pin_state_floats);
1418 * Finds number of output value of a mode_T node which is constrained to
1419 * a single specific register.
1421 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1423 be_foreach_out(node, o) {
1424 const arch_register_req_t *req = arch_get_irn_register_req_out(node, o);
1425 if (req == reg->single_req)
1431 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1433 long pn = get_Proj_proj(node);
1434 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1435 ir_node *new_call = be_transform_node(call);
1436 ir_type *function_type = get_Call_type(call);
1437 calling_convention_t *cconv
1438 = arm_decide_calling_convention(NULL, function_type);
1439 const reg_or_stackslot_t *res = &cconv->results[pn];
1443 /* TODO 64bit modes */
1444 assert(res->reg0 != NULL && res->reg1 == NULL);
1445 regn = find_out_for_reg(new_call, res->reg0);
1447 panic("Internal error in calling convention for return %+F", node);
1449 mode = res->reg0->reg_class->mode;
1451 arm_free_calling_convention(cconv);
1453 return new_r_Proj(new_call, mode, regn);
1456 static ir_node *gen_Proj_Call(ir_node *node)
1458 long pn = get_Proj_proj(node);
1459 ir_node *call = get_Proj_pred(node);
1460 ir_node *new_call = be_transform_node(call);
1462 switch ((pn_Call) pn) {
1464 return new_r_Proj(new_call, mode_M, 0);
1465 case pn_Call_X_regular:
1466 case pn_Call_X_except:
1467 case pn_Call_T_result:
1470 panic("Unexpected Call proj %ld\n", pn);
1474 * Transform a Proj node.
1476 static ir_node *gen_Proj(ir_node *node)
1478 ir_node *pred = get_Proj_pred(node);
1479 long proj = get_Proj_proj(node);
1481 switch (get_irn_opcode(pred)) {
1483 if (proj == pn_Store_M) {
1484 return be_transform_node(pred);
1486 panic("Unsupported Proj from Store");
1489 return gen_Proj_Load(node);
1491 return gen_Proj_Call(node);
1493 return gen_Proj_CopyB(node);
1495 return gen_Proj_Div(node);
1497 return gen_Proj_Start(node);
1501 return be_duplicate_node(node);
1503 ir_node *pred_pred = get_Proj_pred(pred);
1504 if (is_Call(pred_pred)) {
1505 return gen_Proj_Proj_Call(node);
1506 } else if (is_Start(pred_pred)) {
1507 return gen_Proj_Proj_Start(node);
1512 return gen_Proj_Builtin(node);
1514 panic("code selection didn't expect Proj after %+F\n", pred);
1518 static ir_node *gen_Unknown(ir_node *node)
1520 ir_node *block = get_nodes_block(node);
1521 ir_node *new_block = be_transform_node(block);
1522 dbg_info *dbgi = get_irn_dbg_info(node);
1524 /* just produce a 0 */
1525 ir_mode *mode = get_irn_mode(node);
1526 if (mode_is_float(mode)) {
1527 ir_tarval *tv = get_mode_null(mode);
1528 ir_node *fconst = new_bd_arm_fConst(dbgi, new_block, tv);
1530 } else if (mode_needs_gp_reg(mode)) {
1531 return create_const_graph_value(dbgi, new_block, 0);
1534 panic("Unexpected Unknown mode");
1538 * Produces the type which sits between the stack args and the locals on the
1539 * stack. It will contain the return address and space to store the old base
1541 * @return The Firm type modeling the ABI between type.
1543 static ir_type *arm_get_between_type(void)
1545 static ir_type *between_type = NULL;
1547 if (between_type == NULL) {
1548 between_type = new_type_class(new_id_from_str("arm_between_type"));
1549 set_type_size_bytes(between_type, 0);
1552 return between_type;
1555 static void create_stacklayout(ir_graph *irg)
1557 ir_entity *entity = get_irg_entity(irg);
1558 ir_type *function_type = get_entity_type(entity);
1559 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1564 /* calling conventions must be decided by now */
1565 assert(cconv != NULL);
1567 /* construct argument type */
1568 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1569 n_params = get_method_n_params(function_type);
1570 for (p = 0; p < n_params; ++p) {
1571 reg_or_stackslot_t *param = &cconv->parameters[p];
1575 if (param->type == NULL)
1578 snprintf(buf, sizeof(buf), "param_%d", p);
1579 id = new_id_from_str(buf);
1580 param->entity = new_entity(arg_type, id, param->type);
1581 set_entity_offset(param->entity, param->offset);
1584 /* TODO: what about external functions? we don't know most of the stack
1585 * layout for them. And probably don't need all of this... */
1586 memset(layout, 0, sizeof(*layout));
1588 layout->frame_type = get_irg_frame_type(irg);
1589 layout->between_type = arm_get_between_type();
1590 layout->arg_type = arg_type;
1591 layout->initial_offset = 0;
1592 layout->initial_bias = 0;
1593 layout->sp_relative = true;
1595 assert(N_FRAME_TYPES == 3);
1596 layout->order[0] = layout->frame_type;
1597 layout->order[1] = layout->between_type;
1598 layout->order[2] = layout->arg_type;
1602 * transform the start node to the prolog code
1604 static ir_node *gen_Start(ir_node *node)
1606 ir_graph *irg = get_irn_irg(node);
1607 ir_entity *entity = get_irg_entity(irg);
1608 ir_type *function_type = get_entity_type(entity);
1609 ir_node *block = get_nodes_block(node);
1610 ir_node *new_block = be_transform_node(block);
1611 dbg_info *dbgi = get_irn_dbg_info(node);
1615 /* stackpointer is important at function prolog */
1616 be_prolog_add_reg(abihelper, sp_reg,
1617 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1618 /* function parameters in registers */
1619 for (i = 0; i < get_method_n_params(function_type); ++i) {
1620 const reg_or_stackslot_t *param = &cconv->parameters[i];
1621 if (param->reg0 != NULL)
1622 be_prolog_add_reg(abihelper, param->reg0, arch_register_req_type_none);
1623 if (param->reg1 != NULL)
1624 be_prolog_add_reg(abihelper, param->reg1, arch_register_req_type_none);
1626 /* announce that we need the values of the callee save regs */
1627 for (i = 0; i != ARRAY_SIZE(callee_saves); ++i) {
1628 be_prolog_add_reg(abihelper, callee_saves[i], arch_register_req_type_none);
1631 start = be_prolog_create_start(abihelper, dbgi, new_block);
1635 static ir_node *get_stack_pointer_for(ir_node *node)
1637 /* get predecessor in stack_order list */
1638 ir_node *stack_pred = be_get_stack_pred(stackorder, node);
1641 if (stack_pred == NULL) {
1642 /* first stack user in the current block. We can simply use the
1643 * initial sp_proj for it */
1644 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1648 be_transform_node(stack_pred);
1649 stack = pmap_get(ir_node, node_to_stack, stack_pred);
1650 if (stack == NULL) {
1651 return get_stack_pointer_for(stack_pred);
1658 * transform a Return node into epilogue code + return statement
1660 static ir_node *gen_Return(ir_node *node)
1662 ir_node *block = get_nodes_block(node);
1663 ir_node *new_block = be_transform_node(block);
1664 dbg_info *dbgi = get_irn_dbg_info(node);
1665 ir_node *mem = get_Return_mem(node);
1666 ir_node *new_mem = be_transform_node(mem);
1667 size_t n_callee_saves = ARRAY_SIZE(callee_saves);
1668 ir_node *sp_proj = get_stack_pointer_for(node);
1669 size_t n_res = get_Return_n_ress(node);
1673 be_epilog_begin(abihelper);
1674 be_epilog_set_memory(abihelper, new_mem);
1675 /* connect stack pointer with initial stack pointer. fix_stack phase
1676 will later serialize all stack pointer adjusting nodes */
1677 be_epilog_add_reg(abihelper, sp_reg,
1678 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1682 for (i = 0; i < n_res; ++i) {
1683 ir_node *res_value = get_Return_res(node, i);
1684 ir_node *new_res_value = be_transform_node(res_value);
1685 const reg_or_stackslot_t *slot = &cconv->results[i];
1686 const arch_register_t *reg = slot->reg0;
1687 assert(slot->reg1 == NULL);
1688 be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, new_res_value);
1691 /* connect callee saves with their values at the function begin */
1692 for (i = 0; i < n_callee_saves; ++i) {
1693 const arch_register_t *reg = callee_saves[i];
1694 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1695 be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, value);
1698 /* epilog code: an incsp */
1699 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1704 static ir_node *gen_Call(ir_node *node)
1706 ir_graph *irg = get_irn_irg(node);
1707 ir_node *callee = get_Call_ptr(node);
1708 ir_node *block = get_nodes_block(node);
1709 ir_node *new_block = be_transform_node(block);
1710 ir_node *mem = get_Call_mem(node);
1711 ir_node *new_mem = be_transform_node(mem);
1712 dbg_info *dbgi = get_irn_dbg_info(node);
1713 ir_type *type = get_Call_type(node);
1714 calling_convention_t *cconv = arm_decide_calling_convention(NULL, type);
1715 size_t n_params = get_Call_n_params(node);
1716 size_t const n_param_regs = cconv->n_reg_params;
1717 /* max inputs: memory, callee, register arguments */
1718 size_t const max_inputs = 2 + n_param_regs;
1719 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1720 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1721 struct obstack *obst = be_get_be_obst(irg);
1722 const arch_register_req_t **in_req
1723 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1724 size_t in_arity = 0;
1725 size_t sync_arity = 0;
1726 size_t const n_caller_saves = ARRAY_SIZE(caller_saves);
1727 ir_entity *entity = NULL;
1728 ir_node *incsp = NULL;
1735 assert(n_params == get_method_n_params(type));
1737 /* construct arguments */
1740 in_req[in_arity] = arch_no_register_req;
1744 for (p = 0; p < n_params; ++p) {
1745 ir_node *value = get_Call_param(node, p);
1746 ir_node *new_value = be_transform_node(value);
1747 ir_node *new_value1 = NULL;
1748 const reg_or_stackslot_t *param = &cconv->parameters[p];
1749 ir_type *param_type = get_method_param_type(type, p);
1750 ir_mode *mode = get_type_mode(param_type);
1753 if (mode_is_float(mode) && param->reg0 != NULL) {
1754 unsigned size_bits = get_mode_size_bits(mode);
1755 if (size_bits == 64) {
1756 double_to_ints(dbgi, new_block, new_value, &new_value,
1759 assert(size_bits == 32);
1760 new_value = float_to_int(dbgi, new_block, new_value);
1764 /* put value into registers */
1765 if (param->reg0 != NULL) {
1766 in[in_arity] = new_value;
1767 in_req[in_arity] = param->reg0->single_req;
1769 if (new_value1 == NULL)
1772 if (param->reg1 != NULL) {
1773 assert(new_value1 != NULL);
1774 in[in_arity] = new_value1;
1775 in_req[in_arity] = param->reg1->single_req;
1780 /* we need a store if we're here */
1781 if (new_value1 != NULL) {
1782 new_value = new_value1;
1786 /* create a parameter frame if necessary */
1787 if (incsp == NULL) {
1788 ir_node *new_frame = get_stack_pointer_for(node);
1789 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1790 cconv->param_stack_size, 1);
1792 if (mode_is_float(mode)) {
1793 str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem,
1794 mode, NULL, 0, param->offset, true);
1796 str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem,
1797 mode, NULL, 0, param->offset, true);
1799 sync_ins[sync_arity++] = str;
1801 assert(in_arity <= max_inputs);
1803 /* construct memory input */
1804 if (sync_arity == 0) {
1805 in[mem_pos] = new_mem;
1806 } else if (sync_arity == 1) {
1807 in[mem_pos] = sync_ins[0];
1809 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1812 /* TODO: use a generic symconst matcher here */
1813 if (is_SymConst(callee)) {
1814 entity = get_SymConst_entity(callee);
1816 /* TODO: finish load matcher here */
1817 in[in_arity] = be_transform_node(callee);
1818 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1826 out_arity = 1 + n_caller_saves;
1828 if (entity != NULL) {
1829 /* TODO: use a generic symconst matcher here
1830 * so we can also handle entity+offset, etc. */
1831 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1834 * - use a proper shifter_operand matcher
1835 * - we could also use LinkLdrPC
1837 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1841 if (incsp != NULL) {
1842 /* IncSP to destroy the call stackframe */
1843 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
1845 /* if we are the last IncSP producer in a block then we have to keep
1847 * Note: This here keeps all producers which is more than necessary */
1848 add_irn_dep(incsp, res);
1851 pmap_insert(node_to_stack, node, incsp);
1854 arch_set_irn_register_reqs_in(res, in_req);
1856 /* create output register reqs */
1857 arch_set_irn_register_req_out(res, 0, arch_no_register_req);
1858 for (o = 0; o < n_caller_saves; ++o) {
1859 const arch_register_t *reg = caller_saves[o];
1860 arch_set_irn_register_req_out(res, o+1, reg->single_req);
1863 /* copy pinned attribute */
1864 set_irn_pinned(res, get_irn_pinned(node));
1866 arm_free_calling_convention(cconv);
1870 static ir_node *gen_Sel(ir_node *node)
1872 dbg_info *dbgi = get_irn_dbg_info(node);
1873 ir_node *block = get_nodes_block(node);
1874 ir_node *new_block = be_transform_node(block);
1875 ir_node *ptr = get_Sel_ptr(node);
1876 ir_node *new_ptr = be_transform_node(ptr);
1877 ir_entity *entity = get_Sel_entity(node);
1879 /* must be the frame pointer all other sels must have been lowered
1881 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1883 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1886 static ir_node *gen_Phi(ir_node *node)
1888 ir_mode *mode = get_irn_mode(node);
1889 const arch_register_req_t *req;
1890 if (mode_needs_gp_reg(mode)) {
1891 /* we shouldn't have any 64bit stuff around anymore */
1892 assert(get_mode_size_bits(mode) <= 32);
1893 /* all integer operations are on 32bit registers now */
1895 req = arm_reg_classes[CLASS_arm_gp].class_req;
1897 req = arch_no_register_req;
1900 return be_transform_phi(node, req);
1904 * Enters all transform functions into the generic pointer
1906 static void arm_register_transformers(void)
1908 be_start_transform_setup();
1910 be_set_transform_function(op_Add, gen_Add);
1911 be_set_transform_function(op_And, gen_And);
1912 be_set_transform_function(op_Call, gen_Call);
1913 be_set_transform_function(op_Cmp, gen_Cmp);
1914 be_set_transform_function(op_Cond, gen_Cond);
1915 be_set_transform_function(op_Const, gen_Const);
1916 be_set_transform_function(op_Conv, gen_Conv);
1917 be_set_transform_function(op_CopyB, gen_CopyB);
1918 be_set_transform_function(op_Div, gen_Div);
1919 be_set_transform_function(op_Eor, gen_Eor);
1920 be_set_transform_function(op_Jmp, gen_Jmp);
1921 be_set_transform_function(op_Load, gen_Load);
1922 be_set_transform_function(op_Minus, gen_Minus);
1923 be_set_transform_function(op_Mul, gen_Mul);
1924 be_set_transform_function(op_Not, gen_Not);
1925 be_set_transform_function(op_Or, gen_Or);
1926 be_set_transform_function(op_Phi, gen_Phi);
1927 be_set_transform_function(op_Proj, gen_Proj);
1928 be_set_transform_function(op_Return, gen_Return);
1929 be_set_transform_function(op_Rotl, gen_Rotl);
1930 be_set_transform_function(op_Sel, gen_Sel);
1931 be_set_transform_function(op_Shl, gen_Shl);
1932 be_set_transform_function(op_Shr, gen_Shr);
1933 be_set_transform_function(op_Shrs, gen_Shrs);
1934 be_set_transform_function(op_Start, gen_Start);
1935 be_set_transform_function(op_Store, gen_Store);
1936 be_set_transform_function(op_Sub, gen_Sub);
1937 be_set_transform_function(op_Switch, gen_Switch);
1938 be_set_transform_function(op_SymConst, gen_SymConst);
1939 be_set_transform_function(op_Unknown, gen_Unknown);
1940 be_set_transform_function(op_Builtin, gen_Builtin);
1944 * Initialize fpa Immediate support.
1946 static void arm_init_fpa_immediate(void)
1948 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
1949 fpa_imm[FPA_IMM_FLOAT][fpa_null] = get_mode_null(mode_F);
1950 fpa_imm[FPA_IMM_FLOAT][fpa_one] = get_mode_one(mode_F);
1951 fpa_imm[FPA_IMM_FLOAT][fpa_two] = new_tarval_from_str("2", 1, mode_F);
1952 fpa_imm[FPA_IMM_FLOAT][fpa_three] = new_tarval_from_str("3", 1, mode_F);
1953 fpa_imm[FPA_IMM_FLOAT][fpa_four] = new_tarval_from_str("4", 1, mode_F);
1954 fpa_imm[FPA_IMM_FLOAT][fpa_five] = new_tarval_from_str("5", 1, mode_F);
1955 fpa_imm[FPA_IMM_FLOAT][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
1956 fpa_imm[FPA_IMM_FLOAT][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
1958 fpa_imm[FPA_IMM_DOUBLE][fpa_null] = get_mode_null(mode_D);
1959 fpa_imm[FPA_IMM_DOUBLE][fpa_one] = get_mode_one(mode_D);
1960 fpa_imm[FPA_IMM_DOUBLE][fpa_two] = new_tarval_from_str("2", 1, mode_D);
1961 fpa_imm[FPA_IMM_DOUBLE][fpa_three] = new_tarval_from_str("3", 1, mode_D);
1962 fpa_imm[FPA_IMM_DOUBLE][fpa_four] = new_tarval_from_str("4", 1, mode_D);
1963 fpa_imm[FPA_IMM_DOUBLE][fpa_five] = new_tarval_from_str("5", 1, mode_D);
1964 fpa_imm[FPA_IMM_DOUBLE][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
1965 fpa_imm[FPA_IMM_DOUBLE][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
1969 * Transform a Firm graph into an ARM graph.
1971 void arm_transform_graph(ir_graph *irg)
1973 static int imm_initialized = 0;
1974 ir_entity *entity = get_irg_entity(irg);
1975 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1976 ir_type *frame_type;
1981 if (! imm_initialized) {
1982 arm_init_fpa_immediate();
1983 imm_initialized = 1;
1985 arm_register_transformers();
1987 isa = (arm_isa_t*) arch_env;
1989 node_to_stack = pmap_create();
1991 assert(abihelper == NULL);
1992 abihelper = be_abihelper_prepare(irg);
1993 stackorder = be_collect_stacknodes(irg);
1994 assert(cconv == NULL);
1995 cconv = arm_decide_calling_convention(irg, get_entity_type(entity));
1996 create_stacklayout(irg);
1998 be_transform_graph(irg, NULL);
2000 be_abihelper_finish(abihelper);
2002 be_free_stackorder(stackorder);
2005 arm_free_calling_convention(cconv);
2008 frame_type = get_irg_frame_type(irg);
2009 if (get_type_state(frame_type) == layout_undefined) {
2010 default_layout_compound_type(frame_type);
2013 pmap_destroy(node_to_stack);
2014 node_to_stack = NULL;
2016 be_add_missing_keeps(irg);
2019 void arm_init_transform(void)
2021 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");