2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
31 #include "irgraph_t.h"
42 #include "../benode_t.h"
43 #include "bearch_arm_t.h"
45 #include "arm_nodes_attr.h"
46 #include "../arch/archop.h" /* we need this for Min and Max nodes */
47 #include "arm_transform.h"
48 #include "arm_new_nodes.h"
49 #include "arm_map_regs.h"
51 #include "gen_arm_regalloc_if.h"
56 extern ir_op *get_op_Mulh(void);
60 /****************************************************************************************************
62 * | | | | / _| | | (_)
63 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
64 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
65 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
66 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
68 ****************************************************************************************************/
70 typedef struct vals_ {
72 unsigned char values[4];
73 unsigned char shifts[4];
77 static unsigned do_rol(unsigned v, unsigned rol) {
78 return (v << rol) | (v >> (32 - rol));
82 * construct 8bit values und rot amounts for a value
84 static void gen_vals_from_word(unsigned int value, vals *result)
88 memset(result, 0, sizeof(*result));
90 /* special case: we prefer shift amount 0 */
92 result->values[0] = value;
99 unsigned v = do_rol(value, 8) & 0xFFFFFF;
108 shf = (initial + shf - 8) & 0x1F;
109 result->values[result->ops] = v;
110 result->shifts[result->ops] = shf;
113 value ^= do_rol(v, shf) >> initial;
123 * Creates a arm_Const node.
125 static ir_node *create_const_node(ir_node *irn, ir_node *block, long value) {
126 tarval *tv = new_tarval_from_long(value, mode_Iu);
127 dbg_info *dbg = get_irn_dbg_info(irn);
128 return new_rd_arm_Mov_i(dbg, current_ir_graph, block, get_irn_mode(irn), tv);
132 * Creates a arm_Const_Neg node.
134 static ir_node *create_const_neg_node(ir_node *irn, ir_node *block, long value) {
135 tarval *tv = new_tarval_from_long(value, mode_Iu);
136 dbg_info *dbg = get_irn_dbg_info(irn);
137 return new_rd_arm_Mvn_i(dbg, current_ir_graph, block, get_irn_mode(irn), tv);
140 #define NEW_BINOP_NODE(opname, env, op1, op2) new_rd_arm_##opname(env->dbg, current_ir_graph, env->block, op1, op2, env->mode)
143 * Encodes an immediate with shifter operand
145 static unsigned int arm_encode_imm_w_shift(unsigned int shift, unsigned int immediate) {
146 return immediate | ((shift>>1)<<8);
150 * Decode an immediate with shifter operand
152 unsigned int arm_decode_imm_w_shift(tarval *tv) {
153 unsigned l = get_tarval_long(tv);
154 unsigned rol = (l & ~0xFF) >> 7;
156 return do_rol(l & 0xFF, rol);
160 * Creates a possible DAG for an constant.
162 static ir_node *create_const_graph_value(ir_node *irn, ir_node *block, unsigned int value) {
166 ir_mode *mode = get_irn_mode(irn);
167 dbg_info *dbg = get_irn_dbg_info(irn);
169 gen_vals_from_word(value, &v);
170 gen_vals_from_word(~value, &vn);
172 if (vn.ops < v.ops) {
174 result = create_const_neg_node(irn, block, arm_encode_imm_w_shift(vn.shifts[0], vn.values[0]));
176 for (cnt = 1; cnt < vn.ops; ++cnt) {
177 tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]), mode_Iu);
178 ir_node *bic_i_node = new_rd_arm_Bic_i(dbg, current_ir_graph, block, result, mode, tv);
184 result = create_const_node(irn, block, arm_encode_imm_w_shift(v.shifts[0], v.values[0]));
186 for (cnt = 1; cnt < v.ops; ++cnt) {
187 tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]), mode_Iu);
188 ir_node *orr_i_node = new_rd_arm_Or_i(dbg, current_ir_graph, block, result, mode, tv);
196 * Create a DAG constructing a given Const.
198 * @param irn a Firm const
200 static ir_node *create_const_graph(ir_node *irn, ir_node *block) {
201 int value = get_tarval_long(get_Const_tarval(irn));
202 return create_const_graph_value(irn, block, value);
207 * Creates code for a Firm Const node.
209 static ir_node *gen_Const(ir_node *irn, arm_code_gen_t *cg) {
210 ir_graph *irg = current_ir_graph;
211 ir_node *block = get_nodes_block(irn);
212 ir_mode *mode = get_irn_mode(irn);
213 dbg_info *dbg = get_irn_dbg_info(irn);
215 if (mode_is_float(mode)) {
216 if (USE_FPA(cg->isa))
217 return new_rd_arm_fpaConst(dbg, irg, block, mode, get_Const_tarval(irn));
218 else if (USE_VFP(cg->isa))
219 assert(mode != mode_E && "IEEE Extended FP not supported");
222 else if (mode_is_reference(mode))
224 return create_const_graph(irn, block);
227 static ir_node *gen_mask(ir_node *irn, ir_node *op, int result_bits) {
228 ir_node *block = get_nodes_block(irn);
229 unsigned mask_bits = (1 << result_bits) - 1;
230 ir_node *mask_node = create_const_graph_value(irn, block, mask_bits);
231 dbg_info *dbg = get_irn_dbg_info(irn);
232 return new_rd_arm_And(dbg, current_ir_graph, block, op, mask_node, get_irn_mode(irn), ARM_SHF_NONE, NULL);
235 static ir_node *gen_sign_extension(ir_node *irn, ir_node *op, int result_bits) {
236 ir_node *block = get_nodes_block(irn);
237 int shift_width = 32 - result_bits;
238 ir_graph *irg = current_ir_graph;
239 ir_node *shift_const_node = create_const_graph_value(irn, block, shift_width);
240 dbg_info *dbg = get_irn_dbg_info(irn);
241 ir_node *lshift_node = new_rd_arm_Shl(dbg, irg, block, op, shift_const_node, get_irn_mode(op));
242 ir_node *rshift_node = new_rd_arm_Shrs(dbg, irg, block, lshift_node, shift_const_node, get_irn_mode(irn));
247 * Transforms a Conv node.
249 * @param env The transformation environment
250 * @return the created arm Conv node
252 static ir_node *gen_Conv(ir_node *irn, arm_code_gen_t *cg) {
253 ir_graph *irg = current_ir_graph;
254 ir_node *block = get_nodes_block(irn);
255 ir_node *op = get_Conv_op(irn);
256 ir_mode *in_mode = get_irn_mode(op);
257 ir_mode *out_mode = get_irn_mode(irn);
258 dbg_info *dbg = get_irn_dbg_info(irn);
260 if (in_mode == out_mode)
263 if (mode_is_float(in_mode) || mode_is_float(out_mode)) {
266 if (USE_FPA(cg->isa)) {
267 if (mode_is_float(in_mode)) {
268 if (mode_is_float(out_mode)) {
269 /* from float to float */
270 return new_rd_arm_fpaMov(dbg, irg, block, op, out_mode);
273 /* from float to int */
274 return new_rd_arm_fpaFix(dbg, irg, block, op, out_mode);
278 /* from int to float */
279 return new_rd_arm_fpaFlt(dbg, irg, block, op, out_mode);
284 else { /* complete in gp registers */
285 int in_bits = get_mode_size_bits(in_mode);
286 int out_bits = get_mode_size_bits(out_mode);
287 int in_sign = get_mode_sign(in_mode);
288 int out_sign = get_mode_sign(out_mode);
292 if (in_bits == out_bits && in_bits == 32)
296 // unsigned -> unsigned
298 // unsigned -> signed
299 // sign extension (31:16)=(15)
300 // signed -> unsigned
301 // maskieren (31:16)=0
304 if (in_bits == out_bits && out_bits < 32) {
305 if (in_sign && !out_sign) {
306 return gen_mask(irn, op, out_bits);
308 return gen_sign_extension(irn, op, out_bits);
313 // unsigned -> unsigned
315 // unsigned -> signed
317 // signed -> unsigned
318 // sign extension (31:16)=(15)
320 // sign extension (31:16)=(15)
321 if (in_bits < out_bits) {
323 return gen_sign_extension(irn, op, out_bits);
330 // unsigned -> unsigned
331 // maskieren (31:16)=0
332 // unsigned -> signed
333 // maskieren (31:16)=0
334 // signed -> unsigned
335 // maskieren (31:16)=0
337 // sign extension (erledigt auch maskieren) (31:16)=(15)
338 if (in_bits > out_bits) {
339 if (in_sign && out_sign) {
340 return gen_sign_extension(irn, op, out_bits);
342 return gen_mask(irn, op, out_bits);
345 assert(0 && "recheck integer conversion logic!");
352 * Return true if an operand is a shifter operand
354 static int is_shifter_operand(ir_node *n, arm_shift_modifier *pmod) {
355 arm_shift_modifier mod = ARM_SHF_NONE;
358 mod = get_arm_shift_modifier(n);
361 if (mod != ARM_SHF_NONE) {
362 long v = get_tarval_long(get_arm_value(n));
370 * Creates an arm Add.
372 * @param env The transformation environment
373 * @return the created arm Add node
375 static ir_node *gen_Add(ir_node *irn, arm_code_gen_t *cg) {
376 ir_node *block = get_nodes_block(irn);
377 ir_node *op1 = get_Add_left(irn);
378 ir_node *op2 = get_Add_right(irn);
379 ir_mode *mode = get_irn_mode(irn);
380 ir_graph *irg = current_ir_graph;
383 arm_shift_modifier mod;
384 dbg_info *dbg = get_irn_dbg_info(irn);
386 if (mode_is_float(mode)) {
388 if (USE_FPA(cg->isa))
389 return new_rd_arm_fpaAdd(dbg, irg, block, op1, op2, mode);
390 else if (USE_VFP(cg->isa)) {
391 assert(mode != mode_E && "IEEE Extended FP not supported");
395 if (mode_is_numP(mode)) {
396 if (is_arm_Mov_i(op1))
397 return new_rd_arm_Add_i(dbg, irg, block, op2, mode, get_arm_value(op1));
398 if (is_arm_Mov_i(op2))
399 return new_rd_arm_Add_i(dbg, irg, block, op1, mode, get_arm_value(op2));
402 if (is_arm_Mul(op1) && get_irn_n_edges(op1) == 1) {
404 op2 = get_irn_n(op1, 1);
405 op1 = get_irn_n(op1, 0);
407 return new_rd_arm_Mla(dbg, irg, block, op1, op2, op3, mode);
409 if (is_arm_Mul(op2) && get_irn_n_edges(op2) == 1) {
411 op1 = get_irn_n(op2, 0);
412 op2 = get_irn_n(op2, 1);
414 return new_rd_arm_Mla(dbg, irg, block, op1, op2, op3, mode);
417 /* is the first a shifter */
418 v = is_shifter_operand(op1, &mod);
420 op1 = get_irn_n(op1, 0);
421 return new_rd_arm_Add(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu));
423 /* is the second a shifter */
424 v = is_shifter_operand(op2, &mod);
426 op2 = get_irn_n(op2, 0);
427 return new_rd_arm_Add(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu));
431 return new_rd_arm_Add(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL);
434 assert(0 && "unknown mode for add");
439 * Creates an arm Mul.
441 * @param env The transformation environment
442 * @return the created arm Mul node
444 static ir_node *gen_Mul(ir_node *irn, arm_code_gen_t *cg) {
445 ir_node *block = get_nodes_block(irn);
446 ir_node *op1 = get_Mul_left(irn);
447 ir_node *op2 = get_Mul_right(irn);
448 ir_mode *mode = get_irn_mode(irn);
449 ir_graph *irg = current_ir_graph;
450 dbg_info *dbg = get_irn_dbg_info(irn);
452 if (mode_is_float(mode)) {
454 if (USE_FPA(cg->isa))
455 return new_rd_arm_fpaMul(dbg, irg, block, op1, op2, mode);
456 else if (USE_VFP(cg->isa)) {
457 assert(mode != mode_E && "IEEE Extended FP not supported");
461 return new_rd_arm_Mul(dbg, irg, block, op1, op2, mode);
465 * Creates an arm floating point Div.
467 * @param env The transformation environment
468 * @return the created arm fDiv node
470 static ir_node *gen_Quot(ir_node *irn, arm_code_gen_t *cg) {
471 ir_node *block = get_nodes_block(irn);
472 ir_node *op1 = get_Quot_left(irn);
473 ir_node *op2 = get_Quot_right(irn);
474 ir_mode *mode = get_irn_mode(irn);
475 dbg_info *dbg = get_irn_dbg_info(irn);
477 assert(mode != mode_E && "IEEE Extended FP not supported");
480 if (USE_FPA(cg->isa))
481 return new_rd_arm_fpaDiv(dbg, current_ir_graph, block, op1, op2, mode);
482 else if (USE_VFP(cg->isa)) {
483 assert(mode != mode_E && "IEEE Extended FP not supported");
490 #define GEN_INT_OP(op) \
491 static ir_node *gen_ ## op(ir_node *irn, arm_code_gen_t *cg) { \
492 ir_graph *irg = current_ir_graph; \
493 ir_node *block = get_nodes_block(irn); \
494 ir_node *op1 = get_ ## op ## _left(irn); \
495 ir_node *op2 = get_ ## op ## _right(irn); \
497 arm_shift_modifier mod; \
498 ir_mode *mode = get_irn_mode(irn); \
499 dbg_info *dbg = get_irn_dbg_info(irn); \
501 if (is_arm_Mov_i(op1)) \
502 return new_rd_arm_ ## op ## _i(dbg, irg, block, op2, mode, get_arm_value(op1)); \
503 if (is_arm_Mov_i(op2)) \
504 return new_rd_arm_ ## op ## _i(dbg, irg, block, op1, mode, get_arm_value(op2)); \
505 /* is the first a shifter */ \
506 v = is_shifter_operand(op1, &mod); \
508 op1 = get_irn_n(op1, 0); \
509 return new_rd_arm_ ## op(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu)); \
511 /* is the second a shifter */ \
512 v = is_shifter_operand(op2, &mod); \
514 op2 = get_irn_n(op2, 0); \
515 return new_rd_arm_ ## op(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu)); \
518 return new_rd_arm_ ## op(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL); \
523 * Creates an arm And.
525 * @param env The transformation environment
526 * @return the created arm And node
528 static ir_node *gen_And(ir_node *irn, arm_code_gen_t *cg);
532 * Creates an arm Orr.
534 * @param env The transformation environment
535 * @return the created arm Or node
537 static ir_node *gen_Or(ir_node *irn, arm_code_gen_t *cg);
541 * Creates an arm Eor.
543 * @param env The transformation environment
544 * @return the created arm Eor node
546 static ir_node *gen_Eor(ir_node *irn, arm_code_gen_t *cg);
550 * Creates an arm Sub.
552 * @param env The transformation environment
553 * @return the created arm Sub node
555 static ir_node *gen_Sub(ir_node *irn, arm_code_gen_t *cg) {
556 ir_node *block = get_nodes_block(irn);
557 ir_node *op1 = get_Sub_left(irn);
558 ir_node *op2 = get_Sub_right(irn);
560 arm_shift_modifier mod;
561 ir_mode *mode = get_irn_mode(irn);
562 ir_graph *irg = current_ir_graph;
563 dbg_info *dbg = get_irn_dbg_info(irn);
565 if (mode_is_float(mode)) {
567 if (USE_FPA(cg->isa))
568 return new_rd_arm_fpaSub(dbg, irg, block, op1, op2, mode);
569 else if (USE_VFP(cg->isa)) {
570 assert(mode != mode_E && "IEEE Extended FP not supported");
574 if (mode_is_numP(mode)) {
575 if (is_arm_Mov_i(op1))
576 return new_rd_arm_Rsb_i(dbg, irg, block, op2, mode, get_arm_value(op1));
577 if (is_arm_Mov_i(op2))
578 return new_rd_arm_Sub_i(dbg, irg, block, op1, mode, get_arm_value(op2));
580 /* is the first a shifter */
581 v = is_shifter_operand(op1, &mod);
583 op1 = get_irn_n(op1, 0);
584 return new_rd_arm_Rsb(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu));
586 /* is the second a shifter */
587 v = is_shifter_operand(op2, &mod);
589 op2 = get_irn_n(op2, 0);
590 return new_rd_arm_Sub(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu));
593 return new_rd_arm_Sub(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL);
595 assert(0 && "unknown mode for sub");
600 * Creates an arm Shl.
602 * @param env The transformation environment
603 * @return the created arm Shl node
605 static ir_node *gen_Shl(ir_node *irn, arm_code_gen_t *cg) {
607 ir_node *block = get_nodes_block(irn);
608 ir_node *op1 = get_Shl_left(irn);
609 ir_node *op2 = get_Shl_right(irn);
610 ir_mode *mode = get_irn_mode(irn);
611 ir_graph *irg = current_ir_graph;
612 dbg_info *dbg = get_irn_dbg_info(irn);
614 if (is_arm_Mov_i(op2)) {
615 result = new_rd_arm_Mov(dbg, irg, block, op1, mode, ARM_SHF_LSL, get_arm_value(op2));
617 result = new_rd_arm_Shl(dbg, irg, block, op1, op2, mode);
623 * Creates an arm Shr.
625 * @param env The transformation environment
626 * @return the created arm Shr node
628 static ir_node *gen_Shr(ir_node *irn, arm_code_gen_t *cg) {
630 ir_node *block = get_nodes_block(irn);
631 ir_node *op1 = get_Shr_left(irn);
632 ir_node *op2 = get_Shr_right(irn);
633 ir_mode *mode = get_irn_mode(irn);
634 ir_graph *irg = current_ir_graph;
635 dbg_info *dbg = get_irn_dbg_info(irn);
637 if (is_arm_Mov_i(op2)) {
638 result = new_rd_arm_Mov(dbg, irg, block, op1, mode, ARM_SHF_LSR, get_arm_value(op2));
640 result = new_rd_arm_Shr(dbg, irg, block, op1, op2, mode);
646 * Creates an arm Shrs.
648 * @param env The transformation environment
649 * @return the created arm Shrs node
651 static ir_node *gen_Shrs(ir_node *irn, arm_code_gen_t *cg) {
653 ir_node *block = get_nodes_block(irn);
654 ir_node *op1 = get_Shrs_left(irn);
655 ir_node *op2 = get_Shrs_right(irn);
656 ir_mode *mode = get_irn_mode(irn);
657 dbg_info *dbg = get_irn_dbg_info(irn);
659 if (is_arm_Mov_i(op2)) {
660 result = new_rd_arm_Mov(dbg, current_ir_graph, block, op1, mode, ARM_SHF_ASR, get_arm_value(op2));
662 result = new_rd_arm_Shrs(dbg, current_ir_graph, block, op1, op2, mode);
668 * Transforms a Not node.
670 * @param env The transformation environment
671 * @return the created arm Not node
673 static ir_node *gen_Not(ir_node *irn, arm_code_gen_t *cg) {
674 ir_node *block = get_nodes_block(irn);
675 ir_node *op = get_Not_op(irn);
677 arm_shift_modifier mod = ARM_SHF_NONE;
679 dbg_info *dbg = get_irn_dbg_info(irn);
681 v = is_shifter_operand(op, &mod);
683 op = get_irn_n(op, 0);
684 tv = new_tarval_from_long(v, mode_Iu);
686 return new_rd_arm_Mvn(dbg, current_ir_graph, block, op, get_irn_mode(irn), mod, tv);
690 * Transforms an Abs node.
692 * @param env The transformation environment
693 * @return the created arm Abs node
695 static ir_node *gen_Abs(ir_node *irn, arm_code_gen_t *cg) {
696 ir_node *block = get_nodes_block(irn);
697 ir_node *op = get_Abs_op(irn);
698 ir_mode *mode = get_irn_mode(irn);
699 dbg_info *dbg = get_irn_dbg_info(irn);
701 if (mode_is_float(mode)) {
703 if (USE_FPA(cg->isa))
704 return new_rd_arm_fpaAbs(dbg, current_ir_graph, block, op, mode);
705 else if (USE_VFP(cg->isa)) {
706 assert(mode != mode_E && "IEEE Extended FP not supported");
710 return new_rd_arm_Abs(dbg, current_ir_graph, block, op, mode);
714 * Transforms a Minus node.
716 * @param env The transformation environment
717 * @return the created arm Minus node
719 static ir_node *gen_Minus(ir_node *irn, arm_code_gen_t *cg) {
720 ir_node *block = get_nodes_block(irn);
721 ir_node *op = get_Minus_op(irn);
722 ir_mode *mode = get_irn_mode(irn);
723 ir_graph *irg = current_ir_graph;
724 dbg_info *dbg = get_irn_dbg_info(irn);
726 if (mode_is_float(mode)) {
728 if (USE_FPA(cg->isa))
729 return new_rd_arm_fpaMnv(dbg, irg, block, op, mode);
730 else if (USE_VFP(cg->isa)) {
731 assert(mode != mode_E && "IEEE Extended FP not supported");
735 return new_rd_arm_Rsb_i(dbg, irg, block, op, mode, get_mode_null(mode));
741 * @param mod the debug module
742 * @param block the block the new node should belong to
743 * @param node the ir Load node
744 * @param mode node mode
745 * @return the created arm Load node
747 static ir_node *gen_Load(ir_node *irn, arm_code_gen_t *cg) {
748 ir_node *block = get_nodes_block(irn);
749 ir_mode *mode = get_Load_mode(irn);
750 ir_graph *irg = current_ir_graph;
751 dbg_info *dbg = get_irn_dbg_info(irn);
753 if (mode_is_float(mode)) {
755 if (USE_FPA(cg->isa))
756 return new_rd_arm_fpaLdf(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn),
758 else if (USE_VFP(cg->isa)) {
759 assert(mode != mode_E && "IEEE Extended FP not supported");
763 if (mode == mode_Bu) {
764 return new_rd_arm_Loadb(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
766 if (mode == mode_Bs) {
767 return new_rd_arm_Loadbs(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
769 if (mode == mode_Hu) {
770 return new_rd_arm_Loadh(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
772 if (mode == mode_Hs) {
773 return new_rd_arm_Loadhs(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
775 if (mode_is_reference(mode)) {
776 return new_rd_arm_Load(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
778 return new_rd_arm_Load(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
782 * Transforms a Store.
784 * @param mod the debug module
785 * @param block the block the new node should belong to
786 * @param node the ir Store node
787 * @param mode node mode
788 * @return the created arm Store node
790 static ir_node *gen_Store(ir_node *irn, arm_code_gen_t *cg) {
791 ir_node *block = get_nodes_block(irn);
792 ir_mode *mode = get_irn_mode(get_Store_value(irn));
793 ir_graph *irg = current_ir_graph;
794 dbg_info *dbg = get_irn_dbg_info(irn);
796 assert(mode != mode_E && "IEEE Extended FP not supported");
797 if (mode_is_float(mode)) {
799 if (USE_FPA(cg->isa))
800 return new_rd_arm_fpaStf(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn),
801 get_Store_mem(irn), get_irn_mode(get_Store_value(irn)));
802 else if (USE_VFP(cg->isa)) {
803 assert(mode != mode_E && "IEEE Extended FP not supported");
807 if (mode == mode_Bu) {
808 return new_rd_arm_Storeb(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
810 if (mode == mode_Bs) {
811 return new_rd_arm_Storebs(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
813 if (mode == mode_Hu) {
814 return new_rd_arm_Storeh(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
816 if (mode == mode_Hs) {
817 return new_rd_arm_Storehs(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
819 return new_rd_arm_Store(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
823 static ir_node *gen_Cond(ir_node *irn, arm_code_gen_t *cg) {
824 ir_node *result = NULL;
825 ir_node *selector = get_Cond_selector(irn);
826 ir_node *block = get_nodes_block(irn);
827 ir_graph *irg = current_ir_graph;
828 dbg_info *dbg = get_irn_dbg_info(irn);
830 if ( get_irn_mode(selector) == mode_b ) {
832 ir_node *proj_node = get_Cond_selector(irn);
833 ir_node *cmp_node = get_Proj_pred(proj_node);
834 ir_node *op1 = get_Cmp_left(cmp_node);
835 ir_node *op2 = get_Cmp_right(cmp_node);
836 result = new_rd_arm_CondJmp(dbg, irg, block, op1, op2, mode_T);
837 set_arm_proj_num(result, get_Proj_proj(proj_node));
840 ir_node *op = get_irn_n(irn, 0);
841 ir_node *const_graph;
846 const ir_edge_t *edge;
856 foreach_out_edge(irn, edge) {
857 proj = get_edge_src_irn(edge);
858 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
860 pn = get_Proj_proj(proj);
862 min = pn<min ? pn : min;
863 max = pn>max ? pn : max;
866 norm_max = max - translation;
867 norm_min = min - translation;
869 n_projs = norm_max + 1;
870 projs = xcalloc(n_projs , sizeof(ir_node*));
873 foreach_out_edge(irn, edge) {
874 proj = get_edge_src_irn(edge);
875 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
877 pn = get_Proj_proj(proj) - translation;
878 set_Proj_proj(proj, pn);
882 const_node = new_rd_Const(dbg, irg, block, mode_Iu, new_tarval_from_long(translation, mode_Iu));
883 const_graph = gen_Const(const_node, cg);
884 sub = new_rd_arm_Sub(dbg, irg, block, op, const_graph, get_irn_mode(op), ARM_SHF_NONE, NULL);
885 result = new_rd_arm_SwitchJmp(dbg, irg, block, sub, mode_T);
886 set_arm_n_projs(result, n_projs);
887 set_arm_default_proj_num(result, get_Cond_defaultProj(irn)-translation);
893 * Returns the name of a SymConst.
894 * @param symc the SymConst
895 * @return name of the SymConst
897 const char *get_sc_name(ir_node *symc) {
899 if (get_irn_opcode(symc) != iro_SymConst)
902 switch (get_SymConst_kind(symc)) {
903 case symconst_addr_name:
904 return get_id_str(get_SymConst_name(symc));
906 case symconst_addr_ent:
907 ent = get_SymConst_entity(symc);
908 mark_entity_visited(ent);
909 return get_entity_ld_name(ent);
912 assert(0 && "Unsupported SymConst");
918 static ir_node *gen_SymConst(ir_node *irn, arm_code_gen_t *cg) {
919 ir_node *block = get_nodes_block(irn);
920 ir_mode *mode = get_irn_mode(irn);
921 dbg_info *dbg = get_irn_dbg_info(irn);
922 return new_rd_arm_SymConst(dbg, current_ir_graph, block, mode, get_sc_name(irn));
928 * Transforms a CopyB node.
930 * @param env The transformation environment
931 * @return The transformed node.
933 static ir_node *gen_CopyB(ir_node *irn, arm_code_gen_t *cg) {
935 dbg_info *dbg = get_irn_dbg_info(irn);
936 ir_mode *mode = get_irn_mode(irn);
937 ir_node *src = get_CopyB_src(irn);
938 ir_node *dst = get_CopyB_dst(irn);
939 ir_node *mem = get_CopyB_mem(irn);
940 ir_node *block = get_nodes_block(irn);
941 int size = get_type_size_bytes(get_CopyB_type(irn));
942 ir_graph *irg = current_ir_graph;
946 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, src);
947 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, dst);
949 res = new_rd_arm_CopyB( dbg, irg, block, dst_copy, src_copy, new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), mem, mode);
950 set_arm_value(res, new_tarval_from_long(size, mode_Iu));
959 /********************************************
962 * | |__ ___ _ __ ___ __| | ___ ___
963 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
964 * | |_) | __/ | | | (_) | (_| | __/\__ \
965 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
967 ********************************************/
970 * Return an expanding stack offset.
971 * Note that function is called in the transform phase
972 * where the stack offsets are still relative regarding
973 * the first (frame allocating) IncSP.
974 * However this is exactly what we want because frame
975 * access must be done relative the the fist IncSP ...
977 static int get_sp_expand_offset(ir_node *inc_sp) {
978 int offset = be_get_IncSP_offset(inc_sp);
980 if (offset == BE_STACK_FRAME_SIZE_EXPAND)
987 static ir_node *gen_StackParam(ir_node *irn, arm_code_gen_t *cg) {
988 ir_node *new_op = NULL;
989 ir_node *block = get_nodes_block(irn);
990 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
991 ir_node *mem = new_rd_NoMem(env->irg);
992 ir_node *ptr = get_irn_n(irn, 0);
993 ir_entity *ent = be_get_frame_entity(irn);
994 ir_mode *mode = env->mode;
996 // /* If the StackParam has only one user -> */
997 // /* put it in the Block where the user resides */
998 // if (get_irn_n_edges(node) == 1) {
999 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1002 if (mode_is_float(mode)) {
1003 if (USE_SSE2(env->cg))
1004 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1006 env->cg->used_x87 = 1;
1007 new_op = new_rd_ia32_vfld(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1011 new_op = new_rd_ia32_Load(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1014 set_ia32_frame_ent(new_op, ent);
1015 set_ia32_use_frame(new_op);
1017 set_ia32_am_support(new_op, ia32_am_Source);
1018 set_ia32_op_type(new_op, ia32_AddrModeS);
1019 set_ia32_am_flavour(new_op, ia32_B);
1020 set_ia32_ls_mode(new_op, mode);
1022 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1024 return new_rd_Proj(env->dbg, env->irg, block, new_op, mode, 0);
1029 * Transforms a FrameAddr into an ia32 Add.
1031 static ir_node *gen_be_FrameAddr(ir_node *irn, arm_code_gen_t *cg) {
1032 ir_node *block = get_nodes_block(irn);
1033 ir_entity *ent = be_get_frame_entity(irn);
1034 int offset = get_entity_offset(ent);
1035 ir_node *op = get_irn_n(irn, 0);
1037 ir_mode *mode = get_irn_mode(irn);
1038 dbg_info *dbg = get_irn_dbg_info(irn);
1040 if (be_is_IncSP(op)) {
1041 /* BEWARE: we get an offset which is absolute from an offset that
1042 is relative. Both must be merged */
1043 offset += get_sp_expand_offset(op);
1045 cnst = create_const_graph_value(irn, block, (unsigned)offset);
1046 if (is_arm_Mov_i(cnst))
1047 return new_rd_arm_Add_i(dbg, current_ir_graph, block, op, mode, get_arm_value(cnst));
1048 return new_rd_arm_Add(dbg, current_ir_graph, block, op, cnst, mode, ARM_SHF_NONE, NULL);
1053 * Transforms a FrameLoad into an ia32 Load.
1055 static ir_node *gen_FrameLoad(ir_node *irn, arm_code_gen_t *cg) {
1056 ir_node *new_op = NULL;
1057 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1058 ir_node *mem = get_irn_n(irn, 0);
1059 ir_node *ptr = get_irn_n(irn, 1);
1060 ir_entity *ent = be_get_frame_entity(irn);
1061 ir_mode *mode = get_type_mode(get_entity_type(ent));
1063 if (mode_is_float(mode)) {
1064 if (USE_SSE2(env->cg))
1065 new_op = new_rd_ia32_fLoad(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
1067 env->cg->used_x87 = 1;
1068 new_op = new_rd_ia32_vfld(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
1072 new_op = new_rd_ia32_Load(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
1075 set_ia32_frame_ent(new_op, ent);
1076 set_ia32_use_frame(new_op);
1078 set_ia32_am_support(new_op, ia32_am_Source);
1079 set_ia32_op_type(new_op, ia32_AddrModeS);
1080 set_ia32_am_flavour(new_op, ia32_B);
1081 set_ia32_ls_mode(new_op, mode);
1083 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1091 * Transforms a FrameStore into an ia32 Store.
1093 static ir_node *gen_FrameStore(ir_node *irn, arm_code_gen_t *cg) {
1094 ir_node *new_op = NULL;
1095 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1096 ir_node *mem = get_irn_n(irn, 0);
1097 ir_node *ptr = get_irn_n(irn, 1);
1098 ir_node *val = get_irn_n(irn, 2);
1099 ir_entity *ent = be_get_frame_entity(irn);
1100 ir_mode *mode = get_irn_mode(val);
1102 if (mode_is_float(mode)) {
1103 if (USE_SSE2(env->cg))
1104 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1106 env->cg->used_x87 = 1;
1107 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1110 else if (get_mode_size_bits(mode) == 8) {
1111 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1114 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1117 set_ia32_frame_ent(new_op, ent);
1118 set_ia32_use_frame(new_op);
1120 set_ia32_am_support(new_op, ia32_am_Dest);
1121 set_ia32_op_type(new_op, ia32_AddrModeD);
1122 set_ia32_am_flavour(new_op, ia32_B);
1123 set_ia32_ls_mode(new_op, mode);
1125 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1132 // static ir_node *gen_be_Copy(ir_node *irn, arm_code_gen_t *cg) {
1133 // return new_rd_arm_Copy(env->dbg, env->irg, env->block, op, env->mode);
1136 /*********************************************************
1139 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1140 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1141 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1142 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1144 *********************************************************/
1147 * move constants out of the start block
1149 void arm_move_consts(ir_node *node, void *env) {
1156 for (i = get_irn_arity(node) - 1; i >= 0; --i) {
1157 ir_node *pred = get_irn_n(node,i);
1158 ir_opcode pred_code = get_irn_opcode(pred);
1159 if (pred_code == iro_Const) {
1160 ir_node *const_graph;
1161 const_graph = create_const_graph(pred, get_nodes_block(get_irn_n(get_nodes_block(node),i)));
1162 set_irn_n(node, i, const_graph);
1164 else if (pred_code == iro_SymConst) {
1165 /* FIXME: in general, SymConst always require a load, so it
1166 might be better to place them into the first real block
1167 and let the spiller rematerialize them. */
1168 const char *str = get_sc_name(pred);
1169 ir_node *symconst_node;
1170 symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
1171 current_ir_graph, get_nodes_block(get_irn_n(get_nodes_block(node),i)),
1172 get_irn_mode(pred), str);
1173 set_irn_n(node, i, symconst_node);
1178 for (i = 0; i < get_irn_arity(node); i++) {
1179 ir_node *pred = get_irn_n(node,i);
1180 ir_opcode pred_code = get_irn_opcode(pred);
1181 if (pred_code == iro_Const) {
1182 ir_node *const_graph;
1183 const_graph = create_const_graph(pred, get_nodes_block(node));
1184 set_irn_n(node, i, const_graph);
1185 } else if (pred_code == iro_SymConst) {
1186 const char *str = get_sc_name(pred);
1187 ir_node *symconst_node;
1188 symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
1189 current_ir_graph, get_nodes_block(node),
1190 get_irn_mode(pred), str);
1191 set_irn_n(node, i, symconst_node);
1197 /************************************************************************/
1198 /* move symbolic constants out of startblock */
1199 /************************************************************************/
1200 void arm_move_symconsts(ir_node *node, void *env) {
1206 for (i = 0; i < get_irn_arity(node); i++) {
1207 ir_node *pred = get_irn_n(node,i);
1208 ir_opcode pred_code = get_irn_opcode(pred);
1210 if (pred_code == iro_SymConst) {
1211 const char *str = get_sc_name(pred);
1212 ir_node *symconst_node;
1214 symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
1215 current_ir_graph, get_nodes_block(node), get_irn_mode(pred), str);
1216 set_irn_n(node, i, symconst_node);
1222 * the BAD transformer.
1224 static ir_node *bad_transform(ir_node *irn, arm_code_gen_t *cg) {
1225 ir_fprintf(stderr, "Not implemented: %+F\n", irn);
1231 * Enters all transform functions into the generic pointer
1233 void arm_register_transformers(void) {
1234 ir_op *op_Max, *op_Min, *op_Mulh;
1236 /* first clear the generic function pointer for all ops */
1237 clear_irp_opcodes_generic_func();
1239 #define FIRM_OP(a) op_##a->ops.generic = (op_func)gen_##a
1240 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
1243 FIRM_OP(Add); // done
1244 FIRM_OP(Mul); // done
1245 FIRM_OP(Quot); // done
1246 FIRM_OP(And); // done
1247 FIRM_OP(Or); // done
1248 FIRM_OP(Eor); // done
1250 FIRM_OP(Sub); // done
1251 FIRM_OP(Shl); // done
1252 FIRM_OP(Shr); // done
1253 FIRM_OP(Shrs); // done
1255 FIRM_OP(Minus); // done
1256 FIRM_OP(Not); // done
1257 FIRM_OP(Abs); // done
1259 FIRM_OP(CopyB); // done
1260 FIRM_OP(Const); // TODO: floating point consts
1261 FIRM_OP(Conv); // TODO: floating point conversions
1263 FIRM_OP(Load); // done
1264 FIRM_OP(Store); // done
1267 FIRM_OP(Cond); // integer done
1269 /* TODO: implement these nodes */
1271 IGN(Div); // intrinsic lowering
1272 IGN(Mod); // intrinsic lowering
1273 IGN(DivMod); // TODO: implement DivMod
1277 IGN(Cmp); // done, implemented in cond
1279 /* You probably don't need to handle the following nodes */
1291 IGN(Jmp); // emitter done
1309 FIRM_OP(be_FrameAddr);
1311 op_Max = get_op_Max();
1314 op_Min = get_op_Min();
1317 op_Mulh = get_op_Mulh();
1326 typedef ir_node *(transform_func)(ir_node *irn, arm_code_gen_t *cg);
1329 * Transforms the given firm node (and maybe some other related nodes)
1330 * into one or more assembler nodes.
1332 * @param node the firm node
1333 * @param env the debug module
1335 void arm_transform_node(ir_node *node, void *env) {
1336 arm_code_gen_t *cg = (arm_code_gen_t *)env;
1337 ir_op *op = get_irn_op(node);
1338 ir_node *asm_node = NULL;
1343 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
1345 if (op->ops.generic) {
1346 transform_func *transform = (transform_func *)op->ops.generic;
1348 asm_node = (*transform)(node, cg);
1352 exchange(node, asm_node);
1353 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
1356 DB((cg->mod, LEVEL_1, "ignored\n"));