2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
41 #include "../benode.h"
43 #include "../beutil.h"
44 #include "../betranshlp.h"
45 #include "../beabihelper.h"
48 #include "bearch_arm_t.h"
49 #include "arm_nodes_attr.h"
50 #include "arm_transform.h"
51 #include "arm_optimize.h"
52 #include "arm_new_nodes.h"
53 #include "arm_map_regs.h"
54 #include "arm_cconv.h"
56 #include "gen_arm_regalloc_if.h"
60 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 /** hold the current code generator during transformation */
63 static arm_code_gen_t *env_cg;
65 static const arch_register_t *sp_reg = &arm_gp_regs[REG_SP];
66 static ir_mode *mode_gp;
67 static beabi_helper_env_t *abihelper;
68 static calling_convention_t *cconv = NULL;
70 static pmap *node_to_stack;
72 static bool mode_needs_gp_reg(ir_mode *mode)
74 return mode_is_int(mode) || mode_is_reference(mode);
78 * create firm graph for a constant
80 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
87 /* We only have 8 bit immediates. So we possibly have to combine several
88 * operations to construct the desired value.
90 * we can either create the value by adding bits to 0 or by removing bits
91 * from an register with all bits set. Try which alternative needs fewer
93 arm_gen_vals_from_word(value, &v);
94 arm_gen_vals_from_word(~value, &vn);
98 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
99 be_dep_on_frame(result);
101 for (cnt = 1; cnt < vn.ops; ++cnt) {
102 result = new_bd_arm_Bic_imm(dbgi, block, result,
103 vn.values[cnt], vn.rors[cnt]);
107 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
108 be_dep_on_frame(result);
110 for (cnt = 1; cnt < v.ops; ++cnt) {
111 result = new_bd_arm_Or_imm(dbgi, block, result,
112 v.values[cnt], v.rors[cnt]);
119 * Create a DAG constructing a given Const.
121 * @param irn a Firm const
123 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
125 tarval *tv = get_Const_tarval(irn);
126 ir_mode *mode = get_tarval_mode(tv);
129 if (mode_is_reference(mode)) {
130 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
131 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
132 tv = tarval_convert_to(tv, mode_Iu);
134 value = get_tarval_long(tv);
135 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
139 * Create an And that will zero out upper bits.
141 * @param dbgi debug info
142 * @param block the basic block
143 * @param op the original node
144 * param src_bits number of lower bits that will remain
146 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
150 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
151 } else if (src_bits == 16) {
152 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
153 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
156 panic("zero extension only supported for 8 and 16 bits");
161 * Generate code for a sign extension.
163 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
166 int shift_width = 32 - src_bits;
167 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
168 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
172 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
175 int bits = get_mode_size_bits(orig_mode);
179 if (mode_is_signed(orig_mode)) {
180 return gen_sign_extension(dbgi, block, op, bits);
182 return gen_zero_extension(dbgi, block, op, bits);
187 * returns true if it is assured, that the upper bits of a node are "clean"
188 * which means for a 16 or 8 bit value, that the upper bits in the register
189 * are 0 for unsigned and a copy of the last significant bit for signed
192 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
194 (void) transformed_node;
201 * Transforms a Conv node.
203 * @return The created ia32 Conv node
205 static ir_node *gen_Conv(ir_node *node)
207 ir_node *block = be_transform_node(get_nodes_block(node));
208 ir_node *op = get_Conv_op(node);
209 ir_node *new_op = be_transform_node(op);
210 ir_mode *src_mode = get_irn_mode(op);
211 ir_mode *dst_mode = get_irn_mode(node);
212 dbg_info *dbg = get_irn_dbg_info(node);
214 if (src_mode == dst_mode)
217 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
218 env_cg->have_fp_insn = 1;
220 if (USE_FPA(env_cg->isa)) {
221 if (mode_is_float(src_mode)) {
222 if (mode_is_float(dst_mode)) {
223 /* from float to float */
224 return new_bd_arm_fpaMvf(dbg, block, new_op, dst_mode);
226 /* from float to int */
227 return new_bd_arm_fpaFix(dbg, block, new_op, dst_mode);
230 /* from int to float */
231 return new_bd_arm_fpaFlt(dbg, block, new_op, dst_mode);
233 } else if (USE_VFP(env_cg->isa)) {
234 panic("VFP not supported yet");
236 panic("Softfloat not supported yet");
238 } else { /* complete in gp registers */
239 int src_bits = get_mode_size_bits(src_mode);
240 int dst_bits = get_mode_size_bits(dst_mode);
244 if (src_bits == dst_bits) {
245 /* kill unnecessary conv */
249 if (src_bits < dst_bits) {
257 if (upper_bits_clean(new_op, min_mode)) {
261 if (mode_is_signed(min_mode)) {
262 return gen_sign_extension(dbg, block, new_op, min_bits);
264 return gen_zero_extension(dbg, block, new_op, min_bits);
274 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
276 unsigned val, low_pos, high_pos;
281 val = get_tarval_long(get_Const_tarval(node));
293 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
295 So we determine the smallest even position with a bit set
296 and the highest even position with no bit set anymore.
297 If the difference between these 2 is <= 8, then we can encode the value
300 low_pos = ntz(val) & ~1u;
301 high_pos = (32-nlz(val)+1) & ~1u;
303 if (high_pos - low_pos <= 8) {
304 res->imm_8 = val >> low_pos;
305 res->rot = 32 - low_pos;
310 res->rot = 34 - high_pos;
311 val = val >> (32-res->rot) | val << (res->rot);
321 static bool is_downconv(const ir_node *node)
329 /* we only want to skip the conv when we're the only user
330 * (not optimal but for now...)
332 if (get_irn_n_edges(node) > 1)
335 src_mode = get_irn_mode(get_Conv_op(node));
336 dest_mode = get_irn_mode(node);
338 mode_needs_gp_reg(src_mode) &&
339 mode_needs_gp_reg(dest_mode) &&
340 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
343 static ir_node *arm_skip_downconv(ir_node *node)
345 while (is_downconv(node))
346 node = get_Conv_op(node);
352 MATCH_COMMUTATIVE = 1 << 0,
353 MATCH_SIZE_NEUTRAL = 1 << 1,
356 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
357 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
359 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
360 new_binop_reg_func new_reg, new_binop_imm_func new_imm)
362 ir_node *block = be_transform_node(get_nodes_block(node));
363 ir_node *op1 = get_binop_left(node);
365 ir_node *op2 = get_binop_right(node);
367 dbg_info *dbgi = get_irn_dbg_info(node);
370 if (flags & MATCH_SIZE_NEUTRAL) {
371 op1 = arm_skip_downconv(op1);
372 op2 = arm_skip_downconv(op2);
374 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
377 if (try_encode_as_immediate(op2, &imm)) {
378 ir_node *new_op1 = be_transform_node(op1);
379 return new_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
381 new_op2 = be_transform_node(op2);
382 if ((flags & MATCH_COMMUTATIVE) && try_encode_as_immediate(op1, &imm)) {
383 return new_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
385 new_op1 = be_transform_node(op1);
387 return new_reg(dbgi, block, new_op1, new_op2);
391 * Creates an ARM Add.
393 * @return the created arm Add node
395 static ir_node *gen_Add(ir_node *node)
397 ir_mode *mode = get_irn_mode(node);
399 if (mode_is_float(mode)) {
400 ir_node *block = be_transform_node(get_nodes_block(node));
401 ir_node *op1 = get_Add_left(node);
402 ir_node *op2 = get_Add_right(node);
403 dbg_info *dbgi = get_irn_dbg_info(node);
404 ir_node *new_op1 = be_transform_node(op1);
405 ir_node *new_op2 = be_transform_node(op2);
406 env_cg->have_fp_insn = 1;
407 if (USE_FPA(env_cg->isa)) {
409 if (is_arm_fpaMvf_i(new_op1))
410 return new_bd_arm_fpaAdf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1));
411 if (is_arm_fpaMvf_i(new_op2))
412 return new_bd_arm_fpaAdf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2));
414 return new_bd_arm_fpaAdf(dbgi, block, new_op1, new_op2, mode);
415 } else if (USE_VFP(env_cg->isa)) {
416 assert(mode != mode_E && "IEEE Extended FP not supported");
417 panic("VFP not supported yet");
419 panic("Softfloat not supported yet");
424 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
426 new_op2 = get_irn_n(new_op1, 1);
427 new_op1 = get_irn_n(new_op1, 0);
429 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
431 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
433 new_op1 = get_irn_n(new_op2, 0);
434 new_op2 = get_irn_n(new_op2, 1);
436 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
440 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
441 new_bd_arm_Add_reg, new_bd_arm_Add_imm);
446 * Creates an ARM Mul.
448 * @return the created arm Mul node
450 static ir_node *gen_Mul(ir_node *node)
452 ir_node *block = be_transform_node(get_nodes_block(node));
453 ir_node *op1 = get_Mul_left(node);
454 ir_node *new_op1 = be_transform_node(op1);
455 ir_node *op2 = get_Mul_right(node);
456 ir_node *new_op2 = be_transform_node(op2);
457 ir_mode *mode = get_irn_mode(node);
458 dbg_info *dbg = get_irn_dbg_info(node);
460 if (mode_is_float(mode)) {
461 env_cg->have_fp_insn = 1;
462 if (USE_FPA(env_cg->isa)) {
464 if (is_arm_Mov_i(new_op1))
465 return new_bd_arm_fpaMuf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
466 if (is_arm_Mov_i(new_op2))
467 return new_bd_arm_fpaMuf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
469 return new_bd_arm_fpaMuf(dbg, block, new_op1, new_op2, mode);
470 } else if (USE_VFP(env_cg->isa)) {
471 assert(mode != mode_E && "IEEE Extended FP not supported");
472 panic("VFP not supported yet");
474 panic("Softfloat not supported yet");
477 assert(mode_is_data(mode));
478 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
481 static ir_node *gen_Quot(ir_node *node)
483 ir_node *block = be_transform_node(get_nodes_block(node));
484 ir_node *op1 = get_Quot_left(node);
485 ir_node *new_op1 = be_transform_node(op1);
486 ir_node *op2 = get_Quot_right(node);
487 ir_node *new_op2 = be_transform_node(op2);
488 ir_mode *mode = get_irn_mode(node);
489 dbg_info *dbg = get_irn_dbg_info(node);
491 assert(mode != mode_E && "IEEE Extended FP not supported");
493 env_cg->have_fp_insn = 1;
494 if (USE_FPA(env_cg->isa)) {
496 if (is_arm_Mov_i(new_op1))
497 return new_bd_arm_fpaRdf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
498 if (is_arm_Mov_i(new_op2))
499 return new_bd_arm_fpaDvf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
501 return new_bd_arm_fpaDvf(dbg, block, new_op1, new_op2, mode);
502 } else if (USE_VFP(env_cg->isa)) {
503 assert(mode != mode_E && "IEEE Extended FP not supported");
504 panic("VFP not supported yet");
506 panic("Softfloat not supported yet");
510 static ir_node *gen_And(ir_node *node)
512 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
513 new_bd_arm_And_reg, new_bd_arm_And_imm);
516 static ir_node *gen_Or(ir_node *node)
518 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
519 new_bd_arm_Or_reg, new_bd_arm_Or_imm);
522 static ir_node *gen_Eor(ir_node *node)
524 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
525 new_bd_arm_Eor_reg, new_bd_arm_Eor_imm);
528 static ir_node *gen_Sub(ir_node *node)
530 ir_node *block = be_transform_node(get_nodes_block(node));
531 ir_node *op1 = get_Sub_left(node);
532 ir_node *new_op1 = be_transform_node(op1);
533 ir_node *op2 = get_Sub_right(node);
534 ir_node *new_op2 = be_transform_node(op2);
535 ir_mode *mode = get_irn_mode(node);
536 dbg_info *dbgi = get_irn_dbg_info(node);
538 if (mode_is_float(mode)) {
539 env_cg->have_fp_insn = 1;
540 if (USE_FPA(env_cg->isa)) {
542 if (is_arm_Mov_i(new_op1))
543 return new_bd_arm_fpaRsf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1));
544 if (is_arm_Mov_i(new_op2))
545 return new_bd_arm_fpaSuf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2));
547 return new_bd_arm_fpaSuf(dbgi, block, new_op1, new_op2, mode);
548 } else if (USE_VFP(env_cg->isa)) {
549 assert(mode != mode_E && "IEEE Extended FP not supported");
550 panic("VFP not supported yet");
552 panic("Softfloat not supported yet");
555 return gen_int_binop(node, MATCH_SIZE_NEUTRAL,
556 new_bd_arm_Sub_reg, new_bd_arm_Sub_imm);
561 * Checks if a given value can be used as an immediate for the given
564 static bool can_use_shift_constant(unsigned int val,
565 arm_shift_modifier_t modifier)
569 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
575 * generate an ARM shift instruction.
577 * @param node the node
578 * @param flags matching flags
579 * @param shift_modifier initial encoding of the desired shift operation
581 static ir_node *make_shift(ir_node *node, match_flags_t flags,
582 arm_shift_modifier_t shift_modifier)
584 ir_node *block = be_transform_node(get_nodes_block(node));
585 ir_node *op1 = get_binop_left(node);
586 ir_node *op2 = get_binop_right(node);
587 dbg_info *dbgi = get_irn_dbg_info(node);
591 if (flags & MATCH_SIZE_NEUTRAL) {
592 op1 = arm_skip_downconv(op1);
593 op2 = arm_skip_downconv(op2);
596 new_op1 = be_transform_node(op1);
598 tarval *tv = get_Const_tarval(op2);
599 unsigned int val = get_tarval_long(tv);
600 assert(tarval_is_long(tv));
601 if (can_use_shift_constant(val, shift_modifier)) {
602 switch (shift_modifier) {
603 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
604 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
605 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
606 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
607 default: panic("unexpected shift modifier");
609 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
610 shift_modifier, val);
614 new_op2 = be_transform_node(op2);
615 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
619 static ir_node *gen_Shl(ir_node *node)
621 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
624 static ir_node *gen_Shr(ir_node *node)
626 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
629 static ir_node *gen_Shrs(ir_node *node)
631 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
634 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
636 ir_node *block = be_transform_node(get_nodes_block(node));
637 ir_node *new_op1 = be_transform_node(op1);
638 dbg_info *dbgi = get_irn_dbg_info(node);
639 ir_node *new_op2 = be_transform_node(op2);
641 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
645 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
647 ir_node *block = be_transform_node(get_nodes_block(node));
648 ir_node *new_op1 = be_transform_node(op1);
649 dbg_info *dbgi = get_irn_dbg_info(node);
650 ir_node *new_op2 = be_transform_node(op2);
652 /* Note: there is no Rol on arm, we have to use Ror */
653 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
654 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
658 static ir_node *gen_Rotl(ir_node *node)
660 ir_node *rotate = NULL;
661 ir_node *op1 = get_Rotl_left(node);
662 ir_node *op2 = get_Rotl_right(node);
664 /* Firm has only RotL, so we are looking for a right (op2)
665 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
666 that means we can create a RotR. */
669 ir_node *right = get_Add_right(op2);
670 if (is_Const(right)) {
671 tarval *tv = get_Const_tarval(right);
672 ir_mode *mode = get_irn_mode(node);
673 long bits = get_mode_size_bits(mode);
674 ir_node *left = get_Add_left(op2);
676 if (is_Minus(left) &&
677 tarval_is_long(tv) &&
678 get_tarval_long(tv) == bits &&
680 rotate = gen_Ror(node, op1, get_Minus_op(left));
682 } else if (is_Sub(op2)) {
683 ir_node *left = get_Sub_left(op2);
684 if (is_Const(left)) {
685 tarval *tv = get_Const_tarval(left);
686 ir_mode *mode = get_irn_mode(node);
687 long bits = get_mode_size_bits(mode);
688 ir_node *right = get_Sub_right(op2);
690 if (tarval_is_long(tv) &&
691 get_tarval_long(tv) == bits &&
693 rotate = gen_Ror(node, op1, right);
695 } else if (is_Const(op2)) {
696 tarval *tv = get_Const_tarval(op2);
697 ir_mode *mode = get_irn_mode(node);
698 long bits = get_mode_size_bits(mode);
700 if (tarval_is_long(tv) && bits == 32) {
701 ir_node *block = be_transform_node(get_nodes_block(node));
702 ir_node *new_op1 = be_transform_node(op1);
703 dbg_info *dbgi = get_irn_dbg_info(node);
705 bits = (bits - get_tarval_long(tv)) & 31;
706 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
710 if (rotate == NULL) {
711 rotate = gen_Rol(node, op1, op2);
717 static ir_node *gen_Not(ir_node *node)
719 ir_node *block = be_transform_node(get_nodes_block(node));
720 ir_node *op = get_Not_op(node);
721 ir_node *new_op = be_transform_node(op);
722 dbg_info *dbgi = get_irn_dbg_info(node);
724 /* TODO: we could do alot more here with all the Mvn variations */
726 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
729 static ir_node *gen_Abs(ir_node *node)
731 ir_node *block = be_transform_node(get_nodes_block(node));
732 ir_node *op = get_Abs_op(node);
733 ir_node *new_op = be_transform_node(op);
734 dbg_info *dbgi = get_irn_dbg_info(node);
735 ir_mode *mode = get_irn_mode(node);
737 if (mode_is_float(mode)) {
738 env_cg->have_fp_insn = 1;
739 if (USE_FPA(env_cg->isa)) {
740 return new_bd_arm_fpaAbs(dbgi, block, new_op, mode);
741 } else if (USE_VFP(env_cg->isa)) {
742 assert(mode != mode_E && "IEEE Extended FP not supported");
743 panic("VFP not supported yet");
745 panic("Softfloat not supported yet");
748 assert(mode_is_data(mode));
749 return new_bd_arm_Abs(dbgi, block, new_op);
752 static ir_node *gen_Minus(ir_node *node)
754 ir_node *block = be_transform_node(get_nodes_block(node));
755 ir_node *op = get_Minus_op(node);
756 ir_node *new_op = be_transform_node(op);
757 dbg_info *dbgi = get_irn_dbg_info(node);
758 ir_mode *mode = get_irn_mode(node);
760 if (mode_is_float(mode)) {
761 env_cg->have_fp_insn = 1;
762 if (USE_FPA(env_cg->isa)) {
763 return new_bd_arm_fpaMvf(dbgi, block, op, mode);
764 } else if (USE_VFP(env_cg->isa)) {
765 assert(mode != mode_E && "IEEE Extended FP not supported");
766 panic("VFP not supported yet");
768 panic("Softfloat not supported yet");
771 assert(mode_is_data(mode));
772 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
775 static ir_node *gen_Load(ir_node *node)
777 ir_node *block = be_transform_node(get_nodes_block(node));
778 ir_node *ptr = get_Load_ptr(node);
779 ir_node *new_ptr = be_transform_node(ptr);
780 ir_node *mem = get_Load_mem(node);
781 ir_node *new_mem = be_transform_node(mem);
782 ir_mode *mode = get_Load_mode(node);
783 dbg_info *dbgi = get_irn_dbg_info(node);
784 ir_node *new_load = NULL;
786 if (mode_is_float(mode)) {
787 env_cg->have_fp_insn = 1;
788 if (USE_FPA(env_cg->isa)) {
789 new_load = new_bd_arm_fpaLdf(dbgi, block, new_ptr, new_mem, mode);
790 } else if (USE_VFP(env_cg->isa)) {
791 assert(mode != mode_E && "IEEE Extended FP not supported");
792 panic("VFP not supported yet");
794 panic("Softfloat not supported yet");
797 assert(mode_is_data(mode) && "unsupported mode for Load");
799 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
801 set_irn_pinned(new_load, get_irn_pinned(node));
803 /* check for special case: the loaded value might not be used */
804 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
805 /* add a result proj and a Keep to produce a pseudo use */
806 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
807 be_new_Keep(block, 1, &proj);
813 static ir_node *gen_Store(ir_node *node)
815 ir_node *block = be_transform_node(get_nodes_block(node));
816 ir_node *ptr = get_Store_ptr(node);
817 ir_node *new_ptr = be_transform_node(ptr);
818 ir_node *mem = get_Store_mem(node);
819 ir_node *new_mem = be_transform_node(mem);
820 ir_node *val = get_Store_value(node);
821 ir_node *new_val = be_transform_node(val);
822 ir_mode *mode = get_irn_mode(val);
823 dbg_info *dbgi = get_irn_dbg_info(node);
824 ir_node *new_store = NULL;
826 if (mode_is_float(mode)) {
827 env_cg->have_fp_insn = 1;
828 if (USE_FPA(env_cg->isa)) {
829 new_store = new_bd_arm_fpaStf(dbgi, block, new_ptr, new_val,
831 } else if (USE_VFP(env_cg->isa)) {
832 assert(mode != mode_E && "IEEE Extended FP not supported");
833 panic("VFP not supported yet");
835 panic("Softfloat not supported yet");
838 assert(mode_is_data(mode) && "unsupported mode for Store");
839 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
842 set_irn_pinned(new_store, get_irn_pinned(node));
846 static ir_node *gen_Jmp(ir_node *node)
848 ir_node *block = get_nodes_block(node);
849 ir_node *new_block = be_transform_node(block);
850 dbg_info *dbgi = get_irn_dbg_info(node);
852 return new_bd_arm_Jmp(dbgi, new_block);
855 static ir_node *gen_SwitchJmp(ir_node *node)
857 ir_node *block = be_transform_node(get_nodes_block(node));
858 ir_node *selector = get_Cond_selector(node);
859 dbg_info *dbgi = get_irn_dbg_info(node);
860 ir_node *new_op = be_transform_node(selector);
861 ir_node *const_graph;
865 const ir_edge_t *edge;
872 foreach_out_edge(node, edge) {
873 proj = get_edge_src_irn(edge);
874 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
876 pn = get_Proj_proj(proj);
878 min = pn<min ? pn : min;
879 max = pn>max ? pn : max;
882 n_projs = max - translation + 1;
884 foreach_out_edge(node, edge) {
885 proj = get_edge_src_irn(edge);
886 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
888 pn = get_Proj_proj(proj) - translation;
889 set_Proj_proj(proj, pn);
892 const_graph = create_const_graph_value(dbgi, block, translation);
893 sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
894 return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
897 static ir_node *gen_Cmp(ir_node *node)
899 ir_node *block = be_transform_node(get_nodes_block(node));
900 ir_node *op1 = get_Cmp_left(node);
901 ir_node *op2 = get_Cmp_right(node);
902 ir_mode *cmp_mode = get_irn_mode(op1);
903 dbg_info *dbgi = get_irn_dbg_info(node);
908 if (mode_is_float(cmp_mode)) {
909 /* TODO: this is broken... */
910 new_op1 = be_transform_node(op1);
911 new_op2 = be_transform_node(op2);
913 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
915 panic("FloatCmp NIY");
917 ir_node *new_op2 = be_transform_node(op2);
918 /* floating point compare */
919 pn_Cmp pnc = get_Proj_proj(selector);
921 if (pnc & pn_Cmp_Uo) {
922 /* check for unordered, need cmf */
923 return new_bd_arm_fpaCmfBra(dbgi, block, new_op1, new_op2, pnc);
925 /* Hmm: use need cmfe */
926 return new_bd_arm_fpaCmfeBra(dbgi, block, new_op1, new_op2, pnc);
930 assert(get_irn_mode(op2) == cmp_mode);
931 is_unsigned = !mode_is_signed(cmp_mode);
933 /* compare with 0 can be done with Tst */
934 if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) {
935 new_op1 = be_transform_node(op1);
936 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
937 return new_bd_arm_Tst_reg(dbgi, block, new_op1, new_op1, false,
940 if (is_Const(op1) && tarval_is_null(get_Const_tarval(op1))) {
941 new_op2 = be_transform_node(op2);
942 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
943 return new_bd_arm_Tst_reg(dbgi, block, new_op2, new_op2, true,
947 /* integer compare, TODO: use shifter_op in all its combinations */
948 new_op1 = be_transform_node(op1);
949 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
950 new_op2 = be_transform_node(op2);
951 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
952 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
956 static ir_node *gen_Cond(ir_node *node)
958 ir_node *selector = get_Cond_selector(node);
959 ir_mode *mode = get_irn_mode(selector);
964 if (mode != mode_b) {
965 return gen_SwitchJmp(node);
967 assert(is_Proj(selector));
969 block = be_transform_node(get_nodes_block(node));
970 dbgi = get_irn_dbg_info(node);
971 flag_node = be_transform_node(get_Proj_pred(selector));
973 return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector));
976 static tarval *fpa_imm[3][fpa_max];
980 * Check, if a floating point tarval is an fpa immediate, i.e.
981 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
983 static int is_fpa_immediate(tarval *tv)
985 ir_mode *mode = get_tarval_mode(tv);
988 switch (get_mode_size_bits(mode)) {
999 if (tarval_is_negative(tv)) {
1000 tv = tarval_neg(tv);
1004 for (j = 0; j < fpa_max; ++j) {
1005 if (tv == fpa_imm[i][j])
1012 static ir_node *gen_Const(ir_node *node)
1014 ir_node *block = be_transform_node(get_nodes_block(node));
1015 ir_mode *mode = get_irn_mode(node);
1016 dbg_info *dbg = get_irn_dbg_info(node);
1018 if (mode_is_float(mode)) {
1019 env_cg->have_fp_insn = 1;
1020 if (USE_FPA(env_cg->isa)) {
1021 tarval *tv = get_Const_tarval(node);
1023 int imm = is_fpa_immediate(tv);
1025 if (imm != fpa_max) {
1027 node = new_bd_arm_fpaMvf_i(dbg, block, mode, imm);
1029 node = new_bd_arm_fpaMnf_i(dbg, block, mode, -imm);
1034 node = new_bd_arm_fpaConst(dbg, block, tv);
1036 be_dep_on_frame(node);
1038 } else if (USE_VFP(env_cg->isa)) {
1039 assert(mode != mode_E && "IEEE Extended FP not supported");
1040 panic("VFP not supported yet");
1042 panic("Softfloat not supported yet");
1045 return create_const_graph(node, block);
1048 static ir_node *gen_SymConst(ir_node *node)
1050 ir_node *block = be_transform_node(get_nodes_block(node));
1051 ir_entity *entity = get_SymConst_entity(node);
1052 dbg_info *dbgi = get_irn_dbg_info(node);
1055 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
1056 be_dep_on_frame(new_node);
1060 static ir_node *gen_CopyB(ir_node *node)
1062 ir_node *block = be_transform_node(get_nodes_block(node));
1063 ir_node *src = get_CopyB_src(node);
1064 ir_node *new_src = be_transform_node(src);
1065 ir_node *dst = get_CopyB_dst(node);
1066 ir_node *new_dst = be_transform_node(dst);
1067 ir_node *mem = get_CopyB_mem(node);
1068 ir_node *new_mem = be_transform_node(mem);
1069 dbg_info *dbg = get_irn_dbg_info(node);
1070 int size = get_type_size_bytes(get_CopyB_type(node));
1074 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
1075 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
1077 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1078 new_bd_arm_EmptyReg(dbg, block),
1079 new_bd_arm_EmptyReg(dbg, block),
1080 new_bd_arm_EmptyReg(dbg, block),
1084 static ir_node *gen_Proj_Load(ir_node *node)
1086 ir_node *load = get_Proj_pred(node);
1087 ir_node *new_load = be_transform_node(load);
1088 dbg_info *dbgi = get_irn_dbg_info(node);
1089 long proj = get_Proj_proj(node);
1091 /* renumber the proj */
1092 switch (get_arm_irn_opcode(new_load)) {
1094 /* handle all gp loads equal: they have the same proj numbers. */
1095 if (proj == pn_Load_res) {
1096 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1097 } else if (proj == pn_Load_M) {
1098 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1101 case iro_arm_fpaLdf:
1102 if (proj == pn_Load_res) {
1103 ir_mode *mode = get_Load_mode(load);
1104 return new_rd_Proj(dbgi, new_load, mode, pn_arm_fpaLdf_res);
1105 } else if (proj == pn_Load_M) {
1106 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_fpaLdf_M);
1112 panic("Unsupported Proj from Load");
1115 static ir_node *gen_Proj_CopyB(ir_node *node)
1117 ir_node *pred = get_Proj_pred(node);
1118 ir_node *new_pred = be_transform_node(pred);
1119 dbg_info *dbgi = get_irn_dbg_info(node);
1120 long proj = get_Proj_proj(node);
1124 if (is_arm_CopyB(new_pred)) {
1125 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1131 panic("Unsupported Proj from CopyB");
1134 static ir_node *gen_Proj_Quot(ir_node *node)
1136 ir_node *pred = get_Proj_pred(node);
1137 ir_node *new_pred = be_transform_node(pred);
1138 dbg_info *dbgi = get_irn_dbg_info(node);
1139 ir_mode *mode = get_irn_mode(node);
1140 long proj = get_Proj_proj(node);
1144 if (is_arm_fpaDvf(new_pred)) {
1145 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaDvf_M);
1146 } else if (is_arm_fpaRdf(new_pred)) {
1147 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaRdf_M);
1148 } else if (is_arm_fpaFdv(new_pred)) {
1149 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaFdv_M);
1150 } else if (is_arm_fpaFrd(new_pred)) {
1151 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_fpaFrd_M);
1155 if (is_arm_fpaDvf(new_pred)) {
1156 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaDvf_res);
1157 } else if (is_arm_fpaRdf(new_pred)) {
1158 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaRdf_res);
1159 } else if (is_arm_fpaFdv(new_pred)) {
1160 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaFdv_res);
1161 } else if (is_arm_fpaFrd(new_pred)) {
1162 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_fpaFrd_res);
1168 panic("Unsupported Proj from Quot");
1172 * Transform the Projs from a Cmp.
1174 static ir_node *gen_Proj_Cmp(ir_node *node)
1177 /* we should only be here in case of a Mux node */
1181 static ir_node *gen_Proj_Start(ir_node *node)
1183 ir_node *block = get_nodes_block(node);
1184 ir_node *new_block = be_transform_node(block);
1185 ir_node *barrier = be_transform_node(get_Proj_pred(node));
1186 long proj = get_Proj_proj(node);
1188 switch ((pn_Start) proj) {
1189 case pn_Start_X_initial_exec:
1190 /* we exchange the ProjX with a jump */
1191 return new_bd_arm_Jmp(NULL, new_block);
1194 return new_r_Proj(barrier, mode_M, 0);
1196 case pn_Start_T_args:
1200 case pn_Start_P_frame_base:
1201 return be_prolog_get_reg_value(abihelper, sp_reg);
1203 case pn_Start_P_tls:
1204 return new_bd_arm_LdTls(NULL, new_block);
1209 panic("unexpected start proj: %ld\n", proj);
1212 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1214 long pn = get_Proj_proj(node);
1215 const reg_or_stackslot_t *param;
1217 /* Proj->Proj->Start must be a method argument */
1218 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1220 param = &cconv->parameters[pn];
1222 if (param->reg0 != NULL) {
1223 /* argument transmitted in register */
1224 return be_prolog_get_reg_value(abihelper, param->reg0);
1226 /* argument transmitted on stack */
1227 ir_graph *irg = get_irn_irg(node);
1228 ir_node *block = get_nodes_block(node);
1229 ir_node *new_block = be_transform_node(block);
1230 ir_node *fp = get_irg_frame(irg);
1231 ir_node *mem = be_prolog_get_memory(abihelper);
1232 ir_mode *mode = get_type_mode(param->type);
1233 ir_node *load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1234 param->entity, 0, 0, true);
1235 ir_node *value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1236 set_irn_pinned(load, op_pin_state_floats);
1243 * Finds number of output value of a mode_T node which is constrained to
1244 * a single specific register.
1246 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1248 int n_outs = arch_irn_get_n_outs(node);
1251 for (o = 0; o < n_outs; ++o) {
1252 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1253 if (req == reg->single_req)
1259 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1261 long pn = get_Proj_proj(node);
1262 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1263 ir_node *new_call = be_transform_node(call);
1264 ir_type *function_type = get_Call_type(call);
1265 calling_convention_t *cconv = decide_calling_convention(function_type);
1266 const reg_or_stackslot_t *res = &cconv->results[pn];
1270 /* TODO 64bit modes */
1271 assert(res->reg0 != NULL && res->reg1 == NULL);
1272 regn = find_out_for_reg(new_call, res->reg0);
1274 panic("Internal error in calling convention for return %+F", node);
1276 mode = res->reg0->reg_class->mode;
1278 free_calling_convention(cconv);
1280 return new_r_Proj(new_call, mode, regn);
1283 static ir_node *gen_Proj_Call(ir_node *node)
1285 long pn = get_Proj_proj(node);
1286 ir_node *call = get_Proj_pred(node);
1287 ir_node *new_call = be_transform_node(call);
1289 switch ((pn_Call) pn) {
1291 return new_r_Proj(new_call, mode_M, 0);
1292 case pn_Call_X_regular:
1293 case pn_Call_X_except:
1294 case pn_Call_T_result:
1295 case pn_Call_P_value_res_base:
1299 panic("Unexpected Call proj %ld\n", pn);
1303 * Transform a Proj node.
1305 static ir_node *gen_Proj(ir_node *node)
1307 ir_node *pred = get_Proj_pred(node);
1308 long proj = get_Proj_proj(node);
1310 switch (get_irn_opcode(pred)) {
1312 if (proj == pn_Store_M) {
1313 return be_transform_node(pred);
1315 panic("Unsupported Proj from Store");
1318 return gen_Proj_Load(node);
1320 return gen_Proj_Call(node);
1322 return gen_Proj_CopyB(node);
1324 return gen_Proj_Quot(node);
1326 return gen_Proj_Cmp(node);
1328 return gen_Proj_Start(node);
1331 return be_duplicate_node(node);
1333 ir_node *pred_pred = get_Proj_pred(pred);
1334 if (is_Call(pred_pred)) {
1335 return gen_Proj_Proj_Call(node);
1336 } else if (is_Start(pred_pred)) {
1337 return gen_Proj_Proj_Start(node);
1342 panic("code selection didn't expect Proj after %+F\n", pred);
1346 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1348 static inline ir_node *create_const(ir_node **place,
1349 create_const_node_func func,
1350 const arch_register_t* reg)
1352 ir_node *block, *res;
1357 block = get_irg_start_block(env_cg->irg);
1358 res = func(NULL, block);
1359 arch_set_irn_register(res, reg);
1364 static ir_node *gen_Unknown(ir_node *node)
1366 ir_node *block = get_nodes_block(node);
1367 ir_node *new_block = be_transform_node(block);
1368 dbg_info *dbgi = get_irn_dbg_info(node);
1370 /* just produce a 0 */
1371 ir_mode *mode = get_irn_mode(node);
1372 if (mode_is_float(mode)) {
1373 tarval *tv = get_mode_null(mode);
1374 ir_node *node = new_bd_arm_fpaConst(dbgi, new_block, tv);
1375 be_dep_on_frame(node);
1377 } else if (mode_needs_gp_reg(mode)) {
1378 return create_const_graph_value(dbgi, new_block, 0);
1381 panic("Unexpected Unknown mode");
1385 * Produces the type which sits between the stack args and the locals on the
1386 * stack. It will contain the return address and space to store the old base
1388 * @return The Firm type modeling the ABI between type.
1390 static ir_type *arm_get_between_type(void)
1392 static ir_type *between_type = NULL;
1394 if (between_type == NULL) {
1395 between_type = new_type_class(new_id_from_str("arm_between_type"));
1396 set_type_size_bytes(between_type, 0);
1399 return between_type;
1402 static void create_stacklayout(ir_graph *irg)
1404 ir_entity *entity = get_irg_entity(irg);
1405 ir_type *function_type = get_entity_type(entity);
1406 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1411 /* calling conventions must be decided by now */
1412 assert(cconv != NULL);
1414 /* construct argument type */
1415 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1416 n_params = get_method_n_params(function_type);
1417 for (p = 0; p < n_params; ++p) {
1418 reg_or_stackslot_t *param = &cconv->parameters[p];
1422 if (param->type == NULL)
1425 snprintf(buf, sizeof(buf), "param_%d", p);
1426 id = new_id_from_str(buf);
1427 param->entity = new_entity(arg_type, id, param->type);
1428 set_entity_offset(param->entity, param->offset);
1431 /* TODO: what about external functions? we don't know most of the stack
1432 * layout for them. And probably don't need all of this... */
1433 memset(layout, 0, sizeof(*layout));
1435 layout->frame_type = get_irg_frame_type(irg);
1436 layout->between_type = arm_get_between_type();
1437 layout->arg_type = arg_type;
1438 layout->param_map = NULL; /* TODO */
1439 layout->initial_offset = 0;
1440 layout->initial_bias = 0;
1441 layout->stack_dir = -1;
1442 layout->sp_relative = true;
1444 assert(N_FRAME_TYPES == 3);
1445 layout->order[0] = layout->frame_type;
1446 layout->order[1] = layout->between_type;
1447 layout->order[2] = layout->arg_type;
1451 * transform the start node to the prolog code + initial barrier
1453 static ir_node *gen_Start(ir_node *node)
1455 ir_graph *irg = get_irn_irg(node);
1456 ir_entity *entity = get_irg_entity(irg);
1457 ir_type *function_type = get_entity_type(entity);
1458 ir_node *block = get_nodes_block(node);
1459 ir_node *new_block = be_transform_node(block);
1460 dbg_info *dbgi = get_irn_dbg_info(node);
1467 /* stackpointer is important at function prolog */
1468 be_prolog_add_reg(abihelper, sp_reg,
1469 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1470 /* function parameters in registers */
1471 for (i = 0; i < get_method_n_params(function_type); ++i) {
1472 const reg_or_stackslot_t *param = &cconv->parameters[i];
1473 if (param->reg0 != NULL)
1474 be_prolog_add_reg(abihelper, param->reg0, 0);
1475 if (param->reg1 != NULL)
1476 be_prolog_add_reg(abihelper, param->reg1, 0);
1478 /* announce that we need the values of the callee save regs */
1479 for (i = 0; i < (int) (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
1480 be_prolog_add_reg(abihelper, callee_saves[i], 0);
1483 start = be_prolog_create_start(abihelper, dbgi, new_block);
1484 sp = be_prolog_get_reg_value(abihelper, sp_reg);
1485 incsp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
1486 be_prolog_set_reg_value(abihelper, sp_reg, incsp);
1487 barrier = be_prolog_create_barrier(abihelper, new_block);
1492 static ir_node *get_stack_pointer_for(ir_node *node)
1494 /* get predecessor in stack_order list */
1495 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1496 ir_node *stack_pred_transformed;
1499 if (stack_pred == NULL) {
1500 /* first stack user in the current block. We can simply use the
1501 * initial sp_proj for it */
1502 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1506 stack_pred_transformed = be_transform_node(stack_pred);
1507 stack = pmap_get(node_to_stack, stack_pred);
1508 if (stack == NULL) {
1509 return get_stack_pointer_for(stack_pred);
1516 * transform a Return node into epilogue code + return statement
1518 static ir_node *gen_Return(ir_node *node)
1520 ir_node *block = get_nodes_block(node);
1521 ir_node *new_block = be_transform_node(block);
1522 dbg_info *dbgi = get_irn_dbg_info(node);
1523 ir_node *mem = get_Return_mem(node);
1524 ir_node *new_mem = be_transform_node(mem);
1525 int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
1526 ir_node *sp_proj = get_stack_pointer_for(node);
1531 const arch_register_t *const result_regs[] = {
1532 &arm_gp_regs[REG_R0],
1533 &arm_gp_regs[REG_R1]
1536 be_epilog_begin(abihelper);
1537 be_epilog_set_memory(abihelper, new_mem);
1538 /* connect stack pointer with initial stack pointer. fix_stack phase
1539 will later serialize all stack pointer adjusting nodes */
1540 be_epilog_add_reg(abihelper, sp_reg,
1541 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1545 n_res = get_Return_n_ress(node);
1546 if (n_res > (int) (sizeof(result_regs)/sizeof(result_regs[0]))) {
1547 panic("Too many return values for arm backend (%+F)", node);
1549 for (i = 0; i < n_res; ++i) {
1550 ir_node *res_value = get_Return_res(node, i);
1551 ir_node *new_res_value = be_transform_node(res_value);
1552 const arch_register_t *reg = result_regs[i];
1553 be_epilog_add_reg(abihelper, reg, 0, new_res_value);
1556 /* connect callee saves with their values at the function begin */
1557 for (i = 0; i < n_callee_saves; ++i) {
1558 const arch_register_t *reg = callee_saves[i];
1559 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1560 be_epilog_add_reg(abihelper, reg, 0, value);
1563 /* create the barrier before the epilog code */
1564 be_epilog_create_barrier(abihelper, new_block);
1566 /* epilog code: an incsp */
1567 sp_proj = be_epilog_get_reg_value(abihelper, sp_reg);
1568 incsp = be_new_IncSP(sp_reg, new_block, sp_proj,
1569 BE_STACK_FRAME_SIZE_SHRINK, 0);
1570 be_epilog_set_reg_value(abihelper, sp_reg, incsp);
1572 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1578 static ir_node *gen_Call(ir_node *node)
1580 ir_graph *irg = get_irn_irg(node);
1581 ir_node *callee = get_Call_ptr(node);
1582 ir_node *block = get_nodes_block(node);
1583 ir_node *new_block = be_transform_node(block);
1584 ir_node *mem = get_Call_mem(node);
1585 ir_node *new_mem = be_transform_node(mem);
1586 dbg_info *dbgi = get_irn_dbg_info(node);
1587 ir_type *type = get_Call_type(node);
1588 calling_convention_t *cconv = decide_calling_convention(type);
1589 int n_params = get_Call_n_params(node);
1590 int n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
1591 /* max inputs: memory, callee, register arguments */
1592 int max_inputs = 2 + n_param_regs;
1593 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1594 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1595 struct obstack *obst = be_get_be_obst(irg);
1596 const arch_register_req_t **in_req
1597 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1601 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1602 ir_entity *entity = NULL;
1603 ir_node *incsp = NULL;
1610 assert(n_params == get_method_n_params(type));
1612 /* construct arguments */
1615 in_req[in_arity] = arch_no_register_req;
1619 for (p = 0; p < n_params; ++p) {
1620 ir_node *value = get_Call_param(node, p);
1621 ir_node *new_value = be_transform_node(value);
1622 const reg_or_stackslot_t *param = &cconv->parameters[p];
1623 const arch_register_t *reg = param->reg0;
1625 /* double not implemented yet */
1626 assert(get_mode_size_bits(get_irn_mode(value)) <= 32);
1627 assert(param->reg1 == NULL);
1630 in[in_arity] = new_value;
1631 /* this should not happen, LR cannot be a parameter register ... */
1632 assert(reg != &arm_gp_regs[REG_LR]);
1633 in_req[in_arity] = reg->single_req;
1638 if (incsp == NULL) {
1639 /* create a parameter frame */
1640 ir_node *new_frame = get_stack_pointer_for(node);
1641 incsp = be_new_IncSP(sp_reg, new_block, new_frame, cconv->param_stack_size, 1);
1643 mode = get_irn_mode(value);
1644 str = new_bd_arm_Str(dbgi, new_block, incsp, value, new_mem, mode,
1645 NULL, 0, param->offset, true);
1647 sync_ins[sync_arity++] = str;
1650 assert(in_arity <= max_inputs);
1652 /* construct memory input */
1653 if (sync_arity == 0) {
1654 in[mem_pos] = new_mem;
1655 } else if (sync_arity == 1) {
1656 in[mem_pos] = sync_ins[0];
1658 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1661 /* TODO: use a generic symconst matcher here */
1662 if (is_SymConst(callee)) {
1663 entity = get_SymConst_entity(callee);
1665 /* TODO: finish load matcher here */
1668 if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) {
1669 ir_node *load = get_Proj_pred(callee);
1670 ir_node *ptr = get_Load_ptr(load);
1671 ir_node *new_ptr = be_transform_node(ptr);
1672 ir_node *mem = get_Load_mem(load);
1673 ir_node *new_mem = be_transform_node(mem);
1674 ir_mode *mode = get_Load_mode(node);
1678 in[in_arity] = be_transform_node(callee);
1679 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1688 out_arity = 1 + n_caller_saves;
1690 if (entity != NULL) {
1691 /* TODO: use a generic symconst matcher here
1692 * so we can also handle entity+offset, etc. */
1693 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1696 * - use a proper shifter_operand matcher
1697 * - we could also use LinkLdrPC
1699 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1703 if (incsp != NULL) {
1704 /* IncSP to destroy the call stackframe */
1705 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
1707 /* if we are the last IncSP producer in a block then we have to keep
1709 * Note: This here keeps all producers which is more than necessary */
1710 add_irn_dep(incsp, res);
1713 pmap_insert(node_to_stack, node, incsp);
1716 set_arm_in_req_all(res, in_req);
1718 /* create output register reqs */
1719 arch_set_out_register_req(res, 0, arch_no_register_req);
1720 for (o = 0; o < n_caller_saves; ++o) {
1721 const arch_register_t *reg = caller_saves[o];
1722 arch_set_out_register_req(res, o+1, reg->single_req);
1725 /* copy pinned attribute */
1726 set_irn_pinned(res, get_irn_pinned(node));
1728 free_calling_convention(cconv);
1732 static ir_node *gen_Sel(ir_node *node)
1734 dbg_info *dbgi = get_irn_dbg_info(node);
1735 ir_node *block = get_nodes_block(node);
1736 ir_node *new_block = be_transform_node(block);
1737 ir_node *ptr = get_Sel_ptr(node);
1738 ir_node *new_ptr = be_transform_node(ptr);
1739 ir_entity *entity = get_Sel_entity(node);
1741 /* must be the frame pointer all other sels must have been lowered
1743 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1744 /* we should not have value types from parameters anymore - they should be
1746 assert(get_entity_owner(entity) !=
1747 get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
1749 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1753 * Change some phi modes
1755 static ir_node *gen_Phi(ir_node *node)
1757 const arch_register_req_t *req;
1758 ir_node *block = be_transform_node(get_nodes_block(node));
1759 ir_graph *irg = current_ir_graph;
1760 dbg_info *dbgi = get_irn_dbg_info(node);
1761 ir_mode *mode = get_irn_mode(node);
1764 if (mode_needs_gp_reg(mode)) {
1765 /* we shouldn't have any 64bit stuff around anymore */
1766 assert(get_mode_size_bits(mode) <= 32);
1767 /* all integer operations are on 32bit registers now */
1769 req = arm_reg_classes[CLASS_arm_gp].class_req;
1771 req = arch_no_register_req;
1774 /* phi nodes allow loops, so we use the old arguments for now
1775 * and fix this later */
1776 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
1777 get_irn_in(node) + 1);
1778 copy_node_attr(irg, node, phi);
1779 be_duplicate_deps(node, phi);
1781 arch_set_out_register_req(phi, 0, req);
1783 be_enqueue_preds(node);
1790 * Enters all transform functions into the generic pointer
1792 static void arm_register_transformers(void)
1794 be_start_transform_setup();
1796 be_set_transform_function(op_Abs, gen_Abs);
1797 be_set_transform_function(op_Add, gen_Add);
1798 be_set_transform_function(op_And, gen_And);
1799 be_set_transform_function(op_Call, gen_Call);
1800 be_set_transform_function(op_Cmp, gen_Cmp);
1801 be_set_transform_function(op_Cond, gen_Cond);
1802 be_set_transform_function(op_Const, gen_Const);
1803 be_set_transform_function(op_Conv, gen_Conv);
1804 be_set_transform_function(op_CopyB, gen_CopyB);
1805 be_set_transform_function(op_Eor, gen_Eor);
1806 be_set_transform_function(op_Jmp, gen_Jmp);
1807 be_set_transform_function(op_Load, gen_Load);
1808 be_set_transform_function(op_Minus, gen_Minus);
1809 be_set_transform_function(op_Mul, gen_Mul);
1810 be_set_transform_function(op_Not, gen_Not);
1811 be_set_transform_function(op_Or, gen_Or);
1812 be_set_transform_function(op_Phi, gen_Phi);
1813 be_set_transform_function(op_Proj, gen_Proj);
1814 be_set_transform_function(op_Quot, gen_Quot);
1815 be_set_transform_function(op_Return, gen_Return);
1816 be_set_transform_function(op_Rotl, gen_Rotl);
1817 be_set_transform_function(op_Sel, gen_Sel);
1818 be_set_transform_function(op_Shl, gen_Shl);
1819 be_set_transform_function(op_Shr, gen_Shr);
1820 be_set_transform_function(op_Shrs, gen_Shrs);
1821 be_set_transform_function(op_Start, gen_Start);
1822 be_set_transform_function(op_Store, gen_Store);
1823 be_set_transform_function(op_Sub, gen_Sub);
1824 be_set_transform_function(op_SymConst, gen_SymConst);
1825 be_set_transform_function(op_Unknown, gen_Unknown);
1829 * Initialize fpa Immediate support.
1831 static void arm_init_fpa_immediate(void)
1833 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
1834 fpa_imm[0][fpa_null] = get_mode_null(mode_F);
1835 fpa_imm[0][fpa_one] = get_mode_one(mode_F);
1836 fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
1837 fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
1838 fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
1839 fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
1840 fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
1841 fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
1843 fpa_imm[1][fpa_null] = get_mode_null(mode_D);
1844 fpa_imm[1][fpa_one] = get_mode_one(mode_D);
1845 fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
1846 fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
1847 fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
1848 fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
1849 fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
1850 fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
1852 fpa_imm[2][fpa_null] = get_mode_null(mode_E);
1853 fpa_imm[2][fpa_one] = get_mode_one(mode_E);
1854 fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
1855 fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
1856 fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
1857 fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
1858 fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
1859 fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
1863 * Transform a Firm graph into an ARM graph.
1865 void arm_transform_graph(arm_code_gen_t *cg)
1867 static int imm_initialized = 0;
1868 ir_graph *irg = cg->irg;
1869 ir_entity *entity = get_irg_entity(irg);
1870 ir_type *frame_type;
1874 if (! imm_initialized) {
1875 arm_init_fpa_immediate();
1876 imm_initialized = 1;
1878 arm_register_transformers();
1881 node_to_stack = pmap_create();
1883 assert(abihelper == NULL);
1884 abihelper = be_abihelper_prepare(irg);
1885 be_collect_stacknodes(abihelper);
1886 assert(cconv == NULL);
1887 cconv = decide_calling_convention(get_entity_type(entity));
1888 create_stacklayout(irg);
1890 be_transform_graph(cg->irg, NULL);
1892 be_abihelper_finish(abihelper);
1895 free_calling_convention(cconv);
1898 frame_type = get_irg_frame_type(irg);
1899 if (get_type_state(frame_type) == layout_undefined) {
1900 default_layout_compound_type(frame_type);
1903 pmap_destroy(node_to_stack);
1904 node_to_stack = NULL;
1906 be_add_missing_keeps(irg);
1909 void arm_init_transform(void)
1911 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");