2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
31 #include "irgraph_t.h"
42 #include "../benode_t.h"
43 #include "../beirg_t.h"
44 #include "bearch_arm_t.h"
46 #include "arm_nodes_attr.h"
48 #include "arm_transform.h"
49 #include "arm_new_nodes.h"
50 #include "arm_map_regs.h"
52 #include "gen_arm_regalloc_if.h"
57 extern ir_op *get_op_Mulh(void);
61 /****************************************************************************************************
63 * | | | | / _| | | (_)
64 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
65 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
66 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
67 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
69 ****************************************************************************************************/
71 typedef struct vals_ {
73 unsigned char values[4];
74 unsigned char shifts[4];
78 static unsigned do_rol(unsigned v, unsigned rol) {
79 return (v << rol) | (v >> (32 - rol));
83 * construct 8bit values und rot amounts for a value
85 static void gen_vals_from_word(unsigned int value, vals *result)
89 memset(result, 0, sizeof(*result));
91 /* special case: we prefer shift amount 0 */
93 result->values[0] = value;
100 unsigned v = do_rol(value, 8) & 0xFFFFFF;
109 shf = (initial + shf - 8) & 0x1F;
110 result->values[result->ops] = v;
111 result->shifts[result->ops] = shf;
114 value ^= do_rol(v, shf) >> initial;
124 * Creates a arm_Const node.
126 static ir_node *create_const_node(be_abi_irg_t *abi, ir_node *irn, ir_node *block, long value) {
127 tarval *tv = new_tarval_from_long(value, mode_Iu);
128 dbg_info *dbg = get_irn_dbg_info(irn);
129 ir_node *res = new_rd_arm_Mov_i(dbg, current_ir_graph, block, get_irn_mode(irn), tv);
130 /* ensure the const is schedules AFTER the barrier */
131 add_irn_dep(res, be_abi_get_start_barrier(abi));
136 * Creates a arm_Const_Neg node.
138 static ir_node *create_const_neg_node(be_abi_irg_t *abi, ir_node *irn, ir_node *block, long value) {
139 tarval *tv = new_tarval_from_long(value, mode_Iu);
140 dbg_info *dbg = get_irn_dbg_info(irn);
141 ir_node *res = new_rd_arm_Mvn_i(dbg, current_ir_graph, block, get_irn_mode(irn), tv);
142 add_irn_dep(res, be_abi_get_start_barrier(abi));
143 /* ensure the const is schedules AFTER the barrier */
147 #define NEW_BINOP_NODE(opname, env, op1, op2) new_rd_arm_##opname(env->dbg, current_ir_graph, env->block, op1, op2, env->mode)
150 * Encodes an immediate with shifter operand
152 static unsigned int arm_encode_imm_w_shift(unsigned int shift, unsigned int immediate) {
153 return immediate | ((shift>>1)<<8);
157 * Decode an immediate with shifter operand
159 unsigned int arm_decode_imm_w_shift(tarval *tv) {
160 unsigned l = get_tarval_long(tv);
161 unsigned rol = (l & ~0xFF) >> 7;
163 return do_rol(l & 0xFF, rol);
167 * Creates a possible DAG for an constant.
169 static ir_node *create_const_graph_value(be_abi_irg_t *abi, ir_node *irn, ir_node *block, unsigned int value) {
173 ir_mode *mode = get_irn_mode(irn);
174 dbg_info *dbg = get_irn_dbg_info(irn);
176 gen_vals_from_word(value, &v);
177 gen_vals_from_word(~value, &vn);
179 if (vn.ops < v.ops) {
181 result = create_const_neg_node(abi, irn, block, arm_encode_imm_w_shift(vn.shifts[0], vn.values[0]));
183 for (cnt = 1; cnt < vn.ops; ++cnt) {
184 tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]), mode_Iu);
185 ir_node *bic_i_node = new_rd_arm_Bic_i(dbg, current_ir_graph, block, result, mode, tv);
191 result = create_const_node(abi, irn, block, arm_encode_imm_w_shift(v.shifts[0], v.values[0]));
193 for (cnt = 1; cnt < v.ops; ++cnt) {
194 tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]), mode_Iu);
195 ir_node *orr_i_node = new_rd_arm_Or_i(dbg, current_ir_graph, block, result, mode, tv);
203 * Create a DAG constructing a given Const.
205 * @param irn a Firm const
207 static ir_node *create_const_graph(be_abi_irg_t *abi, ir_node *irn, ir_node *block) {
208 int value = get_tarval_long(get_Const_tarval(irn));
209 return create_const_graph_value(abi, irn, block, value);
214 * Creates code for a Firm Const node.
216 static ir_node *gen_Const(ir_node *irn, arm_code_gen_t *cg) {
217 ir_graph *irg = current_ir_graph;
218 ir_node *block = get_nodes_block(irn);
219 ir_mode *mode = get_irn_mode(irn);
220 dbg_info *dbg = get_irn_dbg_info(irn);
222 if (mode_is_float(mode)) {
223 if (USE_FPA(cg->isa))
224 return new_rd_arm_fpaConst(dbg, irg, block, mode, get_Const_tarval(irn));
225 else if (USE_VFP(cg->isa))
226 assert(mode != mode_E && "IEEE Extended FP not supported");
229 else if (mode_is_reference(mode))
231 return create_const_graph(cg->birg->abi, irn, block);
234 static ir_node *gen_mask(be_abi_irg_t *abi, ir_node *irn, ir_node *op, int result_bits) {
235 ir_node *block = get_nodes_block(irn);
236 unsigned mask_bits = (1 << result_bits) - 1;
237 ir_node *mask_node = create_const_graph_value(abi, irn, block, mask_bits);
238 dbg_info *dbg = get_irn_dbg_info(irn);
239 return new_rd_arm_And(dbg, current_ir_graph, block, op, mask_node, get_irn_mode(irn), ARM_SHF_NONE, NULL);
242 static ir_node *gen_sign_extension(be_abi_irg_t *abi, ir_node *irn, ir_node *op, int result_bits) {
243 ir_node *block = get_nodes_block(irn);
244 int shift_width = 32 - result_bits;
245 ir_graph *irg = current_ir_graph;
246 ir_node *shift_const_node = create_const_graph_value(abi, irn, block, shift_width);
247 dbg_info *dbg = get_irn_dbg_info(irn);
248 ir_node *lshift_node = new_rd_arm_Shl(dbg, irg, block, op, shift_const_node, get_irn_mode(op));
249 ir_node *rshift_node = new_rd_arm_Shrs(dbg, irg, block, lshift_node, shift_const_node, get_irn_mode(irn));
254 * Transforms a Conv node.
256 * @param env The transformation environment
257 * @return the created arm Conv node
259 static ir_node *gen_Conv(ir_node *irn, arm_code_gen_t *cg) {
260 ir_graph *irg = current_ir_graph;
261 ir_node *block = get_nodes_block(irn);
262 ir_node *op = get_Conv_op(irn);
263 ir_mode *in_mode = get_irn_mode(op);
264 ir_mode *out_mode = get_irn_mode(irn);
265 dbg_info *dbg = get_irn_dbg_info(irn);
267 if (in_mode == out_mode)
270 if (mode_is_float(in_mode) || mode_is_float(out_mode)) {
273 if (USE_FPA(cg->isa)) {
274 if (mode_is_float(in_mode)) {
275 if (mode_is_float(out_mode)) {
276 /* from float to float */
277 return new_rd_arm_fpaMov(dbg, irg, block, op, out_mode);
280 /* from float to int */
281 return new_rd_arm_fpaFix(dbg, irg, block, op, out_mode);
285 /* from int to float */
286 return new_rd_arm_fpaFlt(dbg, irg, block, op, out_mode);
291 else { /* complete in gp registers */
292 int in_bits = get_mode_size_bits(in_mode);
293 int out_bits = get_mode_size_bits(out_mode);
294 int in_sign = get_mode_sign(in_mode);
295 int out_sign = get_mode_sign(out_mode);
299 if (in_bits == out_bits && in_bits == 32)
303 // unsigned -> unsigned
305 // unsigned -> signed
306 // sign extension (31:16)=(15)
307 // signed -> unsigned
308 // maskieren (31:16)=0
311 if (in_bits == out_bits && out_bits < 32) {
312 if (in_sign && !out_sign) {
313 return gen_mask(cg->birg->abi, irn, op, out_bits);
315 return gen_sign_extension(cg->birg->abi, irn, op, out_bits);
320 // unsigned -> unsigned
322 // unsigned -> signed
324 // signed -> unsigned
325 // sign extension (31:16)=(15)
327 // sign extension (31:16)=(15)
328 if (in_bits < out_bits) {
330 return gen_sign_extension(cg->birg->abi, irn, op, out_bits);
337 // unsigned -> unsigned
338 // maskieren (31:16)=0
339 // unsigned -> signed
340 // maskieren (31:16)=0
341 // signed -> unsigned
342 // maskieren (31:16)=0
344 // sign extension (erledigt auch maskieren) (31:16)=(15)
345 if (in_bits > out_bits) {
346 if (in_sign && out_sign) {
347 return gen_sign_extension(cg->birg->abi, irn, op, out_bits);
349 return gen_mask(cg->birg->abi, irn, op, out_bits);
352 assert(0 && "recheck integer conversion logic!");
359 * Return true if an operand is a shifter operand
361 static int is_shifter_operand(ir_node *n, arm_shift_modifier *pmod) {
362 arm_shift_modifier mod = ARM_SHF_NONE;
365 mod = get_arm_shift_modifier(n);
368 if (mod != ARM_SHF_NONE) {
369 long v = get_tarval_long(get_arm_value(n));
377 * Creates an arm Add.
379 * @param env The transformation environment
380 * @return the created arm Add node
382 static ir_node *gen_Add(ir_node *irn, arm_code_gen_t *cg) {
383 ir_node *block = get_nodes_block(irn);
384 ir_node *op1 = get_Add_left(irn);
385 ir_node *op2 = get_Add_right(irn);
386 ir_mode *mode = get_irn_mode(irn);
387 ir_graph *irg = current_ir_graph;
390 arm_shift_modifier mod;
391 dbg_info *dbg = get_irn_dbg_info(irn);
393 if (mode_is_float(mode)) {
395 if (USE_FPA(cg->isa))
396 return new_rd_arm_fpaAdd(dbg, irg, block, op1, op2, mode);
397 else if (USE_VFP(cg->isa)) {
398 assert(mode != mode_E && "IEEE Extended FP not supported");
402 if (mode_is_numP(mode)) {
403 if (is_arm_Mov_i(op1))
404 return new_rd_arm_Add_i(dbg, irg, block, op2, mode, get_arm_value(op1));
405 if (is_arm_Mov_i(op2))
406 return new_rd_arm_Add_i(dbg, irg, block, op1, mode, get_arm_value(op2));
409 if (is_arm_Mul(op1) && get_irn_n_edges(op1) == 1) {
411 op2 = get_irn_n(op1, 1);
412 op1 = get_irn_n(op1, 0);
414 return new_rd_arm_Mla(dbg, irg, block, op1, op2, op3, mode);
416 if (is_arm_Mul(op2) && get_irn_n_edges(op2) == 1) {
418 op1 = get_irn_n(op2, 0);
419 op2 = get_irn_n(op2, 1);
421 return new_rd_arm_Mla(dbg, irg, block, op1, op2, op3, mode);
424 /* is the first a shifter */
425 v = is_shifter_operand(op1, &mod);
427 op1 = get_irn_n(op1, 0);
428 return new_rd_arm_Add(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu));
430 /* is the second a shifter */
431 v = is_shifter_operand(op2, &mod);
433 op2 = get_irn_n(op2, 0);
434 return new_rd_arm_Add(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu));
438 return new_rd_arm_Add(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL);
441 assert(0 && "unknown mode for add");
446 * Creates an arm Mul.
448 * @param env The transformation environment
449 * @return the created arm Mul node
451 static ir_node *gen_Mul(ir_node *irn, arm_code_gen_t *cg) {
452 ir_node *block = get_nodes_block(irn);
453 ir_node *op1 = get_Mul_left(irn);
454 ir_node *op2 = get_Mul_right(irn);
455 ir_mode *mode = get_irn_mode(irn);
456 ir_graph *irg = current_ir_graph;
457 dbg_info *dbg = get_irn_dbg_info(irn);
459 if (mode_is_float(mode)) {
461 if (USE_FPA(cg->isa))
462 return new_rd_arm_fpaMul(dbg, irg, block, op1, op2, mode);
463 else if (USE_VFP(cg->isa)) {
464 assert(mode != mode_E && "IEEE Extended FP not supported");
468 return new_rd_arm_Mul(dbg, irg, block, op1, op2, mode);
472 * Creates an arm floating point Div.
474 * @param env The transformation environment
475 * @return the created arm fDiv node
477 static ir_node *gen_Quot(ir_node *irn, arm_code_gen_t *cg) {
478 ir_node *block = get_nodes_block(irn);
479 ir_node *op1 = get_Quot_left(irn);
480 ir_node *op2 = get_Quot_right(irn);
481 ir_mode *mode = get_irn_mode(irn);
482 dbg_info *dbg = get_irn_dbg_info(irn);
484 assert(mode != mode_E && "IEEE Extended FP not supported");
487 if (USE_FPA(cg->isa))
488 return new_rd_arm_fpaDiv(dbg, current_ir_graph, block, op1, op2, mode);
489 else if (USE_VFP(cg->isa)) {
490 assert(mode != mode_E && "IEEE Extended FP not supported");
497 #define GEN_INT_OP(op) \
498 static ir_node *gen_ ## op(ir_node *irn, arm_code_gen_t *cg) { \
499 ir_graph *irg = current_ir_graph; \
500 ir_node *block = get_nodes_block(irn); \
501 ir_node *op1 = get_ ## op ## _left(irn); \
502 ir_node *op2 = get_ ## op ## _right(irn); \
504 arm_shift_modifier mod; \
505 ir_mode *mode = get_irn_mode(irn); \
506 dbg_info *dbg = get_irn_dbg_info(irn); \
508 if (is_arm_Mov_i(op1)) \
509 return new_rd_arm_ ## op ## _i(dbg, irg, block, op2, mode, get_arm_value(op1)); \
510 if (is_arm_Mov_i(op2)) \
511 return new_rd_arm_ ## op ## _i(dbg, irg, block, op1, mode, get_arm_value(op2)); \
512 /* is the first a shifter */ \
513 v = is_shifter_operand(op1, &mod); \
515 op1 = get_irn_n(op1, 0); \
516 return new_rd_arm_ ## op(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu)); \
518 /* is the second a shifter */ \
519 v = is_shifter_operand(op2, &mod); \
521 op2 = get_irn_n(op2, 0); \
522 return new_rd_arm_ ## op(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu)); \
525 return new_rd_arm_ ## op(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL); \
530 * Creates an arm And.
532 * @param env The transformation environment
533 * @return the created arm And node
535 static ir_node *gen_And(ir_node *irn, arm_code_gen_t *cg);
539 * Creates an arm Orr.
541 * @param env The transformation environment
542 * @return the created arm Or node
544 static ir_node *gen_Or(ir_node *irn, arm_code_gen_t *cg);
548 * Creates an arm Eor.
550 * @param env The transformation environment
551 * @return the created arm Eor node
553 static ir_node *gen_Eor(ir_node *irn, arm_code_gen_t *cg);
557 * Creates an arm Sub.
559 * @param env The transformation environment
560 * @return the created arm Sub node
562 static ir_node *gen_Sub(ir_node *irn, arm_code_gen_t *cg) {
563 ir_node *block = get_nodes_block(irn);
564 ir_node *op1 = get_Sub_left(irn);
565 ir_node *op2 = get_Sub_right(irn);
567 arm_shift_modifier mod;
568 ir_mode *mode = get_irn_mode(irn);
569 ir_graph *irg = current_ir_graph;
570 dbg_info *dbg = get_irn_dbg_info(irn);
572 if (mode_is_float(mode)) {
574 if (USE_FPA(cg->isa))
575 return new_rd_arm_fpaSub(dbg, irg, block, op1, op2, mode);
576 else if (USE_VFP(cg->isa)) {
577 assert(mode != mode_E && "IEEE Extended FP not supported");
581 if (mode_is_numP(mode)) {
582 if (is_arm_Mov_i(op1))
583 return new_rd_arm_Rsb_i(dbg, irg, block, op2, mode, get_arm_value(op1));
584 if (is_arm_Mov_i(op2))
585 return new_rd_arm_Sub_i(dbg, irg, block, op1, mode, get_arm_value(op2));
587 /* is the first a shifter */
588 v = is_shifter_operand(op1, &mod);
590 op1 = get_irn_n(op1, 0);
591 return new_rd_arm_Rsb(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu));
593 /* is the second a shifter */
594 v = is_shifter_operand(op2, &mod);
596 op2 = get_irn_n(op2, 0);
597 return new_rd_arm_Sub(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu));
600 return new_rd_arm_Sub(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL);
602 assert(0 && "unknown mode for sub");
607 * Creates an arm Shl.
609 * @param env The transformation environment
610 * @return the created arm Shl node
612 static ir_node *gen_Shl(ir_node *irn, arm_code_gen_t *cg) {
614 ir_node *block = get_nodes_block(irn);
615 ir_node *op1 = get_Shl_left(irn);
616 ir_node *op2 = get_Shl_right(irn);
617 ir_mode *mode = get_irn_mode(irn);
618 ir_graph *irg = current_ir_graph;
619 dbg_info *dbg = get_irn_dbg_info(irn);
621 if (is_arm_Mov_i(op2)) {
622 result = new_rd_arm_Mov(dbg, irg, block, op1, mode, ARM_SHF_LSL, get_arm_value(op2));
624 result = new_rd_arm_Shl(dbg, irg, block, op1, op2, mode);
630 * Creates an arm Shr.
632 * @param env The transformation environment
633 * @return the created arm Shr node
635 static ir_node *gen_Shr(ir_node *irn, arm_code_gen_t *cg) {
637 ir_node *block = get_nodes_block(irn);
638 ir_node *op1 = get_Shr_left(irn);
639 ir_node *op2 = get_Shr_right(irn);
640 ir_mode *mode = get_irn_mode(irn);
641 ir_graph *irg = current_ir_graph;
642 dbg_info *dbg = get_irn_dbg_info(irn);
644 if (is_arm_Mov_i(op2)) {
645 result = new_rd_arm_Mov(dbg, irg, block, op1, mode, ARM_SHF_LSR, get_arm_value(op2));
647 result = new_rd_arm_Shr(dbg, irg, block, op1, op2, mode);
653 * Creates an arm Shrs.
655 * @param env The transformation environment
656 * @return the created arm Shrs node
658 static ir_node *gen_Shrs(ir_node *irn, arm_code_gen_t *cg) {
660 ir_node *block = get_nodes_block(irn);
661 ir_node *op1 = get_Shrs_left(irn);
662 ir_node *op2 = get_Shrs_right(irn);
663 ir_mode *mode = get_irn_mode(irn);
664 dbg_info *dbg = get_irn_dbg_info(irn);
666 if (is_arm_Mov_i(op2)) {
667 result = new_rd_arm_Mov(dbg, current_ir_graph, block, op1, mode, ARM_SHF_ASR, get_arm_value(op2));
669 result = new_rd_arm_Shrs(dbg, current_ir_graph, block, op1, op2, mode);
675 * Transforms a Not node.
677 * @param env The transformation environment
678 * @return the created arm Not node
680 static ir_node *gen_Not(ir_node *irn, arm_code_gen_t *cg) {
681 ir_node *block = get_nodes_block(irn);
682 ir_node *op = get_Not_op(irn);
684 arm_shift_modifier mod = ARM_SHF_NONE;
686 dbg_info *dbg = get_irn_dbg_info(irn);
688 v = is_shifter_operand(op, &mod);
690 op = get_irn_n(op, 0);
691 tv = new_tarval_from_long(v, mode_Iu);
693 return new_rd_arm_Mvn(dbg, current_ir_graph, block, op, get_irn_mode(irn), mod, tv);
697 * Transforms an Abs node.
699 * @param env The transformation environment
700 * @return the created arm Abs node
702 static ir_node *gen_Abs(ir_node *irn, arm_code_gen_t *cg) {
703 ir_node *block = get_nodes_block(irn);
704 ir_node *op = get_Abs_op(irn);
705 ir_mode *mode = get_irn_mode(irn);
706 dbg_info *dbg = get_irn_dbg_info(irn);
708 if (mode_is_float(mode)) {
710 if (USE_FPA(cg->isa))
711 return new_rd_arm_fpaAbs(dbg, current_ir_graph, block, op, mode);
712 else if (USE_VFP(cg->isa)) {
713 assert(mode != mode_E && "IEEE Extended FP not supported");
717 return new_rd_arm_Abs(dbg, current_ir_graph, block, op, mode);
721 * Transforms a Minus node.
723 * @param env The transformation environment
724 * @return the created arm Minus node
726 static ir_node *gen_Minus(ir_node *irn, arm_code_gen_t *cg) {
727 ir_node *block = get_nodes_block(irn);
728 ir_node *op = get_Minus_op(irn);
729 ir_mode *mode = get_irn_mode(irn);
730 ir_graph *irg = current_ir_graph;
731 dbg_info *dbg = get_irn_dbg_info(irn);
733 if (mode_is_float(mode)) {
735 if (USE_FPA(cg->isa))
736 return new_rd_arm_fpaMnv(dbg, irg, block, op, mode);
737 else if (USE_VFP(cg->isa)) {
738 assert(mode != mode_E && "IEEE Extended FP not supported");
742 return new_rd_arm_Rsb_i(dbg, irg, block, op, mode, get_mode_null(mode));
748 * @param mod the debug module
749 * @param block the block the new node should belong to
750 * @param node the ir Load node
751 * @param mode node mode
752 * @return the created arm Load node
754 static ir_node *gen_Load(ir_node *irn, arm_code_gen_t *cg) {
755 ir_node *block = get_nodes_block(irn);
756 ir_mode *mode = get_Load_mode(irn);
757 ir_graph *irg = current_ir_graph;
758 dbg_info *dbg = get_irn_dbg_info(irn);
760 if (mode_is_float(mode)) {
762 if (USE_FPA(cg->isa))
763 return new_rd_arm_fpaLdf(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn),
765 else if (USE_VFP(cg->isa)) {
766 assert(mode != mode_E && "IEEE Extended FP not supported");
770 if (mode == mode_Bu) {
771 return new_rd_arm_Loadb(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
773 if (mode == mode_Bs) {
774 return new_rd_arm_Loadbs(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
776 if (mode == mode_Hu) {
777 return new_rd_arm_Loadh(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
779 if (mode == mode_Hs) {
780 return new_rd_arm_Loadhs(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
782 if (mode_is_reference(mode)) {
783 return new_rd_arm_Load(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
785 return new_rd_arm_Load(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
789 * Transforms a Store.
791 * @param mod the debug module
792 * @param block the block the new node should belong to
793 * @param node the ir Store node
794 * @param mode node mode
795 * @return the created arm Store node
797 static ir_node *gen_Store(ir_node *irn, arm_code_gen_t *cg) {
798 ir_node *block = get_nodes_block(irn);
799 ir_mode *mode = get_irn_mode(get_Store_value(irn));
800 ir_graph *irg = current_ir_graph;
801 dbg_info *dbg = get_irn_dbg_info(irn);
803 assert(mode != mode_E && "IEEE Extended FP not supported");
804 if (mode_is_float(mode)) {
806 if (USE_FPA(cg->isa))
807 return new_rd_arm_fpaStf(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn),
808 get_Store_mem(irn), get_irn_mode(get_Store_value(irn)));
809 else if (USE_VFP(cg->isa)) {
810 assert(mode != mode_E && "IEEE Extended FP not supported");
814 if (mode == mode_Bu) {
815 return new_rd_arm_Storeb(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
817 if (mode == mode_Bs) {
818 return new_rd_arm_Storebs(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
820 if (mode == mode_Hu) {
821 return new_rd_arm_Storeh(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
823 if (mode == mode_Hs) {
824 return new_rd_arm_Storehs(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
826 return new_rd_arm_Store(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
830 static ir_node *gen_Cond(ir_node *irn, arm_code_gen_t *cg) {
831 ir_node *result = NULL;
832 ir_node *selector = get_Cond_selector(irn);
833 ir_node *block = get_nodes_block(irn);
834 ir_graph *irg = current_ir_graph;
835 dbg_info *dbg = get_irn_dbg_info(irn);
837 if ( get_irn_mode(selector) == mode_b ) {
839 ir_node *proj_node = get_Cond_selector(irn);
840 ir_node *cmp_node = get_Proj_pred(proj_node);
841 ir_node *op1 = get_Cmp_left(cmp_node);
842 ir_node *op2 = get_Cmp_right(cmp_node);
843 result = new_rd_arm_CondJmp(dbg, irg, block, op1, op2, get_Proj_proj(proj_node));
846 ir_node *op = get_irn_n(irn, 0);
847 ir_node *const_graph;
852 const ir_edge_t *edge;
862 foreach_out_edge(irn, edge) {
863 proj = get_edge_src_irn(edge);
864 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
866 pn = get_Proj_proj(proj);
868 min = pn<min ? pn : min;
869 max = pn>max ? pn : max;
872 norm_max = max - translation;
873 norm_min = min - translation;
875 n_projs = norm_max + 1;
876 projs = xcalloc(n_projs , sizeof(ir_node*));
879 foreach_out_edge(irn, edge) {
880 proj = get_edge_src_irn(edge);
881 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
883 pn = get_Proj_proj(proj) - translation;
884 set_Proj_proj(proj, pn);
888 const_node = new_rd_Const(dbg, irg, block, mode_Iu, new_tarval_from_long(translation, mode_Iu));
889 const_graph = gen_Const(const_node, cg);
890 sub = new_rd_arm_Sub(dbg, irg, block, op, const_graph, get_irn_mode(op), ARM_SHF_NONE, NULL);
891 result = new_rd_arm_SwitchJmp(dbg, irg, block, sub,
892 n_projs, get_Cond_defaultProj(irn)-translation);
898 * Returns the name of a SymConst.
899 * @param symc the SymConst
900 * @return name of the SymConst
902 static ident *get_sc_ident(ir_node *symc) {
905 switch (get_SymConst_kind(symc)) {
906 case symconst_addr_name:
907 return get_SymConst_name(symc);
909 case symconst_addr_ent:
910 ent = get_SymConst_entity(symc);
911 mark_entity_visited(ent);
912 return get_entity_ld_ident(ent);
915 assert(0 && "Unsupported SymConst");
922 * Transforms a SymConst node.
924 static ir_node *gen_SymConst(ir_node *irn, arm_code_gen_t *cg) {
925 ir_node *block = get_nodes_block(irn);
926 ir_mode *mode = get_irn_mode(irn);
927 dbg_info *dbg = get_irn_dbg_info(irn);
928 return new_rd_arm_SymConst(dbg, current_ir_graph, block, mode, get_sc_ident(irn));
934 * Transforms a CopyB node.
936 * @param env The transformation environment
937 * @return The transformed node.
939 static ir_node *gen_CopyB(ir_node *irn, arm_code_gen_t *cg) {
941 dbg_info *dbg = get_irn_dbg_info(irn);
942 ir_mode *mode = get_irn_mode(irn);
943 ir_node *src = get_CopyB_src(irn);
944 ir_node *dst = get_CopyB_dst(irn);
945 ir_node *mem = get_CopyB_mem(irn);
946 ir_node *block = get_nodes_block(irn);
947 int size = get_type_size_bytes(get_CopyB_type(irn));
948 ir_graph *irg = current_ir_graph;
952 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, src);
953 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, dst);
955 res = new_rd_arm_CopyB( dbg, irg, block, dst_copy, src_copy, new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), mem, mode);
956 set_arm_value(res, new_tarval_from_long(size, mode_Iu));
965 /********************************************
968 * | |__ ___ _ __ ___ __| | ___ ___
969 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
970 * | |_) | __/ | | | (_) | (_| | __/\__ \
971 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
973 ********************************************/
976 * Return an expanding stack offset.
977 * Note that function is called in the transform phase
978 * where the stack offsets are still relative regarding
979 * the first (frame allocating) IncSP.
980 * However this is exactly what we want because frame
981 * access must be done relative the the fist IncSP ...
983 static int get_sp_expand_offset(ir_node *inc_sp) {
984 int offset = be_get_IncSP_offset(inc_sp);
986 if (offset == BE_STACK_FRAME_SIZE_EXPAND)
993 static ir_node *gen_StackParam(ir_node *irn, arm_code_gen_t *cg) {
994 ir_node *new_op = NULL;
995 ir_node *block = get_nodes_block(irn);
996 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
997 ir_node *mem = new_rd_NoMem(env->irg);
998 ir_node *ptr = get_irn_n(irn, 0);
999 ir_entity *ent = be_get_frame_entity(irn);
1000 ir_mode *mode = env->mode;
1002 // /* If the StackParam has only one user -> */
1003 // /* put it in the Block where the user resides */
1004 // if (get_irn_n_edges(node) == 1) {
1005 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1008 if (mode_is_float(mode)) {
1009 if (USE_SSE2(env->cg))
1010 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1012 env->cg->used_x87 = 1;
1013 new_op = new_rd_ia32_vfld(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1017 new_op = new_rd_ia32_Load(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1020 set_ia32_frame_ent(new_op, ent);
1021 set_ia32_use_frame(new_op);
1023 set_ia32_am_support(new_op, ia32_am_Source);
1024 set_ia32_op_type(new_op, ia32_AddrModeS);
1025 set_ia32_am_flavour(new_op, ia32_B);
1026 set_ia32_ls_mode(new_op, mode);
1028 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1030 return new_rd_Proj(env->dbg, env->irg, block, new_op, mode, 0);
1035 * Transforms a FrameAddr into an ia32 Add.
1037 static ir_node *gen_be_FrameAddr(ir_node *irn, arm_code_gen_t *cg) {
1038 ir_node *block = get_nodes_block(irn);
1039 ir_entity *ent = be_get_frame_entity(irn);
1040 int offset = get_entity_offset(ent);
1041 ir_node *op = get_irn_n(irn, 0);
1043 ir_mode *mode = get_irn_mode(irn);
1044 dbg_info *dbg = get_irn_dbg_info(irn);
1046 if (be_is_IncSP(op)) {
1047 /* BEWARE: we get an offset which is absolute from an offset that
1048 is relative. Both must be merged */
1049 offset += get_sp_expand_offset(op);
1051 cnst = create_const_graph_value(cg->birg->abi, irn, block, (unsigned)offset);
1052 if (is_arm_Mov_i(cnst))
1053 return new_rd_arm_Add_i(dbg, current_ir_graph, block, op, mode, get_arm_value(cnst));
1054 return new_rd_arm_Add(dbg, current_ir_graph, block, op, cnst, mode, ARM_SHF_NONE, NULL);
1059 * Transforms a FrameLoad into an ia32 Load.
1061 static ir_node *gen_FrameLoad(ir_node *irn, arm_code_gen_t *cg) {
1062 ir_node *new_op = NULL;
1063 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1064 ir_node *mem = get_irn_n(irn, 0);
1065 ir_node *ptr = get_irn_n(irn, 1);
1066 ir_entity *ent = be_get_frame_entity(irn);
1067 ir_mode *mode = get_type_mode(get_entity_type(ent));
1069 if (mode_is_float(mode)) {
1070 if (USE_SSE2(env->cg))
1071 new_op = new_rd_ia32_fLoad(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
1073 env->cg->used_x87 = 1;
1074 new_op = new_rd_ia32_vfld(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
1078 new_op = new_rd_ia32_Load(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
1081 set_ia32_frame_ent(new_op, ent);
1082 set_ia32_use_frame(new_op);
1084 set_ia32_am_support(new_op, ia32_am_Source);
1085 set_ia32_op_type(new_op, ia32_AddrModeS);
1086 set_ia32_am_flavour(new_op, ia32_B);
1087 set_ia32_ls_mode(new_op, mode);
1089 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1097 * Transforms a FrameStore into an ia32 Store.
1099 static ir_node *gen_FrameStore(ir_node *irn, arm_code_gen_t *cg) {
1100 ir_node *new_op = NULL;
1101 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1102 ir_node *mem = get_irn_n(irn, 0);
1103 ir_node *ptr = get_irn_n(irn, 1);
1104 ir_node *val = get_irn_n(irn, 2);
1105 ir_entity *ent = be_get_frame_entity(irn);
1106 ir_mode *mode = get_irn_mode(val);
1108 if (mode_is_float(mode)) {
1109 if (USE_SSE2(env->cg))
1110 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1112 env->cg->used_x87 = 1;
1113 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1116 else if (get_mode_size_bits(mode) == 8) {
1117 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1120 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1123 set_ia32_frame_ent(new_op, ent);
1124 set_ia32_use_frame(new_op);
1126 set_ia32_am_support(new_op, ia32_am_Dest);
1127 set_ia32_op_type(new_op, ia32_AddrModeD);
1128 set_ia32_am_flavour(new_op, ia32_B);
1129 set_ia32_ls_mode(new_op, mode);
1131 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1138 // static ir_node *gen_be_Copy(ir_node *irn, arm_code_gen_t *cg) {
1139 // return new_rd_arm_Copy(env->dbg, env->irg, env->block, op, env->mode);
1142 /*********************************************************
1145 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1146 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1147 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1148 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1150 *********************************************************/
1153 * move constants out of the start block
1155 void arm_move_consts(ir_node *node, void *env) {
1156 arm_code_gen_t *cg = env;
1163 for (i = get_irn_arity(node) - 1; i >= 0; --i) {
1164 ir_node *pred = get_irn_n(node,i);
1165 ir_opcode pred_code = get_irn_opcode(pred);
1166 if (pred_code == iro_Const) {
1167 ir_node *const_graph;
1168 const_graph = create_const_graph(cg->birg->abi, pred, get_nodes_block(get_irn_n(get_nodes_block(node),i)));
1169 set_irn_n(node, i, const_graph);
1171 else if (pred_code == iro_SymConst) {
1172 /* FIXME: in general, SymConst always require a load, so it
1173 might be better to place them into the first real block
1174 and let the spiller rematerialize them. */
1175 ident *id = get_sc_ident(pred);
1176 ir_node *symconst_node;
1177 symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
1178 current_ir_graph, get_nodes_block(get_irn_n(get_nodes_block(node),i)),
1179 get_irn_mode(pred), id);
1180 set_irn_n(node, i, symconst_node);
1185 for (i = 0; i < get_irn_arity(node); i++) {
1186 ir_node *pred = get_irn_n(node,i);
1187 ir_opcode pred_code = get_irn_opcode(pred);
1188 if (pred_code == iro_Const) {
1189 ir_node *const_graph;
1190 const_graph = create_const_graph(cg->birg->abi, pred, get_nodes_block(node));
1191 set_irn_n(node, i, const_graph);
1192 } else if (pred_code == iro_SymConst) {
1193 ident *id = get_sc_ident(pred);
1194 ir_node *symconst_node;
1195 symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
1196 current_ir_graph, get_nodes_block(node),
1197 get_irn_mode(pred), id);
1198 set_irn_n(node, i, symconst_node);
1205 * the BAD transformer.
1207 static ir_node *bad_transform(ir_node *irn, arm_code_gen_t *cg) {
1208 ir_fprintf(stderr, "Not implemented: %+F\n", irn);
1214 * Enters all transform functions into the generic pointer
1216 void arm_register_transformers(void) {
1217 ir_op *op_Max, *op_Min, *op_Mulh;
1219 /* first clear the generic function pointer for all ops */
1220 clear_irp_opcodes_generic_func();
1222 #define FIRM_OP(a) op_##a->ops.generic = (op_func)gen_##a
1223 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
1226 FIRM_OP(Add); // done
1227 FIRM_OP(Mul); // done
1228 FIRM_OP(Quot); // done
1229 FIRM_OP(And); // done
1230 FIRM_OP(Or); // done
1231 FIRM_OP(Eor); // done
1233 FIRM_OP(Sub); // done
1234 FIRM_OP(Shl); // done
1235 FIRM_OP(Shr); // done
1236 FIRM_OP(Shrs); // done
1238 FIRM_OP(Minus); // done
1239 FIRM_OP(Not); // done
1240 FIRM_OP(Abs); // done
1242 FIRM_OP(CopyB); // done
1243 FIRM_OP(Const); // TODO: floating point consts
1244 FIRM_OP(Conv); // TODO: floating point conversions
1246 FIRM_OP(Load); // done
1247 FIRM_OP(Store); // done
1250 FIRM_OP(Cond); // integer done
1252 /* TODO: implement these nodes */
1254 IGN(Div); // intrinsic lowering
1255 IGN(Mod); // intrinsic lowering
1256 IGN(DivMod); // TODO: implement DivMod
1260 IGN(Cmp); // done, implemented in cond
1262 /* You probably don't need to handle the following nodes */
1274 IGN(Jmp); // emitter done
1292 FIRM_OP(be_FrameAddr);
1294 op_Max = get_op_Max();
1297 op_Min = get_op_Min();
1300 op_Mulh = get_op_Mulh();
1309 typedef ir_node *(transform_func)(ir_node *irn, arm_code_gen_t *cg);
1312 * Transforms the given firm node (and maybe some other related nodes)
1313 * into one or more assembler nodes.
1315 * @param node the firm node
1316 * @param env the debug module
1318 void arm_transform_node(ir_node *node, void *env) {
1319 arm_code_gen_t *cg = (arm_code_gen_t *)env;
1320 ir_op *op = get_irn_op(node);
1321 ir_node *asm_node = NULL;
1326 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
1328 if (op->ops.generic) {
1329 transform_func *transform = (transform_func *)op->ops.generic;
1331 asm_node = (*transform)(node, cg);
1335 exchange(node, asm_node);
1336 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
1339 DB((cg->mod, LEVEL_1, "ignored\n"));