1 /* The codegenerator (transform FIRM into arm FIRM */
20 #include "../benode_t.h"
21 #include "bearch_arm_t.h"
23 #include "arm_nodes_attr.h"
24 #include "../arch/archop.h" /* we need this for Min and Max nodes */
25 #include "arm_transform.h"
26 #include "arm_new_nodes.h"
27 #include "arm_map_regs.h"
29 #include "gen_arm_regalloc_if.h"
34 extern ir_op *get_op_Mulh(void);
38 /****************************************************************************************************
40 * | | | | / _| | | (_)
41 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
42 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
43 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
44 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
46 ****************************************************************************************************/
48 typedef struct vals_ {
50 unsigned char values[4];
51 unsigned char shifts[4];
55 static unsigned do_rol(unsigned v, unsigned rol) {
56 return (v << rol) | (v >> (32 - rol));
60 * construct 8bit values und rot amounts for a value
62 static void gen_vals_from_word(unsigned int value, vals *result)
66 memset(result, 0, sizeof(*result));
68 /* special case: we prefer shift amount 0 */
70 result->values[0] = value;
77 unsigned v = do_rol(value, 8) & 0xFFFFFF;
86 shf = (initial + shf - 8) & 0x1F;
87 result->values[result->ops] = v;
88 result->shifts[result->ops] = shf;
91 value ^= do_rol(v, shf) >> initial;
101 * Creates a arm_Const node.
103 static ir_node *create_const_node(ir_node *irn, ir_node *block, long value) {
104 tarval *tv = new_tarval_from_long(value, mode_Iu);
105 dbg_info *dbg = get_irn_dbg_info(irn);
106 return new_rd_arm_Mov_i(dbg, current_ir_graph, block, get_irn_mode(irn), tv);
110 * Creates a arm_Const_Neg node.
112 static ir_node *create_const_neg_node(ir_node *irn, ir_node *block, long value) {
113 tarval *tv = new_tarval_from_long(value, mode_Iu);
114 dbg_info *dbg = get_irn_dbg_info(irn);
115 return new_rd_arm_Mvn_i(dbg, current_ir_graph, block, get_irn_mode(irn), tv);
118 #define NEW_BINOP_NODE(opname, env, op1, op2) new_rd_arm_##opname(env->dbg, current_ir_graph, env->block, op1, op2, env->mode)
121 * Encodes an immediate with shifter operand
123 static unsigned int arm_encode_imm_w_shift(unsigned int shift, unsigned int immediate) {
124 return immediate | ((shift>>1)<<8);
128 * Decode an immediate with shifter operand
130 unsigned int arm_decode_imm_w_shift(tarval *tv) {
131 unsigned l = get_tarval_long(tv);
132 unsigned rol = (l & ~0xFF) >> 7;
134 return do_rol(l & 0xFF, rol);
138 * Creates a possible DAG for an constant.
140 static ir_node *create_const_graph_value(ir_node *irn, ir_node *block, unsigned int value) {
144 ir_mode *mode = get_irn_mode(irn);
145 dbg_info *dbg = get_irn_dbg_info(irn);
147 gen_vals_from_word(value, &v);
148 gen_vals_from_word(~value, &vn);
150 if (vn.ops < v.ops) {
152 result = create_const_neg_node(irn, block, arm_encode_imm_w_shift(vn.shifts[0], vn.values[0]));
154 for (cnt = 1; cnt < vn.ops; ++cnt) {
155 tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]), mode_Iu);
156 ir_node *bic_i_node = new_rd_arm_Bic_i(dbg, current_ir_graph, block, result, mode, tv);
162 result = create_const_node(irn, block, arm_encode_imm_w_shift(v.shifts[0], v.values[0]));
164 for (cnt = 1; cnt < v.ops; ++cnt) {
165 tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]), mode_Iu);
166 ir_node *orr_i_node = new_rd_arm_Or_i(dbg, current_ir_graph, block, result, mode, tv);
174 * Create a DAG constructing a given Const.
176 * @param irn a Firm const
178 static ir_node *create_const_graph(ir_node *irn, ir_node *block) {
179 int value = get_tarval_long(get_Const_tarval(irn));
180 return create_const_graph_value(irn, block, value);
185 * Creates code for a Firm Const node.
187 static ir_node *gen_Const(ir_node *irn, arm_code_gen_t *cg) {
188 ir_graph *irg = current_ir_graph;
189 ir_node *block = get_nodes_block(irn);
190 ir_mode *mode = get_irn_mode(irn);
191 dbg_info *dbg = get_irn_dbg_info(irn);
193 if (mode_is_float(mode)) {
194 if (USE_FPA(cg->isa))
195 return new_rd_arm_fpaConst(dbg, irg, block, mode, get_Const_tarval(irn));
196 else if (USE_VFP(cg->isa))
197 assert(mode != mode_E && "IEEE Extended FP not supported");
200 else if (mode_is_reference(mode))
202 return create_const_graph(irn, block);
205 static ir_node *gen_mask(ir_node *irn, ir_node *op, int result_bits) {
206 ir_node *block = get_nodes_block(irn);
207 unsigned mask_bits = (1 << result_bits) - 1;
208 ir_node *mask_node = create_const_graph_value(irn, block, mask_bits);
209 dbg_info *dbg = get_irn_dbg_info(irn);
210 return new_rd_arm_And(dbg, current_ir_graph, block, op, mask_node, get_irn_mode(irn), ARM_SHF_NONE, NULL);
213 static ir_node *gen_sign_extension(ir_node *irn, ir_node *op, int result_bits) {
214 ir_node *block = get_nodes_block(irn);
215 int shift_width = 32 - result_bits;
216 ir_graph *irg = current_ir_graph;
217 ir_node *shift_const_node = create_const_graph_value(irn, block, shift_width);
218 dbg_info *dbg = get_irn_dbg_info(irn);
219 ir_node *lshift_node = new_rd_arm_Shl(dbg, irg, block, op, shift_const_node, get_irn_mode(op));
220 ir_node *rshift_node = new_rd_arm_Shrs(dbg, irg, block, lshift_node, shift_const_node, get_irn_mode(irn));
225 * Transforms a Conv node.
227 * @param env The transformation environment
228 * @return the created arm Conv node
230 static ir_node *gen_Conv(ir_node *irn, arm_code_gen_t *cg) {
231 ir_graph *irg = current_ir_graph;
232 ir_node *block = get_nodes_block(irn);
233 ir_node *op = get_Conv_op(irn);
234 ir_mode *in_mode = get_irn_mode(op);
235 ir_mode *out_mode = get_irn_mode(irn);
236 dbg_info *dbg = get_irn_dbg_info(irn);
238 if (in_mode == out_mode)
241 if (mode_is_float(in_mode) || mode_is_float(out_mode)) {
244 if (USE_FPA(cg->isa)) {
245 if (mode_is_float(in_mode)) {
246 if (mode_is_float(out_mode)) {
247 /* from float to float */
248 return new_rd_arm_fpaMov(dbg, irg, block, op, out_mode);
251 /* from float to int */
252 return new_rd_arm_fpaFix(dbg, irg, block, op, out_mode);
256 /* from int to float */
257 return new_rd_arm_fpaFlt(dbg, irg, block, op, out_mode);
262 else { /* complete in gp registers */
263 int in_bits = get_mode_size_bits(in_mode);
264 int out_bits = get_mode_size_bits(out_mode);
265 int in_sign = get_mode_sign(in_mode);
266 int out_sign = get_mode_sign(out_mode);
270 if (in_bits == out_bits && in_bits == 32)
274 // unsigned -> unsigned
276 // unsigned -> signed
277 // sign extension (31:16)=(15)
278 // signed -> unsigned
279 // maskieren (31:16)=0
282 if (in_bits == out_bits && out_bits < 32) {
283 if (in_sign && !out_sign) {
284 return gen_mask(irn, op, out_bits);
286 return gen_sign_extension(irn, op, out_bits);
291 // unsigned -> unsigned
293 // unsigned -> signed
295 // signed -> unsigned
296 // sign extension (31:16)=(15)
298 // sign extension (31:16)=(15)
299 if (in_bits < out_bits) {
301 return gen_sign_extension(irn, op, out_bits);
308 // unsigned -> unsigned
309 // maskieren (31:16)=0
310 // unsigned -> signed
311 // maskieren (31:16)=0
312 // signed -> unsigned
313 // maskieren (31:16)=0
315 // sign extension (erledigt auch maskieren) (31:16)=(15)
316 if (in_bits > out_bits) {
317 if (in_sign && out_sign) {
318 return gen_sign_extension(irn, op, out_bits);
320 return gen_mask(irn, op, out_bits);
323 assert(0 && "recheck integer conversion logic!");
330 * Return true if an operand is a shifter operand
332 static int is_shifter_operand(ir_node *n, arm_shift_modifier *pmod) {
333 arm_shift_modifier mod = ARM_SHF_NONE;
336 mod = get_arm_shift_modifier(n);
339 if (mod != ARM_SHF_NONE) {
340 long v = get_tarval_long(get_arm_value(n));
348 * Creates an arm Add.
350 * @param env The transformation environment
351 * @return the created arm Add node
353 static ir_node *gen_Add(ir_node *irn, arm_code_gen_t *cg) {
354 ir_node *block = get_nodes_block(irn);
355 ir_node *op1 = get_Add_left(irn);
356 ir_node *op2 = get_Add_right(irn);
357 ir_mode *mode = get_irn_mode(irn);
358 ir_graph *irg = current_ir_graph;
361 arm_shift_modifier mod;
362 dbg_info *dbg = get_irn_dbg_info(irn);
364 if (mode_is_float(mode)) {
366 if (USE_FPA(cg->isa))
367 return new_rd_arm_fpaAdd(dbg, irg, block, op1, op2, mode);
368 else if (USE_VFP(cg->isa)) {
369 assert(mode != mode_E && "IEEE Extended FP not supported");
373 if (mode_is_numP(mode)) {
374 if (is_arm_Mov_i(op1))
375 return new_rd_arm_Add_i(dbg, irg, block, op2, mode, get_arm_value(op1));
376 if (is_arm_Mov_i(op2))
377 return new_rd_arm_Add_i(dbg, irg, block, op1, mode, get_arm_value(op2));
380 if (is_arm_Mul(op1) && get_irn_n_edges(op1) == 1) {
382 op2 = get_irn_n(op1, 1);
383 op1 = get_irn_n(op1, 0);
385 return new_rd_arm_Mla(dbg, irg, block, op1, op2, op3, mode);
387 if (is_arm_Mul(op2) && get_irn_n_edges(op2) == 1) {
389 op1 = get_irn_n(op2, 0);
390 op2 = get_irn_n(op2, 1);
392 return new_rd_arm_Mla(dbg, irg, block, op1, op2, op3, mode);
395 /* is the first a shifter */
396 v = is_shifter_operand(op1, &mod);
398 op1 = get_irn_n(op1, 0);
399 return new_rd_arm_Add(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu));
401 /* is the second a shifter */
402 v = is_shifter_operand(op2, &mod);
404 op2 = get_irn_n(op2, 0);
405 return new_rd_arm_Add(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu));
409 return new_rd_arm_Add(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL);
412 assert(0 && "unknown mode for add");
417 * Creates an arm Mul.
419 * @param env The transformation environment
420 * @return the created arm Mul node
422 static ir_node *gen_Mul(ir_node *irn, arm_code_gen_t *cg) {
423 ir_node *block = get_nodes_block(irn);
424 ir_node *op1 = get_Mul_left(irn);
425 ir_node *op2 = get_Mul_right(irn);
426 ir_mode *mode = get_irn_mode(irn);
427 ir_graph *irg = current_ir_graph;
428 dbg_info *dbg = get_irn_dbg_info(irn);
430 if (mode_is_float(mode)) {
432 if (USE_FPA(cg->isa))
433 return new_rd_arm_fpaMul(dbg, irg, block, op1, op2, mode);
434 else if (USE_VFP(cg->isa)) {
435 assert(mode != mode_E && "IEEE Extended FP not supported");
439 return new_rd_arm_Mul(dbg, irg, block, op1, op2, mode);
443 * Creates an arm floating point Div.
445 * @param env The transformation environment
446 * @return the created arm fDiv node
448 static ir_node *gen_Quot(ir_node *irn, arm_code_gen_t *cg) {
449 ir_node *block = get_nodes_block(irn);
450 ir_node *op1 = get_Quot_left(irn);
451 ir_node *op2 = get_Quot_right(irn);
452 ir_mode *mode = get_irn_mode(irn);
453 dbg_info *dbg = get_irn_dbg_info(irn);
455 assert(mode != mode_E && "IEEE Extended FP not supported");
458 if (USE_FPA(cg->isa))
459 return new_rd_arm_fpaDiv(dbg, current_ir_graph, block, op1, op2, mode);
460 else if (USE_VFP(cg->isa)) {
461 assert(mode != mode_E && "IEEE Extended FP not supported");
468 #define GEN_INT_OP(op) \
469 static ir_node *gen_ ## op(ir_node *irn, arm_code_gen_t *cg) { \
470 ir_graph *irg = current_ir_graph; \
471 ir_node *block = get_nodes_block(irn); \
472 ir_node *op1 = get_ ## op ## _left(irn); \
473 ir_node *op2 = get_ ## op ## _right(irn); \
475 arm_shift_modifier mod; \
476 ir_mode *mode = get_irn_mode(irn); \
477 dbg_info *dbg = get_irn_dbg_info(irn); \
479 if (is_arm_Mov_i(op1)) \
480 return new_rd_arm_ ## op ## _i(dbg, irg, block, op2, mode, get_arm_value(op1)); \
481 if (is_arm_Mov_i(op2)) \
482 return new_rd_arm_ ## op ## _i(dbg, irg, block, op1, mode, get_arm_value(op2)); \
483 /* is the first a shifter */ \
484 v = is_shifter_operand(op1, &mod); \
486 op1 = get_irn_n(op1, 0); \
487 return new_rd_arm_ ## op(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu)); \
489 /* is the second a shifter */ \
490 v = is_shifter_operand(op2, &mod); \
492 op2 = get_irn_n(op2, 0); \
493 return new_rd_arm_ ## op(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu)); \
496 return new_rd_arm_ ## op(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL); \
501 * Creates an arm And.
503 * @param env The transformation environment
504 * @return the created arm And node
506 static ir_node *gen_And(ir_node *irn, arm_code_gen_t *cg);
510 * Creates an arm Orr.
512 * @param env The transformation environment
513 * @return the created arm Or node
515 static ir_node *gen_Or(ir_node *irn, arm_code_gen_t *cg);
519 * Creates an arm Eor.
521 * @param env The transformation environment
522 * @return the created arm Eor node
524 static ir_node *gen_Eor(ir_node *irn, arm_code_gen_t *cg);
528 * Creates an arm Sub.
530 * @param env The transformation environment
531 * @return the created arm Sub node
533 static ir_node *gen_Sub(ir_node *irn, arm_code_gen_t *cg) {
534 ir_node *block = get_nodes_block(irn);
535 ir_node *op1 = get_Sub_left(irn);
536 ir_node *op2 = get_Sub_right(irn);
538 arm_shift_modifier mod;
539 ir_mode *mode = get_irn_mode(irn);
540 ir_graph *irg = current_ir_graph;
541 dbg_info *dbg = get_irn_dbg_info(irn);
543 if (mode_is_float(mode)) {
545 if (USE_FPA(cg->isa))
546 return new_rd_arm_fpaSub(dbg, irg, block, op1, op2, mode);
547 else if (USE_VFP(cg->isa)) {
548 assert(mode != mode_E && "IEEE Extended FP not supported");
552 if (mode_is_numP(mode)) {
553 if (is_arm_Mov_i(op1))
554 return new_rd_arm_Rsb_i(dbg, irg, block, op2, mode, get_arm_value(op1));
555 if (is_arm_Mov_i(op2))
556 return new_rd_arm_Sub_i(dbg, irg, block, op1, mode, get_arm_value(op2));
558 /* is the first a shifter */
559 v = is_shifter_operand(op1, &mod);
561 op1 = get_irn_n(op1, 0);
562 return new_rd_arm_Rsb(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu));
564 /* is the second a shifter */
565 v = is_shifter_operand(op2, &mod);
567 op2 = get_irn_n(op2, 0);
568 return new_rd_arm_Sub(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu));
571 return new_rd_arm_Sub(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL);
573 assert(0 && "unknown mode for sub");
578 * Creates an arm Shl.
580 * @param env The transformation environment
581 * @return the created arm Shl node
583 static ir_node *gen_Shl(ir_node *irn, arm_code_gen_t *cg) {
585 ir_node *block = get_nodes_block(irn);
586 ir_node *op1 = get_Shl_left(irn);
587 ir_node *op2 = get_Shl_right(irn);
588 ir_mode *mode = get_irn_mode(irn);
589 ir_graph *irg = current_ir_graph;
590 dbg_info *dbg = get_irn_dbg_info(irn);
592 if (is_arm_Mov_i(op2)) {
593 result = new_rd_arm_Mov(dbg, irg, block, op1, mode, ARM_SHF_LSL, get_arm_value(op2));
595 result = new_rd_arm_Shl(dbg, irg, block, op1, op2, mode);
601 * Creates an arm Shr.
603 * @param env The transformation environment
604 * @return the created arm Shr node
606 static ir_node *gen_Shr(ir_node *irn, arm_code_gen_t *cg) {
608 ir_node *block = get_nodes_block(irn);
609 ir_node *op1 = get_Shr_left(irn);
610 ir_node *op2 = get_Shr_right(irn);
611 ir_mode *mode = get_irn_mode(irn);
612 ir_graph *irg = current_ir_graph;
613 dbg_info *dbg = get_irn_dbg_info(irn);
615 if (is_arm_Mov_i(op2)) {
616 result = new_rd_arm_Mov(dbg, irg, block, op1, mode, ARM_SHF_LSR, get_arm_value(op2));
618 result = new_rd_arm_Shr(dbg, irg, block, op1, op2, mode);
624 * Creates an arm Shrs.
626 * @param env The transformation environment
627 * @return the created arm Shrs node
629 static ir_node *gen_Shrs(ir_node *irn, arm_code_gen_t *cg) {
631 ir_node *block = get_nodes_block(irn);
632 ir_node *op1 = get_Shrs_left(irn);
633 ir_node *op2 = get_Shrs_right(irn);
634 ir_mode *mode = get_irn_mode(irn);
635 dbg_info *dbg = get_irn_dbg_info(irn);
637 if (is_arm_Mov_i(op2)) {
638 result = new_rd_arm_Mov(dbg, current_ir_graph, block, op1, mode, ARM_SHF_ASR, get_arm_value(op2));
640 result = new_rd_arm_Shrs(dbg, current_ir_graph, block, op1, op2, mode);
646 * Transforms a Not node.
648 * @param env The transformation environment
649 * @return the created arm Not node
651 static ir_node *gen_Not(ir_node *irn, arm_code_gen_t *cg) {
652 ir_node *block = get_nodes_block(irn);
653 ir_node *op = get_Not_op(irn);
655 arm_shift_modifier mod = ARM_SHF_NONE;
657 dbg_info *dbg = get_irn_dbg_info(irn);
659 v = is_shifter_operand(op, &mod);
661 op = get_irn_n(op, 0);
662 tv = new_tarval_from_long(v, mode_Iu);
664 return new_rd_arm_Mvn(dbg, current_ir_graph, block, op, get_irn_mode(irn), mod, tv);
668 * Transforms an Abs node.
670 * @param env The transformation environment
671 * @return the created arm Abs node
673 static ir_node *gen_Abs(ir_node *irn, arm_code_gen_t *cg) {
674 ir_node *block = get_nodes_block(irn);
675 ir_node *op = get_Abs_op(irn);
676 ir_mode *mode = get_irn_mode(irn);
677 dbg_info *dbg = get_irn_dbg_info(irn);
679 if (mode_is_float(mode)) {
681 if (USE_FPA(cg->isa))
682 return new_rd_arm_fpaAbs(dbg, current_ir_graph, block, op, mode);
683 else if (USE_VFP(cg->isa)) {
684 assert(mode != mode_E && "IEEE Extended FP not supported");
688 return new_rd_arm_Abs(dbg, current_ir_graph, block, op, mode);
692 * Transforms a Minus node.
694 * @param env The transformation environment
695 * @return the created arm Minus node
697 static ir_node *gen_Minus(ir_node *irn, arm_code_gen_t *cg) {
698 ir_node *block = get_nodes_block(irn);
699 ir_node *op = get_Minus_op(irn);
700 ir_mode *mode = get_irn_mode(irn);
701 ir_graph *irg = current_ir_graph;
702 dbg_info *dbg = get_irn_dbg_info(irn);
704 if (mode_is_float(mode)) {
706 if (USE_FPA(cg->isa))
707 return new_rd_arm_fpaMnv(dbg, irg, block, op, mode);
708 else if (USE_VFP(cg->isa)) {
709 assert(mode != mode_E && "IEEE Extended FP not supported");
713 return new_rd_arm_Rsb_i(dbg, irg, block, op, mode, get_mode_null(mode));
719 * @param mod the debug module
720 * @param block the block the new node should belong to
721 * @param node the ir Load node
722 * @param mode node mode
723 * @return the created arm Load node
725 static ir_node *gen_Load(ir_node *irn, arm_code_gen_t *cg) {
726 ir_node *block = get_nodes_block(irn);
727 ir_mode *mode = get_Load_mode(irn);
728 ir_graph *irg = current_ir_graph;
729 dbg_info *dbg = get_irn_dbg_info(irn);
731 if (mode_is_float(mode)) {
733 if (USE_FPA(cg->isa))
734 return new_rd_arm_fpaLdf(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn),
736 else if (USE_VFP(cg->isa)) {
737 assert(mode != mode_E && "IEEE Extended FP not supported");
741 if (mode == mode_Bu) {
742 return new_rd_arm_Loadb(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
744 if (mode == mode_Bs) {
745 return new_rd_arm_Loadbs(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
747 if (mode == mode_Hu) {
748 return new_rd_arm_Loadh(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
750 if (mode == mode_Hs) {
751 return new_rd_arm_Loadhs(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
753 if (mode_is_reference(mode)) {
754 return new_rd_arm_Load(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
756 return new_rd_arm_Load(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
760 * Transforms a Store.
762 * @param mod the debug module
763 * @param block the block the new node should belong to
764 * @param node the ir Store node
765 * @param mode node mode
766 * @return the created arm Store node
768 static ir_node *gen_Store(ir_node *irn, arm_code_gen_t *cg) {
769 ir_node *block = get_nodes_block(irn);
770 ir_mode *mode = get_irn_mode(get_Store_value(irn));
771 ir_graph *irg = current_ir_graph;
772 dbg_info *dbg = get_irn_dbg_info(irn);
774 assert(mode != mode_E && "IEEE Extended FP not supported");
775 if (mode_is_float(mode)) {
777 if (USE_FPA(cg->isa))
778 return new_rd_arm_fpaStf(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn),
779 get_Store_mem(irn), get_irn_mode(get_Store_value(irn)));
780 else if (USE_VFP(cg->isa)) {
781 assert(mode != mode_E && "IEEE Extended FP not supported");
785 if (mode == mode_Bu) {
786 return new_rd_arm_Storeb(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
788 if (mode == mode_Bs) {
789 return new_rd_arm_Storebs(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
791 if (mode == mode_Hu) {
792 return new_rd_arm_Storeh(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
794 if (mode == mode_Hs) {
795 return new_rd_arm_Storehs(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
797 return new_rd_arm_Store(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
801 static ir_node *gen_Cond(ir_node *irn, arm_code_gen_t *cg) {
802 ir_node *result = NULL;
803 ir_node *selector = get_Cond_selector(irn);
804 ir_node *block = get_nodes_block(irn);
805 ir_graph *irg = current_ir_graph;
806 dbg_info *dbg = get_irn_dbg_info(irn);
808 if ( get_irn_mode(selector) == mode_b ) {
810 ir_node *proj_node = get_Cond_selector(irn);
811 ir_node *cmp_node = get_Proj_pred(proj_node);
812 ir_node *op1 = get_Cmp_left(cmp_node);
813 ir_node *op2 = get_Cmp_right(cmp_node);
814 result = new_rd_arm_CondJmp(dbg, irg, block, op1, op2, mode_T);
815 set_arm_proj_num(result, get_Proj_proj(proj_node));
818 ir_node *op = get_irn_n(irn, 0);
819 ir_node *const_graph;
824 const ir_edge_t *edge;
834 foreach_out_edge(irn, edge) {
835 proj = get_edge_src_irn(edge);
836 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
838 pn = get_Proj_proj(proj);
840 min = pn<min ? pn : min;
841 max = pn>max ? pn : max;
844 norm_max = max - translation;
845 norm_min = min - translation;
847 n_projs = norm_max + 1;
848 projs = xcalloc(n_projs , sizeof(ir_node*));
851 foreach_out_edge(irn, edge) {
852 proj = get_edge_src_irn(edge);
853 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
855 pn = get_Proj_proj(proj) - translation;
856 set_Proj_proj(proj, pn);
860 const_node = new_rd_Const(dbg, irg, block, mode_Iu, new_tarval_from_long(translation, mode_Iu));
861 const_graph = gen_Const(const_node, cg);
862 sub = new_rd_arm_Sub(dbg, irg, block, op, const_graph, get_irn_mode(op), ARM_SHF_NONE, NULL);
863 result = new_rd_arm_SwitchJmp(dbg, irg, block, sub, mode_T);
864 set_arm_n_projs(result, n_projs);
865 set_arm_default_proj_num(result, get_Cond_defaultProj(irn)-translation);
871 * Returns the name of a SymConst.
872 * @param symc the SymConst
873 * @return name of the SymConst
875 const char *get_sc_name(ir_node *symc) {
876 if (get_irn_opcode(symc) != iro_SymConst)
879 switch (get_SymConst_kind(symc)) {
880 case symconst_addr_name:
881 return get_id_str(get_SymConst_name(symc));
883 case symconst_addr_ent:
884 return get_entity_ld_name(get_SymConst_entity(symc));
887 assert(0 && "Unsupported SymConst");
893 static ir_node *gen_SymConst(ir_node *irn, arm_code_gen_t *cg) {
894 ir_node *block = get_nodes_block(irn);
895 ir_mode *mode = get_irn_mode(irn);
896 dbg_info *dbg = get_irn_dbg_info(irn);
897 return new_rd_arm_SymConst(dbg, current_ir_graph, block, mode, get_sc_name(irn));
903 * Transforms a CopyB node.
905 * @param env The transformation environment
906 * @return The transformed node.
908 static ir_node *gen_CopyB(ir_node *irn, arm_code_gen_t *cg) {
910 dbg_info *dbg = get_irn_dbg_info(irn);
911 ir_mode *mode = get_irn_mode(irn);
912 ir_node *src = get_CopyB_src(irn);
913 ir_node *dst = get_CopyB_dst(irn);
914 ir_node *mem = get_CopyB_mem(irn);
915 ir_node *block = get_nodes_block(irn);
916 int size = get_type_size_bytes(get_CopyB_type(irn));
917 ir_graph *irg = current_ir_graph;
921 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, src);
922 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, dst);
924 res = new_rd_arm_CopyB( dbg, irg, block, dst_copy, src_copy, new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), mem, mode);
925 set_arm_value(res, new_tarval_from_long(size, mode_Iu));
934 /********************************************
937 * | |__ ___ _ __ ___ __| | ___ ___
938 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
939 * | |_) | __/ | | | (_) | (_| | __/\__ \
940 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
942 ********************************************/
945 * Return an expanding stack offset.
946 * Note that function is called in the transform phase
947 * where the stack offsets are still relative regarding
948 * the first (frame allocating) IncSP.
949 * However this is exactly what we want because frame
950 * access must be done relative the the fist IncSP ...
952 static int get_sp_expand_offset(ir_node *inc_sp) {
953 int offset = be_get_IncSP_offset(inc_sp);
955 if (offset == BE_STACK_FRAME_SIZE_EXPAND)
961 static ir_node *gen_StackParam(ir_node *irn, arm_code_gen_t *cg) {
963 ir_node *new_op = NULL;
964 ir_node *block = get_nodes_block(irn);
965 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
966 ir_node *mem = new_rd_NoMem(env->irg);
967 ir_node *ptr = get_irn_n(irn, 0);
968 entity *ent = be_get_frame_entity(irn);
969 ir_mode *mode = env->mode;
971 // /* If the StackParam has only one user -> */
972 // /* put it in the Block where the user resides */
973 // if (get_irn_n_edges(node) == 1) {
974 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
977 if (mode_is_float(mode)) {
978 if (USE_SSE2(env->cg))
979 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
981 env->cg->used_x87 = 1;
982 new_op = new_rd_ia32_vfld(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
986 new_op = new_rd_ia32_Load(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
989 set_ia32_frame_ent(new_op, ent);
990 set_ia32_use_frame(new_op);
992 set_ia32_am_support(new_op, ia32_am_Source);
993 set_ia32_op_type(new_op, ia32_AddrModeS);
994 set_ia32_am_flavour(new_op, ia32_B);
995 set_ia32_ls_mode(new_op, mode);
997 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
999 return new_rd_Proj(env->dbg, env->irg, block, new_op, mode, 0);
1004 * Transforms a FrameAddr into an ia32 Add.
1006 static ir_node *gen_be_FrameAddr(ir_node *irn, arm_code_gen_t *cg) {
1007 ir_node *block = get_nodes_block(irn);
1008 entity *ent = be_get_frame_entity(irn);
1009 int offset = get_entity_offset_bytes(ent);
1010 ir_node *op = get_irn_n(irn, 0);
1012 ir_mode *mode = get_irn_mode(irn);
1013 dbg_info *dbg = get_irn_dbg_info(irn);
1015 if (be_is_IncSP(op)) {
1016 /* BEWARE: we get an offset which is absolute from an offset that
1017 is relative. Both must be merged */
1018 offset += get_sp_expand_offset(op);
1020 cnst = create_const_graph_value(irn, block, (unsigned)offset);
1021 if (is_arm_Mov_i(cnst))
1022 return new_rd_arm_Add_i(dbg, current_ir_graph, block, op, mode, get_arm_value(cnst));
1023 return new_rd_arm_Add(dbg, current_ir_graph, block, op, cnst, mode, ARM_SHF_NONE, NULL);
1027 * Transforms a FrameLoad into an ia32 Load.
1029 static ir_node *gen_FrameLoad(ir_node *irn, arm_code_gen_t *cg) {
1031 ir_node *new_op = NULL;
1032 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1033 ir_node *mem = get_irn_n(irn, 0);
1034 ir_node *ptr = get_irn_n(irn, 1);
1035 entity *ent = be_get_frame_entity(irn);
1036 ir_mode *mode = get_type_mode(get_entity_type(ent));
1038 if (mode_is_float(mode)) {
1039 if (USE_SSE2(env->cg))
1040 new_op = new_rd_ia32_fLoad(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
1042 env->cg->used_x87 = 1;
1043 new_op = new_rd_ia32_vfld(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
1047 new_op = new_rd_ia32_Load(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
1050 set_ia32_frame_ent(new_op, ent);
1051 set_ia32_use_frame(new_op);
1053 set_ia32_am_support(new_op, ia32_am_Source);
1054 set_ia32_op_type(new_op, ia32_AddrModeS);
1055 set_ia32_am_flavour(new_op, ia32_B);
1056 set_ia32_ls_mode(new_op, mode);
1058 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1066 * Transforms a FrameStore into an ia32 Store.
1068 static ir_node *gen_FrameStore(ir_node *irn, arm_code_gen_t *cg) {
1070 ir_node *new_op = NULL;
1071 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1072 ir_node *mem = get_irn_n(irn, 0);
1073 ir_node *ptr = get_irn_n(irn, 1);
1074 ir_node *val = get_irn_n(irn, 2);
1075 entity *ent = be_get_frame_entity(irn);
1076 ir_mode *mode = get_irn_mode(val);
1078 if (mode_is_float(mode)) {
1079 if (USE_SSE2(env->cg))
1080 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1082 env->cg->used_x87 = 1;
1083 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1086 else if (get_mode_size_bits(mode) == 8) {
1087 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1090 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1093 set_ia32_frame_ent(new_op, ent);
1094 set_ia32_use_frame(new_op);
1096 set_ia32_am_support(new_op, ia32_am_Dest);
1097 set_ia32_op_type(new_op, ia32_AddrModeD);
1098 set_ia32_am_flavour(new_op, ia32_B);
1099 set_ia32_ls_mode(new_op, mode);
1101 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1108 // static ir_node *gen_be_Copy(ir_node *irn, arm_code_gen_t *cg) {
1109 // return new_rd_arm_Copy(env->dbg, env->irg, env->block, op, env->mode);
1112 /*********************************************************
1115 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1116 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1117 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1118 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1120 *********************************************************/
1123 * move constants out of the start block
1125 void arm_move_consts(ir_node *node, void *env) {
1132 for (i = get_irn_arity(node) - 1; i >= 0; --i) {
1133 ir_node *pred = get_irn_n(node,i);
1134 opcode pred_code = get_irn_opcode(pred);
1135 if (pred_code == iro_Const) {
1136 ir_node *const_graph;
1137 const_graph = create_const_graph(pred, get_nodes_block(get_irn_n(get_nodes_block(node),i)));
1138 set_irn_n(node, i, const_graph);
1140 else if (pred_code == iro_SymConst) {
1141 /* FIXME: in general, SymConst always require a load, so it
1142 might be better to place them into the first real block
1143 and let the spiller rematerialize them. */
1144 const char *str = get_sc_name(pred);
1145 ir_node *symconst_node;
1146 symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
1147 current_ir_graph, get_nodes_block(get_irn_n(get_nodes_block(node),i)),
1148 get_irn_mode(pred), str);
1149 set_irn_n(node, i, symconst_node);
1154 for (i = 0; i < get_irn_arity(node); i++) {
1155 ir_node *pred = get_irn_n(node,i);
1156 opcode pred_code = get_irn_opcode(pred);
1157 if (pred_code == iro_Const) {
1158 ir_node *const_graph;
1159 const_graph = create_const_graph(pred, get_nodes_block(node));
1160 set_irn_n(node, i, const_graph);
1161 } else if (pred_code == iro_SymConst) {
1162 const char *str = get_sc_name(pred);
1163 ir_node *symconst_node;
1164 symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
1165 current_ir_graph, get_nodes_block(node),
1166 get_irn_mode(pred), str);
1167 set_irn_n(node, i, symconst_node);
1173 /************************************************************************/
1174 /* move symbolic constants out of startblock */
1175 /************************************************************************/
1176 void arm_move_symconsts(ir_node *node, void *env) {
1182 for (i = 0; i < get_irn_arity(node); i++) {
1183 ir_node *pred = get_irn_n(node,i);
1184 opcode pred_code = get_irn_opcode(pred);
1186 if (pred_code == iro_SymConst) {
1187 const char *str = get_sc_name(pred);
1188 ir_node *symconst_node;
1190 symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
1191 current_ir_graph, get_nodes_block(node), get_irn_mode(pred), str);
1192 set_irn_n(node, i, symconst_node);
1198 * the BAD transformer.
1200 static ir_node *bad_transform(ir_node *irn, arm_code_gen_t *cg) {
1201 ir_fprintf(stderr, "Not implemented: %+F\n", irn);
1207 * Enters all transform functions into the generic pointer
1209 void arm_register_transformers(void) {
1210 ir_op *op_Max, *op_Min, *op_Mulh;
1212 /* first clear the generic function pointer for all ops */
1213 clear_irp_opcodes_generic_func();
1215 #define FIRM_OP(a) op_##a->ops.generic = (op_func)gen_##a
1216 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
1219 FIRM_OP(Add); // done
1220 FIRM_OP(Mul); // done
1221 FIRM_OP(Quot); // done
1222 FIRM_OP(And); // done
1223 FIRM_OP(Or); // done
1224 FIRM_OP(Eor); // done
1226 FIRM_OP(Sub); // done
1227 FIRM_OP(Shl); // done
1228 FIRM_OP(Shr); // done
1229 FIRM_OP(Shrs); // done
1231 FIRM_OP(Minus); // done
1232 FIRM_OP(Not); // done
1233 FIRM_OP(Abs); // done
1235 FIRM_OP(CopyB); // done
1236 FIRM_OP(Const); // TODO: floating point consts
1237 FIRM_OP(Conv); // TODO: floating point conversions
1239 FIRM_OP(Load); // done
1240 FIRM_OP(Store); // done
1243 FIRM_OP(Cond); // integer done
1245 /* TODO: implement these nodes */
1247 IGN(Div); // intrinsic lowering
1248 IGN(Mod); // intrinsic lowering
1249 IGN(DivMod); // TODO: implement DivMod
1253 IGN(Cmp); // done, implemented in cond
1255 /* You probably don't need to handle the following nodes */
1267 IGN(Jmp); // emitter done
1285 FIRM_OP(be_FrameAddr);
1287 op_Max = get_op_Max();
1290 op_Min = get_op_Min();
1293 op_Mulh = get_op_Mulh();
1302 typedef ir_node *(transform_func)(ir_node *irn, arm_code_gen_t *cg);
1305 * Transforms the given firm node (and maybe some other related nodes)
1306 * into one or more assembler nodes.
1308 * @param node the firm node
1309 * @param env the debug module
1311 void arm_transform_node(ir_node *node, void *env) {
1312 arm_code_gen_t *cg = (arm_code_gen_t *)env;
1313 ir_op *op = get_irn_op(node);
1314 ir_node *asm_node = NULL;
1319 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
1321 if (op->ops.generic) {
1322 transform_func *transform = (transform_func *)op->ops.generic;
1324 asm_node = (*transform)(node, cg);
1328 exchange(node, asm_node);
1329 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
1332 DB((cg->mod, LEVEL_1, "ignored\n"));