2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
41 #include "../benode_t.h"
42 #include "../beirg_t.h"
43 #include "../beutil.h"
44 #include "../betranshlp.h"
45 #include "bearch_arm_t.h"
47 #include "arm_nodes_attr.h"
48 #include "arm_transform.h"
49 #include "arm_optimize.h"
50 #include "arm_new_nodes.h"
51 #include "arm_map_regs.h"
53 #include "gen_arm_regalloc_if.h"
58 /** hold the current code generator during transformation */
59 static arm_code_gen_t *env_cg;
61 extern ir_op *get_op_Mulh(void);
64 /****************************************************************************************************
66 * | | | | / _| | | (_)
67 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
68 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
69 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
70 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
72 ****************************************************************************************************/
74 static inline int mode_needs_gp_reg(ir_mode *mode) {
75 return mode_is_int(mode) || mode_is_reference(mode);
79 * Creates a arm_Const node.
81 static ir_node *create_mov_node(dbg_info *dbg, ir_node *block, long value) {
82 ir_mode *mode = mode_Iu;
85 if (mode_needs_gp_reg(mode))
87 res = new_bd_arm_Mov_i(dbg, block, mode, value);
93 * Creates a arm_Const_Neg node.
95 static ir_node *create_mvn_node(dbg_info *dbg, ir_node *block, long value) {
96 ir_mode *mode = mode_Iu;
99 if (mode_needs_gp_reg(mode))
101 res = new_bd_arm_Mvn_i(dbg, block, mode, value);
102 be_dep_on_frame(res);
106 #define NEW_BINOP_NODE(opname, env, op1, op2) new_bd_arm_##opname(env->dbg, current_ir_graph, env->block, op1, op2, env->mode)
109 * Creates a possible DAG for an constant.
111 static ir_node *create_const_graph_value(dbg_info *dbg, ir_node *block, unsigned int value) {
115 ir_mode *mode = mode_Iu;
117 arm_gen_vals_from_word(value, &v);
118 arm_gen_vals_from_word(~value, &vn);
120 if (vn.ops < v.ops) {
122 result = create_mvn_node(dbg, block, arm_encode_imm_w_shift(vn.shifts[0], vn.values[0]));
124 for (cnt = 1; cnt < vn.ops; ++cnt) {
125 long value = arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]);
126 ir_node *bic_i_node = new_bd_arm_Bic_i(dbg, block, result, mode, value);
132 result = create_mov_node(dbg, block, arm_encode_imm_w_shift(v.shifts[0], v.values[0]));
134 for (cnt = 1; cnt < v.ops; ++cnt) {
135 long value = arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]);
136 ir_node *orr_i_node = new_bd_arm_Or_i(dbg, block, result, mode, value);
144 * Create a DAG constructing a given Const.
146 * @param irn a Firm const
148 static ir_node *create_const_graph(ir_node *irn, ir_node *block) {
149 tarval *tv = get_Const_tarval(irn);
150 ir_mode *mode = get_tarval_mode(tv);
153 if (mode_is_reference(mode)) {
154 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
155 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
156 tv = tarval_convert_to(tv, mode_Iu);
158 value = get_tarval_long(tv);
159 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
163 * Create an And that will mask all upper bits
165 static ir_node *gen_zero_extension(dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) {
166 unsigned mask_bits = (1 << result_bits) - 1;
167 ir_node *mask_node = create_const_graph_value(dbg, block, mask_bits);
168 return new_bd_arm_And(dbg, block, op, mask_node, mode_Iu, ARM_SHF_NONE, 0);
172 * Generate code for a sign extension.
174 static ir_node *gen_sign_extension(dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) {
175 int shift_width = 32 - result_bits;
176 ir_node *shift_const_node = create_const_graph_value(dbg, block, shift_width);
177 ir_node *lshift_node = new_bd_arm_Shl(dbg, block, op, shift_const_node, mode_Iu);
178 ir_node *rshift_node = new_bd_arm_Shrs(dbg, block, lshift_node, shift_const_node, mode_Iu);
183 * Transforms a Conv node.
185 * @return The created ia32 Conv node
187 static ir_node *gen_Conv(ir_node *node) {
188 ir_node *block = be_transform_node(get_nodes_block(node));
189 ir_node *op = get_Conv_op(node);
190 ir_node *new_op = be_transform_node(op);
191 ir_mode *src_mode = get_irn_mode(op);
192 ir_mode *dst_mode = get_irn_mode(node);
193 dbg_info *dbg = get_irn_dbg_info(node);
195 if (src_mode == dst_mode)
198 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
199 env_cg->have_fp_insn = 1;
201 if (USE_FPA(env_cg->isa)) {
202 if (mode_is_float(src_mode)) {
203 if (mode_is_float(dst_mode)) {
204 /* from float to float */
205 return new_bd_arm_fpaMvf(dbg, block, new_op, dst_mode);
208 /* from float to int */
209 return new_bd_arm_fpaFix(dbg, block, new_op, dst_mode);
213 /* from int to float */
214 return new_bd_arm_fpaFlt(dbg, block, new_op, dst_mode);
217 else if (USE_VFP(env_cg->isa)) {
218 panic("VFP not supported yet");
222 panic("Softfloat not supported yet");
226 else { /* complete in gp registers */
227 int src_bits = get_mode_size_bits(src_mode);
228 int dst_bits = get_mode_size_bits(dst_mode);
232 if (is_Load(skip_Proj(op))) {
233 if (src_bits == dst_bits) {
234 /* kill unneccessary conv */
237 /* after a load, the bit size is already converted */
241 if (src_bits == dst_bits) {
242 /* kill unneccessary conv */
244 } else if (dst_bits <= 32 && src_bits <= 32) {
245 if (src_bits < dst_bits) {
252 if (mode_is_signed(min_mode)) {
253 return gen_sign_extension(dbg, block, new_op, min_bits);
255 return gen_zero_extension(dbg, block, new_op, min_bits);
258 panic("Cannot handle Conv %+F->%+F with %d->%d bits", src_mode, dst_mode,
266 * Return true if an operand is a shifter operand
268 static int is_shifter_operand(ir_node *n, arm_shift_modifier *pmod) {
269 arm_shift_modifier mod = ARM_SHF_NONE;
272 mod = get_arm_shift_modifier(n);
275 if (mod != ARM_SHF_NONE) {
276 long v = get_arm_imm_value(n);
284 * Creates an ARM Add.
286 * @return the created arm Add node
288 static ir_node *gen_Add(ir_node *node) {
289 ir_node *block = be_transform_node(get_nodes_block(node));
290 ir_node *op1 = get_Add_left(node);
291 ir_node *new_op1 = be_transform_node(op1);
292 ir_node *op2 = get_Add_right(node);
293 ir_node *new_op2 = be_transform_node(op2);
294 ir_mode *mode = get_irn_mode(node);
297 arm_shift_modifier mod;
298 dbg_info *dbg = get_irn_dbg_info(node);
300 if (mode_is_float(mode)) {
301 env_cg->have_fp_insn = 1;
302 if (USE_FPA(env_cg->isa)) {
303 if (is_arm_fpaMvf_i(new_op1))
304 return new_bd_arm_fpaAdf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
305 if (is_arm_fpaMvf_i(new_op2))
306 return new_bd_arm_fpaAdf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
307 return new_bd_arm_fpaAdf(dbg, block, new_op1, new_op2, mode);
308 } else if (USE_VFP(env_cg->isa)) {
309 assert(mode != mode_E && "IEEE Extended FP not supported");
310 panic("VFP not supported yet");
314 panic("Softfloat not supported yet");
318 assert(mode_is_data(mode));
321 if (is_arm_Mov_i(new_op1))
322 return new_bd_arm_Add_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
323 if (is_arm_Mov_i(new_op2))
324 return new_bd_arm_Add_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
327 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
329 new_op2 = get_irn_n(new_op1, 1);
330 new_op1 = get_irn_n(new_op1, 0);
332 return new_bd_arm_Mla(dbg, block, new_op1, new_op2, new_op3, mode);
334 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
336 new_op1 = get_irn_n(new_op2, 0);
337 new_op2 = get_irn_n(new_op2, 1);
339 return new_bd_arm_Mla(dbg, block, new_op1, new_op2, new_op3, mode);
342 /* is the first a shifter */
343 v = is_shifter_operand(new_op1, &mod);
345 new_op1 = get_irn_n(new_op1, 0);
346 return new_bd_arm_Add(dbg, block, new_op2, new_op1, mode, mod, v);
348 /* is the second a shifter */
349 v = is_shifter_operand(new_op2, &mod);
351 new_op2 = get_irn_n(new_op2, 0);
352 return new_bd_arm_Add(dbg, block, new_op1, new_op2, mode, mod, v);
356 return new_bd_arm_Add(dbg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0);
361 * Creates an ARM Mul.
363 * @return the created arm Mul node
365 static ir_node *gen_Mul(ir_node *node) {
366 ir_node *block = be_transform_node(get_nodes_block(node));
367 ir_node *op1 = get_Mul_left(node);
368 ir_node *new_op1 = be_transform_node(op1);
369 ir_node *op2 = get_Mul_right(node);
370 ir_node *new_op2 = be_transform_node(op2);
371 ir_mode *mode = get_irn_mode(node);
372 dbg_info *dbg = get_irn_dbg_info(node);
374 if (mode_is_float(mode)) {
375 env_cg->have_fp_insn = 1;
376 if (USE_FPA(env_cg->isa)) {
377 if (is_arm_Mov_i(new_op1))
378 return new_bd_arm_fpaMuf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
379 if (is_arm_Mov_i(new_op2))
380 return new_bd_arm_fpaMuf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
381 return new_bd_arm_fpaMuf(dbg, block, new_op1, new_op2, mode);
383 else if (USE_VFP(env_cg->isa)) {
384 assert(mode != mode_E && "IEEE Extended FP not supported");
385 panic("VFP not supported yet");
389 panic("Softfloat not supported yet");
393 assert(mode_is_data(mode));
395 return new_bd_arm_Mul(dbg, block, new_op1, new_op2, mode);
399 * Creates an ARM floating point Div.
401 * @param env The transformation environment
402 * @return the created arm fDiv node
404 static ir_node *gen_Quot(ir_node *node) {
405 ir_node *block = be_transform_node(get_nodes_block(node));
406 ir_node *op1 = get_Quot_left(node);
407 ir_node *new_op1 = be_transform_node(op1);
408 ir_node *op2 = get_Quot_right(node);
409 ir_node *new_op2 = be_transform_node(op2);
410 ir_mode *mode = get_irn_mode(node);
411 dbg_info *dbg = get_irn_dbg_info(node);
413 assert(mode != mode_E && "IEEE Extended FP not supported");
415 env_cg->have_fp_insn = 1;
416 if (USE_FPA(env_cg->isa)) {
417 if (is_arm_Mov_i(new_op1))
418 return new_bd_arm_fpaRdf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
419 if (is_arm_Mov_i(new_op2))
420 return new_bd_arm_fpaDvf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
421 return new_bd_arm_fpaDvf(dbg, block, new_op1, new_op2, mode);
422 } else if (USE_VFP(env_cg->isa)) {
423 assert(mode != mode_E && "IEEE Extended FP not supported");
424 panic("VFP not supported yet");
427 panic("Softfloat not supported yet");
432 #define GEN_INT_OP(op) \
433 ir_node *block = be_transform_node(get_nodes_block(node)); \
434 ir_node *op1 = get_ ## op ## _left(node); \
435 ir_node *new_op1 = be_transform_node(op1); \
436 ir_node *op2 = get_ ## op ## _right(node); \
437 ir_node *new_op2 = be_transform_node(op2); \
438 ir_mode *mode = mode_Iu; \
439 dbg_info *dbg = get_irn_dbg_info(node); \
441 arm_shift_modifier mod; \
443 if (is_arm_Mov_i(new_op1)) \
444 return new_bd_arm_ ## op ## _i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1)); \
445 if (is_arm_Mov_i(new_op2)) \
446 return new_bd_arm_ ## op ## _i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2)); \
447 /* is the first a shifter */ \
448 v = is_shifter_operand(new_op1, &mod); \
450 new_op1 = get_irn_n(new_op1, 0); \
451 return new_bd_arm_ ## op(dbg, block, new_op2, new_op1, mode, mod, v); \
453 /* is the second a shifter */ \
454 v = is_shifter_operand(new_op2, &mod); \
456 new_op2 = get_irn_n(new_op2, 0); \
457 return new_bd_arm_ ## op(dbg, block, new_op1, new_op2, mode, mod, v); \
460 return new_bd_arm_ ## op(dbg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0) \
463 * Creates an ARM And.
465 * @return the created arm And node
467 static ir_node *gen_And(ir_node *node) {
472 * Creates an ARM Orr.
474 * @param env The transformation environment
475 * @return the created arm Or node
477 static ir_node *gen_Or(ir_node *node) {
482 * Creates an ARM Eor.
484 * @return the created arm Eor node
486 static ir_node *gen_Eor(ir_node *node) {
491 * Creates an ARM Sub.
493 * @return the created arm Sub node
495 static ir_node *gen_Sub(ir_node *node) {
496 ir_node *block = be_transform_node(get_nodes_block(node));
497 ir_node *op1 = get_Sub_left(node);
498 ir_node *new_op1 = be_transform_node(op1);
499 ir_node *op2 = get_Sub_right(node);
500 ir_node *new_op2 = be_transform_node(op2);
501 ir_mode *mode = get_irn_mode(node);
502 dbg_info *dbg = get_irn_dbg_info(node);
504 arm_shift_modifier mod;
506 if (mode_is_float(mode)) {
507 env_cg->have_fp_insn = 1;
508 if (USE_FPA(env_cg->isa)) {
509 if (is_arm_Mov_i(new_op1))
510 return new_bd_arm_fpaRsf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
511 if (is_arm_Mov_i(new_op2))
512 return new_bd_arm_fpaSuf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
513 return new_bd_arm_fpaSuf(dbg, block, new_op1, new_op2, mode);
514 } else if (USE_VFP(env_cg->isa)) {
515 assert(mode != mode_E && "IEEE Extended FP not supported");
516 panic("VFP not supported yet");
520 panic("Softfloat not supported yet");
525 assert(mode_is_data(mode) && "unknown mode for Sub");
528 if (is_arm_Mov_i(new_op1))
529 return new_bd_arm_Rsb_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
530 if (is_arm_Mov_i(new_op2))
531 return new_bd_arm_Sub_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
533 /* is the first a shifter */
534 v = is_shifter_operand(new_op1, &mod);
536 new_op1 = get_irn_n(new_op1, 0);
537 return new_bd_arm_Rsb(dbg, block, new_op2, new_op1, mode, mod, v);
539 /* is the second a shifter */
540 v = is_shifter_operand(new_op2, &mod);
542 new_op2 = get_irn_n(new_op2, 0);
543 return new_bd_arm_Sub(dbg, block, new_op1, new_op2, mode, mod, v);
546 return new_bd_arm_Sub(dbg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0);
551 * Creates an ARM Shl.
553 * @return the created ARM Shl node
555 static ir_node *gen_Shl(ir_node *node) {
556 ir_node *block = be_transform_node(get_nodes_block(node));
557 ir_node *op1 = get_Shl_left(node);
558 ir_node *new_op1 = be_transform_node(op1);
559 ir_node *op2 = get_Shl_right(node);
560 ir_node *new_op2 = be_transform_node(op2);
561 ir_mode *mode = mode_Iu;
562 dbg_info *dbg = get_irn_dbg_info(node);
564 if (is_arm_Mov_i(new_op2)) {
565 return new_bd_arm_Mov(dbg, block, new_op1, mode, ARM_SHF_LSL, get_arm_imm_value(new_op2));
567 return new_bd_arm_Shl(dbg, block, new_op1, new_op2, mode);
571 * Creates an ARM Shr.
573 * @return the created ARM Shr node
575 static ir_node *gen_Shr(ir_node *node) {
576 ir_node *block = be_transform_node(get_nodes_block(node));
577 ir_node *op1 = get_Shr_left(node);
578 ir_node *new_op1 = be_transform_node(op1);
579 ir_node *op2 = get_Shr_right(node);
580 ir_node *new_op2 = be_transform_node(op2);
581 ir_mode *mode = mode_Iu;
582 dbg_info *dbg = get_irn_dbg_info(node);
584 if (is_arm_Mov_i(new_op2)) {
585 return new_bd_arm_Mov(dbg, block, new_op1, mode, ARM_SHF_LSR, get_arm_imm_value(new_op2));
587 return new_bd_arm_Shr(dbg, block, new_op1, new_op2, mode);
591 * Creates an ARM Shrs.
593 * @return the created ARM Shrs node
595 static ir_node *gen_Shrs(ir_node *node) {
596 ir_node *block = be_transform_node(get_nodes_block(node));
597 ir_node *op1 = get_Shrs_left(node);
598 ir_node *new_op1 = be_transform_node(op1);
599 ir_node *op2 = get_Shrs_right(node);
600 ir_node *new_op2 = be_transform_node(op2);
601 ir_mode *mode = mode_Iu;
602 dbg_info *dbg = get_irn_dbg_info(node);
604 if (is_arm_Mov_i(new_op2)) {
605 return new_bd_arm_Mov(dbg, block, new_op1, mode, ARM_SHF_ASR, get_arm_imm_value(new_op2));
607 return new_bd_arm_Shrs(dbg, block, new_op1, new_op2, mode);
611 * Creates an ARM Ror.
613 * @return the created ARM Ror node
615 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2) {
616 ir_node *block = be_transform_node(get_nodes_block(node));
617 ir_node *new_op1 = be_transform_node(op1);
618 ir_node *new_op2 = be_transform_node(op2);
619 ir_mode *mode = mode_Iu;
620 dbg_info *dbg = get_irn_dbg_info(node);
622 if (is_arm_Mov_i(new_op2)) {
623 return new_bd_arm_Mov(dbg, block, new_op1, mode, ARM_SHF_ROR, get_arm_imm_value(new_op2));
625 return new_bd_arm_Ror(dbg, block, new_op1, new_op2, mode);
629 * Creates an ARM Rol.
631 * @return the created ARM Rol node
633 * Note: there is no Rol on arm, we have to use Ror
635 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2) {
636 ir_node *block = be_transform_node(get_nodes_block(node));
637 ir_node *new_op1 = be_transform_node(op1);
638 ir_mode *mode = mode_Iu;
639 dbg_info *dbg = get_irn_dbg_info(node);
640 ir_node *new_op2 = be_transform_node(op2);
642 new_op2 = new_bd_arm_Rsb_i(dbg, block, new_op2, mode, 32);
643 return new_bd_arm_Ror(dbg, block, new_op1, new_op2, mode);
647 * Creates an ARM ROR from a Firm Rotl.
649 * @return the created ARM Ror node
651 static ir_node *gen_Rotl(ir_node *node) {
652 ir_node *rotate = NULL;
653 ir_node *op1 = get_Rotl_left(node);
654 ir_node *op2 = get_Rotl_right(node);
656 /* Firm has only RotL, so we are looking for a right (op2)
657 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
658 that means we can create a RotR. */
661 ir_node *right = get_Add_right(op2);
662 if (is_Const(right)) {
663 tarval *tv = get_Const_tarval(right);
664 ir_mode *mode = get_irn_mode(node);
665 long bits = get_mode_size_bits(mode);
666 ir_node *left = get_Add_left(op2);
668 if (is_Minus(left) &&
669 tarval_is_long(tv) &&
670 get_tarval_long(tv) == bits &&
672 rotate = gen_Ror(node, op1, get_Minus_op(left));
674 } else if (is_Sub(op2)) {
675 ir_node *left = get_Sub_left(op2);
676 if (is_Const(left)) {
677 tarval *tv = get_Const_tarval(left);
678 ir_mode *mode = get_irn_mode(node);
679 long bits = get_mode_size_bits(mode);
680 ir_node *right = get_Sub_right(op2);
682 if (tarval_is_long(tv) &&
683 get_tarval_long(tv) == bits &&
685 rotate = gen_Ror(node, op1, right);
687 } else if (is_Const(op2)) {
688 tarval *tv = get_Const_tarval(op2);
689 ir_mode *mode = get_irn_mode(node);
690 long bits = get_mode_size_bits(mode);
692 if (tarval_is_long(tv) && bits == 32) {
693 ir_node *block = be_transform_node(get_nodes_block(node));
694 ir_node *new_op1 = be_transform_node(op1);
695 ir_mode *mode = mode_Iu;
696 dbg_info *dbg = get_irn_dbg_info(node);
698 bits = (bits - get_tarval_long(tv)) & 31;
699 rotate = new_bd_arm_Mov(dbg, block, new_op1, mode, ARM_SHF_ROR, bits);
703 if (rotate == NULL) {
704 rotate = gen_Rol(node, op1, op2);
711 * Transforms a Not node.
713 * @return the created ARM Not node
715 static ir_node *gen_Not(ir_node *node) {
716 ir_node *block = be_transform_node(get_nodes_block(node));
717 ir_node *op = get_Not_op(node);
718 ir_node *new_op = be_transform_node(op);
719 dbg_info *dbg = get_irn_dbg_info(node);
720 ir_mode *mode = mode_Iu;
721 arm_shift_modifier mod = ARM_SHF_NONE;
722 int v = is_shifter_operand(new_op, &mod);
725 new_op = get_irn_n(new_op, 0);
727 return new_bd_arm_Mvn(dbg, block, new_op, mode, mod, v);
731 * Transforms an Abs node.
733 * @param env The transformation environment
734 * @return the created ARM Abs node
736 static ir_node *gen_Abs(ir_node *node) {
737 ir_node *block = be_transform_node(get_nodes_block(node));
738 ir_node *op = get_Abs_op(node);
739 ir_node *new_op = be_transform_node(op);
740 dbg_info *dbg = get_irn_dbg_info(node);
741 ir_mode *mode = get_irn_mode(node);
743 if (mode_is_float(mode)) {
744 env_cg->have_fp_insn = 1;
745 if (USE_FPA(env_cg->isa))
746 return new_bd_arm_fpaAbs(dbg, block, new_op, mode);
747 else if (USE_VFP(env_cg->isa)) {
748 assert(mode != mode_E && "IEEE Extended FP not supported");
749 panic("VFP not supported yet");
752 panic("Softfloat not supported yet");
755 assert(mode_is_data(mode));
757 return new_bd_arm_Abs(dbg, block, new_op, mode);
761 * Transforms a Minus node.
763 * @return the created ARM Minus node
765 static ir_node *gen_Minus(ir_node *node) {
766 ir_node *block = be_transform_node(get_nodes_block(node));
767 ir_node *op = get_Minus_op(node);
768 ir_node *new_op = be_transform_node(op);
769 dbg_info *dbg = get_irn_dbg_info(node);
770 ir_mode *mode = get_irn_mode(node);
772 if (mode_is_float(mode)) {
773 env_cg->have_fp_insn = 1;
774 if (USE_FPA(env_cg->isa))
775 return new_bd_arm_fpaMvf(dbg, block, op, mode);
776 else if (USE_VFP(env_cg->isa)) {
777 assert(mode != mode_E && "IEEE Extended FP not supported");
778 panic("VFP not supported yet");
781 panic("Softfloat not supported yet");
784 assert(mode_is_data(mode));
786 return new_bd_arm_Rsb_i(dbg, block, new_op, mode, 0);
792 * @return the created ARM Load node
794 static ir_node *gen_Load(ir_node *node) {
795 ir_node *block = be_transform_node(get_nodes_block(node));
796 ir_node *ptr = get_Load_ptr(node);
797 ir_node *new_ptr = be_transform_node(ptr);
798 ir_node *mem = get_Load_mem(node);
799 ir_node *new_mem = be_transform_node(mem);
800 ir_mode *mode = get_Load_mode(node);
801 dbg_info *dbg = get_irn_dbg_info(node);
802 ir_node *new_load = NULL;
804 if (mode_is_float(mode)) {
805 env_cg->have_fp_insn = 1;
806 if (USE_FPA(env_cg->isa))
807 new_load = new_bd_arm_fpaLdf(dbg, block, new_ptr, new_mem, mode);
808 else if (USE_VFP(env_cg->isa)) {
809 assert(mode != mode_E && "IEEE Extended FP not supported");
810 panic("VFP not supported yet");
813 panic("Softfloat not supported yet");
817 assert(mode_is_data(mode) && "unsupported mode for Load");
819 if (mode_is_signed(mode)) {
820 /* sign extended loads */
821 switch (get_mode_size_bits(mode)) {
823 new_load = new_bd_arm_Loadbs(dbg, block, new_ptr, new_mem);
826 new_load = new_bd_arm_Loadhs(dbg, block, new_ptr, new_mem);
829 new_load = new_bd_arm_Load(dbg, block, new_ptr, new_mem);
832 panic("mode size not supported");
835 /* zero extended loads */
836 switch (get_mode_size_bits(mode)) {
838 new_load = new_bd_arm_Loadb(dbg, block, new_ptr, new_mem);
841 new_load = new_bd_arm_Loadh(dbg, block, new_ptr, new_mem);
844 new_load = new_bd_arm_Load(dbg, block, new_ptr, new_mem);
847 panic("mode size not supported");
851 set_irn_pinned(new_load, get_irn_pinned(node));
853 /* check for special case: the loaded value might not be used */
854 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
855 ir_graph *irg = current_ir_graph;
857 /* add a result proj and a Keep to produce a pseudo use */
858 ir_node *proj = new_r_Proj(irg, block, new_load, mode_Iu, pn_arm_Load_res);
859 be_new_Keep(arch_get_irn_reg_class_out(proj), irg, block, 1, &proj);
866 * Transforms a Store.
868 * @return the created ARM Store node
870 static ir_node *gen_Store(ir_node *node) {
871 ir_node *block = be_transform_node(get_nodes_block(node));
872 ir_node *ptr = get_Store_ptr(node);
873 ir_node *new_ptr = be_transform_node(ptr);
874 ir_node *mem = get_Store_mem(node);
875 ir_node *new_mem = be_transform_node(mem);
876 ir_node *val = get_Store_value(node);
877 ir_node *new_val = be_transform_node(val);
878 ir_mode *mode = get_irn_mode(val);
879 dbg_info *dbg = get_irn_dbg_info(node);
880 ir_node *new_store = NULL;
882 if (mode_is_float(mode)) {
883 env_cg->have_fp_insn = 1;
884 if (USE_FPA(env_cg->isa))
885 new_store = new_bd_arm_fpaStf(dbg, block, new_ptr, new_val, new_mem, mode);
886 else if (USE_VFP(env_cg->isa)) {
887 assert(mode != mode_E && "IEEE Extended FP not supported");
888 panic("VFP not supported yet");
890 panic("Softfloat not supported yet");
893 assert(mode_is_data(mode) && "unsupported mode for Store");
894 switch (get_mode_size_bits(mode)) {
896 new_store = new_bd_arm_Storeb(dbg, block, new_ptr, new_val, new_mem);
898 new_store = new_bd_arm_Storeh(dbg, block, new_ptr, new_val, new_mem);
900 new_store = new_bd_arm_Store(dbg, block, new_ptr, new_val, new_mem);
903 set_irn_pinned(new_store, get_irn_pinned(node));
910 * @return the created ARM Cond node
912 static ir_node *gen_Cond(ir_node *node) {
913 ir_node *block = be_transform_node(get_nodes_block(node));
914 ir_node *selector = get_Cond_selector(node);
915 dbg_info *dbg = get_irn_dbg_info(node);
916 ir_mode *mode = get_irn_mode(selector);
918 if (mode == mode_b) {
919 /* an conditional jump */
920 ir_node *cmp_node = get_Proj_pred(selector);
921 ir_node *op1 = get_Cmp_left(cmp_node);
922 ir_node *new_op1 = be_transform_node(op1);
923 ir_node *op2 = get_Cmp_right(cmp_node);
925 if (mode_is_float(get_irn_mode(op1))) {
926 ir_node *new_op2 = be_transform_node(op2);
927 /* floating point compare */
928 pn_Cmp pnc = get_Proj_proj(selector);
930 if (pnc & pn_Cmp_Uo) {
931 /* check for unordered, need cmf */
932 return new_bd_arm_fpaCmfBra(dbg, block, new_op1, new_op2, pnc);
934 /* Hmm: use need cmfe */
935 return new_bd_arm_fpaCmfeBra(dbg, block, new_op1, new_op2, pnc);
936 } else if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) {
938 return new_bd_arm_TstBra(dbg, block, new_op1, new_op1, get_Proj_proj(selector));
940 /* integer compare */
941 ir_node *new_op2 = be_transform_node(op2);
942 return new_bd_arm_CmpBra(dbg, block, new_op1, new_op2, get_Proj_proj(selector));
946 ir_node *new_op = be_transform_node(selector);
947 ir_node *const_graph;
951 const ir_edge_t *edge;
958 foreach_out_edge(node, edge) {
959 proj = get_edge_src_irn(edge);
960 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
962 pn = get_Proj_proj(proj);
964 min = pn<min ? pn : min;
965 max = pn>max ? pn : max;
968 n_projs = max - translation + 1;
970 foreach_out_edge(node, edge) {
971 proj = get_edge_src_irn(edge);
972 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
974 pn = get_Proj_proj(proj) - translation;
975 set_Proj_proj(proj, pn);
978 const_graph = create_const_graph_value(dbg, block, translation);
979 sub = new_bd_arm_Sub(dbg, block, new_op, const_graph, mode, ARM_SHF_NONE, 0);
980 return new_bd_arm_SwitchJmp(dbg, block, sub, n_projs, get_Cond_defaultProj(node) - translation);
985 * Returns the name of a SymConst.
986 * @param symc the SymConst
987 * @return name of the SymConst
989 static ident *get_sc_ident(ir_node *symc) {
992 switch (get_SymConst_kind(symc)) {
993 case symconst_addr_name:
994 return get_SymConst_name(symc);
996 case symconst_addr_ent:
997 ent = get_SymConst_entity(symc);
998 set_entity_backend_marked(ent, 1);
999 return get_entity_ld_ident(ent);
1002 assert(0 && "Unsupported SymConst");
1008 static tarval *fpa_imm[3][fpa_max];
1011 * Check, if a floating point tarval is an fpa immediate, i.e.
1012 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
1014 static int is_fpa_immediate(tarval *tv) {
1015 ir_mode *mode = get_tarval_mode(tv);
1018 switch (get_mode_size_bits(mode)) {
1029 if (tarval_cmp(tv, get_tarval_null(mode)) & pn_Cmp_Lt) {
1030 tv = tarval_neg(tv);
1034 for (j = 0; j < fpa_max; ++j) {
1035 if (tv == fpa_imm[i][j])
1042 * Transforms a Const node.
1044 * @return The transformed ARM node.
1046 static ir_node *gen_Const(ir_node *node) {
1047 ir_node *block = be_transform_node(get_nodes_block(node));
1048 ir_mode *mode = get_irn_mode(node);
1049 dbg_info *dbg = get_irn_dbg_info(node);
1051 if (mode_is_float(mode)) {
1052 env_cg->have_fp_insn = 1;
1053 if (USE_FPA(env_cg->isa)) {
1054 tarval *tv = get_Const_tarval(node);
1055 int imm = is_fpa_immediate(tv);
1057 if (imm != fpa_max) {
1059 node = new_bd_arm_fpaMvf_i(dbg, block, mode, imm);
1061 node = new_bd_arm_fpaMnf_i(dbg, block, mode, -imm);
1063 node = new_bd_arm_fpaConst(dbg, block, tv);
1065 be_dep_on_frame(node);
1068 else if (USE_VFP(env_cg->isa)) {
1069 assert(mode != mode_E && "IEEE Extended FP not supported");
1070 panic("VFP not supported yet");
1073 panic("Softfloat not supported yet");
1076 return create_const_graph(node, block);
1080 * Transforms a SymConst node.
1082 * @return The transformed ARM node.
1084 static ir_node *gen_SymConst(ir_node *node) {
1085 ir_node *block = be_transform_node(get_nodes_block(node));
1086 ir_mode *mode = mode_Iu;
1087 dbg_info *dbg = get_irn_dbg_info(node);
1090 res = new_bd_arm_SymConst(dbg, block, mode, get_sc_ident(node));
1091 be_dep_on_frame(res);
1096 * Transforms a CopyB node.
1098 * @return The transformed ARM node.
1100 static ir_node *gen_CopyB(ir_node *node) {
1101 ir_node *block = be_transform_node(get_nodes_block(node));
1102 ir_node *src = get_CopyB_src(node);
1103 ir_node *new_src = be_transform_node(src);
1104 ir_node *dst = get_CopyB_dst(node);
1105 ir_node *new_dst = be_transform_node(dst);
1106 ir_node *mem = get_CopyB_mem(node);
1107 ir_node *new_mem = be_transform_node(mem);
1108 ir_graph *irg = current_ir_graph;
1109 dbg_info *dbg = get_irn_dbg_info(node);
1110 int size = get_type_size_bytes(get_CopyB_type(node));
1114 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, new_src);
1115 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, new_dst);
1117 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1118 new_bd_arm_EmptyReg(dbg, block, mode_Iu),
1119 new_bd_arm_EmptyReg(dbg, block, mode_Iu),
1120 new_bd_arm_EmptyReg(dbg, block, mode_Iu),
1125 /********************************************
1128 * | |__ ___ _ __ ___ __| | ___ ___
1129 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1130 * | |_) | __/ | | | (_) | (_| | __/\__ \
1131 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1133 ********************************************/
1136 * Return an expanding stack offset.
1137 * Note that function is called in the transform phase
1138 * where the stack offsets are still relative regarding
1139 * the first (frame allocating) IncSP.
1140 * However this is exactly what we want because frame
1141 * access must be done relative the the fist IncSP ...
1143 static int get_sp_expand_offset(ir_node *inc_sp) {
1144 int offset = be_get_IncSP_offset(inc_sp);
1146 if (offset == BE_STACK_FRAME_SIZE_EXPAND)
1153 static ir_node *gen_StackParam(ir_node *irn) {
1154 ir_node *block = be_transform_node(get_nodes_block(node));
1155 ir_node *new_op = NULL;
1156 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1157 ir_node *mem = new_NoMem();
1158 ir_node *ptr = get_irn_n(irn, 0);
1159 ir_entity *ent = be_get_frame_entity(irn);
1160 ir_mode *mode = env->mode;
1162 // /* If the StackParam has only one user -> */
1163 // /* put it in the Block where the user resides */
1164 // if (get_irn_n_edges(node) == 1) {
1165 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1168 if (mode_is_float(mode)) {
1169 if (USE_SSE2(env->cg))
1170 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1172 env->cg->used_x87 = 1;
1173 new_op = new_rd_ia32_vfld(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1177 new_op = new_rd_ia32_Load(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1180 set_ia32_frame_ent(new_op, ent);
1181 set_ia32_use_frame(new_op);
1183 set_ia32_am_support(new_op, ia32_am_Source);
1184 set_ia32_op_type(new_op, ia32_AddrModeS);
1185 set_ia32_am_flavour(new_op, ia32_B);
1186 set_ia32_ls_mode(new_op, mode);
1188 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1190 return new_rd_Proj(env->dbg, env->irg, block, new_op, mode, 0);
1195 * Transforms a FrameAddr into an ARM Add.
1197 static ir_node *gen_be_FrameAddr(ir_node *node) {
1198 ir_node *block = be_transform_node(get_nodes_block(node));
1199 ir_entity *ent = be_get_frame_entity(node);
1200 int offset = get_entity_offset(ent);
1201 ir_node *op = be_get_FrameAddr_frame(node);
1202 ir_node *new_op = be_transform_node(op);
1203 dbg_info *dbg = get_irn_dbg_info(node);
1204 ir_mode *mode = mode_Iu;
1207 if (be_is_IncSP(op)) {
1208 /* BEWARE: we get an offset which is absolute from an offset that
1209 is relative. Both must be merged */
1210 offset += get_sp_expand_offset(op);
1212 cnst = create_const_graph_value(dbg, block, (unsigned)offset);
1213 if (is_arm_Mov_i(cnst))
1214 return new_bd_arm_Add_i(dbg, block, new_op, mode, get_arm_imm_value(cnst));
1215 return new_bd_arm_Add(dbg, block, new_op, cnst, mode, ARM_SHF_NONE, 0);
1219 * Transform a be_AddSP into an arm_AddSP. Eat up const sizes.
1221 static ir_node *gen_be_AddSP(ir_node *node) {
1222 ir_node *block = be_transform_node(get_nodes_block(node));
1223 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
1224 ir_node *new_sz = be_transform_node(sz);
1225 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
1226 ir_node *new_sp = be_transform_node(sp);
1227 dbg_info *dbgi = get_irn_dbg_info(node);
1228 ir_node *nomem = new_NoMem();
1231 /* ARM stack grows in reverse direction, make a SubSPandCopy */
1232 new_op = new_bd_arm_SubSPandCopy(dbgi, block, new_sp, new_sz, nomem);
1238 * Transform a be_SubSP into an arm_SubSP. Eat up const sizes.
1240 static ir_node *gen_be_SubSP(ir_node *node) {
1241 ir_node *block = be_transform_node(get_nodes_block(node));
1242 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
1243 ir_node *new_sz = be_transform_node(sz);
1244 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
1245 ir_node *new_sp = be_transform_node(sp);
1246 dbg_info *dbgi = get_irn_dbg_info(node);
1247 ir_node *nomem = new_NoMem();
1250 /* ARM stack grows in reverse direction, make an AddSP */
1251 new_op = new_bd_arm_AddSP(dbgi, block, new_sp, new_sz, nomem);
1257 * Transform a be_Copy.
1259 static ir_node *gen_be_Copy(ir_node *node) {
1260 ir_node *result = be_duplicate_node(node);
1261 ir_mode *mode = get_irn_mode(result);
1263 if (mode_needs_gp_reg(mode)) {
1264 set_irn_mode(node, mode_Iu);
1271 * Transform a Proj from a Load.
1273 static ir_node *gen_Proj_Load(ir_node *node) {
1274 ir_node *block = be_transform_node(get_nodes_block(node));
1275 ir_node *load = get_Proj_pred(node);
1276 ir_node *new_load = be_transform_node(load);
1277 ir_graph *irg = current_ir_graph;
1278 dbg_info *dbgi = get_irn_dbg_info(node);
1279 long proj = get_Proj_proj(node);
1281 /* renumber the proj */
1282 switch (get_arm_irn_opcode(new_load)) {
1285 case iro_arm_Loadbs:
1287 case iro_arm_Loadhs:
1288 /* handle all gp loads equal: they have the same proj numbers. */
1289 if (proj == pn_Load_res) {
1290 return new_rd_Proj(dbgi, irg, block, new_load, mode_Iu, pn_arm_Load_res);
1291 } else if (proj == pn_Load_M) {
1292 return new_rd_Proj(dbgi, irg, block, new_load, mode_M, pn_arm_Load_M);
1295 case iro_arm_fpaLdf:
1296 if (proj == pn_Load_res) {
1297 ir_mode *mode = get_Load_mode(load);
1298 return new_rd_Proj(dbgi, irg, block, new_load, mode, pn_arm_fpaLdf_res);
1299 } else if (proj == pn_Load_M) {
1300 return new_rd_Proj(dbgi, irg, block, new_load, mode_M, pn_arm_fpaLdf_M);
1306 panic("Unsupported Proj from Load");
1310 * Transform and renumber the Projs from a CopyB.
1312 static ir_node *gen_Proj_CopyB(ir_node *node) {
1313 ir_node *block = be_transform_node(get_nodes_block(node));
1314 ir_node *pred = get_Proj_pred(node);
1315 ir_node *new_pred = be_transform_node(pred);
1316 ir_graph *irg = current_ir_graph;
1317 dbg_info *dbgi = get_irn_dbg_info(node);
1318 long proj = get_Proj_proj(node);
1321 case pn_CopyB_M_regular:
1322 if (is_arm_CopyB(new_pred)) {
1323 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_CopyB_M);
1329 panic("Unsupported Proj from CopyB");
1333 * Transform and renumber the Projs from a Quot.
1335 static ir_node *gen_Proj_Quot(ir_node *node) {
1336 ir_node *block = be_transform_node(get_nodes_block(node));
1337 ir_node *pred = get_Proj_pred(node);
1338 ir_node *new_pred = be_transform_node(pred);
1339 ir_graph *irg = current_ir_graph;
1340 dbg_info *dbgi = get_irn_dbg_info(node);
1341 ir_mode *mode = get_irn_mode(node);
1342 long proj = get_Proj_proj(node);
1346 if (is_arm_fpaDvf(new_pred) || is_arm_fpaDvf_i(new_pred)) {
1347 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaDvf_M);
1348 } else if (is_arm_fpaRdf(new_pred) || is_arm_fpaRdf_i(new_pred)) {
1349 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaRdf_M);
1350 } else if (is_arm_fpaFdv(new_pred) || is_arm_fpaFdv_i(new_pred)) {
1351 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaFdv_M);
1352 } else if (is_arm_fpaFrd(new_pred) || is_arm_fpaFrd_i(new_pred)) {
1353 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaFrd_M);
1357 if (is_arm_fpaDvf(new_pred) || is_arm_fpaDvf_i(new_pred)) {
1358 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaDvf_res);
1359 } else if (is_arm_fpaRdf(new_pred) || is_arm_fpaRdf_i(new_pred)) {
1360 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaRdf_res);
1361 } else if (is_arm_fpaFdv(new_pred) || is_arm_fpaFdv_i(new_pred)) {
1362 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaFdv_res);
1363 } else if (is_arm_fpaFrd(new_pred) || is_arm_fpaFrd_i(new_pred)) {
1364 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaFrd_res);
1370 panic("Unsupported Proj from Quot");
1374 * Transform the Projs of a be_AddSP.
1376 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
1377 ir_node *block = be_transform_node(get_nodes_block(node));
1378 ir_node *pred = get_Proj_pred(node);
1379 ir_node *new_pred = be_transform_node(pred);
1380 ir_graph *irg = current_ir_graph;
1381 dbg_info *dbgi = get_irn_dbg_info(node);
1382 long proj = get_Proj_proj(node);
1384 if (proj == pn_be_AddSP_sp) {
1385 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
1386 pn_arm_SubSPandCopy_stack);
1387 arch_set_irn_register(res, &arm_gp_regs[REG_SP]);
1389 } else if(proj == pn_be_AddSP_res) {
1390 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
1391 pn_arm_SubSPandCopy_addr);
1392 } else if (proj == pn_be_AddSP_M) {
1393 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_SubSPandCopy_M);
1395 panic("Unsupported Proj from AddSP");
1399 * Transform the Projs of a be_SubSP.
1401 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
1402 ir_node *block = be_transform_node(get_nodes_block(node));
1403 ir_node *pred = get_Proj_pred(node);
1404 ir_node *new_pred = be_transform_node(pred);
1405 ir_graph *irg = current_ir_graph;
1406 dbg_info *dbgi = get_irn_dbg_info(node);
1407 long proj = get_Proj_proj(node);
1409 if (proj == pn_be_SubSP_sp) {
1410 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
1411 pn_arm_AddSP_stack);
1412 arch_set_irn_register(res, &arm_gp_regs[REG_SP]);
1414 } else if (proj == pn_be_SubSP_M) {
1415 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_AddSP_M);
1417 panic("Unsupported Proj from SubSP");
1421 * Transform the Projs from a Cmp.
1423 static ir_node *gen_Proj_Cmp(ir_node *node) {
1430 * Transform the Thread Local Storage Proj.
1432 static ir_node *gen_Proj_tls(ir_node *node) {
1433 ir_node *block = be_transform_node(get_nodes_block(node));
1434 dbg_info *dbgi = NULL;
1436 return new_bd_arm_LdTls(dbgi, block, mode_Iu);
1440 * Transform a Proj node.
1442 static ir_node *gen_Proj(ir_node *node) {
1443 ir_graph *irg = current_ir_graph;
1444 dbg_info *dbgi = get_irn_dbg_info(node);
1445 ir_node *pred = get_Proj_pred(node);
1446 long proj = get_Proj_proj(node);
1448 if (is_Store(pred)) {
1449 if (proj == pn_Store_M) {
1450 return be_transform_node(pred);
1452 panic("Unsupported Proj from Store");
1454 } else if (is_Load(pred)) {
1455 return gen_Proj_Load(node);
1456 } else if (is_CopyB(pred)) {
1457 return gen_Proj_CopyB(node);
1458 } else if (is_Quot(pred)) {
1459 return gen_Proj_Quot(node);
1460 } else if (be_is_SubSP(pred)) {
1461 return gen_Proj_be_SubSP(node);
1462 } else if (be_is_AddSP(pred)) {
1463 return gen_Proj_be_AddSP(node);
1464 } else if (is_Cmp(pred)) {
1465 return gen_Proj_Cmp(node);
1466 } else if (is_Start(pred)) {
1467 if (proj == pn_Start_X_initial_exec) {
1468 ir_node *block = get_nodes_block(pred);
1471 /* we exchange the ProjX with a jump */
1472 block = be_transform_node(block);
1473 jump = new_rd_Jmp(dbgi, irg, block);
1476 if (node == get_irg_anchor(irg, anchor_tls)) {
1477 return gen_Proj_tls(node);
1480 ir_node *new_pred = be_transform_node(pred);
1481 ir_mode *mode = get_irn_mode(node);
1482 if (mode_needs_gp_reg(mode)) {
1483 ir_node *block = be_transform_node(get_nodes_block(node));
1484 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
1485 get_Proj_proj(node));
1486 #ifdef DEBUG_libfirm
1487 new_proj->node_nr = node->node_nr;
1493 return be_duplicate_node(node);
1496 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1498 static inline ir_node *create_const(ir_node **place,
1499 create_const_node_func func,
1500 const arch_register_t* reg)
1502 ir_node *block, *res;
1507 block = get_irg_start_block(env_cg->irg);
1508 res = func(NULL, block);
1509 arch_set_irn_register(res, reg);
1514 static ir_node *arm_new_Unknown_gp(void) {
1515 return create_const(&env_cg->unknown_gp, new_bd_arm_Unknown_GP,
1516 &arm_gp_regs[REG_GP_UKNWN]);
1519 static ir_node *arm_new_Unknown_fpa(void) {
1520 return create_const(&env_cg->unknown_fpa, new_bd_arm_Unknown_FPA,
1521 &arm_fpa_regs[REG_FPA_UKNWN]);
1525 * This function just sets the register for the Unknown node
1526 * as this is not done during register allocation because Unknown
1527 * is an "ignore" node.
1529 static ir_node *gen_Unknown(ir_node *node) {
1530 ir_mode *mode = get_irn_mode(node);
1531 if (mode_is_float(mode)) {
1532 if (USE_FPA(env_cg->isa))
1533 return arm_new_Unknown_fpa();
1534 else if (USE_VFP(env_cg->isa))
1535 panic("VFP not supported yet");
1537 panic("Softfloat not supported yet");
1538 } else if (mode_needs_gp_reg(mode)) {
1539 return arm_new_Unknown_gp();
1541 assert(0 && "unsupported Unknown-Mode");
1548 * Change some phi modes
1550 static ir_node *gen_Phi(ir_node *node) {
1551 ir_node *block = be_transform_node(get_nodes_block(node));
1552 ir_graph *irg = current_ir_graph;
1553 dbg_info *dbgi = get_irn_dbg_info(node);
1554 ir_mode *mode = get_irn_mode(node);
1557 if (mode_needs_gp_reg(mode)) {
1558 /* we shouldn't have any 64bit stuff around anymore */
1559 assert(get_mode_size_bits(mode) <= 32);
1560 /* all integer operations are on 32bit registers now */
1564 /* phi nodes allow loops, so we use the old arguments for now
1565 * and fix this later */
1566 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
1567 copy_node_attr(node, phi);
1568 be_duplicate_deps(node, phi);
1570 be_enqueue_preds(node);
1575 /*********************************************************
1578 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1579 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1580 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1581 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1583 *********************************************************/
1586 * the BAD transformer.
1588 static ir_node *bad_transform(ir_node *irn) {
1589 panic("ARM backend: Not implemented: %+F", irn);
1594 * Set a node emitter. Make it a bit more type safe.
1596 static inline void set_transformer(ir_op *op, be_transform_func arm_transform_func) {
1597 op->ops.generic = (op_func)arm_transform_func;
1601 * Enters all transform functions into the generic pointer
1603 static void arm_register_transformers(void) {
1604 /* first clear the generic function pointer for all ops */
1605 clear_irp_opcodes_generic_func();
1607 #define GEN(a) set_transformer(op_##a, gen_##a)
1608 #define BAD(a) set_transformer(op_##a, bad_transform)
1613 BAD(Mulh); /* unsupported yet */
1625 /* should be lowered */
1639 BAD(ASM); /* unsupported yet */
1641 BAD(Mux); /* unsupported yet */
1648 /* we should never see these nodes */
1663 /* handle builtins */
1666 /* handle generic backend nodes */
1674 /* set the register for all Unknown nodes */
1682 * Pre-transform all unknown nodes.
1684 static void arm_pretransform_node(void)
1686 arm_code_gen_t *cg = env_cg;
1688 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
1689 cg->unknown_fpa = be_pre_transform_node(cg->unknown_fpa);
1693 * Initialize fpa Immediate support.
1695 static void arm_init_fpa_immediate(void) {
1696 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
1697 fpa_imm[0][fpa_null] = get_tarval_null(mode_F);
1698 fpa_imm[0][fpa_one] = get_tarval_one(mode_F);
1699 fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
1700 fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
1701 fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
1702 fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
1703 fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
1704 fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
1706 fpa_imm[1][fpa_null] = get_tarval_null(mode_D);
1707 fpa_imm[1][fpa_one] = get_tarval_one(mode_D);
1708 fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
1709 fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
1710 fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
1711 fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
1712 fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
1713 fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
1715 fpa_imm[2][fpa_null] = get_tarval_null(mode_E);
1716 fpa_imm[2][fpa_one] = get_tarval_one(mode_E);
1717 fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
1718 fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
1719 fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
1720 fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
1721 fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
1722 fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
1726 * Transform a Firm graph into an ARM graph.
1728 void arm_transform_graph(arm_code_gen_t *cg) {
1729 static int imm_initialized = 0;
1731 if (! imm_initialized) {
1732 arm_init_fpa_immediate();
1733 imm_initialized = 1;
1735 arm_register_transformers();
1737 be_transform_graph(cg->birg, arm_pretransform_node);
1740 void arm_init_transform(void) {
1741 // FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");