2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
31 #include "irgraph_t.h"
43 #include "../benode_t.h"
44 #include "../beirg_t.h"
45 #include "../beutil.h"
46 #include "../betranshlp.h"
47 #include "bearch_arm_t.h"
49 #include "arm_nodes_attr.h"
51 #include "arm_transform.h"
52 #include "arm_optimize.h"
53 #include "arm_new_nodes.h"
54 #include "arm_map_regs.h"
56 #include "gen_arm_regalloc_if.h"
61 /** hold the current code generator during transformation */
62 static arm_code_gen_t *env_cg;
64 extern ir_op *get_op_Mulh(void);
67 /****************************************************************************************************
69 * | | | | / _| | | (_)
70 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
71 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
72 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
73 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
75 ****************************************************************************************************/
77 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
78 return mode_is_int(mode) || mode_is_reference(mode);
82 * Creates a arm_Const node.
84 static ir_node *create_mov_node(dbg_info *dbg, ir_node *block, long value) {
85 ir_mode *mode = mode_Iu;
86 ir_graph *irg = current_ir_graph;
89 if (mode_needs_gp_reg(mode))
91 res = new_rd_arm_Mov_i(dbg, irg, block, mode, value);
92 /* ensure the const is scheduled AFTER the stack frame */
93 add_irn_dep(res, get_irg_frame(irg));
98 * Creates a arm_Const_Neg node.
100 static ir_node *create_mvn_node(dbg_info *dbg, ir_node *block, long value) {
101 ir_mode *mode = mode_Iu;
102 ir_graph *irg = current_ir_graph;
105 if (mode_needs_gp_reg(mode))
107 res = new_rd_arm_Mvn_i(dbg, irg, block, mode, value);
108 /* ensure the const is scheduled AFTER the stack frame */
109 add_irn_dep(res, get_irg_frame(irg));
113 #define NEW_BINOP_NODE(opname, env, op1, op2) new_rd_arm_##opname(env->dbg, current_ir_graph, env->block, op1, op2, env->mode)
116 * Creates a possible DAG for an constant.
118 static ir_node *create_const_graph_value(dbg_info *dbg, ir_node *block, unsigned int value) {
122 ir_mode *mode = mode_Iu;
124 arm_gen_vals_from_word(value, &v);
125 arm_gen_vals_from_word(~value, &vn);
127 if (vn.ops < v.ops) {
129 result = create_mvn_node(dbg, block, arm_encode_imm_w_shift(vn.shifts[0], vn.values[0]));
131 for (cnt = 1; cnt < vn.ops; ++cnt) {
132 long value = arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]);
133 ir_node *bic_i_node = new_rd_arm_Bic_i(dbg, current_ir_graph, block, result, mode, value);
139 result = create_mov_node(dbg, block, arm_encode_imm_w_shift(v.shifts[0], v.values[0]));
141 for (cnt = 1; cnt < v.ops; ++cnt) {
142 long value = arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]);
143 ir_node *orr_i_node = new_rd_arm_Or_i(dbg, current_ir_graph, block, result, mode, value);
151 * Create a DAG constructing a given Const.
153 * @param irn a Firm const
155 static ir_node *create_const_graph(ir_node *irn, ir_node *block) {
156 tarval *tv = get_Const_tarval(irn);
157 ir_mode *mode = get_tarval_mode(tv);
160 if (mode_is_reference(mode)) {
161 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
162 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
163 tv = tarval_convert_to(tv, mode_Iu);
165 value = get_tarval_long(tv);
166 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
170 * Create an And that will mask all upper bits
172 static ir_node *gen_zero_extension(dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) {
173 unsigned mask_bits = (1 << result_bits) - 1;
174 ir_node *mask_node = create_const_graph_value(dbg, block, mask_bits);
175 return new_rd_arm_And(dbg, current_ir_graph, block, op, mask_node, mode_Iu, ARM_SHF_NONE, 0);
179 * Generate code for a sign extension.
181 static ir_node *gen_sign_extension(dbg_info *dbg, ir_node *block, ir_node *op, int result_bits) {
182 ir_graph *irg = current_ir_graph;
183 int shift_width = 32 - result_bits;
184 ir_node *shift_const_node = create_const_graph_value(dbg, block, shift_width);
185 ir_node *lshift_node = new_rd_arm_Shl(dbg, irg, block, op, shift_const_node, mode_Iu);
186 ir_node *rshift_node = new_rd_arm_Shrs(dbg, irg, block, lshift_node, shift_const_node, mode_Iu);
191 * Transforms a Conv node.
193 * @return The created ia32 Conv node
195 static ir_node *gen_Conv(ir_node *node) {
196 ir_node *block = be_transform_node(get_nodes_block(node));
197 ir_node *op = get_Conv_op(node);
198 ir_node *new_op = be_transform_node(op);
199 ir_graph *irg = current_ir_graph;
200 ir_mode *src_mode = get_irn_mode(op);
201 ir_mode *dst_mode = get_irn_mode(node);
202 dbg_info *dbg = get_irn_dbg_info(node);
204 if (src_mode == dst_mode)
207 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
208 env_cg->have_fp_insn = 1;
210 if (USE_FPA(env_cg->isa)) {
211 if (mode_is_float(src_mode)) {
212 if (mode_is_float(dst_mode)) {
213 /* from float to float */
214 return new_rd_arm_fpaMvf(dbg, irg, block, new_op, dst_mode);
217 /* from float to int */
218 return new_rd_arm_fpaFix(dbg, irg, block, new_op, dst_mode);
222 /* from int to float */
223 return new_rd_arm_fpaFlt(dbg, irg, block, new_op, dst_mode);
226 else if (USE_VFP(env_cg->isa)) {
227 panic("VFP not supported yet\n");
231 panic("Softfloat not supported yet\n");
235 else { /* complete in gp registers */
236 int src_bits = get_mode_size_bits(src_mode);
237 int dst_bits = get_mode_size_bits(dst_mode);
241 if (is_Load(skip_Proj(op))) {
242 if (src_bits == dst_bits) {
243 /* kill unneccessary conv */
246 /* after a load, the bit size is already converted */
250 if (src_bits == dst_bits) {
251 /* kill unneccessary conv */
253 } else if (dst_bits <= 32 && src_bits <= 32) {
254 if (src_bits < dst_bits) {
261 if (mode_is_signed(min_mode)) {
262 return gen_sign_extension(dbg, block, new_op, min_bits);
264 return gen_zero_extension(dbg, block, new_op, min_bits);
267 panic("Cannot handle Conv %+F->%+F with %d->%d bits\n", src_mode, dst_mode,
275 * Return true if an operand is a shifter operand
277 static int is_shifter_operand(ir_node *n, arm_shift_modifier *pmod) {
278 arm_shift_modifier mod = ARM_SHF_NONE;
281 mod = get_arm_shift_modifier(n);
284 if (mod != ARM_SHF_NONE) {
285 long v = get_arm_imm_value(n);
293 * Creates an ARM Add.
295 * @return the created arm Add node
297 static ir_node *gen_Add(ir_node *node) {
298 ir_node *block = be_transform_node(get_nodes_block(node));
299 ir_node *op1 = get_Add_left(node);
300 ir_node *new_op1 = be_transform_node(op1);
301 ir_node *op2 = get_Add_right(node);
302 ir_node *new_op2 = be_transform_node(op2);
303 ir_mode *mode = get_irn_mode(node);
304 ir_graph *irg = current_ir_graph;
307 arm_shift_modifier mod;
308 dbg_info *dbg = get_irn_dbg_info(node);
310 if (mode_is_float(mode)) {
311 env_cg->have_fp_insn = 1;
312 if (USE_FPA(env_cg->isa)) {
313 if (is_arm_fpaMvf_i(new_op1))
314 return new_rd_arm_fpaAdf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1));
315 if (is_arm_fpaMvf_i(new_op2))
316 return new_rd_arm_fpaAdf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2));
317 return new_rd_arm_fpaAdf(dbg, irg, block, new_op1, new_op2, mode);
318 } else if (USE_VFP(env_cg->isa)) {
319 assert(mode != mode_E && "IEEE Extended FP not supported");
320 panic("VFP not supported yet\n");
324 panic("Softfloat not supported yet\n");
328 assert(mode_is_data(mode));
331 if (is_arm_Mov_i(new_op1))
332 return new_rd_arm_Add_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1));
333 if (is_arm_Mov_i(new_op2))
334 return new_rd_arm_Add_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2));
337 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
339 new_op2 = get_irn_n(new_op1, 1);
340 new_op1 = get_irn_n(new_op1, 0);
342 return new_rd_arm_Mla(dbg, irg, block, new_op1, new_op2, new_op3, mode);
344 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
346 new_op1 = get_irn_n(new_op2, 0);
347 new_op2 = get_irn_n(new_op2, 1);
349 return new_rd_arm_Mla(dbg, irg, block, new_op1, new_op2, new_op3, mode);
352 /* is the first a shifter */
353 v = is_shifter_operand(new_op1, &mod);
355 new_op1 = get_irn_n(new_op1, 0);
356 return new_rd_arm_Add(dbg, irg, block, new_op2, new_op1, mode, mod, v);
358 /* is the second a shifter */
359 v = is_shifter_operand(new_op2, &mod);
361 new_op2 = get_irn_n(new_op2, 0);
362 return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, mod, v);
366 return new_rd_arm_Add(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0);
371 * Creates an ARM Mul.
373 * @return the created arm Mul node
375 static ir_node *gen_Mul(ir_node *node) {
376 ir_node *block = be_transform_node(get_nodes_block(node));
377 ir_node *op1 = get_Mul_left(node);
378 ir_node *new_op1 = be_transform_node(op1);
379 ir_node *op2 = get_Mul_right(node);
380 ir_node *new_op2 = be_transform_node(op2);
381 ir_mode *mode = get_irn_mode(node);
382 ir_graph *irg = current_ir_graph;
383 dbg_info *dbg = get_irn_dbg_info(node);
385 if (mode_is_float(mode)) {
386 env_cg->have_fp_insn = 1;
387 if (USE_FPA(env_cg->isa)) {
388 if (is_arm_Mov_i(new_op1))
389 return new_rd_arm_fpaMuf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1));
390 if (is_arm_Mov_i(new_op2))
391 return new_rd_arm_fpaMuf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2));
392 return new_rd_arm_fpaMuf(dbg, irg, block, new_op1, new_op2, mode);
394 else if (USE_VFP(env_cg->isa)) {
395 assert(mode != mode_E && "IEEE Extended FP not supported");
396 panic("VFP not supported yet\n");
400 panic("Softfloat not supported yet\n");
404 assert(mode_is_data(mode));
406 return new_rd_arm_Mul(dbg, irg, block, new_op1, new_op2, mode);
410 * Creates an ARM floating point Div.
412 * @param env The transformation environment
413 * @return the created arm fDiv node
415 static ir_node *gen_Quot(ir_node *node) {
416 ir_node *block = be_transform_node(get_nodes_block(node));
417 ir_node *op1 = get_Quot_left(node);
418 ir_node *new_op1 = be_transform_node(op1);
419 ir_node *op2 = get_Quot_right(node);
420 ir_node *new_op2 = be_transform_node(op2);
421 ir_mode *mode = get_irn_mode(node);
422 dbg_info *dbg = get_irn_dbg_info(node);
424 assert(mode != mode_E && "IEEE Extended FP not supported");
426 env_cg->have_fp_insn = 1;
427 if (USE_FPA(env_cg->isa)) {
428 if (is_arm_Mov_i(new_op1))
429 return new_rd_arm_fpaRdf_i(dbg, current_ir_graph, block, new_op2, mode, get_arm_imm_value(new_op1));
430 if (is_arm_Mov_i(new_op2))
431 return new_rd_arm_fpaDvf_i(dbg, current_ir_graph, block, new_op1, mode, get_arm_imm_value(new_op2));
432 return new_rd_arm_fpaDvf(dbg, current_ir_graph, block, new_op1, new_op2, mode);
433 } else if (USE_VFP(env_cg->isa)) {
434 assert(mode != mode_E && "IEEE Extended FP not supported");
435 panic("VFP not supported yet\n");
438 panic("Softfloat not supported yet\n");
443 #define GEN_INT_OP(op) \
444 ir_node *block = be_transform_node(get_nodes_block(node)); \
445 ir_node *op1 = get_ ## op ## _left(node); \
446 ir_node *new_op1 = be_transform_node(op1); \
447 ir_node *op2 = get_ ## op ## _right(node); \
448 ir_node *new_op2 = be_transform_node(op2); \
449 ir_graph *irg = current_ir_graph; \
450 ir_mode *mode = mode_Iu; \
451 dbg_info *dbg = get_irn_dbg_info(node); \
453 arm_shift_modifier mod; \
455 if (is_arm_Mov_i(new_op1)) \
456 return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1)); \
457 if (is_arm_Mov_i(new_op2)) \
458 return new_rd_arm_ ## op ## _i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2)); \
459 /* is the first a shifter */ \
460 v = is_shifter_operand(new_op1, &mod); \
462 new_op1 = get_irn_n(new_op1, 0); \
463 return new_rd_arm_ ## op(dbg, irg, block, new_op2, new_op1, mode, mod, v); \
465 /* is the second a shifter */ \
466 v = is_shifter_operand(new_op2, &mod); \
468 new_op2 = get_irn_n(new_op2, 0); \
469 return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, mod, v); \
472 return new_rd_arm_ ## op(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0) \
475 * Creates an ARM And.
477 * @return the created arm And node
479 static ir_node *gen_And(ir_node *node) {
484 * Creates an ARM Orr.
486 * @param env The transformation environment
487 * @return the created arm Or node
489 static ir_node *gen_Or(ir_node *node) {
494 * Creates an ARM Eor.
496 * @return the created arm Eor node
498 static ir_node *gen_Eor(ir_node *node) {
503 * Creates an ARM Sub.
505 * @return the created arm Sub node
507 static ir_node *gen_Sub(ir_node *node) {
508 ir_node *block = be_transform_node(get_nodes_block(node));
509 ir_node *op1 = get_Sub_left(node);
510 ir_node *new_op1 = be_transform_node(op1);
511 ir_node *op2 = get_Sub_right(node);
512 ir_node *new_op2 = be_transform_node(op2);
513 ir_mode *mode = get_irn_mode(node);
514 ir_graph *irg = current_ir_graph;
515 dbg_info *dbg = get_irn_dbg_info(node);
517 arm_shift_modifier mod;
519 if (mode_is_float(mode)) {
520 env_cg->have_fp_insn = 1;
521 if (USE_FPA(env_cg->isa)) {
522 if (is_arm_Mov_i(new_op1))
523 return new_rd_arm_fpaRsf_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1));
524 if (is_arm_Mov_i(new_op2))
525 return new_rd_arm_fpaSuf_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2));
526 return new_rd_arm_fpaSuf(dbg, irg, block, new_op1, new_op2, mode);
527 } else if (USE_VFP(env_cg->isa)) {
528 assert(mode != mode_E && "IEEE Extended FP not supported");
529 panic("VFP not supported yet\n");
533 panic("Softfloat not supported yet\n");
538 assert(mode_is_data(mode) && "unknown mode for Sub");
541 if (is_arm_Mov_i(new_op1))
542 return new_rd_arm_Rsb_i(dbg, irg, block, new_op2, mode, get_arm_imm_value(new_op1));
543 if (is_arm_Mov_i(new_op2))
544 return new_rd_arm_Sub_i(dbg, irg, block, new_op1, mode, get_arm_imm_value(new_op2));
546 /* is the first a shifter */
547 v = is_shifter_operand(new_op1, &mod);
549 new_op1 = get_irn_n(new_op1, 0);
550 return new_rd_arm_Rsb(dbg, irg, block, new_op2, new_op1, mode, mod, v);
552 /* is the second a shifter */
553 v = is_shifter_operand(new_op2, &mod);
555 new_op2 = get_irn_n(new_op2, 0);
556 return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, mod, v);
559 return new_rd_arm_Sub(dbg, irg, block, new_op1, new_op2, mode, ARM_SHF_NONE, 0);
564 * Creates an ARM Shl.
566 * @return the created ARM Shl node
568 static ir_node *gen_Shl(ir_node *node) {
569 ir_node *block = be_transform_node(get_nodes_block(node));
570 ir_node *op1 = get_Shl_left(node);
571 ir_node *new_op1 = be_transform_node(op1);
572 ir_node *op2 = get_Shl_right(node);
573 ir_node *new_op2 = be_transform_node(op2);
574 ir_mode *mode = mode_Iu;
575 dbg_info *dbg = get_irn_dbg_info(node);
577 if (is_arm_Mov_i(new_op2)) {
578 return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSL, get_arm_imm_value(new_op2));
580 return new_rd_arm_Shl(dbg, current_ir_graph, block, new_op1, new_op2, mode);
584 * Creates an ARM Shr.
586 * @return the created ARM Shr node
588 static ir_node *gen_Shr(ir_node *node) {
589 ir_node *block = be_transform_node(get_nodes_block(node));
590 ir_node *op1 = get_Shr_left(node);
591 ir_node *new_op1 = be_transform_node(op1);
592 ir_node *op2 = get_Shr_right(node);
593 ir_node *new_op2 = be_transform_node(op2);
594 ir_mode *mode = mode_Iu;
595 dbg_info *dbg = get_irn_dbg_info(node);
597 if (is_arm_Mov_i(new_op2)) {
598 return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_LSR, get_arm_imm_value(new_op2));
600 return new_rd_arm_Shr(dbg, current_ir_graph, block, new_op1, new_op2, mode);
604 * Creates an ARM Shrs.
606 * @return the created ARM Shrs node
608 static ir_node *gen_Shrs(ir_node *node) {
609 ir_node *block = be_transform_node(get_nodes_block(node));
610 ir_node *op1 = get_Shrs_left(node);
611 ir_node *new_op1 = be_transform_node(op1);
612 ir_node *op2 = get_Shrs_right(node);
613 ir_node *new_op2 = be_transform_node(op2);
614 ir_mode *mode = mode_Iu;
615 dbg_info *dbg = get_irn_dbg_info(node);
617 if (is_arm_Mov_i(new_op2)) {
618 return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_ASR, get_arm_imm_value(new_op2));
620 return new_rd_arm_Shrs(dbg, current_ir_graph, block, new_op1, new_op2, mode);
624 * Creates an ARM Ror.
626 * @return the created ARM Ror node
628 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2) {
629 ir_node *block = be_transform_node(get_nodes_block(node));
630 ir_node *new_op1 = be_transform_node(op1);
631 ir_node *new_op2 = be_transform_node(op2);
632 ir_mode *mode = mode_Iu;
633 dbg_info *dbg = get_irn_dbg_info(node);
635 if (is_arm_Mov_i(new_op2)) {
636 return new_rd_arm_Mov(dbg, current_ir_graph, block, new_op1, mode, ARM_SHF_ROR, get_arm_imm_value(new_op2));
638 return new_rd_arm_Ror(dbg, current_ir_graph, block, new_op1, new_op2, mode);
642 * Creates an ARM Rol.
644 * @return the created ARM Rol node
646 * Note: there is no Rol on arm, we have to use Ror
648 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2) {
649 ir_node *block = be_transform_node(get_nodes_block(node));
650 ir_node *new_op1 = be_transform_node(op1);
651 ir_mode *mode = mode_Iu;
652 dbg_info *dbg = get_irn_dbg_info(node);
653 ir_node *new_op2 = new_rd_arm_Rsb_i(dbg, current_ir_graph, block, op2, mode, 32);
654 return new_rd_arm_Ror(dbg, current_ir_graph, block, new_op1, new_op2, mode);
658 * Creates an ARM ROR from a Firm Rotl.
660 * @return the created ARM Ror node
662 static ir_node *gen_Rotl(ir_node *node) {
663 ir_node *rotate = NULL;
664 ir_node *op1 = get_Rotl_left(node);
665 ir_node *op2 = get_Rotl_right(node);
667 /* Firm has only RotL, so we are looking for a right (op2)
668 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
669 that means we can create a RotR. */
673 ir_node *left = get_Add_left(add);
674 ir_node *right = get_Add_right(add);
675 if (is_Const(right)) {
676 tarval *tv = get_Const_tarval(right);
677 ir_mode *mode = get_irn_mode(node);
678 long bits = get_mode_size_bits(mode);
680 if (is_Minus(left) &&
681 tarval_is_long(tv) &&
682 get_tarval_long(tv) == bits &&
684 rotate = gen_Ror(node, op1, get_Minus_op(left));
688 if (rotate == NULL) {
689 rotate = gen_Rol(node, op1, op2);
696 * Transforms a Not node.
698 * @return the created ARM Not node
700 static ir_node *gen_Not(ir_node *node) {
701 ir_node *block = be_transform_node(get_nodes_block(node));
702 ir_node *op = get_Not_op(node);
703 ir_node *new_op = be_transform_node(op);
704 dbg_info *dbg = get_irn_dbg_info(node);
705 ir_mode *mode = mode_Iu;
706 arm_shift_modifier mod = ARM_SHF_NONE;
707 int v = is_shifter_operand(new_op, &mod);
710 new_op = get_irn_n(new_op, 0);
712 return new_rd_arm_Mvn(dbg, current_ir_graph, block, new_op, mode, mod, v);
716 * Transforms an Abs node.
718 * @param env The transformation environment
719 * @return the created ARM Abs node
721 static ir_node *gen_Abs(ir_node *node) {
722 ir_node *block = be_transform_node(get_nodes_block(node));
723 ir_node *op = get_Abs_op(node);
724 ir_node *new_op = be_transform_node(op);
725 dbg_info *dbg = get_irn_dbg_info(node);
726 ir_mode *mode = get_irn_mode(node);
728 if (mode_is_float(mode)) {
729 env_cg->have_fp_insn = 1;
730 if (USE_FPA(env_cg->isa))
731 return new_rd_arm_fpaAbs(dbg, current_ir_graph, block, new_op, mode);
732 else if (USE_VFP(env_cg->isa)) {
733 assert(mode != mode_E && "IEEE Extended FP not supported");
734 panic("VFP not supported yet\n");
737 panic("Softfloat not supported yet\n");
740 assert(mode_is_data(mode));
742 return new_rd_arm_Abs(dbg, current_ir_graph, block, new_op, mode);
746 * Transforms a Minus node.
748 * @return the created ARM Minus node
750 static ir_node *gen_Minus(ir_node *node) {
751 ir_node *block = be_transform_node(get_nodes_block(node));
752 ir_node *op = get_Minus_op(node);
753 ir_node *new_op = be_transform_node(op);
754 dbg_info *dbg = get_irn_dbg_info(node);
755 ir_mode *mode = get_irn_mode(node);
757 if (mode_is_float(mode)) {
758 env_cg->have_fp_insn = 1;
759 if (USE_FPA(env_cg->isa))
760 return new_rd_arm_fpaMvf(dbg, current_ir_graph, block, op, mode);
761 else if (USE_VFP(env_cg->isa)) {
762 assert(mode != mode_E && "IEEE Extended FP not supported");
763 panic("VFP not supported yet\n");
766 panic("Softfloat not supported yet\n");
769 assert(mode_is_data(mode));
771 return new_rd_arm_Rsb_i(dbg, current_ir_graph, block, new_op, mode, 0);
777 * @return the created ARM Load node
779 static ir_node *gen_Load(ir_node *node) {
780 ir_node *block = be_transform_node(get_nodes_block(node));
781 ir_node *ptr = get_Load_ptr(node);
782 ir_node *new_ptr = be_transform_node(ptr);
783 ir_node *mem = get_Load_mem(node);
784 ir_node *new_mem = be_transform_node(mem);
785 ir_mode *mode = get_Load_mode(node);
786 ir_graph *irg = current_ir_graph;
787 dbg_info *dbg = get_irn_dbg_info(node);
788 ir_node *new_load = NULL;
790 if (mode_is_float(mode)) {
791 env_cg->have_fp_insn = 1;
792 if (USE_FPA(env_cg->isa))
793 new_load = new_rd_arm_fpaLdf(dbg, irg, block, new_ptr, new_mem, mode);
794 else if (USE_VFP(env_cg->isa)) {
795 assert(mode != mode_E && "IEEE Extended FP not supported");
796 panic("VFP not supported yet\n");
799 panic("Softfloat not supported yet\n");
803 assert(mode_is_data(mode) && "unsupported mode for Load");
805 if (mode_is_signed(mode)) {
806 /* sign extended loads */
807 switch (get_mode_size_bits(mode)) {
809 new_load = new_rd_arm_Loadbs(dbg, irg, block, new_ptr, new_mem);
812 new_load = new_rd_arm_Loadhs(dbg, irg, block, new_ptr, new_mem);
815 new_load = new_rd_arm_Load(dbg, irg, block, new_ptr, new_mem);
818 panic("mode size not supported\n");
821 /* zero extended loads */
822 switch (get_mode_size_bits(mode)) {
824 new_load = new_rd_arm_Loadb(dbg, irg, block, new_ptr, new_mem);
827 new_load = new_rd_arm_Loadh(dbg, irg, block, new_ptr, new_mem);
830 new_load = new_rd_arm_Load(dbg, irg, block, new_ptr, new_mem);
833 panic("mode size not supported\n");
837 set_irn_pinned(new_load, get_irn_pinned(node));
839 /* check for special case: the loaded value might not be used */
840 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
841 /* add a result proj and a Keep to produce a pseudo use */
842 ir_node *proj = new_r_Proj(irg, block, new_load, mode_Iu, pn_arm_Load_res);
843 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
850 * Transforms a Store.
852 * @return the created ARM Store node
854 static ir_node *gen_Store(ir_node *node) {
855 ir_node *block = be_transform_node(get_nodes_block(node));
856 ir_node *ptr = get_Store_ptr(node);
857 ir_node *new_ptr = be_transform_node(ptr);
858 ir_node *mem = get_Store_mem(node);
859 ir_node *new_mem = be_transform_node(mem);
860 ir_node *val = get_Store_value(node);
861 ir_node *new_val = be_transform_node(val);
862 ir_mode *mode = get_irn_mode(val);
863 ir_graph *irg = current_ir_graph;
864 dbg_info *dbg = get_irn_dbg_info(node);
865 ir_node *new_store = NULL;
867 if (mode_is_float(mode)) {
868 env_cg->have_fp_insn = 1;
869 if (USE_FPA(env_cg->isa))
870 new_store = new_rd_arm_fpaStf(dbg, irg, block, new_ptr, new_val, new_mem, mode);
871 else if (USE_VFP(env_cg->isa)) {
872 assert(mode != mode_E && "IEEE Extended FP not supported");
873 panic("VFP not supported yet\n");
875 panic("Softfloat not supported yet\n");
878 assert(mode_is_data(mode) && "unsupported mode for Store");
879 switch (get_mode_size_bits(mode)) {
881 new_store = new_rd_arm_Storeb(dbg, irg, block, new_ptr, new_val, new_mem);
883 new_store = new_rd_arm_Storeh(dbg, irg, block, new_ptr, new_val, new_mem);
885 new_store = new_rd_arm_Store(dbg, irg, block, new_ptr, new_val, new_mem);
888 set_irn_pinned(new_store, get_irn_pinned(node));
895 * @return the created ARM Cond node
897 static ir_node *gen_Cond(ir_node *node) {
898 ir_node *block = be_transform_node(get_nodes_block(node));
899 ir_node *selector = get_Cond_selector(node);
900 ir_graph *irg = current_ir_graph;
901 dbg_info *dbg = get_irn_dbg_info(node);
902 ir_mode *mode = get_irn_mode(selector);
904 if (mode == mode_b) {
905 /* an conditional jump */
906 ir_node *cmp_node = get_Proj_pred(selector);
907 ir_node *op1 = get_Cmp_left(cmp_node);
908 ir_node *new_op1 = be_transform_node(op1);
909 ir_node *op2 = get_Cmp_right(cmp_node);
910 ir_node *new_op2 = be_transform_node(op2);
912 if (mode_is_float(get_irn_mode(op1))) {
913 /* floating point compare */
914 pn_Cmp pnc = get_Proj_proj(selector);
916 if (pnc & pn_Cmp_Uo) {
917 /* check for unordered, need cmf */
918 return new_rd_arm_fpaCmfBra(dbg, irg, block, new_op1, new_op2, pnc);
920 /* Hmm: use need cmfe */
921 return new_rd_arm_fpaCmfeBra(dbg, irg, block, new_op1, new_op2, pnc);
923 /* integer compare */
924 return new_rd_arm_CmpBra(dbg, irg, block, new_op1, new_op2, get_Proj_proj(selector));
928 ir_node *new_op = be_transform_node(selector);
929 ir_node *const_graph;
933 const ir_edge_t *edge;
940 foreach_out_edge(node, edge) {
941 proj = get_edge_src_irn(edge);
942 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
944 pn = get_Proj_proj(proj);
946 min = pn<min ? pn : min;
947 max = pn>max ? pn : max;
950 n_projs = max - translation + 1;
952 foreach_out_edge(node, edge) {
953 proj = get_edge_src_irn(edge);
954 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
956 pn = get_Proj_proj(proj) - translation;
957 set_Proj_proj(proj, pn);
960 const_graph = create_const_graph_value(dbg, block, translation);
961 sub = new_rd_arm_Sub(dbg, irg, block, new_op, const_graph, mode, ARM_SHF_NONE, 0);
962 return new_rd_arm_SwitchJmp(dbg, irg, block, sub, n_projs, get_Cond_defaultProj(node) - translation);
967 * Returns the name of a SymConst.
968 * @param symc the SymConst
969 * @return name of the SymConst
971 static ident *get_sc_ident(ir_node *symc) {
974 switch (get_SymConst_kind(symc)) {
975 case symconst_addr_name:
976 return get_SymConst_name(symc);
978 case symconst_addr_ent:
979 ent = get_SymConst_entity(symc);
980 set_entity_backend_marked(ent, 1);
981 return get_entity_ld_ident(ent);
984 assert(0 && "Unsupported SymConst");
990 static tarval *fpa_imm[3][fpa_max];
993 * Check, if a floating point tarval is an fpa immediate, i.e.
994 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
996 static int is_fpa_immediate(tarval *tv) {
997 ir_mode *mode = get_tarval_mode(tv);
1000 switch (get_mode_size_bits(mode)) {
1011 if (tarval_cmp(tv, get_tarval_null(mode)) & pn_Cmp_Lt) {
1012 tv = tarval_neg(tv);
1016 for (j = 0; j < fpa_max; ++j) {
1017 if (tv == fpa_imm[i][j])
1024 * Transforms a Const node.
1026 * @return The transformed ARM node.
1028 static ir_node *gen_Const(ir_node *node) {
1029 ir_node *block = be_transform_node(get_nodes_block(node));
1030 ir_graph *irg = current_ir_graph;
1031 ir_mode *mode = get_irn_mode(node);
1032 dbg_info *dbg = get_irn_dbg_info(node);
1034 if (mode_is_float(mode)) {
1035 env_cg->have_fp_insn = 1;
1036 if (USE_FPA(env_cg->isa)) {
1037 tarval *tv = get_Const_tarval(node);
1038 int imm = is_fpa_immediate(tv);
1040 if (imm != fpa_max) {
1042 node = new_rd_arm_fpaMvf_i(dbg, irg, block, mode, imm);
1044 node = new_rd_arm_fpaMnf_i(dbg, irg, block, mode, -imm);
1046 node = new_rd_arm_fpaConst(dbg, irg, block, tv);
1048 /* ensure the const is scheduled AFTER the stack frame */
1049 add_irn_dep(node, get_irg_frame(irg));
1052 else if (USE_VFP(env_cg->isa)) {
1053 assert(mode != mode_E && "IEEE Extended FP not supported");
1054 panic("VFP not supported yet\n");
1057 panic("Softfloat not supported yet\n");
1060 return create_const_graph(node, block);
1064 * Transforms a SymConst node.
1066 * @return The transformed ARM node.
1068 static ir_node *gen_SymConst(ir_node *node) {
1069 ir_node *block = be_transform_node(get_nodes_block(node));
1070 ir_mode *mode = mode_Iu;
1071 dbg_info *dbg = get_irn_dbg_info(node);
1072 ir_graph *irg = current_ir_graph;
1075 res = new_rd_arm_SymConst(dbg, irg, block, mode, get_sc_ident(node));
1076 /* ensure the const is scheduled AFTER the stack frame */
1077 add_irn_dep(res, get_irg_frame(irg));
1082 * Transforms a CopyB node.
1084 * @return The transformed ARM node.
1086 static ir_node *gen_CopyB(ir_node *node) {
1087 ir_node *block = be_transform_node(get_nodes_block(node));
1088 ir_node *src = get_CopyB_src(node);
1089 ir_node *new_src = be_transform_node(src);
1090 ir_node *dst = get_CopyB_dst(node);
1091 ir_node *new_dst = be_transform_node(dst);
1092 ir_node *mem = get_CopyB_mem(node);
1093 ir_node *new_mem = be_transform_node(mem);
1094 ir_graph *irg = current_ir_graph;
1095 dbg_info *dbg = get_irn_dbg_info(node);
1096 int size = get_type_size_bytes(get_CopyB_type(node));
1100 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, new_src);
1101 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, new_dst);
1103 return new_rd_arm_CopyB(dbg, irg, block, dst_copy, src_copy,
1104 new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu),
1105 new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu),
1106 new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu),
1111 /********************************************
1114 * | |__ ___ _ __ ___ __| | ___ ___
1115 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1116 * | |_) | __/ | | | (_) | (_| | __/\__ \
1117 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1119 ********************************************/
1122 * Return an expanding stack offset.
1123 * Note that function is called in the transform phase
1124 * where the stack offsets are still relative regarding
1125 * the first (frame allocating) IncSP.
1126 * However this is exactly what we want because frame
1127 * access must be done relative the the fist IncSP ...
1129 static int get_sp_expand_offset(ir_node *inc_sp) {
1130 int offset = be_get_IncSP_offset(inc_sp);
1132 if (offset == BE_STACK_FRAME_SIZE_EXPAND)
1139 static ir_node *gen_StackParam(ir_node *irn) {
1140 ir_node *block = be_transform_node(get_nodes_block(node));
1141 ir_node *new_op = NULL;
1142 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1143 ir_node *mem = new_rd_NoMem(env->irg);
1144 ir_node *ptr = get_irn_n(irn, 0);
1145 ir_entity *ent = be_get_frame_entity(irn);
1146 ir_mode *mode = env->mode;
1148 // /* If the StackParam has only one user -> */
1149 // /* put it in the Block where the user resides */
1150 // if (get_irn_n_edges(node) == 1) {
1151 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1154 if (mode_is_float(mode)) {
1155 if (USE_SSE2(env->cg))
1156 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1158 env->cg->used_x87 = 1;
1159 new_op = new_rd_ia32_vfld(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1163 new_op = new_rd_ia32_Load(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
1166 set_ia32_frame_ent(new_op, ent);
1167 set_ia32_use_frame(new_op);
1169 set_ia32_am_support(new_op, ia32_am_Source);
1170 set_ia32_op_type(new_op, ia32_AddrModeS);
1171 set_ia32_am_flavour(new_op, ia32_B);
1172 set_ia32_ls_mode(new_op, mode);
1174 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1176 return new_rd_Proj(env->dbg, env->irg, block, new_op, mode, 0);
1181 * Transforms a FrameAddr into an ARM Add.
1183 static ir_node *gen_be_FrameAddr(ir_node *node) {
1184 ir_node *block = be_transform_node(get_nodes_block(node));
1185 ir_entity *ent = be_get_frame_entity(node);
1186 int offset = get_entity_offset(ent);
1187 ir_node *op = be_get_FrameAddr_frame(node);
1188 ir_node *new_op = be_transform_node(op);
1189 dbg_info *dbg = get_irn_dbg_info(node);
1190 ir_mode *mode = mode_Iu;
1193 if (be_is_IncSP(op)) {
1194 /* BEWARE: we get an offset which is absolute from an offset that
1195 is relative. Both must be merged */
1196 offset += get_sp_expand_offset(op);
1198 cnst = create_const_graph_value(dbg, block, (unsigned)offset);
1199 if (is_arm_Mov_i(cnst))
1200 return new_rd_arm_Add_i(dbg, current_ir_graph, block, new_op, mode, get_arm_imm_value(cnst));
1201 return new_rd_arm_Add(dbg, current_ir_graph, block, new_op, cnst, mode, ARM_SHF_NONE, 0);
1205 * Transform a be_AddSP into an arm_AddSP. Eat up const sizes.
1207 static ir_node *gen_be_AddSP(ir_node *node) {
1208 ir_node *block = be_transform_node(get_nodes_block(node));
1209 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
1210 ir_node *new_sz = be_transform_node(sz);
1211 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
1212 ir_node *new_sp = be_transform_node(sp);
1213 ir_graph *irg = current_ir_graph;
1214 dbg_info *dbgi = get_irn_dbg_info(node);
1215 ir_node *nomem = new_NoMem();
1218 /* ARM stack grows in reverse direction, make a SubSPandCopy */
1219 new_op = new_rd_arm_SubSPandCopy(dbgi, irg, block, new_sp, new_sz, nomem);
1225 * Transform a be_SubSP into an arm_SubSP. Eat up const sizes.
1227 static ir_node *gen_be_SubSP(ir_node *node) {
1228 ir_node *block = be_transform_node(get_nodes_block(node));
1229 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
1230 ir_node *new_sz = be_transform_node(sz);
1231 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
1232 ir_node *new_sp = be_transform_node(sp);
1233 ir_graph *irg = current_ir_graph;
1234 dbg_info *dbgi = get_irn_dbg_info(node);
1235 ir_node *nomem = new_NoMem();
1238 /* ARM stack grows in reverse direction, make an AddSP */
1239 new_op = new_rd_arm_AddSP(dbgi, irg, block, new_sp, new_sz, nomem);
1245 * Transform a be_Copy.
1247 static ir_node *gen_be_Copy(ir_node *node) {
1248 ir_node *result = be_duplicate_node(node);
1249 ir_mode *mode = get_irn_mode(result);
1251 if (mode_needs_gp_reg(mode)) {
1252 set_irn_mode(node, mode_Iu);
1259 * Transform a Proj from a Load.
1261 static ir_node *gen_Proj_Load(ir_node *node) {
1262 ir_node *block = be_transform_node(get_nodes_block(node));
1263 ir_node *load = get_Proj_pred(node);
1264 ir_node *new_load = be_transform_node(load);
1265 ir_graph *irg = current_ir_graph;
1266 dbg_info *dbgi = get_irn_dbg_info(node);
1267 long proj = get_Proj_proj(node);
1269 /* renumber the proj */
1270 switch (get_arm_irn_opcode(new_load)) {
1273 case iro_arm_Loadbs:
1275 case iro_arm_Loadhs:
1276 /* handle all gp loads equal: they have the same proj numbers. */
1277 if (proj == pn_Load_res) {
1278 return new_rd_Proj(dbgi, irg, block, new_load, mode_Iu, pn_arm_Load_res);
1279 } else if (proj == pn_Load_M) {
1280 return new_rd_Proj(dbgi, irg, block, new_load, mode_M, pn_arm_Load_M);
1283 case iro_arm_fpaLdf:
1284 if (proj == pn_Load_res) {
1285 ir_mode *mode = get_Load_mode(load);
1286 return new_rd_Proj(dbgi, irg, block, new_load, mode, pn_arm_fpaLdf_res);
1287 } else if (proj == pn_Load_M) {
1288 return new_rd_Proj(dbgi, irg, block, new_load, mode_M, pn_arm_fpaLdf_M);
1295 return new_rd_Unknown(irg, get_irn_mode(node));
1299 * Transform and renumber the Projs from a CopyB.
1301 static ir_node *gen_Proj_CopyB(ir_node *node) {
1302 ir_node *block = be_transform_node(get_nodes_block(node));
1303 ir_node *pred = get_Proj_pred(node);
1304 ir_node *new_pred = be_transform_node(pred);
1305 ir_graph *irg = current_ir_graph;
1306 dbg_info *dbgi = get_irn_dbg_info(node);
1307 ir_mode *mode = get_irn_mode(node);
1308 long proj = get_Proj_proj(node);
1311 case pn_CopyB_M_regular:
1312 if (is_arm_CopyB(new_pred)) {
1313 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_CopyB_M);
1320 return new_rd_Unknown(irg, mode);
1324 * Transform and renumber the Projs from a Quot.
1326 static ir_node *gen_Proj_Quot(ir_node *node) {
1327 ir_node *block = be_transform_node(get_nodes_block(node));
1328 ir_node *pred = get_Proj_pred(node);
1329 ir_node *new_pred = be_transform_node(pred);
1330 ir_graph *irg = current_ir_graph;
1331 dbg_info *dbgi = get_irn_dbg_info(node);
1332 ir_mode *mode = get_irn_mode(node);
1333 long proj = get_Proj_proj(node);
1337 if (is_arm_fpaDvf(new_pred) || is_arm_fpaDvf_i(new_pred)) {
1338 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaDvf_M);
1339 } else if (is_arm_fpaRdf(new_pred) || is_arm_fpaRdf_i(new_pred)) {
1340 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaRdf_M);
1341 } else if (is_arm_fpaFdv(new_pred) || is_arm_fpaFdv_i(new_pred)) {
1342 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaFdv_M);
1343 } else if (is_arm_fpaFrd(new_pred) || is_arm_fpaFrd_i(new_pred)) {
1344 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_fpaFrd_M);
1348 if (is_arm_fpaDvf(new_pred) || is_arm_fpaDvf_i(new_pred)) {
1349 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaDvf_res);
1350 } else if (is_arm_fpaRdf(new_pred) || is_arm_fpaRdf_i(new_pred)) {
1351 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaRdf_res);
1352 } else if (is_arm_fpaFdv(new_pred) || is_arm_fpaFdv_i(new_pred)) {
1353 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaFdv_res);
1354 } else if (is_arm_fpaFrd(new_pred) || is_arm_fpaFrd_i(new_pred)) {
1355 return new_rd_Proj(dbgi, irg, block, new_pred, mode, pn_arm_fpaFrd_res);
1362 return new_rd_Unknown(irg, mode);
1366 * Transform the Projs of a be_AddSP.
1368 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
1369 ir_node *block = be_transform_node(get_nodes_block(node));
1370 ir_node *pred = get_Proj_pred(node);
1371 ir_node *new_pred = be_transform_node(pred);
1372 ir_graph *irg = current_ir_graph;
1373 dbg_info *dbgi = get_irn_dbg_info(node);
1374 long proj = get_Proj_proj(node);
1376 if (proj == pn_be_AddSP_sp) {
1377 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
1378 pn_arm_SubSPandCopy_stack);
1379 arch_set_irn_register(env_cg->arch_env, res, &arm_gp_regs[REG_SP]);
1381 } else if(proj == pn_be_AddSP_res) {
1382 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
1383 pn_arm_SubSPandCopy_addr);
1384 } else if (proj == pn_be_AddSP_M) {
1385 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_SubSPandCopy_M);
1389 return new_rd_Unknown(irg, get_irn_mode(node));
1393 * Transform the Projs of a be_SubSP.
1395 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
1396 ir_node *block = be_transform_node(get_nodes_block(node));
1397 ir_node *pred = get_Proj_pred(node);
1398 ir_node *new_pred = be_transform_node(pred);
1399 ir_graph *irg = current_ir_graph;
1400 dbg_info *dbgi = get_irn_dbg_info(node);
1401 long proj = get_Proj_proj(node);
1403 if (proj == pn_be_SubSP_sp) {
1404 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
1405 pn_arm_AddSP_stack);
1406 arch_set_irn_register(env_cg->arch_env, res, &arm_gp_regs[REG_SP]);
1408 } else if (proj == pn_be_SubSP_M) {
1409 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_arm_AddSP_M);
1413 return new_rd_Unknown(irg, get_irn_mode(node));
1417 * Transform the Projs from a Cmp.
1419 static ir_node *gen_Proj_Cmp(ir_node *node) {
1426 * Transform the Thread Local Storage Proj.
1428 static ir_node *gen_Proj_tls(ir_node *node) {
1429 ir_node *block = be_transform_node(get_nodes_block(node));
1430 ir_graph *irg = current_ir_graph;
1431 dbg_info *dbgi = NULL;
1433 return new_rd_arm_LdTls(dbgi, irg, block, mode_Iu);
1437 * Transform a Proj node.
1439 static ir_node *gen_Proj(ir_node *node) {
1440 ir_graph *irg = current_ir_graph;
1441 dbg_info *dbgi = get_irn_dbg_info(node);
1442 ir_node *pred = get_Proj_pred(node);
1443 long proj = get_Proj_proj(node);
1445 if (is_Store(pred)) {
1446 if (proj == pn_Store_M) {
1447 return be_transform_node(pred);
1450 return new_r_Bad(irg);
1452 } else if (is_Load(pred)) {
1453 return gen_Proj_Load(node);
1454 } else if (is_CopyB(pred)) {
1455 return gen_Proj_CopyB(node);
1456 } else if (is_Quot(pred)) {
1457 return gen_Proj_Quot(node);
1458 } else if (be_is_SubSP(pred)) {
1459 return gen_Proj_be_SubSP(node);
1460 } else if (be_is_AddSP(pred)) {
1461 return gen_Proj_be_AddSP(node);
1462 } else if (is_Cmp(pred)) {
1463 return gen_Proj_Cmp(node);
1464 } else if (get_irn_op(pred) == op_Start) {
1465 if (proj == pn_Start_X_initial_exec) {
1466 ir_node *block = get_nodes_block(pred);
1469 /* we exchange the ProjX with a jump */
1470 block = be_transform_node(block);
1471 jump = new_rd_Jmp(dbgi, irg, block);
1474 if (node == get_irg_anchor(irg, anchor_tls)) {
1475 return gen_Proj_tls(node);
1478 ir_node *new_pred = be_transform_node(pred);
1479 ir_mode *mode = get_irn_mode(node);
1480 if (mode_needs_gp_reg(mode)) {
1481 ir_node *block = be_transform_node(get_nodes_block(node));
1482 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
1483 get_Proj_proj(node));
1484 #ifdef DEBUG_libfirm
1485 new_proj->node_nr = node->node_nr;
1491 return be_duplicate_node(node);
1494 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_graph *irg, ir_node *block);
1496 static INLINE ir_node *create_const(ir_node **place,
1497 create_const_node_func func,
1498 const arch_register_t* reg)
1500 ir_node *block, *res;
1505 block = get_irg_start_block(env_cg->irg);
1506 res = func(NULL, env_cg->irg, block);
1507 arch_set_irn_register(env_cg->arch_env, res, reg);
1510 add_irn_dep(get_irg_end(env_cg->irg), res);
1514 static ir_node *arm_new_Unknown_gp(void) {
1515 return create_const(&env_cg->unknown_gp, new_rd_arm_Unknown_GP,
1516 &arm_gp_regs[REG_GP_UKNWN]);
1519 static ir_node *arm_new_Unknown_fpa(void) {
1520 return create_const(&env_cg->unknown_fpa, new_rd_arm_Unknown_FPA,
1521 &arm_fpa_regs[REG_FPA_UKNWN]);
1525 * This function just sets the register for the Unknown node
1526 * as this is not done during register allocation because Unknown
1527 * is an "ignore" node.
1529 static ir_node *gen_Unknown(ir_node *node) {
1530 ir_mode *mode = get_irn_mode(node);
1531 if (mode_is_float(mode)) {
1532 if (USE_FPA(env_cg->isa))
1533 return arm_new_Unknown_fpa();
1534 else if (USE_VFP(env_cg->isa))
1535 panic("VFP not supported yet");
1537 panic("Softfloat not supported yet");
1538 } else if (mode_needs_gp_reg(mode)) {
1539 return arm_new_Unknown_gp();
1541 assert(0 && "unsupported Unknown-Mode");
1548 * Change some phi modes
1550 static ir_node *gen_Phi(ir_node *node) {
1551 ir_node *block = be_transform_node(get_nodes_block(node));
1552 ir_graph *irg = current_ir_graph;
1553 dbg_info *dbgi = get_irn_dbg_info(node);
1554 ir_mode *mode = get_irn_mode(node);
1557 if (mode_needs_gp_reg(mode)) {
1558 /* we shouldn't have any 64bit stuff around anymore */
1559 assert(get_mode_size_bits(mode) <= 32);
1560 /* all integer operations are on 32bit registers now */
1564 /* phi nodes allow loops, so we use the old arguments for now
1565 * and fix this later */
1566 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
1567 copy_node_attr(node, phi);
1568 be_duplicate_deps(node, phi);
1570 be_set_transformed_node(node, phi);
1571 be_enqueue_preds(node);
1576 /*********************************************************
1579 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1580 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1581 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1582 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1584 *********************************************************/
1587 * the BAD transformer.
1589 static ir_node *bad_transform(ir_node *irn) {
1590 panic("ARM backend: Not implemented: %+F\n", irn);
1595 * Set a node emitter. Make it a bit more type safe.
1597 static INLINE void set_transformer(ir_op *op, be_transform_func arm_transform_func) {
1598 op->ops.generic = (op_func)arm_transform_func;
1602 * Enters all transform functions into the generic pointer
1604 static void arm_register_transformers(void) {
1605 ir_op *op_Max, *op_Min, *op_Mulh;
1607 /* first clear the generic function pointer for all ops */
1608 clear_irp_opcodes_generic_func();
1610 #define GEN(a) set_transformer(op_##a, gen_##a)
1611 #define BAD(a) set_transformer(op_##a, bad_transform)
1627 /* should be lowered */
1641 BAD(ASM); /* unsupported yet */
1644 BAD(Psi); /* unsupported yet */
1651 /* we should never see these nodes */
1666 /* handle generic backend nodes */
1674 /* set the register for all Unknown nodes */
1677 op_Max = get_op_Max();
1679 BAD(Max); /* unsupported yet */
1680 op_Min = get_op_Min();
1682 BAD(Min); /* unsupported yet */
1683 op_Mulh = get_op_Mulh();
1685 BAD(Mulh); /* unsupported yet */
1692 * Pre-transform all unknown nodes.
1694 static void arm_pretransform_node(void *arch_cg) {
1695 arm_code_gen_t *cg = arch_cg;
1697 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
1698 cg->unknown_fpa = be_pre_transform_node(cg->unknown_fpa);
1702 * Initialize fpa Immediate support.
1704 static void arm_init_fpa_immediate(void) {
1705 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
1706 fpa_imm[0][fpa_null] = get_tarval_null(mode_F);
1707 fpa_imm[0][fpa_one] = get_tarval_one(mode_F);
1708 fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
1709 fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
1710 fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
1711 fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
1712 fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
1713 fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
1715 fpa_imm[1][fpa_null] = get_tarval_null(mode_D);
1716 fpa_imm[1][fpa_one] = get_tarval_one(mode_D);
1717 fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
1718 fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
1719 fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
1720 fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
1721 fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
1722 fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
1724 fpa_imm[2][fpa_null] = get_tarval_null(mode_E);
1725 fpa_imm[2][fpa_one] = get_tarval_one(mode_E);
1726 fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
1727 fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
1728 fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
1729 fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
1730 fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
1731 fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
1735 * Transform a Firm graph into an ARM graph.
1737 void arm_transform_graph(arm_code_gen_t *cg) {
1738 static int imm_initialized = 0;
1740 if (! imm_initialized) {
1741 arm_init_fpa_immediate();
1742 imm_initialized = 1;
1744 arm_register_transformers();
1746 be_transform_graph(cg->birg, arm_pretransform_node, cg);
1749 void arm_init_transform(void) {
1750 // FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");