2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
41 #include "../benode.h"
43 #include "../beutil.h"
44 #include "../betranshlp.h"
45 #include "../beabihelper.h"
48 #include "bearch_arm_t.h"
49 #include "arm_nodes_attr.h"
50 #include "arm_transform.h"
51 #include "arm_optimize.h"
52 #include "arm_new_nodes.h"
53 #include "arm_map_regs.h"
54 #include "arm_cconv.h"
56 #include "gen_arm_regalloc_if.h"
60 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 /** hold the current code generator during transformation */
63 static arm_code_gen_t *env_cg;
65 static const arch_register_t *sp_reg = &arm_gp_regs[REG_SP];
66 static ir_mode *mode_gp;
67 static ir_mode *mode_fp;
68 static beabi_helper_env_t *abihelper;
69 static calling_convention_t *cconv = NULL;
71 static pmap *node_to_stack;
73 static bool mode_needs_gp_reg(ir_mode *mode)
75 return mode_is_int(mode) || mode_is_reference(mode);
79 * create firm graph for a constant
81 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
88 /* We only have 8 bit immediates. So we possibly have to combine several
89 * operations to construct the desired value.
91 * we can either create the value by adding bits to 0 or by removing bits
92 * from an register with all bits set. Try which alternative needs fewer
94 arm_gen_vals_from_word(value, &v);
95 arm_gen_vals_from_word(~value, &vn);
99 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
100 be_dep_on_frame(result);
102 for (cnt = 1; cnt < vn.ops; ++cnt) {
103 result = new_bd_arm_Bic_imm(dbgi, block, result,
104 vn.values[cnt], vn.rors[cnt]);
108 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
109 be_dep_on_frame(result);
111 for (cnt = 1; cnt < v.ops; ++cnt) {
112 result = new_bd_arm_Or_imm(dbgi, block, result,
113 v.values[cnt], v.rors[cnt]);
120 * Create a DAG constructing a given Const.
122 * @param irn a Firm const
124 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
126 tarval *tv = get_Const_tarval(irn);
127 ir_mode *mode = get_tarval_mode(tv);
130 if (mode_is_reference(mode)) {
131 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
132 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
133 tv = tarval_convert_to(tv, mode_Iu);
135 value = get_tarval_long(tv);
136 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
140 * Create an And that will zero out upper bits.
142 * @param dbgi debug info
143 * @param block the basic block
144 * @param op the original node
145 * param src_bits number of lower bits that will remain
147 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
151 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
152 } else if (src_bits == 16) {
153 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
154 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
157 panic("zero extension only supported for 8 and 16 bits");
162 * Generate code for a sign extension.
164 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
167 int shift_width = 32 - src_bits;
168 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
169 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
173 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
176 int bits = get_mode_size_bits(orig_mode);
180 if (mode_is_signed(orig_mode)) {
181 return gen_sign_extension(dbgi, block, op, bits);
183 return gen_zero_extension(dbgi, block, op, bits);
188 * returns true if it is assured, that the upper bits of a node are "clean"
189 * which means for a 16 or 8 bit value, that the upper bits in the register
190 * are 0 for unsigned and a copy of the last significant bit for signed
193 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
195 (void) transformed_node;
202 * Transforms a Conv node.
204 * @return The created ia32 Conv node
206 static ir_node *gen_Conv(ir_node *node)
208 ir_node *block = be_transform_node(get_nodes_block(node));
209 ir_node *op = get_Conv_op(node);
210 ir_node *new_op = be_transform_node(op);
211 ir_mode *src_mode = get_irn_mode(op);
212 ir_mode *dst_mode = get_irn_mode(node);
213 dbg_info *dbg = get_irn_dbg_info(node);
215 if (src_mode == dst_mode)
218 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
219 if (USE_FPA(env_cg->isa)) {
220 if (mode_is_float(src_mode)) {
221 if (mode_is_float(dst_mode)) {
222 /* from float to float */
223 return new_bd_arm_Mvf(dbg, block, new_op, dst_mode);
225 /* from float to int */
229 /* from int to float */
230 if (!mode_is_signed(src_mode)) {
233 return new_bd_arm_FltX(dbg, block, new_op, dst_mode);
236 } else if (USE_VFP(env_cg->isa)) {
237 panic("VFP not supported yet");
239 panic("Softfloat not supported yet");
241 } else { /* complete in gp registers */
242 int src_bits = get_mode_size_bits(src_mode);
243 int dst_bits = get_mode_size_bits(dst_mode);
247 if (src_bits == dst_bits) {
248 /* kill unnecessary conv */
252 if (src_bits < dst_bits) {
260 if (upper_bits_clean(new_op, min_mode)) {
264 if (mode_is_signed(min_mode)) {
265 return gen_sign_extension(dbg, block, new_op, min_bits);
267 return gen_zero_extension(dbg, block, new_op, min_bits);
277 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
279 unsigned val, low_pos, high_pos;
284 val = get_tarval_long(get_Const_tarval(node));
296 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
298 So we determine the smallest even position with a bit set
299 and the highest even position with no bit set anymore.
300 If the difference between these 2 is <= 8, then we can encode the value
303 low_pos = ntz(val) & ~1u;
304 high_pos = (32-nlz(val)+1) & ~1u;
306 if (high_pos - low_pos <= 8) {
307 res->imm_8 = val >> low_pos;
308 res->rot = 32 - low_pos;
313 res->rot = 34 - high_pos;
314 val = val >> (32-res->rot) | val << (res->rot);
324 static bool is_downconv(const ir_node *node)
332 /* we only want to skip the conv when we're the only user
333 * (not optimal but for now...)
335 if (get_irn_n_edges(node) > 1)
338 src_mode = get_irn_mode(get_Conv_op(node));
339 dest_mode = get_irn_mode(node);
341 mode_needs_gp_reg(src_mode) &&
342 mode_needs_gp_reg(dest_mode) &&
343 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
346 static ir_node *arm_skip_downconv(ir_node *node)
348 while (is_downconv(node))
349 node = get_Conv_op(node);
355 MATCH_COMMUTATIVE = 1 << 0,
356 MATCH_SIZE_NEUTRAL = 1 << 1,
359 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
360 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
362 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
363 new_binop_reg_func new_reg, new_binop_imm_func new_imm)
365 ir_node *block = be_transform_node(get_nodes_block(node));
366 ir_node *op1 = get_binop_left(node);
368 ir_node *op2 = get_binop_right(node);
370 dbg_info *dbgi = get_irn_dbg_info(node);
373 if (flags & MATCH_SIZE_NEUTRAL) {
374 op1 = arm_skip_downconv(op1);
375 op2 = arm_skip_downconv(op2);
377 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
380 if (try_encode_as_immediate(op2, &imm)) {
381 ir_node *new_op1 = be_transform_node(op1);
382 return new_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
384 new_op2 = be_transform_node(op2);
385 if ((flags & MATCH_COMMUTATIVE) && try_encode_as_immediate(op1, &imm)) {
386 return new_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
388 new_op1 = be_transform_node(op1);
390 return new_reg(dbgi, block, new_op1, new_op2);
394 * Creates an ARM Add.
396 * @return the created arm Add node
398 static ir_node *gen_Add(ir_node *node)
400 ir_mode *mode = get_irn_mode(node);
402 if (mode_is_float(mode)) {
403 ir_node *block = be_transform_node(get_nodes_block(node));
404 ir_node *op1 = get_Add_left(node);
405 ir_node *op2 = get_Add_right(node);
406 dbg_info *dbgi = get_irn_dbg_info(node);
407 ir_node *new_op1 = be_transform_node(op1);
408 ir_node *new_op2 = be_transform_node(op2);
409 if (USE_FPA(env_cg->isa)) {
410 return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
411 } else if (USE_VFP(env_cg->isa)) {
412 assert(mode != mode_E && "IEEE Extended FP not supported");
413 panic("VFP not supported yet");
415 panic("Softfloat not supported yet");
420 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
422 new_op2 = get_irn_n(new_op1, 1);
423 new_op1 = get_irn_n(new_op1, 0);
425 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
427 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
429 new_op1 = get_irn_n(new_op2, 0);
430 new_op2 = get_irn_n(new_op2, 1);
432 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
436 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
437 new_bd_arm_Add_reg, new_bd_arm_Add_imm);
442 * Creates an ARM Mul.
444 * @return the created arm Mul node
446 static ir_node *gen_Mul(ir_node *node)
448 ir_node *block = be_transform_node(get_nodes_block(node));
449 ir_node *op1 = get_Mul_left(node);
450 ir_node *new_op1 = be_transform_node(op1);
451 ir_node *op2 = get_Mul_right(node);
452 ir_node *new_op2 = be_transform_node(op2);
453 ir_mode *mode = get_irn_mode(node);
454 dbg_info *dbg = get_irn_dbg_info(node);
456 if (mode_is_float(mode)) {
457 if (USE_FPA(env_cg->isa)) {
458 return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
459 } else if (USE_VFP(env_cg->isa)) {
460 assert(mode != mode_E && "IEEE Extended FP not supported");
461 panic("VFP not supported yet");
463 panic("Softfloat not supported yet");
466 assert(mode_is_data(mode));
467 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
470 static ir_node *gen_Quot(ir_node *node)
472 ir_node *block = be_transform_node(get_nodes_block(node));
473 ir_node *op1 = get_Quot_left(node);
474 ir_node *new_op1 = be_transform_node(op1);
475 ir_node *op2 = get_Quot_right(node);
476 ir_node *new_op2 = be_transform_node(op2);
477 ir_mode *mode = get_irn_mode(node);
478 dbg_info *dbg = get_irn_dbg_info(node);
480 assert(mode != mode_E && "IEEE Extended FP not supported");
482 if (USE_FPA(env_cg->isa)) {
483 return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
484 } else if (USE_VFP(env_cg->isa)) {
485 assert(mode != mode_E && "IEEE Extended FP not supported");
486 panic("VFP not supported yet");
488 panic("Softfloat not supported yet");
492 static ir_node *gen_And(ir_node *node)
494 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
495 new_bd_arm_And_reg, new_bd_arm_And_imm);
498 static ir_node *gen_Or(ir_node *node)
500 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
501 new_bd_arm_Or_reg, new_bd_arm_Or_imm);
504 static ir_node *gen_Eor(ir_node *node)
506 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
507 new_bd_arm_Eor_reg, new_bd_arm_Eor_imm);
510 static ir_node *gen_Sub(ir_node *node)
512 ir_node *block = be_transform_node(get_nodes_block(node));
513 ir_node *op1 = get_Sub_left(node);
514 ir_node *new_op1 = be_transform_node(op1);
515 ir_node *op2 = get_Sub_right(node);
516 ir_node *new_op2 = be_transform_node(op2);
517 ir_mode *mode = get_irn_mode(node);
518 dbg_info *dbgi = get_irn_dbg_info(node);
520 if (mode_is_float(mode)) {
521 if (USE_FPA(env_cg->isa)) {
522 return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
523 } else if (USE_VFP(env_cg->isa)) {
524 assert(mode != mode_E && "IEEE Extended FP not supported");
525 panic("VFP not supported yet");
527 panic("Softfloat not supported yet");
530 return gen_int_binop(node, MATCH_SIZE_NEUTRAL,
531 new_bd_arm_Sub_reg, new_bd_arm_Sub_imm);
536 * Checks if a given value can be used as an immediate for the given
539 static bool can_use_shift_constant(unsigned int val,
540 arm_shift_modifier_t modifier)
544 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
550 * generate an ARM shift instruction.
552 * @param node the node
553 * @param flags matching flags
554 * @param shift_modifier initial encoding of the desired shift operation
556 static ir_node *make_shift(ir_node *node, match_flags_t flags,
557 arm_shift_modifier_t shift_modifier)
559 ir_node *block = be_transform_node(get_nodes_block(node));
560 ir_node *op1 = get_binop_left(node);
561 ir_node *op2 = get_binop_right(node);
562 dbg_info *dbgi = get_irn_dbg_info(node);
566 if (flags & MATCH_SIZE_NEUTRAL) {
567 op1 = arm_skip_downconv(op1);
568 op2 = arm_skip_downconv(op2);
571 new_op1 = be_transform_node(op1);
573 tarval *tv = get_Const_tarval(op2);
574 unsigned int val = get_tarval_long(tv);
575 assert(tarval_is_long(tv));
576 if (can_use_shift_constant(val, shift_modifier)) {
577 switch (shift_modifier) {
578 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
579 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
580 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
581 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
582 default: panic("unexpected shift modifier");
584 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
585 shift_modifier, val);
589 new_op2 = be_transform_node(op2);
590 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
594 static ir_node *gen_Shl(ir_node *node)
596 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
599 static ir_node *gen_Shr(ir_node *node)
601 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
604 static ir_node *gen_Shrs(ir_node *node)
606 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
609 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
611 ir_node *block = be_transform_node(get_nodes_block(node));
612 ir_node *new_op1 = be_transform_node(op1);
613 dbg_info *dbgi = get_irn_dbg_info(node);
614 ir_node *new_op2 = be_transform_node(op2);
616 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
620 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
622 ir_node *block = be_transform_node(get_nodes_block(node));
623 ir_node *new_op1 = be_transform_node(op1);
624 dbg_info *dbgi = get_irn_dbg_info(node);
625 ir_node *new_op2 = be_transform_node(op2);
627 /* Note: there is no Rol on arm, we have to use Ror */
628 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
629 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
633 static ir_node *gen_Rotl(ir_node *node)
635 ir_node *rotate = NULL;
636 ir_node *op1 = get_Rotl_left(node);
637 ir_node *op2 = get_Rotl_right(node);
639 /* Firm has only RotL, so we are looking for a right (op2)
640 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
641 that means we can create a RotR. */
644 ir_node *right = get_Add_right(op2);
645 if (is_Const(right)) {
646 tarval *tv = get_Const_tarval(right);
647 ir_mode *mode = get_irn_mode(node);
648 long bits = get_mode_size_bits(mode);
649 ir_node *left = get_Add_left(op2);
651 if (is_Minus(left) &&
652 tarval_is_long(tv) &&
653 get_tarval_long(tv) == bits &&
655 rotate = gen_Ror(node, op1, get_Minus_op(left));
657 } else if (is_Sub(op2)) {
658 ir_node *left = get_Sub_left(op2);
659 if (is_Const(left)) {
660 tarval *tv = get_Const_tarval(left);
661 ir_mode *mode = get_irn_mode(node);
662 long bits = get_mode_size_bits(mode);
663 ir_node *right = get_Sub_right(op2);
665 if (tarval_is_long(tv) &&
666 get_tarval_long(tv) == bits &&
668 rotate = gen_Ror(node, op1, right);
670 } else if (is_Const(op2)) {
671 tarval *tv = get_Const_tarval(op2);
672 ir_mode *mode = get_irn_mode(node);
673 long bits = get_mode_size_bits(mode);
675 if (tarval_is_long(tv) && bits == 32) {
676 ir_node *block = be_transform_node(get_nodes_block(node));
677 ir_node *new_op1 = be_transform_node(op1);
678 dbg_info *dbgi = get_irn_dbg_info(node);
680 bits = (bits - get_tarval_long(tv)) & 31;
681 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
685 if (rotate == NULL) {
686 rotate = gen_Rol(node, op1, op2);
692 static ir_node *gen_Not(ir_node *node)
694 ir_node *block = be_transform_node(get_nodes_block(node));
695 ir_node *op = get_Not_op(node);
696 ir_node *new_op = be_transform_node(op);
697 dbg_info *dbgi = get_irn_dbg_info(node);
699 /* TODO: we could do alot more here with all the Mvn variations */
701 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
704 static ir_node *gen_Minus(ir_node *node)
706 ir_node *block = be_transform_node(get_nodes_block(node));
707 ir_node *op = get_Minus_op(node);
708 ir_node *new_op = be_transform_node(op);
709 dbg_info *dbgi = get_irn_dbg_info(node);
710 ir_mode *mode = get_irn_mode(node);
712 if (mode_is_float(mode)) {
713 if (USE_FPA(env_cg->isa)) {
714 return new_bd_arm_Mvf(dbgi, block, op, mode);
715 } else if (USE_VFP(env_cg->isa)) {
716 assert(mode != mode_E && "IEEE Extended FP not supported");
717 panic("VFP not supported yet");
719 panic("Softfloat not supported yet");
722 assert(mode_is_data(mode));
723 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
726 static ir_node *gen_Load(ir_node *node)
728 ir_node *block = be_transform_node(get_nodes_block(node));
729 ir_node *ptr = get_Load_ptr(node);
730 ir_node *new_ptr = be_transform_node(ptr);
731 ir_node *mem = get_Load_mem(node);
732 ir_node *new_mem = be_transform_node(mem);
733 ir_mode *mode = get_Load_mode(node);
734 dbg_info *dbgi = get_irn_dbg_info(node);
735 ir_node *new_load = NULL;
737 if (mode_is_float(mode)) {
738 if (USE_FPA(env_cg->isa)) {
739 new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
741 } else if (USE_VFP(env_cg->isa)) {
742 assert(mode != mode_E && "IEEE Extended FP not supported");
743 panic("VFP not supported yet");
745 panic("Softfloat not supported yet");
748 assert(mode_is_data(mode) && "unsupported mode for Load");
750 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
752 set_irn_pinned(new_load, get_irn_pinned(node));
754 /* check for special case: the loaded value might not be used */
755 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
756 /* add a result proj and a Keep to produce a pseudo use */
757 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
758 be_new_Keep(block, 1, &proj);
764 static ir_node *gen_Store(ir_node *node)
766 ir_node *block = be_transform_node(get_nodes_block(node));
767 ir_node *ptr = get_Store_ptr(node);
768 ir_node *new_ptr = be_transform_node(ptr);
769 ir_node *mem = get_Store_mem(node);
770 ir_node *new_mem = be_transform_node(mem);
771 ir_node *val = get_Store_value(node);
772 ir_node *new_val = be_transform_node(val);
773 ir_mode *mode = get_irn_mode(val);
774 dbg_info *dbgi = get_irn_dbg_info(node);
775 ir_node *new_store = NULL;
777 if (mode_is_float(mode)) {
778 if (USE_FPA(env_cg->isa)) {
779 new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
780 new_mem, mode, NULL, 0, 0, false);
781 } else if (USE_VFP(env_cg->isa)) {
782 assert(mode != mode_E && "IEEE Extended FP not supported");
783 panic("VFP not supported yet");
785 panic("Softfloat not supported yet");
788 assert(mode_is_data(mode) && "unsupported mode for Store");
789 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
792 set_irn_pinned(new_store, get_irn_pinned(node));
796 static ir_node *gen_Jmp(ir_node *node)
798 ir_node *block = get_nodes_block(node);
799 ir_node *new_block = be_transform_node(block);
800 dbg_info *dbgi = get_irn_dbg_info(node);
802 return new_bd_arm_Jmp(dbgi, new_block);
805 static ir_node *gen_SwitchJmp(ir_node *node)
807 ir_node *block = be_transform_node(get_nodes_block(node));
808 ir_node *selector = get_Cond_selector(node);
809 dbg_info *dbgi = get_irn_dbg_info(node);
810 ir_node *new_op = be_transform_node(selector);
811 ir_node *const_graph;
815 const ir_edge_t *edge;
822 foreach_out_edge(node, edge) {
823 proj = get_edge_src_irn(edge);
824 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
826 pn = get_Proj_proj(proj);
828 min = pn<min ? pn : min;
829 max = pn>max ? pn : max;
832 n_projs = max - translation + 1;
834 foreach_out_edge(node, edge) {
835 proj = get_edge_src_irn(edge);
836 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
838 pn = get_Proj_proj(proj) - translation;
839 set_Proj_proj(proj, pn);
842 const_graph = create_const_graph_value(dbgi, block, translation);
843 sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
844 return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
847 static ir_node *gen_Cmp(ir_node *node)
849 ir_node *block = be_transform_node(get_nodes_block(node));
850 ir_node *op1 = get_Cmp_left(node);
851 ir_node *op2 = get_Cmp_right(node);
852 ir_mode *cmp_mode = get_irn_mode(op1);
853 dbg_info *dbgi = get_irn_dbg_info(node);
858 if (mode_is_float(cmp_mode)) {
859 /* TODO: this is broken... */
860 new_op1 = be_transform_node(op1);
861 new_op2 = be_transform_node(op2);
863 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
865 panic("FloatCmp NIY");
867 ir_node *new_op2 = be_transform_node(op2);
868 /* floating point compare */
869 pn_Cmp pnc = get_Proj_proj(selector);
871 if (pnc & pn_Cmp_Uo) {
872 /* check for unordered, need cmf */
873 return new_bd_arm_CmfBra(dbgi, block, new_op1, new_op2, pnc);
875 /* Hmm: use need cmfe */
876 return new_bd_arm_CmfeBra(dbgi, block, new_op1, new_op2, pnc);
880 assert(get_irn_mode(op2) == cmp_mode);
881 is_unsigned = !mode_is_signed(cmp_mode);
883 /* compare with 0 can be done with Tst */
884 if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) {
885 new_op1 = be_transform_node(op1);
886 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
887 return new_bd_arm_Tst_reg(dbgi, block, new_op1, new_op1, false,
890 if (is_Const(op1) && tarval_is_null(get_Const_tarval(op1))) {
891 new_op2 = be_transform_node(op2);
892 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
893 return new_bd_arm_Tst_reg(dbgi, block, new_op2, new_op2, true,
897 /* integer compare, TODO: use shifter_op in all its combinations */
898 new_op1 = be_transform_node(op1);
899 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
900 new_op2 = be_transform_node(op2);
901 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
902 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
906 static ir_node *gen_Cond(ir_node *node)
908 ir_node *selector = get_Cond_selector(node);
909 ir_mode *mode = get_irn_mode(selector);
914 if (mode != mode_b) {
915 return gen_SwitchJmp(node);
917 assert(is_Proj(selector));
919 block = be_transform_node(get_nodes_block(node));
920 dbgi = get_irn_dbg_info(node);
921 flag_node = be_transform_node(get_Proj_pred(selector));
923 return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector));
926 static tarval *fpa_imm[3][fpa_max];
930 * Check, if a floating point tarval is an fpa immediate, i.e.
931 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
933 static int is_fpa_immediate(tarval *tv)
935 ir_mode *mode = get_tarval_mode(tv);
938 switch (get_mode_size_bits(mode)) {
949 if (tarval_is_negative(tv)) {
954 for (j = 0; j < fpa_max; ++j) {
955 if (tv == fpa_imm[i][j])
962 static ir_node *gen_Const(ir_node *node)
964 ir_node *block = be_transform_node(get_nodes_block(node));
965 ir_mode *mode = get_irn_mode(node);
966 dbg_info *dbg = get_irn_dbg_info(node);
968 if (mode_is_float(mode)) {
969 if (USE_FPA(env_cg->isa)) {
970 tarval *tv = get_Const_tarval(node);
971 node = new_bd_arm_fConst(dbg, block, tv);
972 be_dep_on_frame(node);
974 } else if (USE_VFP(env_cg->isa)) {
975 assert(mode != mode_E && "IEEE Extended FP not supported");
976 panic("VFP not supported yet");
978 panic("Softfloat not supported yet");
981 return create_const_graph(node, block);
984 static ir_node *gen_SymConst(ir_node *node)
986 ir_node *block = be_transform_node(get_nodes_block(node));
987 ir_entity *entity = get_SymConst_entity(node);
988 dbg_info *dbgi = get_irn_dbg_info(node);
991 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
992 be_dep_on_frame(new_node);
996 static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0,
999 /* the good way to do this would be to use the stm (store multiple)
1000 * instructions, since our input is nearly always 2 consecutive 32bit
1002 ir_graph *irg = current_ir_graph;
1003 ir_node *stack = get_irg_frame(irg);
1004 ir_node *nomem = new_NoMem();
1005 ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp,
1007 ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp,
1009 ir_node *in[2] = { str0, str1 };
1010 ir_node *sync = new_r_Sync(block, 2, in);
1012 set_irn_pinned(str0, op_pin_state_floats);
1013 set_irn_pinned(str1, op_pin_state_floats);
1015 ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true);
1016 set_irn_pinned(ldf, op_pin_state_floats);
1018 return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1021 static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node)
1023 ir_graph *irg = current_ir_graph;
1024 ir_node *stack = get_irg_frame(irg);
1025 ir_node *nomem = new_NoMem();
1026 ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp,
1029 set_irn_pinned(str, op_pin_state_floats);
1031 ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true);
1032 set_irn_pinned(ldf, op_pin_state_floats);
1034 return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1037 static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node)
1039 ir_graph *irg = current_ir_graph;
1040 ir_node *stack = get_irg_frame(irg);
1041 ir_node *nomem = new_NoMem();
1042 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F,
1045 set_irn_pinned(stf, op_pin_state_floats);
1047 ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1048 set_irn_pinned(ldr, op_pin_state_floats);
1050 return new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1053 static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node,
1054 ir_node **out_value0, ir_node **out_value1)
1056 ir_graph *irg = current_ir_graph;
1057 ir_node *stack = get_irg_frame(irg);
1058 ir_node *nomem = new_NoMem();
1059 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D,
1061 ir_node *ldr0, *ldr1;
1062 set_irn_pinned(stf, op_pin_state_floats);
1064 ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1065 set_irn_pinned(ldr0, op_pin_state_floats);
1066 ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true);
1067 set_irn_pinned(ldr1, op_pin_state_floats);
1069 *out_value0 = new_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
1070 *out_value1 = new_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
1073 static ir_node *gen_CopyB(ir_node *node)
1075 ir_node *block = be_transform_node(get_nodes_block(node));
1076 ir_node *src = get_CopyB_src(node);
1077 ir_node *new_src = be_transform_node(src);
1078 ir_node *dst = get_CopyB_dst(node);
1079 ir_node *new_dst = be_transform_node(dst);
1080 ir_node *mem = get_CopyB_mem(node);
1081 ir_node *new_mem = be_transform_node(mem);
1082 dbg_info *dbg = get_irn_dbg_info(node);
1083 int size = get_type_size_bytes(get_CopyB_type(node));
1087 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
1088 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
1090 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1091 new_bd_arm_EmptyReg(dbg, block),
1092 new_bd_arm_EmptyReg(dbg, block),
1093 new_bd_arm_EmptyReg(dbg, block),
1097 static ir_node *gen_Proj_Load(ir_node *node)
1099 ir_node *load = get_Proj_pred(node);
1100 ir_node *new_load = be_transform_node(load);
1101 dbg_info *dbgi = get_irn_dbg_info(node);
1102 long proj = get_Proj_proj(node);
1104 /* renumber the proj */
1105 switch (get_arm_irn_opcode(new_load)) {
1107 /* handle all gp loads equal: they have the same proj numbers. */
1108 if (proj == pn_Load_res) {
1109 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1110 } else if (proj == pn_Load_M) {
1111 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1115 if (proj == pn_Load_res) {
1116 ir_mode *mode = get_Load_mode(load);
1117 return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res);
1118 } else if (proj == pn_Load_M) {
1119 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M);
1125 panic("Unsupported Proj from Load");
1128 static ir_node *gen_Proj_CopyB(ir_node *node)
1130 ir_node *pred = get_Proj_pred(node);
1131 ir_node *new_pred = be_transform_node(pred);
1132 dbg_info *dbgi = get_irn_dbg_info(node);
1133 long proj = get_Proj_proj(node);
1137 if (is_arm_CopyB(new_pred)) {
1138 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1144 panic("Unsupported Proj from CopyB");
1147 static ir_node *gen_Proj_Quot(ir_node *node)
1149 ir_node *pred = get_Proj_pred(node);
1150 ir_node *new_pred = be_transform_node(pred);
1151 dbg_info *dbgi = get_irn_dbg_info(node);
1152 ir_mode *mode = get_irn_mode(node);
1153 long proj = get_Proj_proj(node);
1157 if (is_arm_Dvf(new_pred)) {
1158 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
1162 if (is_arm_Dvf(new_pred)) {
1163 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
1169 panic("Unsupported Proj from Quot");
1173 * Transform the Projs from a Cmp.
1175 static ir_node *gen_Proj_Cmp(ir_node *node)
1178 /* we should only be here in case of a Mux node */
1182 static ir_node *gen_Proj_Start(ir_node *node)
1184 ir_node *block = get_nodes_block(node);
1185 ir_node *new_block = be_transform_node(block);
1186 ir_node *barrier = be_transform_node(get_Proj_pred(node));
1187 long proj = get_Proj_proj(node);
1189 switch ((pn_Start) proj) {
1190 case pn_Start_X_initial_exec:
1191 /* we exchange the ProjX with a jump */
1192 return new_bd_arm_Jmp(NULL, new_block);
1195 return new_r_Proj(barrier, mode_M, 0);
1197 case pn_Start_T_args:
1200 case pn_Start_P_frame_base:
1201 return be_prolog_get_reg_value(abihelper, sp_reg);
1203 case pn_Start_P_tls:
1209 panic("unexpected start proj: %ld\n", proj);
1212 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1214 long pn = get_Proj_proj(node);
1215 ir_node *block = get_nodes_block(node);
1216 ir_node *new_block = be_transform_node(block);
1217 ir_entity *entity = get_irg_entity(current_ir_graph);
1218 ir_type *method_type = get_entity_type(entity);
1219 ir_type *param_type = get_method_param_type(method_type, pn);
1220 const reg_or_stackslot_t *param;
1222 /* Proj->Proj->Start must be a method argument */
1223 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1225 param = &cconv->parameters[pn];
1227 if (param->reg0 != NULL) {
1228 /* argument transmitted in register */
1229 ir_mode *mode = get_type_mode(param_type);
1230 ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0);
1232 if (mode_is_float(mode)) {
1233 ir_node *value1 = NULL;
1235 if (param->reg1 != NULL) {
1236 value1 = be_prolog_get_reg_value(abihelper, param->reg1);
1237 } else if (param->entity != NULL) {
1238 ir_graph *irg = get_irn_irg(node);
1239 ir_node *fp = get_irg_frame(irg);
1240 ir_node *mem = be_prolog_get_memory(abihelper);
1241 ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem,
1242 mode_gp, param->entity,
1244 value1 = new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1247 /* convert integer value to float */
1248 if (value1 == NULL) {
1249 value = int_to_float(NULL, new_block, value);
1251 value = ints_to_double(NULL, new_block, value, value1);
1256 /* argument transmitted on stack */
1257 ir_graph *irg = get_irn_irg(node);
1258 ir_node *fp = get_irg_frame(irg);
1259 ir_node *mem = be_prolog_get_memory(abihelper);
1260 ir_mode *mode = get_type_mode(param->type);
1264 if (mode_is_float(mode)) {
1265 load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode,
1266 param->entity, 0, 0, true);
1267 value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res);
1269 load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1270 param->entity, 0, 0, true);
1271 value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1273 set_irn_pinned(load, op_pin_state_floats);
1280 * Finds number of output value of a mode_T node which is constrained to
1281 * a single specific register.
1283 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1285 int n_outs = arch_irn_get_n_outs(node);
1288 for (o = 0; o < n_outs; ++o) {
1289 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1290 if (req == reg->single_req)
1296 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1298 long pn = get_Proj_proj(node);
1299 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1300 ir_node *new_call = be_transform_node(call);
1301 ir_type *function_type = get_Call_type(call);
1302 calling_convention_t *cconv = decide_calling_convention(function_type);
1303 const reg_or_stackslot_t *res = &cconv->results[pn];
1307 /* TODO 64bit modes */
1308 assert(res->reg0 != NULL && res->reg1 == NULL);
1309 regn = find_out_for_reg(new_call, res->reg0);
1311 panic("Internal error in calling convention for return %+F", node);
1313 mode = res->reg0->reg_class->mode;
1315 free_calling_convention(cconv);
1317 return new_r_Proj(new_call, mode, regn);
1320 static ir_node *gen_Proj_Call(ir_node *node)
1322 long pn = get_Proj_proj(node);
1323 ir_node *call = get_Proj_pred(node);
1324 ir_node *new_call = be_transform_node(call);
1326 switch ((pn_Call) pn) {
1328 return new_r_Proj(new_call, mode_M, 0);
1329 case pn_Call_X_regular:
1330 case pn_Call_X_except:
1331 case pn_Call_T_result:
1332 case pn_Call_P_value_res_base:
1336 panic("Unexpected Call proj %ld\n", pn);
1340 * Transform a Proj node.
1342 static ir_node *gen_Proj(ir_node *node)
1344 ir_node *pred = get_Proj_pred(node);
1345 long proj = get_Proj_proj(node);
1347 switch (get_irn_opcode(pred)) {
1349 if (proj == pn_Store_M) {
1350 return be_transform_node(pred);
1352 panic("Unsupported Proj from Store");
1355 return gen_Proj_Load(node);
1357 return gen_Proj_Call(node);
1359 return gen_Proj_CopyB(node);
1361 return gen_Proj_Quot(node);
1363 return gen_Proj_Cmp(node);
1365 return gen_Proj_Start(node);
1368 return be_duplicate_node(node);
1370 ir_node *pred_pred = get_Proj_pred(pred);
1371 if (is_Call(pred_pred)) {
1372 return gen_Proj_Proj_Call(node);
1373 } else if (is_Start(pred_pred)) {
1374 return gen_Proj_Proj_Start(node);
1379 panic("code selection didn't expect Proj after %+F\n", pred);
1383 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1385 static inline ir_node *create_const(ir_node **place,
1386 create_const_node_func func,
1387 const arch_register_t* reg)
1389 ir_node *block, *res;
1394 block = get_irg_start_block(env_cg->irg);
1395 res = func(NULL, block);
1396 arch_set_irn_register(res, reg);
1401 static ir_node *gen_Unknown(ir_node *node)
1403 ir_node *block = get_nodes_block(node);
1404 ir_node *new_block = be_transform_node(block);
1405 dbg_info *dbgi = get_irn_dbg_info(node);
1407 /* just produce a 0 */
1408 ir_mode *mode = get_irn_mode(node);
1409 if (mode_is_float(mode)) {
1410 tarval *tv = get_mode_null(mode);
1411 ir_node *node = new_bd_arm_fConst(dbgi, new_block, tv);
1412 be_dep_on_frame(node);
1414 } else if (mode_needs_gp_reg(mode)) {
1415 return create_const_graph_value(dbgi, new_block, 0);
1418 panic("Unexpected Unknown mode");
1422 * Produces the type which sits between the stack args and the locals on the
1423 * stack. It will contain the return address and space to store the old base
1425 * @return The Firm type modeling the ABI between type.
1427 static ir_type *arm_get_between_type(void)
1429 static ir_type *between_type = NULL;
1431 if (between_type == NULL) {
1432 between_type = new_type_class(new_id_from_str("arm_between_type"));
1433 set_type_size_bytes(between_type, 0);
1436 return between_type;
1439 static void create_stacklayout(ir_graph *irg)
1441 ir_entity *entity = get_irg_entity(irg);
1442 ir_type *function_type = get_entity_type(entity);
1443 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1448 /* calling conventions must be decided by now */
1449 assert(cconv != NULL);
1451 /* construct argument type */
1452 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1453 n_params = get_method_n_params(function_type);
1454 for (p = 0; p < n_params; ++p) {
1455 reg_or_stackslot_t *param = &cconv->parameters[p];
1459 if (param->type == NULL)
1462 snprintf(buf, sizeof(buf), "param_%d", p);
1463 id = new_id_from_str(buf);
1464 param->entity = new_entity(arg_type, id, param->type);
1465 set_entity_offset(param->entity, param->offset);
1468 /* TODO: what about external functions? we don't know most of the stack
1469 * layout for them. And probably don't need all of this... */
1470 memset(layout, 0, sizeof(*layout));
1472 layout->frame_type = get_irg_frame_type(irg);
1473 layout->between_type = arm_get_between_type();
1474 layout->arg_type = arg_type;
1475 layout->param_map = NULL; /* TODO */
1476 layout->initial_offset = 0;
1477 layout->initial_bias = 0;
1478 layout->stack_dir = -1;
1479 layout->sp_relative = true;
1481 assert(N_FRAME_TYPES == 3);
1482 layout->order[0] = layout->frame_type;
1483 layout->order[1] = layout->between_type;
1484 layout->order[2] = layout->arg_type;
1488 * transform the start node to the prolog code + initial barrier
1490 static ir_node *gen_Start(ir_node *node)
1492 ir_graph *irg = get_irn_irg(node);
1493 ir_entity *entity = get_irg_entity(irg);
1494 ir_type *function_type = get_entity_type(entity);
1495 ir_node *block = get_nodes_block(node);
1496 ir_node *new_block = be_transform_node(block);
1497 dbg_info *dbgi = get_irn_dbg_info(node);
1504 /* stackpointer is important at function prolog */
1505 be_prolog_add_reg(abihelper, sp_reg,
1506 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1507 /* function parameters in registers */
1508 for (i = 0; i < get_method_n_params(function_type); ++i) {
1509 const reg_or_stackslot_t *param = &cconv->parameters[i];
1510 if (param->reg0 != NULL)
1511 be_prolog_add_reg(abihelper, param->reg0, 0);
1512 if (param->reg1 != NULL)
1513 be_prolog_add_reg(abihelper, param->reg1, 0);
1515 /* announce that we need the values of the callee save regs */
1516 for (i = 0; i < (int) (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
1517 be_prolog_add_reg(abihelper, callee_saves[i], 0);
1520 start = be_prolog_create_start(abihelper, dbgi, new_block);
1521 sp = be_prolog_get_reg_value(abihelper, sp_reg);
1522 incsp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
1523 be_prolog_set_reg_value(abihelper, sp_reg, incsp);
1524 barrier = be_prolog_create_barrier(abihelper, new_block);
1529 static ir_node *get_stack_pointer_for(ir_node *node)
1531 /* get predecessor in stack_order list */
1532 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1533 ir_node *stack_pred_transformed;
1536 if (stack_pred == NULL) {
1537 /* first stack user in the current block. We can simply use the
1538 * initial sp_proj for it */
1539 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1543 stack_pred_transformed = be_transform_node(stack_pred);
1544 stack = pmap_get(node_to_stack, stack_pred);
1545 if (stack == NULL) {
1546 return get_stack_pointer_for(stack_pred);
1553 * transform a Return node into epilogue code + return statement
1555 static ir_node *gen_Return(ir_node *node)
1557 ir_node *block = get_nodes_block(node);
1558 ir_node *new_block = be_transform_node(block);
1559 dbg_info *dbgi = get_irn_dbg_info(node);
1560 ir_node *mem = get_Return_mem(node);
1561 ir_node *new_mem = be_transform_node(mem);
1562 int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
1563 ir_node *sp_proj = get_stack_pointer_for(node);
1564 int n_res = get_Return_n_ress(node);
1569 be_epilog_begin(abihelper);
1570 be_epilog_set_memory(abihelper, new_mem);
1571 /* connect stack pointer with initial stack pointer. fix_stack phase
1572 will later serialize all stack pointer adjusting nodes */
1573 be_epilog_add_reg(abihelper, sp_reg,
1574 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1578 for (i = 0; i < n_res; ++i) {
1579 ir_node *res_value = get_Return_res(node, i);
1580 ir_node *new_res_value = be_transform_node(res_value);
1581 const reg_or_stackslot_t *slot = &cconv->results[i];
1582 const arch_register_t *reg = slot->reg0;
1583 assert(slot->reg1 == NULL);
1584 be_epilog_add_reg(abihelper, reg, 0, new_res_value);
1587 /* connect callee saves with their values at the function begin */
1588 for (i = 0; i < n_callee_saves; ++i) {
1589 const arch_register_t *reg = callee_saves[i];
1590 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1591 be_epilog_add_reg(abihelper, reg, 0, value);
1594 /* create the barrier before the epilog code */
1595 be_epilog_create_barrier(abihelper, new_block);
1597 /* epilog code: an incsp */
1598 sp_proj = be_epilog_get_reg_value(abihelper, sp_reg);
1599 incsp = be_new_IncSP(sp_reg, new_block, sp_proj,
1600 BE_STACK_FRAME_SIZE_SHRINK, 0);
1601 be_epilog_set_reg_value(abihelper, sp_reg, incsp);
1603 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1609 static ir_node *gen_Call(ir_node *node)
1611 ir_graph *irg = get_irn_irg(node);
1612 ir_node *callee = get_Call_ptr(node);
1613 ir_node *block = get_nodes_block(node);
1614 ir_node *new_block = be_transform_node(block);
1615 ir_node *mem = get_Call_mem(node);
1616 ir_node *new_mem = be_transform_node(mem);
1617 dbg_info *dbgi = get_irn_dbg_info(node);
1618 ir_type *type = get_Call_type(node);
1619 calling_convention_t *cconv = decide_calling_convention(type);
1620 int n_params = get_Call_n_params(node);
1621 int n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
1622 /* max inputs: memory, callee, register arguments */
1623 int max_inputs = 2 + n_param_regs;
1624 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1625 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1626 struct obstack *obst = be_get_be_obst(irg);
1627 const arch_register_req_t **in_req
1628 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1632 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1633 ir_entity *entity = NULL;
1634 ir_node *incsp = NULL;
1641 assert(n_params == get_method_n_params(type));
1643 /* construct arguments */
1646 in_req[in_arity] = arch_no_register_req;
1650 for (p = 0; p < n_params; ++p) {
1651 ir_node *value = get_Call_param(node, p);
1652 ir_node *new_value = be_transform_node(value);
1653 ir_node *new_value1 = NULL;
1654 const reg_or_stackslot_t *param = &cconv->parameters[p];
1655 ir_type *param_type = get_method_param_type(type, p);
1656 ir_mode *mode = get_type_mode(param_type);
1659 if (mode_is_float(mode) && param->reg0 != NULL) {
1660 unsigned size_bits = get_mode_size_bits(mode);
1661 if (size_bits == 64) {
1662 double_to_ints(dbgi, new_block, new_value, &new_value,
1665 assert(size_bits == 32);
1666 new_value = float_to_int(dbgi, new_block, new_value);
1670 /* put value into registers */
1671 if (param->reg0 != NULL) {
1672 in[in_arity] = new_value;
1673 in_req[in_arity] = param->reg0->single_req;
1675 if (new_value1 == NULL)
1678 if (param->reg1 != NULL) {
1679 assert(new_value1 != NULL);
1680 in[in_arity] = new_value1;
1681 in_req[in_arity] = param->reg1->single_req;
1686 /* we need a store if we're here */
1687 if (new_value1 != NULL) {
1688 new_value = new_value1;
1692 /* create a parameter frame if necessary */
1693 if (incsp == NULL) {
1694 ir_node *new_frame = get_stack_pointer_for(node);
1695 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1696 cconv->param_stack_size, 1);
1698 if (mode_is_float(mode)) {
1699 str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem,
1700 mode, NULL, 0, param->offset, true);
1702 str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem,
1703 mode, NULL, 0, param->offset, true);
1705 sync_ins[sync_arity++] = str;
1707 assert(in_arity <= max_inputs);
1709 /* construct memory input */
1710 if (sync_arity == 0) {
1711 in[mem_pos] = new_mem;
1712 } else if (sync_arity == 1) {
1713 in[mem_pos] = sync_ins[0];
1715 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1718 /* TODO: use a generic symconst matcher here */
1719 if (is_SymConst(callee)) {
1720 entity = get_SymConst_entity(callee);
1722 /* TODO: finish load matcher here */
1725 if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) {
1726 ir_node *load = get_Proj_pred(callee);
1727 ir_node *ptr = get_Load_ptr(load);
1728 ir_node *new_ptr = be_transform_node(ptr);
1729 ir_node *mem = get_Load_mem(load);
1730 ir_node *new_mem = be_transform_node(mem);
1731 ir_mode *mode = get_Load_mode(node);
1735 in[in_arity] = be_transform_node(callee);
1736 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1745 out_arity = 1 + n_caller_saves;
1747 if (entity != NULL) {
1748 /* TODO: use a generic symconst matcher here
1749 * so we can also handle entity+offset, etc. */
1750 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1753 * - use a proper shifter_operand matcher
1754 * - we could also use LinkLdrPC
1756 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1760 if (incsp != NULL) {
1761 /* IncSP to destroy the call stackframe */
1762 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
1764 /* if we are the last IncSP producer in a block then we have to keep
1766 * Note: This here keeps all producers which is more than necessary */
1767 add_irn_dep(incsp, res);
1770 pmap_insert(node_to_stack, node, incsp);
1773 set_arm_in_req_all(res, in_req);
1775 /* create output register reqs */
1776 arch_set_out_register_req(res, 0, arch_no_register_req);
1777 for (o = 0; o < n_caller_saves; ++o) {
1778 const arch_register_t *reg = caller_saves[o];
1779 arch_set_out_register_req(res, o+1, reg->single_req);
1782 /* copy pinned attribute */
1783 set_irn_pinned(res, get_irn_pinned(node));
1785 free_calling_convention(cconv);
1789 static ir_node *gen_Sel(ir_node *node)
1791 dbg_info *dbgi = get_irn_dbg_info(node);
1792 ir_node *block = get_nodes_block(node);
1793 ir_node *new_block = be_transform_node(block);
1794 ir_node *ptr = get_Sel_ptr(node);
1795 ir_node *new_ptr = be_transform_node(ptr);
1796 ir_entity *entity = get_Sel_entity(node);
1798 /* must be the frame pointer all other sels must have been lowered
1800 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1801 /* we should not have value types from parameters anymore - they should be
1803 assert(get_entity_owner(entity) !=
1804 get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
1806 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1810 * Change some phi modes
1812 static ir_node *gen_Phi(ir_node *node)
1814 const arch_register_req_t *req;
1815 ir_node *block = be_transform_node(get_nodes_block(node));
1816 ir_graph *irg = current_ir_graph;
1817 dbg_info *dbgi = get_irn_dbg_info(node);
1818 ir_mode *mode = get_irn_mode(node);
1821 if (mode_needs_gp_reg(mode)) {
1822 /* we shouldn't have any 64bit stuff around anymore */
1823 assert(get_mode_size_bits(mode) <= 32);
1824 /* all integer operations are on 32bit registers now */
1826 req = arm_reg_classes[CLASS_arm_gp].class_req;
1828 req = arch_no_register_req;
1831 /* phi nodes allow loops, so we use the old arguments for now
1832 * and fix this later */
1833 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
1834 get_irn_in(node) + 1);
1835 copy_node_attr(irg, node, phi);
1836 be_duplicate_deps(node, phi);
1838 arch_set_out_register_req(phi, 0, req);
1840 be_enqueue_preds(node);
1847 * Enters all transform functions into the generic pointer
1849 static void arm_register_transformers(void)
1851 be_start_transform_setup();
1853 be_set_transform_function(op_Add, gen_Add);
1854 be_set_transform_function(op_And, gen_And);
1855 be_set_transform_function(op_Call, gen_Call);
1856 be_set_transform_function(op_Cmp, gen_Cmp);
1857 be_set_transform_function(op_Cond, gen_Cond);
1858 be_set_transform_function(op_Const, gen_Const);
1859 be_set_transform_function(op_Conv, gen_Conv);
1860 be_set_transform_function(op_CopyB, gen_CopyB);
1861 be_set_transform_function(op_Eor, gen_Eor);
1862 be_set_transform_function(op_Jmp, gen_Jmp);
1863 be_set_transform_function(op_Load, gen_Load);
1864 be_set_transform_function(op_Minus, gen_Minus);
1865 be_set_transform_function(op_Mul, gen_Mul);
1866 be_set_transform_function(op_Not, gen_Not);
1867 be_set_transform_function(op_Or, gen_Or);
1868 be_set_transform_function(op_Phi, gen_Phi);
1869 be_set_transform_function(op_Proj, gen_Proj);
1870 be_set_transform_function(op_Quot, gen_Quot);
1871 be_set_transform_function(op_Return, gen_Return);
1872 be_set_transform_function(op_Rotl, gen_Rotl);
1873 be_set_transform_function(op_Sel, gen_Sel);
1874 be_set_transform_function(op_Shl, gen_Shl);
1875 be_set_transform_function(op_Shr, gen_Shr);
1876 be_set_transform_function(op_Shrs, gen_Shrs);
1877 be_set_transform_function(op_Start, gen_Start);
1878 be_set_transform_function(op_Store, gen_Store);
1879 be_set_transform_function(op_Sub, gen_Sub);
1880 be_set_transform_function(op_SymConst, gen_SymConst);
1881 be_set_transform_function(op_Unknown, gen_Unknown);
1885 * Initialize fpa Immediate support.
1887 static void arm_init_fpa_immediate(void)
1889 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
1890 fpa_imm[0][fpa_null] = get_mode_null(mode_F);
1891 fpa_imm[0][fpa_one] = get_mode_one(mode_F);
1892 fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
1893 fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
1894 fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
1895 fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
1896 fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
1897 fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
1899 fpa_imm[1][fpa_null] = get_mode_null(mode_D);
1900 fpa_imm[1][fpa_one] = get_mode_one(mode_D);
1901 fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
1902 fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
1903 fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
1904 fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
1905 fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
1906 fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
1908 fpa_imm[2][fpa_null] = get_mode_null(mode_E);
1909 fpa_imm[2][fpa_one] = get_mode_one(mode_E);
1910 fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
1911 fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
1912 fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
1913 fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
1914 fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
1915 fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
1919 * Transform a Firm graph into an ARM graph.
1921 void arm_transform_graph(arm_code_gen_t *cg)
1923 static int imm_initialized = 0;
1924 ir_graph *irg = cg->irg;
1925 ir_entity *entity = get_irg_entity(irg);
1926 ir_type *frame_type;
1931 if (! imm_initialized) {
1932 arm_init_fpa_immediate();
1933 imm_initialized = 1;
1935 arm_register_transformers();
1938 node_to_stack = pmap_create();
1940 assert(abihelper == NULL);
1941 abihelper = be_abihelper_prepare(irg);
1942 be_collect_stacknodes(abihelper);
1943 assert(cconv == NULL);
1944 cconv = decide_calling_convention(get_entity_type(entity));
1945 create_stacklayout(irg);
1947 be_transform_graph(cg->irg, NULL);
1949 be_abihelper_finish(abihelper);
1952 free_calling_convention(cconv);
1955 frame_type = get_irg_frame_type(irg);
1956 if (get_type_state(frame_type) == layout_undefined) {
1957 default_layout_compound_type(frame_type);
1960 pmap_destroy(node_to_stack);
1961 node_to_stack = NULL;
1963 be_add_missing_keeps(irg);
1966 void arm_init_transform(void)
1968 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");