2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
41 #include "../benode.h"
43 #include "../beutil.h"
44 #include "../betranshlp.h"
45 #include "bearch_arm_t.h"
47 #include "arm_nodes_attr.h"
48 #include "arm_transform.h"
49 #include "arm_optimize.h"
50 #include "arm_new_nodes.h"
51 #include "arm_map_regs.h"
53 #include "gen_arm_regalloc_if.h"
57 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
59 /** hold the current code generator during transformation */
60 static arm_code_gen_t *env_cg;
62 static inline int mode_needs_gp_reg(ir_mode *mode)
64 return mode_is_int(mode) || mode_is_reference(mode);
68 * Creates a possible DAG for an constant.
70 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
77 arm_gen_vals_from_word(value, &v);
78 arm_gen_vals_from_word(~value, &vn);
82 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
83 be_dep_on_frame(result);
85 for (cnt = 1; cnt < vn.ops; ++cnt) {
86 result = new_bd_arm_Bic_imm(dbgi, block, result,
87 vn.values[cnt], vn.rors[cnt]);
91 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
92 be_dep_on_frame(result);
94 for (cnt = 1; cnt < v.ops; ++cnt) {
95 result = new_bd_arm_Or_imm(dbgi, block, result,
96 v.values[cnt], v.rors[cnt]);
103 * Create a DAG constructing a given Const.
105 * @param irn a Firm const
107 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
109 tarval *tv = get_Const_tarval(irn);
110 ir_mode *mode = get_tarval_mode(tv);
113 if (mode_is_reference(mode)) {
114 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
115 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
116 tv = tarval_convert_to(tv, mode_Iu);
118 value = get_tarval_long(tv);
119 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
123 * Create an And that will mask all upper bits
125 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
129 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
130 } else if (src_bits == 16) {
131 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
132 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
135 panic("zero extension only supported for 8 and 16 bits");
140 * Generate code for a sign extension.
142 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
145 int shift_width = 32 - src_bits;
146 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
147 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
151 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
154 int bits = get_mode_size_bits(orig_mode);
158 if (mode_is_signed(orig_mode)) {
159 return gen_sign_extension(dbgi, block, op, bits);
161 return gen_zero_extension(dbgi, block, op, bits);
166 * returns true if it is assured, that the upper bits of a node are "clean"
167 * which means for a 16 or 8 bit value, that the upper bits in the register
168 * are 0 for unsigned and a copy of the last significant bit for signed
171 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
173 (void) transformed_node;
180 * Transforms a Conv node.
182 * @return The created ia32 Conv node
184 static ir_node *gen_Conv(ir_node *node) {
185 ir_node *block = be_transform_node(get_nodes_block(node));
186 ir_node *op = get_Conv_op(node);
187 ir_node *new_op = be_transform_node(op);
188 ir_mode *src_mode = get_irn_mode(op);
189 ir_mode *dst_mode = get_irn_mode(node);
190 dbg_info *dbg = get_irn_dbg_info(node);
192 if (src_mode == dst_mode)
195 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
196 env_cg->have_fp_insn = 1;
198 if (USE_FPA(env_cg->isa)) {
199 if (mode_is_float(src_mode)) {
200 if (mode_is_float(dst_mode)) {
201 /* from float to float */
202 return new_bd_arm_fpaMvf(dbg, block, new_op, dst_mode);
205 /* from float to int */
206 return new_bd_arm_fpaFix(dbg, block, new_op, dst_mode);
210 /* from int to float */
211 return new_bd_arm_fpaFlt(dbg, block, new_op, dst_mode);
213 } else if (USE_VFP(env_cg->isa)) {
214 panic("VFP not supported yet");
217 panic("Softfloat not supported yet");
220 } else { /* complete in gp registers */
221 int src_bits = get_mode_size_bits(src_mode);
222 int dst_bits = get_mode_size_bits(dst_mode);
226 if (src_bits == dst_bits) {
227 /* kill unneccessary conv */
231 if (src_bits < dst_bits) {
239 if (upper_bits_clean(new_op, min_mode)) {
243 if (mode_is_signed(min_mode)) {
244 return gen_sign_extension(dbg, block, new_op, min_bits);
246 return gen_zero_extension(dbg, block, new_op, min_bits);
256 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
258 unsigned val, low_pos, high_pos;
263 val = get_tarval_long(get_Const_tarval(node));
275 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
277 So we determine the smallest even position with a bit set
278 and the highest even position with no bit set anymore.
279 If the difference between these 2 is <= 8, then we can encode the value
282 low_pos = ntz(val) & ~1u;
283 high_pos = (32-nlz(val)+1) & ~1u;
285 if (high_pos - low_pos <= 8) {
286 res->imm_8 = val >> low_pos;
287 res->rot = 32 - low_pos;
292 res->rot = 34 - high_pos;
293 val = val >> (32-res->rot) | val << (res->rot);
303 static int is_downconv(const ir_node *node)
311 /* we only want to skip the conv when we're the only user
312 * (not optimal but for now...)
314 if (get_irn_n_edges(node) > 1)
317 src_mode = get_irn_mode(get_Conv_op(node));
318 dest_mode = get_irn_mode(node);
320 mode_needs_gp_reg(src_mode) &&
321 mode_needs_gp_reg(dest_mode) &&
322 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
325 static ir_node *arm_skip_downconv(ir_node *node)
327 while (is_downconv(node))
328 node = get_Conv_op(node);
334 MATCH_COMMUTATIVE = 1 << 0,
335 MATCH_SIZE_NEUTRAL = 1 << 1,
338 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
339 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
341 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
342 new_binop_reg_func new_reg, new_binop_imm_func new_imm)
344 ir_node *block = be_transform_node(get_nodes_block(node));
345 ir_node *op1 = get_binop_left(node);
347 ir_node *op2 = get_binop_right(node);
349 dbg_info *dbgi = get_irn_dbg_info(node);
352 if (flags & MATCH_SIZE_NEUTRAL) {
353 op1 = arm_skip_downconv(op1);
354 op2 = arm_skip_downconv(op2);
356 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
359 if (try_encode_as_immediate(op2, &imm)) {
360 ir_node *new_op1 = be_transform_node(op1);
361 return new_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
363 new_op2 = be_transform_node(op2);
364 if ((flags & MATCH_COMMUTATIVE) && try_encode_as_immediate(op1, &imm)) {
365 return new_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
367 new_op1 = be_transform_node(op1);
369 return new_reg(dbgi, block, new_op1, new_op2);
373 * Creates an ARM Add.
375 * @return the created arm Add node
377 static ir_node *gen_Add(ir_node *node)
379 ir_mode *mode = get_irn_mode(node);
381 if (mode_is_float(mode)) {
382 ir_node *block = be_transform_node(get_nodes_block(node));
383 ir_node *op1 = get_Add_left(node);
384 ir_node *op2 = get_Add_right(node);
385 dbg_info *dbgi = get_irn_dbg_info(node);
386 ir_node *new_op1 = be_transform_node(op1);
387 ir_node *new_op2 = be_transform_node(op2);
388 env_cg->have_fp_insn = 1;
389 if (USE_FPA(env_cg->isa)) {
391 if (is_arm_fpaMvf_i(new_op1))
392 return new_bd_arm_fpaAdf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1));
393 if (is_arm_fpaMvf_i(new_op2))
394 return new_bd_arm_fpaAdf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2));
396 return new_bd_arm_fpaAdf(dbgi, block, new_op1, new_op2, mode);
397 } else if (USE_VFP(env_cg->isa)) {
398 assert(mode != mode_E && "IEEE Extended FP not supported");
399 panic("VFP not supported yet");
403 panic("Softfloat not supported yet");
409 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
411 new_op2 = get_irn_n(new_op1, 1);
412 new_op1 = get_irn_n(new_op1, 0);
414 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
416 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
418 new_op1 = get_irn_n(new_op2, 0);
419 new_op2 = get_irn_n(new_op2, 1);
421 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
425 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
426 new_bd_arm_Add_reg, new_bd_arm_Add_imm);
431 * Creates an ARM Mul.
433 * @return the created arm Mul node
435 static ir_node *gen_Mul(ir_node *node) {
436 ir_node *block = be_transform_node(get_nodes_block(node));
437 ir_node *op1 = get_Mul_left(node);
438 ir_node *new_op1 = be_transform_node(op1);
439 ir_node *op2 = get_Mul_right(node);
440 ir_node *new_op2 = be_transform_node(op2);
441 ir_mode *mode = get_irn_mode(node);
442 dbg_info *dbg = get_irn_dbg_info(node);
444 if (mode_is_float(mode)) {
445 env_cg->have_fp_insn = 1;
446 if (USE_FPA(env_cg->isa)) {
448 if (is_arm_Mov_i(new_op1))
449 return new_bd_arm_fpaMuf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
450 if (is_arm_Mov_i(new_op2))
451 return new_bd_arm_fpaMuf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
453 return new_bd_arm_fpaMuf(dbg, block, new_op1, new_op2, mode);
455 else if (USE_VFP(env_cg->isa)) {
456 assert(mode != mode_E && "IEEE Extended FP not supported");
457 panic("VFP not supported yet");
461 panic("Softfloat not supported yet");
465 assert(mode_is_data(mode));
466 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
470 * Creates an ARM floating point Div.
472 * @param env The transformation environment
473 * @return the created arm fDiv node
475 static ir_node *gen_Quot(ir_node *node) {
476 ir_node *block = be_transform_node(get_nodes_block(node));
477 ir_node *op1 = get_Quot_left(node);
478 ir_node *new_op1 = be_transform_node(op1);
479 ir_node *op2 = get_Quot_right(node);
480 ir_node *new_op2 = be_transform_node(op2);
481 ir_mode *mode = get_irn_mode(node);
482 dbg_info *dbg = get_irn_dbg_info(node);
484 assert(mode != mode_E && "IEEE Extended FP not supported");
486 env_cg->have_fp_insn = 1;
487 if (USE_FPA(env_cg->isa)) {
489 if (is_arm_Mov_i(new_op1))
490 return new_bd_arm_fpaRdf_i(dbg, block, new_op2, mode, get_arm_imm_value(new_op1));
491 if (is_arm_Mov_i(new_op2))
492 return new_bd_arm_fpaDvf_i(dbg, block, new_op1, mode, get_arm_imm_value(new_op2));
494 return new_bd_arm_fpaDvf(dbg, block, new_op1, new_op2, mode);
495 } else if (USE_VFP(env_cg->isa)) {
496 assert(mode != mode_E && "IEEE Extended FP not supported");
497 panic("VFP not supported yet");
500 panic("Softfloat not supported yet");
506 * Creates an ARM And.
508 * @return the created arm And node
510 static ir_node *gen_And(ir_node *node)
512 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
513 new_bd_arm_And_reg, new_bd_arm_And_imm);
517 * Creates an ARM Orr.
519 * @param env The transformation environment
520 * @return the created arm Or node
522 static ir_node *gen_Or(ir_node *node)
524 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
525 new_bd_arm_Or_reg, new_bd_arm_Or_imm);
529 * Creates an ARM Eor.
531 * @return the created arm Eor node
533 static ir_node *gen_Eor(ir_node *node)
535 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
536 new_bd_arm_Eor_reg, new_bd_arm_Eor_imm);
540 * Creates an ARM Sub.
542 * @return the created arm Sub node
544 static ir_node *gen_Sub(ir_node *node)
546 ir_node *block = be_transform_node(get_nodes_block(node));
547 ir_node *op1 = get_Sub_left(node);
548 ir_node *new_op1 = be_transform_node(op1);
549 ir_node *op2 = get_Sub_right(node);
550 ir_node *new_op2 = be_transform_node(op2);
551 ir_mode *mode = get_irn_mode(node);
552 dbg_info *dbgi = get_irn_dbg_info(node);
554 if (mode_is_float(mode)) {
555 env_cg->have_fp_insn = 1;
556 if (USE_FPA(env_cg->isa)) {
558 if (is_arm_Mov_i(new_op1))
559 return new_bd_arm_fpaRsf_i(dbgi, block, new_op2, mode, get_arm_imm_value(new_op1));
560 if (is_arm_Mov_i(new_op2))
561 return new_bd_arm_fpaSuf_i(dbgi, block, new_op1, mode, get_arm_imm_value(new_op2));
563 return new_bd_arm_fpaSuf(dbgi, block, new_op1, new_op2, mode);
564 } else if (USE_VFP(env_cg->isa)) {
565 assert(mode != mode_E && "IEEE Extended FP not supported");
566 panic("VFP not supported yet");
569 panic("Softfloat not supported yet");
573 return gen_int_binop(node, MATCH_SIZE_NEUTRAL,
574 new_bd_arm_Sub_reg, new_bd_arm_Sub_imm);
578 static ir_node *make_shift(ir_node *node, match_flags_t flags,
579 arm_shift_modifier shift_modifier)
581 ir_node *block = be_transform_node(get_nodes_block(node));
582 ir_node *op1 = get_binop_left(node);
583 ir_node *op2 = get_binop_right(node);
584 dbg_info *dbgi = get_irn_dbg_info(node);
588 if (flags & MATCH_SIZE_NEUTRAL) {
589 op1 = arm_skip_downconv(op1);
590 op2 = arm_skip_downconv(op2);
592 new_op1 = be_transform_node(op1);
593 new_op2 = be_transform_node(op2);
594 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2, shift_modifier);
598 * Creates an ARM Shl.
600 * @return the created ARM Shl node
602 static ir_node *gen_Shl(ir_node *node)
604 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
608 * Creates an ARM Shr.
610 * @return the created ARM Shr node
612 static ir_node *gen_Shr(ir_node *node)
614 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
618 * Creates an ARM Shrs.
620 * @return the created ARM Shrs node
622 static ir_node *gen_Shrs(ir_node *node)
624 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
628 * Creates an ARM Ror.
630 * @return the created ARM Ror node
632 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
634 ir_node *block = be_transform_node(get_nodes_block(node));
635 ir_node *new_op1 = be_transform_node(op1);
636 dbg_info *dbgi = get_irn_dbg_info(node);
637 ir_node *new_op2 = be_transform_node(op2);
639 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
644 * Creates an ARM Rol.
646 * @return the created ARM Rol node
648 * Note: there is no Rol on arm, we have to use Ror
650 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
652 ir_node *block = be_transform_node(get_nodes_block(node));
653 ir_node *new_op1 = be_transform_node(op1);
654 dbg_info *dbgi = get_irn_dbg_info(node);
655 ir_node *new_op2 = be_transform_node(op2);
657 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
658 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
663 * Creates an ARM ROR from a Firm Rotl.
665 * @return the created ARM Ror node
667 static ir_node *gen_Rotl(ir_node *node)
669 ir_node *rotate = NULL;
670 ir_node *op1 = get_Rotl_left(node);
671 ir_node *op2 = get_Rotl_right(node);
673 /* Firm has only RotL, so we are looking for a right (op2)
674 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
675 that means we can create a RotR. */
678 ir_node *right = get_Add_right(op2);
679 if (is_Const(right)) {
680 tarval *tv = get_Const_tarval(right);
681 ir_mode *mode = get_irn_mode(node);
682 long bits = get_mode_size_bits(mode);
683 ir_node *left = get_Add_left(op2);
685 if (is_Minus(left) &&
686 tarval_is_long(tv) &&
687 get_tarval_long(tv) == bits &&
689 rotate = gen_Ror(node, op1, get_Minus_op(left));
691 } else if (is_Sub(op2)) {
692 ir_node *left = get_Sub_left(op2);
693 if (is_Const(left)) {
694 tarval *tv = get_Const_tarval(left);
695 ir_mode *mode = get_irn_mode(node);
696 long bits = get_mode_size_bits(mode);
697 ir_node *right = get_Sub_right(op2);
699 if (tarval_is_long(tv) &&
700 get_tarval_long(tv) == bits &&
702 rotate = gen_Ror(node, op1, right);
704 } else if (is_Const(op2)) {
705 tarval *tv = get_Const_tarval(op2);
706 ir_mode *mode = get_irn_mode(node);
707 long bits = get_mode_size_bits(mode);
709 if (tarval_is_long(tv) && bits == 32) {
710 ir_node *block = be_transform_node(get_nodes_block(node));
711 ir_node *new_op1 = be_transform_node(op1);
712 dbg_info *dbgi = get_irn_dbg_info(node);
714 bits = (bits - get_tarval_long(tv)) & 31;
715 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
719 if (rotate == NULL) {
720 rotate = gen_Rol(node, op1, op2);
727 * Transforms a Not node.
729 * @return the created ARM Not node
731 static ir_node *gen_Not(ir_node *node)
733 ir_node *block = be_transform_node(get_nodes_block(node));
734 ir_node *op = get_Not_op(node);
735 ir_node *new_op = be_transform_node(op);
736 dbg_info *dbgi = get_irn_dbg_info(node);
738 /* TODO: we could do alot more here with all the Mvn variations */
740 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
744 * Transforms an Abs node.
746 * @param env The transformation environment
747 * @return the created ARM Abs node
749 static ir_node *gen_Abs(ir_node *node)
751 ir_node *block = be_transform_node(get_nodes_block(node));
752 ir_node *op = get_Abs_op(node);
753 ir_node *new_op = be_transform_node(op);
754 dbg_info *dbgi = get_irn_dbg_info(node);
755 ir_mode *mode = get_irn_mode(node);
757 if (mode_is_float(mode)) {
758 env_cg->have_fp_insn = 1;
759 if (USE_FPA(env_cg->isa))
760 return new_bd_arm_fpaAbs(dbgi, block, new_op, mode);
761 else if (USE_VFP(env_cg->isa)) {
762 assert(mode != mode_E && "IEEE Extended FP not supported");
763 panic("VFP not supported yet");
766 panic("Softfloat not supported yet");
769 assert(mode_is_data(mode));
770 return new_bd_arm_Abs(dbgi, block, new_op);
774 * Transforms a Minus node.
776 * @return the created ARM Minus node
778 static ir_node *gen_Minus(ir_node *node)
780 ir_node *block = be_transform_node(get_nodes_block(node));
781 ir_node *op = get_Minus_op(node);
782 ir_node *new_op = be_transform_node(op);
783 dbg_info *dbgi = get_irn_dbg_info(node);
784 ir_mode *mode = get_irn_mode(node);
786 if (mode_is_float(mode)) {
787 env_cg->have_fp_insn = 1;
788 if (USE_FPA(env_cg->isa))
789 return new_bd_arm_fpaMvf(dbgi, block, op, mode);
790 else if (USE_VFP(env_cg->isa)) {
791 assert(mode != mode_E && "IEEE Extended FP not supported");
792 panic("VFP not supported yet");
795 panic("Softfloat not supported yet");
798 assert(mode_is_data(mode));
799 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
805 * @return the created ARM Load node
807 static ir_node *gen_Load(ir_node *node) {
808 ir_node *block = be_transform_node(get_nodes_block(node));
809 ir_node *ptr = get_Load_ptr(node);
810 ir_node *new_ptr = be_transform_node(ptr);
811 ir_node *mem = get_Load_mem(node);
812 ir_node *new_mem = be_transform_node(mem);
813 ir_mode *mode = get_Load_mode(node);
814 dbg_info *dbgi = get_irn_dbg_info(node);
815 ir_node *new_load = NULL;
817 if (mode_is_float(mode)) {
818 env_cg->have_fp_insn = 1;
819 if (USE_FPA(env_cg->isa))
820 new_load = new_bd_arm_fpaLdf(dbgi, block, new_ptr, new_mem, mode);
821 else if (USE_VFP(env_cg->isa)) {
822 assert(mode != mode_E && "IEEE Extended FP not supported");
823 panic("VFP not supported yet");
825 panic("Softfloat not supported yet");
828 assert(mode_is_data(mode) && "unsupported mode for Load");
830 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
832 set_irn_pinned(new_load, get_irn_pinned(node));
834 /* check for special case: the loaded value might not be used */
835 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
836 /* add a result proj and a Keep to produce a pseudo use */
837 ir_node *proj = new_r_Proj(block, new_load, mode_Iu, pn_arm_Ldr_res);
838 be_new_Keep(block, 1, &proj);
845 * Transforms a Store.
847 * @return the created ARM Store node
849 static ir_node *gen_Store(ir_node *node)
851 ir_node *block = be_transform_node(get_nodes_block(node));
852 ir_node *ptr = get_Store_ptr(node);
853 ir_node *new_ptr = be_transform_node(ptr);
854 ir_node *mem = get_Store_mem(node);
855 ir_node *new_mem = be_transform_node(mem);
856 ir_node *val = get_Store_value(node);
857 ir_node *new_val = be_transform_node(val);
858 ir_mode *mode = get_irn_mode(val);
859 dbg_info *dbgi = get_irn_dbg_info(node);
860 ir_node *new_store = NULL;
862 if (mode_is_float(mode)) {
863 env_cg->have_fp_insn = 1;
864 if (USE_FPA(env_cg->isa))
865 new_store = new_bd_arm_fpaStf(dbgi, block, new_ptr, new_val,
867 else if (USE_VFP(env_cg->isa)) {
868 assert(mode != mode_E && "IEEE Extended FP not supported");
869 panic("VFP not supported yet");
871 panic("Softfloat not supported yet");
874 assert(mode_is_data(mode) && "unsupported mode for Store");
875 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
878 set_irn_pinned(new_store, get_irn_pinned(node));
882 static ir_node *gen_Jmp(ir_node *node)
884 ir_node *block = get_nodes_block(node);
885 ir_node *new_block = be_transform_node(block);
886 dbg_info *dbgi = get_irn_dbg_info(node);
888 return new_bd_arm_Jmp(dbgi, new_block);
891 static ir_node *gen_be_Call(ir_node *node)
893 ir_node *res = be_duplicate_node(node);
894 arch_irn_add_flags(res, arch_irn_flags_modify_flags);
899 static ir_node *gen_SwitchJmp(ir_node *node)
901 ir_node *block = be_transform_node(get_nodes_block(node));
902 ir_node *selector = get_Cond_selector(node);
903 dbg_info *dbgi = get_irn_dbg_info(node);
904 ir_node *new_op = be_transform_node(selector);
905 ir_node *const_graph;
909 const ir_edge_t *edge;
916 foreach_out_edge(node, edge) {
917 proj = get_edge_src_irn(edge);
918 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
920 pn = get_Proj_proj(proj);
922 min = pn<min ? pn : min;
923 max = pn>max ? pn : max;
926 n_projs = max - translation + 1;
928 foreach_out_edge(node, edge) {
929 proj = get_edge_src_irn(edge);
930 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
932 pn = get_Proj_proj(proj) - translation;
933 set_Proj_proj(proj, pn);
936 const_graph = create_const_graph_value(dbgi, block, translation);
937 sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
938 return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
941 static ir_node *gen_Cmp(ir_node *node)
943 ir_node *block = be_transform_node(get_nodes_block(node));
944 ir_node *op1 = get_Cmp_left(node);
945 ir_node *op2 = get_Cmp_right(node);
946 ir_mode *cmp_mode = get_irn_mode(op1);
947 dbg_info *dbgi = get_irn_dbg_info(node);
952 if (mode_is_float(cmp_mode)) {
953 /* TODO: revivie this code */
954 panic("FloatCmp NIY");
956 ir_node *new_op2 = be_transform_node(op2);
957 /* floating point compare */
958 pn_Cmp pnc = get_Proj_proj(selector);
960 if (pnc & pn_Cmp_Uo) {
961 /* check for unordered, need cmf */
962 return new_bd_arm_fpaCmfBra(dbgi, block, new_op1, new_op2, pnc);
964 /* Hmm: use need cmfe */
965 return new_bd_arm_fpaCmfeBra(dbgi, block, new_op1, new_op2, pnc);
969 assert(get_irn_mode(op2) == cmp_mode);
970 is_unsigned = !mode_is_signed(cmp_mode);
972 /* compare with 0 can be done with Tst */
973 if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) {
974 new_op1 = be_transform_node(op1);
975 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
976 return new_bd_arm_Tst_reg(dbgi, block, new_op1, new_op1, false,
979 if (is_Const(op1) && tarval_is_null(get_Const_tarval(op1))) {
980 new_op2 = be_transform_node(op2);
981 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
982 return new_bd_arm_Tst_reg(dbgi, block, new_op2, new_op2, true,
986 /* integer compare, TODO: use shifer_op in all its combinations */
987 new_op1 = be_transform_node(op1);
988 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
989 new_op2 = be_transform_node(op2);
990 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
991 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
998 * @return the created ARM Cond node
1000 static ir_node *gen_Cond(ir_node *node)
1002 ir_node *selector = get_Cond_selector(node);
1003 ir_mode *mode = get_irn_mode(selector);
1008 if (mode != mode_b) {
1009 return gen_SwitchJmp(node);
1011 assert(is_Proj(selector));
1013 block = be_transform_node(get_nodes_block(node));
1014 dbgi = get_irn_dbg_info(node);
1015 flag_node = be_transform_node(get_Proj_pred(selector));
1017 return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector));
1020 static tarval *fpa_imm[3][fpa_max];
1024 * Check, if a floating point tarval is an fpa immediate, i.e.
1025 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
1027 static int is_fpa_immediate(tarval *tv)
1029 ir_mode *mode = get_tarval_mode(tv);
1032 switch (get_mode_size_bits(mode)) {
1043 if (tarval_cmp(tv, get_tarval_null(mode)) & pn_Cmp_Lt) {
1044 tv = tarval_neg(tv);
1048 for (j = 0; j < fpa_max; ++j) {
1049 if (tv == fpa_imm[i][j])
1057 * Transforms a Const node.
1059 * @return The transformed ARM node.
1061 static ir_node *gen_Const(ir_node *node) {
1062 ir_node *block = be_transform_node(get_nodes_block(node));
1063 ir_mode *mode = get_irn_mode(node);
1064 dbg_info *dbg = get_irn_dbg_info(node);
1066 if (mode_is_float(mode)) {
1067 env_cg->have_fp_insn = 1;
1068 if (USE_FPA(env_cg->isa)) {
1069 tarval *tv = get_Const_tarval(node);
1071 int imm = is_fpa_immediate(tv);
1073 if (imm != fpa_max) {
1075 node = new_bd_arm_fpaMvf_i(dbg, block, mode, imm);
1077 node = new_bd_arm_fpaMnf_i(dbg, block, mode, -imm);
1081 node = new_bd_arm_fpaConst(dbg, block, tv);
1083 be_dep_on_frame(node);
1086 else if (USE_VFP(env_cg->isa)) {
1087 assert(mode != mode_E && "IEEE Extended FP not supported");
1088 panic("VFP not supported yet");
1091 panic("Softfloat not supported yet");
1094 return create_const_graph(node, block);
1098 * Transforms a SymConst node.
1100 * @return The transformed ARM node.
1102 static ir_node *gen_SymConst(ir_node *node)
1104 ir_node *block = be_transform_node(get_nodes_block(node));
1105 ir_entity *entity = get_SymConst_entity(node);
1106 dbg_info *dbgi = get_irn_dbg_info(node);
1109 new_node = new_bd_arm_SymConst(dbgi, block, entity);
1110 be_dep_on_frame(new_node);
1115 * Transforms a CopyB node.
1117 * @return The transformed ARM node.
1119 static ir_node *gen_CopyB(ir_node *node) {
1120 ir_node *block = be_transform_node(get_nodes_block(node));
1121 ir_node *src = get_CopyB_src(node);
1122 ir_node *new_src = be_transform_node(src);
1123 ir_node *dst = get_CopyB_dst(node);
1124 ir_node *new_dst = be_transform_node(dst);
1125 ir_node *mem = get_CopyB_mem(node);
1126 ir_node *new_mem = be_transform_node(mem);
1127 dbg_info *dbg = get_irn_dbg_info(node);
1128 int size = get_type_size_bytes(get_CopyB_type(node));
1132 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
1133 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
1135 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1136 new_bd_arm_EmptyReg(dbg, block),
1137 new_bd_arm_EmptyReg(dbg, block),
1138 new_bd_arm_EmptyReg(dbg, block),
1143 * Transforms a FrameAddr into an ARM Add.
1145 static ir_node *gen_be_FrameAddr(ir_node *node)
1147 ir_node *block = be_transform_node(get_nodes_block(node));
1148 ir_entity *ent = be_get_frame_entity(node);
1149 ir_node *fp = be_get_FrameAddr_frame(node);
1150 ir_node *new_fp = be_transform_node(fp);
1151 dbg_info *dbgi = get_irn_dbg_info(node);
1154 new_node = new_bd_arm_FrameAddr(dbgi, block, new_fp, ent);
1159 * Transform a be_AddSP into an arm_AddSP. Eat up const sizes.
1161 static ir_node *gen_be_AddSP(ir_node *node) {
1162 ir_node *block = be_transform_node(get_nodes_block(node));
1163 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
1164 ir_node *new_sz = be_transform_node(sz);
1165 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
1166 ir_node *new_sp = be_transform_node(sp);
1167 dbg_info *dbgi = get_irn_dbg_info(node);
1168 ir_node *nomem = new_NoMem();
1171 /* ARM stack grows in reverse direction, make a SubSPandCopy */
1172 new_op = new_bd_arm_SubSPandCopy(dbgi, block, new_sp, new_sz, nomem);
1178 * Transform a be_SubSP into an arm_SubSP. Eat up const sizes.
1180 static ir_node *gen_be_SubSP(ir_node *node) {
1181 ir_node *block = be_transform_node(get_nodes_block(node));
1182 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
1183 ir_node *new_sz = be_transform_node(sz);
1184 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
1185 ir_node *new_sp = be_transform_node(sp);
1186 dbg_info *dbgi = get_irn_dbg_info(node);
1187 ir_node *nomem = new_NoMem();
1190 /* ARM stack grows in reverse direction, make an AddSP */
1191 new_op = new_bd_arm_AddSP(dbgi, block, new_sp, new_sz, nomem);
1197 * Transform a be_Copy.
1199 static ir_node *gen_be_Copy(ir_node *node) {
1200 ir_node *result = be_duplicate_node(node);
1201 ir_mode *mode = get_irn_mode(result);
1203 if (mode_needs_gp_reg(mode)) {
1204 set_irn_mode(node, mode_Iu);
1211 * Transform a Proj from a Load.
1213 static ir_node *gen_Proj_Load(ir_node *node) {
1214 ir_node *block = be_transform_node(get_nodes_block(node));
1215 ir_node *load = get_Proj_pred(node);
1216 ir_node *new_load = be_transform_node(load);
1217 dbg_info *dbgi = get_irn_dbg_info(node);
1218 long proj = get_Proj_proj(node);
1220 /* renumber the proj */
1221 switch (get_arm_irn_opcode(new_load)) {
1223 /* handle all gp loads equal: they have the same proj numbers. */
1224 if (proj == pn_Load_res) {
1225 return new_rd_Proj(dbgi, block, new_load, mode_Iu, pn_arm_Ldr_res);
1226 } else if (proj == pn_Load_M) {
1227 return new_rd_Proj(dbgi, block, new_load, mode_M, pn_arm_Ldr_M);
1230 case iro_arm_fpaLdf:
1231 if (proj == pn_Load_res) {
1232 ir_mode *mode = get_Load_mode(load);
1233 return new_rd_Proj(dbgi, block, new_load, mode, pn_arm_fpaLdf_res);
1234 } else if (proj == pn_Load_M) {
1235 return new_rd_Proj(dbgi, block, new_load, mode_M, pn_arm_fpaLdf_M);
1241 panic("Unsupported Proj from Load");
1245 * Transform and renumber the Projs from a CopyB.
1247 static ir_node *gen_Proj_CopyB(ir_node *node) {
1248 ir_node *block = be_transform_node(get_nodes_block(node));
1249 ir_node *pred = get_Proj_pred(node);
1250 ir_node *new_pred = be_transform_node(pred);
1251 dbg_info *dbgi = get_irn_dbg_info(node);
1252 long proj = get_Proj_proj(node);
1255 case pn_CopyB_M_regular:
1256 if (is_arm_CopyB(new_pred)) {
1257 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_arm_CopyB_M);
1263 panic("Unsupported Proj from CopyB");
1267 * Transform and renumber the Projs from a Quot.
1269 static ir_node *gen_Proj_Quot(ir_node *node) {
1270 ir_node *block = be_transform_node(get_nodes_block(node));
1271 ir_node *pred = get_Proj_pred(node);
1272 ir_node *new_pred = be_transform_node(pred);
1273 dbg_info *dbgi = get_irn_dbg_info(node);
1274 ir_mode *mode = get_irn_mode(node);
1275 long proj = get_Proj_proj(node);
1279 if (is_arm_fpaDvf(new_pred)) {
1280 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_arm_fpaDvf_M);
1281 } else if (is_arm_fpaRdf(new_pred)) {
1282 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_arm_fpaRdf_M);
1283 } else if (is_arm_fpaFdv(new_pred)) {
1284 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_arm_fpaFdv_M);
1285 } else if (is_arm_fpaFrd(new_pred)) {
1286 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_arm_fpaFrd_M);
1290 if (is_arm_fpaDvf(new_pred)) {
1291 return new_rd_Proj(dbgi, block, new_pred, mode, pn_arm_fpaDvf_res);
1292 } else if (is_arm_fpaRdf(new_pred)) {
1293 return new_rd_Proj(dbgi, block, new_pred, mode, pn_arm_fpaRdf_res);
1294 } else if (is_arm_fpaFdv(new_pred)) {
1295 return new_rd_Proj(dbgi, block, new_pred, mode, pn_arm_fpaFdv_res);
1296 } else if (is_arm_fpaFrd(new_pred)) {
1297 return new_rd_Proj(dbgi, block, new_pred, mode, pn_arm_fpaFrd_res);
1303 panic("Unsupported Proj from Quot");
1307 * Transform the Projs of a be_AddSP.
1309 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
1310 ir_node *block = be_transform_node(get_nodes_block(node));
1311 ir_node *pred = get_Proj_pred(node);
1312 ir_node *new_pred = be_transform_node(pred);
1313 dbg_info *dbgi = get_irn_dbg_info(node);
1314 long proj = get_Proj_proj(node);
1316 if (proj == pn_be_AddSP_sp) {
1317 ir_node *res = new_rd_Proj(dbgi, block, new_pred, mode_Iu,
1318 pn_arm_SubSPandCopy_stack);
1319 arch_set_irn_register(res, &arm_gp_regs[REG_SP]);
1321 } else if(proj == pn_be_AddSP_res) {
1322 return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_arm_SubSPandCopy_addr);
1323 } else if (proj == pn_be_AddSP_M) {
1324 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_arm_SubSPandCopy_M);
1326 panic("Unsupported Proj from AddSP");
1330 * Transform the Projs of a be_SubSP.
1332 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
1333 ir_node *block = be_transform_node(get_nodes_block(node));
1334 ir_node *pred = get_Proj_pred(node);
1335 ir_node *new_pred = be_transform_node(pred);
1336 dbg_info *dbgi = get_irn_dbg_info(node);
1337 long proj = get_Proj_proj(node);
1339 if (proj == pn_be_SubSP_sp) {
1340 ir_node *res = new_rd_Proj(dbgi, block, new_pred, mode_Iu,
1341 pn_arm_AddSP_stack);
1342 arch_set_irn_register(res, &arm_gp_regs[REG_SP]);
1344 } else if (proj == pn_be_SubSP_M) {
1345 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_arm_AddSP_M);
1347 panic("Unsupported Proj from SubSP");
1351 * Transform the Projs from a Cmp.
1353 static ir_node *gen_Proj_Cmp(ir_node *node) {
1360 * Transform the Thread Local Storage Proj.
1362 static ir_node *gen_Proj_tls(ir_node *node) {
1363 ir_node *block = be_transform_node(get_nodes_block(node));
1364 dbg_info *dbgi = NULL;
1366 return new_bd_arm_LdTls(dbgi, block, mode_Iu);
1370 * Transform a Proj node.
1372 static ir_node *gen_Proj(ir_node *node) {
1373 ir_graph *irg = current_ir_graph;
1374 dbg_info *dbgi = get_irn_dbg_info(node);
1375 ir_node *pred = get_Proj_pred(node);
1376 long proj = get_Proj_proj(node);
1378 if (is_Store(pred)) {
1379 if (proj == pn_Store_M) {
1380 return be_transform_node(pred);
1382 panic("Unsupported Proj from Store");
1384 } else if (is_Load(pred)) {
1385 return gen_Proj_Load(node);
1386 } else if (is_CopyB(pred)) {
1387 return gen_Proj_CopyB(node);
1388 } else if (is_Quot(pred)) {
1389 return gen_Proj_Quot(node);
1390 } else if (be_is_SubSP(pred)) {
1391 return gen_Proj_be_SubSP(node);
1392 } else if (be_is_AddSP(pred)) {
1393 return gen_Proj_be_AddSP(node);
1394 } else if (is_Cmp(pred)) {
1395 return gen_Proj_Cmp(node);
1396 } else if (is_Start(pred)) {
1397 if (proj == pn_Start_X_initial_exec) {
1398 ir_node *block = get_nodes_block(pred);
1401 /* we exchange the ProjX with a jump */
1402 block = be_transform_node(block);
1403 jump = new_rd_Jmp(dbgi, block);
1406 if (node == get_irg_anchor(irg, anchor_tls)) {
1407 return gen_Proj_tls(node);
1410 ir_node *new_pred = be_transform_node(pred);
1411 ir_mode *mode = get_irn_mode(node);
1412 if (mode_needs_gp_reg(mode)) {
1413 ir_node *block = be_transform_node(get_nodes_block(node));
1414 ir_node *new_proj = new_r_Proj(block, new_pred, mode_Iu,
1415 get_Proj_proj(node));
1416 new_proj->node_nr = node->node_nr;
1421 return be_duplicate_node(node);
1424 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1426 static inline ir_node *create_const(ir_node **place,
1427 create_const_node_func func,
1428 const arch_register_t* reg)
1430 ir_node *block, *res;
1435 block = get_irg_start_block(env_cg->irg);
1436 res = func(NULL, block);
1437 arch_set_irn_register(res, reg);
1442 static ir_node *gen_Unknown(ir_node *node)
1444 ir_node *block = get_nodes_block(node);
1445 ir_node *new_block = be_transform_node(block);
1446 dbg_info *dbgi = get_irn_dbg_info(node);
1448 /* just produce a 0 */
1449 ir_mode *mode = get_irn_mode(node);
1450 if (mode_is_float(mode)) {
1451 tarval *tv = get_mode_null(mode);
1452 ir_node *node = new_bd_arm_fpaConst(dbgi, new_block, tv);
1453 be_dep_on_frame(node);
1455 } else if (mode_needs_gp_reg(mode)) {
1456 return create_const_graph_value(dbgi, new_block, 0);
1459 panic("Unexpected Unknown mode");
1463 * Change some phi modes
1465 static ir_node *gen_Phi(ir_node *node)
1467 const arch_register_req_t *req;
1468 ir_node *block = be_transform_node(get_nodes_block(node));
1469 ir_graph *irg = current_ir_graph;
1470 dbg_info *dbgi = get_irn_dbg_info(node);
1471 ir_mode *mode = get_irn_mode(node);
1474 if (mode_needs_gp_reg(mode)) {
1475 /* we shouldn't have any 64bit stuff around anymore */
1476 assert(get_mode_size_bits(mode) <= 32);
1477 /* all integer operations are on 32bit registers now */
1479 req = arm_reg_classes[CLASS_arm_gp].class_req;
1481 req = arch_no_register_req;
1484 /* phi nodes allow loops, so we use the old arguments for now
1485 * and fix this later */
1486 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
1487 get_irn_in(node) + 1);
1488 copy_node_attr(node, phi);
1489 be_duplicate_deps(node, phi);
1491 arch_set_out_register_req(phi, 0, req);
1493 be_enqueue_preds(node);
1499 * the BAD transformer.
1501 static ir_node *bad_transform(ir_node *irn)
1503 panic("ARM backend: Not implemented: %+F", irn);
1507 * Set a node emitter. Make it a bit more type safe.
1509 static void set_transformer(ir_op *op, be_transform_func arm_transform_func)
1511 op->ops.generic = (op_func)arm_transform_func;
1515 * Enters all transform functions into the generic pointer
1517 static void arm_register_transformers(void)
1519 /* first clear the generic function pointer for all ops */
1520 clear_irp_opcodes_generic_func();
1522 set_transformer(op_Abs, gen_Abs);
1523 set_transformer(op_Add, gen_Add);
1524 set_transformer(op_And, gen_And);
1525 set_transformer(op_be_AddSP, gen_be_AddSP);
1526 set_transformer(op_be_Call, gen_be_Call);
1527 set_transformer(op_be_Copy, gen_be_Copy);
1528 set_transformer(op_be_FrameAddr, gen_be_FrameAddr);
1529 set_transformer(op_be_SubSP, gen_be_SubSP);
1530 set_transformer(op_Cmp, gen_Cmp);
1531 set_transformer(op_Cond, gen_Cond);
1532 set_transformer(op_Const, gen_Const);
1533 set_transformer(op_Conv, gen_Conv);
1534 set_transformer(op_CopyB, gen_CopyB);
1535 set_transformer(op_Eor, gen_Eor);
1536 set_transformer(op_Jmp, gen_Jmp);
1537 set_transformer(op_Load, gen_Load);
1538 set_transformer(op_Minus, gen_Minus);
1539 set_transformer(op_Mul, gen_Mul);
1540 set_transformer(op_Not, gen_Not);
1541 set_transformer(op_Or, gen_Or);
1542 set_transformer(op_Phi, gen_Phi);
1543 set_transformer(op_Proj, gen_Proj);
1544 set_transformer(op_Quot, gen_Quot);
1545 set_transformer(op_Rotl, gen_Rotl);
1546 set_transformer(op_Shl, gen_Shl);
1547 set_transformer(op_Shr, gen_Shr);
1548 set_transformer(op_Shrs, gen_Shrs);
1549 set_transformer(op_Store, gen_Store);
1550 set_transformer(op_Sub, gen_Sub);
1551 set_transformer(op_SymConst, gen_SymConst);
1552 set_transformer(op_Unknown, gen_Unknown);
1554 set_transformer(op_ASM, bad_transform);
1555 set_transformer(op_Builtin, bad_transform);
1556 set_transformer(op_CallBegin, bad_transform);
1557 set_transformer(op_Cast, bad_transform);
1558 set_transformer(op_Confirm, bad_transform);
1559 set_transformer(op_DivMod, bad_transform);
1560 set_transformer(op_EndExcept, bad_transform);
1561 set_transformer(op_EndReg, bad_transform);
1562 set_transformer(op_Filter, bad_transform);
1563 set_transformer(op_Free, bad_transform);
1564 set_transformer(op_Id, bad_transform);
1565 set_transformer(op_InstOf, bad_transform);
1566 set_transformer(op_Mulh, bad_transform);
1567 set_transformer(op_Mux, bad_transform);
1568 set_transformer(op_Raise, bad_transform);
1569 set_transformer(op_Sel, bad_transform);
1570 set_transformer(op_Tuple, bad_transform);
1574 * Pre-transform all unknown nodes.
1576 static void arm_pretransform_node(void)
1578 arm_code_gen_t *cg = env_cg;
1580 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
1581 cg->unknown_fpa = be_pre_transform_node(cg->unknown_fpa);
1585 * Initialize fpa Immediate support.
1587 static void arm_init_fpa_immediate(void)
1589 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
1590 fpa_imm[0][fpa_null] = get_tarval_null(mode_F);
1591 fpa_imm[0][fpa_one] = get_tarval_one(mode_F);
1592 fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
1593 fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
1594 fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
1595 fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
1596 fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
1597 fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
1599 fpa_imm[1][fpa_null] = get_tarval_null(mode_D);
1600 fpa_imm[1][fpa_one] = get_tarval_one(mode_D);
1601 fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
1602 fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
1603 fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
1604 fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
1605 fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
1606 fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
1608 fpa_imm[2][fpa_null] = get_tarval_null(mode_E);
1609 fpa_imm[2][fpa_one] = get_tarval_one(mode_E);
1610 fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
1611 fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
1612 fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
1613 fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
1614 fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
1615 fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
1619 * Transform a Firm graph into an ARM graph.
1621 void arm_transform_graph(arm_code_gen_t *cg)
1623 static int imm_initialized = 0;
1625 if (! imm_initialized) {
1626 arm_init_fpa_immediate();
1627 imm_initialized = 1;
1629 arm_register_transformers();
1631 be_transform_graph(cg->birg, arm_pretransform_node);
1634 void arm_init_transform(void)
1636 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");