2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
41 #include "../benode.h"
43 #include "../beutil.h"
44 #include "../betranshlp.h"
45 #include "../beabihelper.h"
48 #include "bearch_arm_t.h"
49 #include "arm_nodes_attr.h"
50 #include "arm_transform.h"
51 #include "arm_optimize.h"
52 #include "arm_new_nodes.h"
53 #include "arm_map_regs.h"
54 #include "arm_cconv.h"
56 #include "gen_arm_regalloc_if.h"
60 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 /** hold the current code generator during transformation */
63 static arm_code_gen_t *env_cg;
65 static const arch_register_t *sp_reg = &arm_gp_regs[REG_SP];
66 static ir_mode *mode_gp;
67 static ir_mode *mode_fp;
68 static beabi_helper_env_t *abihelper;
69 static calling_convention_t *cconv = NULL;
71 static pmap *node_to_stack;
73 static bool mode_needs_gp_reg(ir_mode *mode)
75 return mode_is_int(mode) || mode_is_reference(mode);
79 * create firm graph for a constant
81 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
88 /* We only have 8 bit immediates. So we possibly have to combine several
89 * operations to construct the desired value.
91 * we can either create the value by adding bits to 0 or by removing bits
92 * from an register with all bits set. Try which alternative needs fewer
94 arm_gen_vals_from_word(value, &v);
95 arm_gen_vals_from_word(~value, &vn);
99 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
100 be_dep_on_frame(result);
102 for (cnt = 1; cnt < vn.ops; ++cnt) {
103 result = new_bd_arm_Bic_imm(dbgi, block, result,
104 vn.values[cnt], vn.rors[cnt]);
108 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
109 be_dep_on_frame(result);
111 for (cnt = 1; cnt < v.ops; ++cnt) {
112 result = new_bd_arm_Or_imm(dbgi, block, result,
113 v.values[cnt], v.rors[cnt]);
120 * Create a DAG constructing a given Const.
122 * @param irn a Firm const
124 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
126 tarval *tv = get_Const_tarval(irn);
127 ir_mode *mode = get_tarval_mode(tv);
130 if (mode_is_reference(mode)) {
131 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
132 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
133 tv = tarval_convert_to(tv, mode_Iu);
135 value = get_tarval_long(tv);
136 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
140 * Create an And that will zero out upper bits.
142 * @param dbgi debug info
143 * @param block the basic block
144 * @param op the original node
145 * param src_bits number of lower bits that will remain
147 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
151 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
152 } else if (src_bits == 16) {
153 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
154 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
157 panic("zero extension only supported for 8 and 16 bits");
162 * Generate code for a sign extension.
164 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
167 int shift_width = 32 - src_bits;
168 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
169 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
173 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
176 int bits = get_mode_size_bits(orig_mode);
180 if (mode_is_signed(orig_mode)) {
181 return gen_sign_extension(dbgi, block, op, bits);
183 return gen_zero_extension(dbgi, block, op, bits);
188 * returns true if it is assured, that the upper bits of a node are "clean"
189 * which means for a 16 or 8 bit value, that the upper bits in the register
190 * are 0 for unsigned and a copy of the last significant bit for signed
193 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
195 (void) transformed_node;
202 * Transforms a Conv node.
204 * @return The created ia32 Conv node
206 static ir_node *gen_Conv(ir_node *node)
208 ir_node *block = be_transform_node(get_nodes_block(node));
209 ir_node *op = get_Conv_op(node);
210 ir_node *new_op = be_transform_node(op);
211 ir_mode *src_mode = get_irn_mode(op);
212 ir_mode *dst_mode = get_irn_mode(node);
213 dbg_info *dbg = get_irn_dbg_info(node);
215 if (src_mode == dst_mode)
218 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
219 if (USE_FPA(env_cg->isa)) {
220 if (mode_is_float(src_mode)) {
221 if (mode_is_float(dst_mode)) {
222 /* from float to float */
223 return new_bd_arm_Mvf(dbg, block, new_op, dst_mode);
225 /* from float to int */
229 /* from int to float */
230 if (!mode_is_signed(src_mode)) {
233 return new_bd_arm_FltX(dbg, block, new_op, dst_mode);
236 } else if (USE_VFP(env_cg->isa)) {
237 panic("VFP not supported yet");
239 panic("Softfloat not supported yet");
241 } else { /* complete in gp registers */
242 int src_bits = get_mode_size_bits(src_mode);
243 int dst_bits = get_mode_size_bits(dst_mode);
247 if (src_bits == dst_bits) {
248 /* kill unnecessary conv */
252 if (src_bits < dst_bits) {
260 if (upper_bits_clean(new_op, min_mode)) {
264 if (mode_is_signed(min_mode)) {
265 return gen_sign_extension(dbg, block, new_op, min_bits);
267 return gen_zero_extension(dbg, block, new_op, min_bits);
277 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
279 unsigned val, low_pos, high_pos;
284 val = get_tarval_long(get_Const_tarval(node));
296 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
298 So we determine the smallest even position with a bit set
299 and the highest even position with no bit set anymore.
300 If the difference between these 2 is <= 8, then we can encode the value
303 low_pos = ntz(val) & ~1u;
304 high_pos = (32-nlz(val)+1) & ~1u;
306 if (high_pos - low_pos <= 8) {
307 res->imm_8 = val >> low_pos;
308 res->rot = 32 - low_pos;
313 res->rot = 34 - high_pos;
314 val = val >> (32-res->rot) | val << (res->rot);
324 static bool is_downconv(const ir_node *node)
332 /* we only want to skip the conv when we're the only user
333 * (not optimal but for now...)
335 if (get_irn_n_edges(node) > 1)
338 src_mode = get_irn_mode(get_Conv_op(node));
339 dest_mode = get_irn_mode(node);
341 mode_needs_gp_reg(src_mode) &&
342 mode_needs_gp_reg(dest_mode) &&
343 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
346 static ir_node *arm_skip_downconv(ir_node *node)
348 while (is_downconv(node))
349 node = get_Conv_op(node);
355 MATCH_COMMUTATIVE = 1 << 0, /**< commutative node */
356 MATCH_REVERSE = 1 << 1, /**< support reverse opcode */
357 MATCH_SIZE_NEUTRAL = 1 << 2,
358 MATCH_SKIP_NOT = 1 << 3, /**< skip Not on ONE input */
362 * possible binop constructors.
364 typedef struct arm_binop_factory_t {
365 /** normal reg op reg operation. */
366 ir_node *(*new_binop_reg)(dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
367 /** normal reg op imm operation. */
368 ir_node *(*new_binop_imm)(dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
369 /** barrel shifter reg op (reg shift reg operation. */
370 ir_node *(*new_binop_reg_shift_reg)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *shift, arm_shift_modifier_t shift_modifier);
371 /** barrel shifter reg op (reg shift imm operation. */
372 ir_node *(*new_binop_reg_shift_imm)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, arm_shift_modifier_t shift_modifier, unsigned shift_immediate);
373 } arm_binop_factory_t;
375 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
376 const arm_binop_factory_t *factory)
378 ir_node *block = be_transform_node(get_nodes_block(node));
379 ir_node *op1 = get_binop_left(node);
381 ir_node *op2 = get_binop_right(node);
383 dbg_info *dbgi = get_irn_dbg_info(node);
386 if (flags & MATCH_SKIP_NOT) {
388 op1 = get_Not_op(op1);
389 else if (is_Not(op2))
390 op2 = get_Not_op(op2);
392 panic("cannot execute MATCH_SKIP_NOT");
394 if (flags & MATCH_SIZE_NEUTRAL) {
395 op1 = arm_skip_downconv(op1);
396 op2 = arm_skip_downconv(op2);
398 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
401 if (try_encode_as_immediate(op2, &imm)) {
402 ir_node *new_op1 = be_transform_node(op1);
403 return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
405 new_op2 = be_transform_node(op2);
406 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && try_encode_as_immediate(op1, &imm)) {
407 if (flags & MATCH_REVERSE)
408 return factory[1].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
410 return factory[0].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
412 new_op1 = be_transform_node(op1);
414 /* check if we can fold in a Mov */
415 if (is_arm_Mov(new_op2)) {
416 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op2);
418 switch (attr->shift_modifier) {
420 case ARM_SHF_ASR_IMM:
421 case ARM_SHF_LSL_IMM:
422 case ARM_SHF_LSR_IMM:
423 case ARM_SHF_ROR_IMM:
424 if (factory->new_binop_reg_shift_imm) {
425 ir_node *mov_op = get_irn_n(new_op2, 0);
426 return factory->new_binop_reg_shift_imm(dbgi, block, new_op1, mov_op,
427 attr->shift_modifier, attr->shift_immediate);
431 case ARM_SHF_ASR_REG:
432 case ARM_SHF_LSL_REG:
433 case ARM_SHF_LSR_REG:
434 case ARM_SHF_ROR_REG:
435 if (factory->new_binop_reg_shift_reg) {
436 ir_node *mov_op = get_irn_n(new_op2, 0);
437 ir_node *mov_sft = get_irn_n(new_op2, 1);
438 return factory->new_binop_reg_shift_reg(dbgi, block, new_op1, mov_op, mov_sft,
439 attr->shift_modifier);
444 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && is_arm_Mov(new_op1)) {
445 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op1);
446 int idx = flags & MATCH_REVERSE ? 1 : 0;
448 switch (attr->shift_modifier) {
449 ir_node *mov_op, *mov_sft;
452 case ARM_SHF_ASR_IMM:
453 case ARM_SHF_LSL_IMM:
454 case ARM_SHF_LSR_IMM:
455 case ARM_SHF_ROR_IMM:
456 if (factory[idx].new_binop_reg_shift_imm) {
457 mov_op = get_irn_n(new_op1, 0);
458 return factory[idx].new_binop_reg_shift_imm(dbgi, block, new_op2, mov_op,
459 attr->shift_modifier, attr->shift_immediate);
463 case ARM_SHF_ASR_REG:
464 case ARM_SHF_LSL_REG:
465 case ARM_SHF_LSR_REG:
466 case ARM_SHF_ROR_REG:
467 if (factory[idx].new_binop_reg_shift_reg) {
468 mov_op = get_irn_n(new_op1, 0);
469 mov_sft = get_irn_n(new_op1, 1);
470 return factory[idx].new_binop_reg_shift_reg(dbgi, block, new_op2, mov_op, mov_sft,
471 attr->shift_modifier);
476 return factory->new_binop_reg(dbgi, block, new_op1, new_op2);
480 * Creates an ARM Add.
482 * @return the created arm Add node
484 static ir_node *gen_Add(ir_node *node)
486 static const arm_binop_factory_t add_factory = {
489 new_bd_arm_Add_reg_shift_reg,
490 new_bd_arm_Add_reg_shift_imm
493 ir_mode *mode = get_irn_mode(node);
495 if (mode_is_float(mode)) {
496 ir_node *block = be_transform_node(get_nodes_block(node));
497 ir_node *op1 = get_Add_left(node);
498 ir_node *op2 = get_Add_right(node);
499 dbg_info *dbgi = get_irn_dbg_info(node);
500 ir_node *new_op1 = be_transform_node(op1);
501 ir_node *new_op2 = be_transform_node(op2);
502 if (USE_FPA(env_cg->isa)) {
503 return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
504 } else if (USE_VFP(env_cg->isa)) {
505 assert(mode != mode_E && "IEEE Extended FP not supported");
506 panic("VFP not supported yet");
508 panic("Softfloat not supported yet");
513 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
515 new_op2 = get_irn_n(new_op1, 1);
516 new_op1 = get_irn_n(new_op1, 0);
518 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
520 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
522 new_op1 = get_irn_n(new_op2, 0);
523 new_op2 = get_irn_n(new_op2, 1);
525 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
529 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &add_factory);
534 * Creates an ARM Mul.
536 * @return the created arm Mul node
538 static ir_node *gen_Mul(ir_node *node)
540 ir_node *block = be_transform_node(get_nodes_block(node));
541 ir_node *op1 = get_Mul_left(node);
542 ir_node *new_op1 = be_transform_node(op1);
543 ir_node *op2 = get_Mul_right(node);
544 ir_node *new_op2 = be_transform_node(op2);
545 ir_mode *mode = get_irn_mode(node);
546 dbg_info *dbg = get_irn_dbg_info(node);
548 if (mode_is_float(mode)) {
549 if (USE_FPA(env_cg->isa)) {
550 return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
551 } else if (USE_VFP(env_cg->isa)) {
552 assert(mode != mode_E && "IEEE Extended FP not supported");
553 panic("VFP not supported yet");
555 panic("Softfloat not supported yet");
558 assert(mode_is_data(mode));
559 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
562 static ir_node *gen_Quot(ir_node *node)
564 ir_node *block = be_transform_node(get_nodes_block(node));
565 ir_node *op1 = get_Quot_left(node);
566 ir_node *new_op1 = be_transform_node(op1);
567 ir_node *op2 = get_Quot_right(node);
568 ir_node *new_op2 = be_transform_node(op2);
569 ir_mode *mode = get_irn_mode(node);
570 dbg_info *dbg = get_irn_dbg_info(node);
572 assert(mode != mode_E && "IEEE Extended FP not supported");
574 if (USE_FPA(env_cg->isa)) {
575 return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
576 } else if (USE_VFP(env_cg->isa)) {
577 assert(mode != mode_E && "IEEE Extended FP not supported");
578 panic("VFP not supported yet");
580 panic("Softfloat not supported yet");
584 static ir_node *gen_And(ir_node *node)
586 static const arm_binop_factory_t and_factory = {
589 new_bd_arm_And_reg_shift_reg,
590 new_bd_arm_And_reg_shift_imm
592 static const arm_binop_factory_t bic_factory = {
595 new_bd_arm_Bic_reg_shift_reg,
596 new_bd_arm_Bic_reg_shift_imm
599 /* check for and not */
600 ir_node *left = get_And_left(node);
601 ir_node *right = get_And_right(node);
603 if (is_Not(left) || is_Not(right)) {
604 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL | MATCH_SKIP_NOT,
608 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &and_factory);
611 static ir_node *gen_Or(ir_node *node)
613 static const arm_binop_factory_t or_factory = {
616 new_bd_arm_Or_reg_shift_reg,
617 new_bd_arm_Or_reg_shift_imm
620 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &or_factory);
623 static ir_node *gen_Eor(ir_node *node)
625 static const arm_binop_factory_t eor_factory = {
628 new_bd_arm_Eor_reg_shift_reg,
629 new_bd_arm_Eor_reg_shift_imm
632 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &eor_factory);
635 static ir_node *gen_Sub(ir_node *node)
637 static const arm_binop_factory_t sub_rsb_factory[2] = {
641 new_bd_arm_Sub_reg_shift_reg,
642 new_bd_arm_Sub_reg_shift_imm
647 new_bd_arm_Rsb_reg_shift_reg,
648 new_bd_arm_Rsb_reg_shift_imm
652 ir_node *block = be_transform_node(get_nodes_block(node));
653 ir_node *op1 = get_Sub_left(node);
654 ir_node *new_op1 = be_transform_node(op1);
655 ir_node *op2 = get_Sub_right(node);
656 ir_node *new_op2 = be_transform_node(op2);
657 ir_mode *mode = get_irn_mode(node);
658 dbg_info *dbgi = get_irn_dbg_info(node);
660 if (mode_is_float(mode)) {
661 if (USE_FPA(env_cg->isa)) {
662 return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
663 } else if (USE_VFP(env_cg->isa)) {
664 assert(mode != mode_E && "IEEE Extended FP not supported");
665 panic("VFP not supported yet");
667 panic("Softfloat not supported yet");
670 return gen_int_binop(node, MATCH_SIZE_NEUTRAL | MATCH_REVERSE, sub_rsb_factory);
675 * Checks if a given value can be used as an immediate for the given
678 static bool can_use_shift_constant(unsigned int val,
679 arm_shift_modifier_t modifier)
683 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
689 * generate an ARM shift instruction.
691 * @param node the node
692 * @param flags matching flags
693 * @param shift_modifier initial encoding of the desired shift operation
695 static ir_node *make_shift(ir_node *node, match_flags_t flags,
696 arm_shift_modifier_t shift_modifier)
698 ir_node *block = be_transform_node(get_nodes_block(node));
699 ir_node *op1 = get_binop_left(node);
700 ir_node *op2 = get_binop_right(node);
701 dbg_info *dbgi = get_irn_dbg_info(node);
705 if (flags & MATCH_SIZE_NEUTRAL) {
706 op1 = arm_skip_downconv(op1);
707 op2 = arm_skip_downconv(op2);
710 new_op1 = be_transform_node(op1);
712 tarval *tv = get_Const_tarval(op2);
713 unsigned int val = get_tarval_long(tv);
714 assert(tarval_is_long(tv));
715 if (can_use_shift_constant(val, shift_modifier)) {
716 switch (shift_modifier) {
717 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
718 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
719 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
720 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
721 default: panic("unexpected shift modifier");
723 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
724 shift_modifier, val);
728 new_op2 = be_transform_node(op2);
729 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
733 static ir_node *gen_Shl(ir_node *node)
735 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
738 static ir_node *gen_Shr(ir_node *node)
740 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
743 static ir_node *gen_Shrs(ir_node *node)
745 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
748 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
750 ir_node *block = be_transform_node(get_nodes_block(node));
751 ir_node *new_op1 = be_transform_node(op1);
752 dbg_info *dbgi = get_irn_dbg_info(node);
753 ir_node *new_op2 = be_transform_node(op2);
755 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
759 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
761 ir_node *block = be_transform_node(get_nodes_block(node));
762 ir_node *new_op1 = be_transform_node(op1);
763 dbg_info *dbgi = get_irn_dbg_info(node);
764 ir_node *new_op2 = be_transform_node(op2);
766 /* Note: there is no Rol on arm, we have to use Ror */
767 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
768 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
772 static ir_node *gen_Rotl(ir_node *node)
774 ir_node *rotate = NULL;
775 ir_node *op1 = get_Rotl_left(node);
776 ir_node *op2 = get_Rotl_right(node);
778 /* Firm has only RotL, so we are looking for a right (op2)
779 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
780 that means we can create a RotR. */
783 ir_node *right = get_Add_right(op2);
784 if (is_Const(right)) {
785 tarval *tv = get_Const_tarval(right);
786 ir_mode *mode = get_irn_mode(node);
787 long bits = get_mode_size_bits(mode);
788 ir_node *left = get_Add_left(op2);
790 if (is_Minus(left) &&
791 tarval_is_long(tv) &&
792 get_tarval_long(tv) == bits &&
794 rotate = gen_Ror(node, op1, get_Minus_op(left));
796 } else if (is_Sub(op2)) {
797 ir_node *left = get_Sub_left(op2);
798 if (is_Const(left)) {
799 tarval *tv = get_Const_tarval(left);
800 ir_mode *mode = get_irn_mode(node);
801 long bits = get_mode_size_bits(mode);
802 ir_node *right = get_Sub_right(op2);
804 if (tarval_is_long(tv) &&
805 get_tarval_long(tv) == bits &&
807 rotate = gen_Ror(node, op1, right);
809 } else if (is_Const(op2)) {
810 tarval *tv = get_Const_tarval(op2);
811 ir_mode *mode = get_irn_mode(node);
812 long bits = get_mode_size_bits(mode);
814 if (tarval_is_long(tv) && bits == 32) {
815 ir_node *block = be_transform_node(get_nodes_block(node));
816 ir_node *new_op1 = be_transform_node(op1);
817 dbg_info *dbgi = get_irn_dbg_info(node);
819 bits = (bits - get_tarval_long(tv)) & 31;
820 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
824 if (rotate == NULL) {
825 rotate = gen_Rol(node, op1, op2);
831 static ir_node *gen_Not(ir_node *node)
833 ir_node *block = be_transform_node(get_nodes_block(node));
834 ir_node *op = get_Not_op(node);
835 ir_node *new_op = be_transform_node(op);
836 dbg_info *dbgi = get_irn_dbg_info(node);
838 /* check if we can fold in a Mov */
839 if (is_arm_Mov(new_op)) {
840 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op);
842 switch (attr->shift_modifier) {
843 ir_node *mov_op, *mov_sft;
846 case ARM_SHF_ASR_IMM:
847 case ARM_SHF_LSL_IMM:
848 case ARM_SHF_LSR_IMM:
849 case ARM_SHF_ROR_IMM:
850 mov_op = get_irn_n(new_op, 0);
851 return new_bd_arm_Mvn_reg_shift_imm(dbgi, block, mov_op,
852 attr->shift_modifier, attr->shift_immediate);
854 case ARM_SHF_ASR_REG:
855 case ARM_SHF_LSL_REG:
856 case ARM_SHF_LSR_REG:
857 case ARM_SHF_ROR_REG:
858 mov_op = get_irn_n(new_op, 0);
859 mov_sft = get_irn_n(new_op, 1);
860 return new_bd_arm_Mvn_reg_shift_reg(dbgi, block, mov_op, mov_sft,
861 attr->shift_modifier);
865 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
868 static ir_node *gen_Minus(ir_node *node)
870 ir_node *block = be_transform_node(get_nodes_block(node));
871 ir_node *op = get_Minus_op(node);
872 ir_node *new_op = be_transform_node(op);
873 dbg_info *dbgi = get_irn_dbg_info(node);
874 ir_mode *mode = get_irn_mode(node);
876 if (mode_is_float(mode)) {
877 if (USE_FPA(env_cg->isa)) {
878 return new_bd_arm_Mvf(dbgi, block, op, mode);
879 } else if (USE_VFP(env_cg->isa)) {
880 assert(mode != mode_E && "IEEE Extended FP not supported");
881 panic("VFP not supported yet");
883 panic("Softfloat not supported yet");
886 assert(mode_is_data(mode));
887 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
890 static ir_node *gen_Load(ir_node *node)
892 ir_node *block = be_transform_node(get_nodes_block(node));
893 ir_node *ptr = get_Load_ptr(node);
894 ir_node *new_ptr = be_transform_node(ptr);
895 ir_node *mem = get_Load_mem(node);
896 ir_node *new_mem = be_transform_node(mem);
897 ir_mode *mode = get_Load_mode(node);
898 dbg_info *dbgi = get_irn_dbg_info(node);
899 ir_node *new_load = NULL;
901 if (mode_is_float(mode)) {
902 if (USE_FPA(env_cg->isa)) {
903 new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
905 } else if (USE_VFP(env_cg->isa)) {
906 assert(mode != mode_E && "IEEE Extended FP not supported");
907 panic("VFP not supported yet");
909 panic("Softfloat not supported yet");
912 assert(mode_is_data(mode) && "unsupported mode for Load");
914 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
916 set_irn_pinned(new_load, get_irn_pinned(node));
918 /* check for special case: the loaded value might not be used */
919 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
920 /* add a result proj and a Keep to produce a pseudo use */
921 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
922 be_new_Keep(block, 1, &proj);
928 static ir_node *gen_Store(ir_node *node)
930 ir_node *block = be_transform_node(get_nodes_block(node));
931 ir_node *ptr = get_Store_ptr(node);
932 ir_node *new_ptr = be_transform_node(ptr);
933 ir_node *mem = get_Store_mem(node);
934 ir_node *new_mem = be_transform_node(mem);
935 ir_node *val = get_Store_value(node);
936 ir_node *new_val = be_transform_node(val);
937 ir_mode *mode = get_irn_mode(val);
938 dbg_info *dbgi = get_irn_dbg_info(node);
939 ir_node *new_store = NULL;
941 if (mode_is_float(mode)) {
942 if (USE_FPA(env_cg->isa)) {
943 new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
944 new_mem, mode, NULL, 0, 0, false);
945 } else if (USE_VFP(env_cg->isa)) {
946 assert(mode != mode_E && "IEEE Extended FP not supported");
947 panic("VFP not supported yet");
949 panic("Softfloat not supported yet");
952 assert(mode_is_data(mode) && "unsupported mode for Store");
953 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
956 set_irn_pinned(new_store, get_irn_pinned(node));
960 static ir_node *gen_Jmp(ir_node *node)
962 ir_node *block = get_nodes_block(node);
963 ir_node *new_block = be_transform_node(block);
964 dbg_info *dbgi = get_irn_dbg_info(node);
966 return new_bd_arm_Jmp(dbgi, new_block);
969 static ir_node *gen_SwitchJmp(ir_node *node)
971 ir_node *block = be_transform_node(get_nodes_block(node));
972 ir_node *selector = get_Cond_selector(node);
973 dbg_info *dbgi = get_irn_dbg_info(node);
974 ir_node *new_op = be_transform_node(selector);
975 ir_node *const_graph;
979 const ir_edge_t *edge;
986 foreach_out_edge(node, edge) {
987 proj = get_edge_src_irn(edge);
988 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
990 pn = get_Proj_proj(proj);
992 min = pn<min ? pn : min;
993 max = pn>max ? pn : max;
996 n_projs = max - translation + 1;
998 foreach_out_edge(node, edge) {
999 proj = get_edge_src_irn(edge);
1000 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1002 pn = get_Proj_proj(proj) - translation;
1003 set_Proj_proj(proj, pn);
1006 const_graph = create_const_graph_value(dbgi, block, translation);
1007 sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
1008 return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
1011 static ir_node *gen_Cmp(ir_node *node)
1013 ir_node *block = be_transform_node(get_nodes_block(node));
1014 ir_node *op1 = get_Cmp_left(node);
1015 ir_node *op2 = get_Cmp_right(node);
1016 ir_mode *cmp_mode = get_irn_mode(op1);
1017 dbg_info *dbgi = get_irn_dbg_info(node);
1022 if (mode_is_float(cmp_mode)) {
1023 /* TODO: this is broken... */
1024 new_op1 = be_transform_node(op1);
1025 new_op2 = be_transform_node(op2);
1027 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
1029 panic("FloatCmp NIY");
1031 ir_node *new_op2 = be_transform_node(op2);
1032 /* floating point compare */
1033 pn_Cmp pnc = get_Proj_proj(selector);
1035 if (pnc & pn_Cmp_Uo) {
1036 /* check for unordered, need cmf */
1037 return new_bd_arm_CmfBra(dbgi, block, new_op1, new_op2, pnc);
1039 /* Hmm: use need cmfe */
1040 return new_bd_arm_CmfeBra(dbgi, block, new_op1, new_op2, pnc);
1044 assert(get_irn_mode(op2) == cmp_mode);
1045 is_unsigned = !mode_is_signed(cmp_mode);
1047 /* compare with 0 can be done with Tst */
1048 if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) {
1049 new_op1 = be_transform_node(op1);
1050 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
1051 return new_bd_arm_Tst_reg(dbgi, block, new_op1, new_op1, false,
1054 if (is_Const(op1) && tarval_is_null(get_Const_tarval(op1))) {
1055 new_op2 = be_transform_node(op2);
1056 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
1057 return new_bd_arm_Tst_reg(dbgi, block, new_op2, new_op2, true,
1061 /* integer compare, TODO: use shifter_op in all its combinations */
1062 new_op1 = be_transform_node(op1);
1063 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
1064 new_op2 = be_transform_node(op2);
1065 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
1066 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
1070 static ir_node *gen_Cond(ir_node *node)
1072 ir_node *selector = get_Cond_selector(node);
1073 ir_mode *mode = get_irn_mode(selector);
1078 if (mode != mode_b) {
1079 return gen_SwitchJmp(node);
1081 assert(is_Proj(selector));
1083 block = be_transform_node(get_nodes_block(node));
1084 dbgi = get_irn_dbg_info(node);
1085 flag_node = be_transform_node(get_Proj_pred(selector));
1087 return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector));
1090 static tarval *fpa_imm[3][fpa_max];
1094 * Check, if a floating point tarval is an fpa immediate, i.e.
1095 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
1097 static int is_fpa_immediate(tarval *tv)
1099 ir_mode *mode = get_tarval_mode(tv);
1102 switch (get_mode_size_bits(mode)) {
1113 if (tarval_is_negative(tv)) {
1114 tv = tarval_neg(tv);
1118 for (j = 0; j < fpa_max; ++j) {
1119 if (tv == fpa_imm[i][j])
1126 static ir_node *gen_Const(ir_node *node)
1128 ir_node *block = be_transform_node(get_nodes_block(node));
1129 ir_mode *mode = get_irn_mode(node);
1130 dbg_info *dbg = get_irn_dbg_info(node);
1132 if (mode_is_float(mode)) {
1133 if (USE_FPA(env_cg->isa)) {
1134 tarval *tv = get_Const_tarval(node);
1135 node = new_bd_arm_fConst(dbg, block, tv);
1136 be_dep_on_frame(node);
1138 } else if (USE_VFP(env_cg->isa)) {
1139 assert(mode != mode_E && "IEEE Extended FP not supported");
1140 panic("VFP not supported yet");
1142 panic("Softfloat not supported yet");
1145 return create_const_graph(node, block);
1148 static ir_node *gen_SymConst(ir_node *node)
1150 ir_node *block = be_transform_node(get_nodes_block(node));
1151 ir_entity *entity = get_SymConst_entity(node);
1152 dbg_info *dbgi = get_irn_dbg_info(node);
1155 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
1156 be_dep_on_frame(new_node);
1160 static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0,
1163 /* the good way to do this would be to use the stm (store multiple)
1164 * instructions, since our input is nearly always 2 consecutive 32bit
1166 ir_graph *irg = current_ir_graph;
1167 ir_node *stack = get_irg_frame(irg);
1168 ir_node *nomem = new_NoMem();
1169 ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp,
1171 ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp,
1173 ir_node *in[2] = { str0, str1 };
1174 ir_node *sync = new_r_Sync(block, 2, in);
1176 set_irn_pinned(str0, op_pin_state_floats);
1177 set_irn_pinned(str1, op_pin_state_floats);
1179 ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true);
1180 set_irn_pinned(ldf, op_pin_state_floats);
1182 return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1185 static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node)
1187 ir_graph *irg = current_ir_graph;
1188 ir_node *stack = get_irg_frame(irg);
1189 ir_node *nomem = new_NoMem();
1190 ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp,
1193 set_irn_pinned(str, op_pin_state_floats);
1195 ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true);
1196 set_irn_pinned(ldf, op_pin_state_floats);
1198 return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1201 static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node)
1203 ir_graph *irg = current_ir_graph;
1204 ir_node *stack = get_irg_frame(irg);
1205 ir_node *nomem = new_NoMem();
1206 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F,
1209 set_irn_pinned(stf, op_pin_state_floats);
1211 ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1212 set_irn_pinned(ldr, op_pin_state_floats);
1214 return new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1217 static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node,
1218 ir_node **out_value0, ir_node **out_value1)
1220 ir_graph *irg = current_ir_graph;
1221 ir_node *stack = get_irg_frame(irg);
1222 ir_node *nomem = new_NoMem();
1223 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D,
1225 ir_node *ldr0, *ldr1;
1226 set_irn_pinned(stf, op_pin_state_floats);
1228 ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1229 set_irn_pinned(ldr0, op_pin_state_floats);
1230 ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true);
1231 set_irn_pinned(ldr1, op_pin_state_floats);
1233 *out_value0 = new_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
1234 *out_value1 = new_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
1237 static ir_node *gen_CopyB(ir_node *node)
1239 ir_node *block = be_transform_node(get_nodes_block(node));
1240 ir_node *src = get_CopyB_src(node);
1241 ir_node *new_src = be_transform_node(src);
1242 ir_node *dst = get_CopyB_dst(node);
1243 ir_node *new_dst = be_transform_node(dst);
1244 ir_node *mem = get_CopyB_mem(node);
1245 ir_node *new_mem = be_transform_node(mem);
1246 dbg_info *dbg = get_irn_dbg_info(node);
1247 int size = get_type_size_bytes(get_CopyB_type(node));
1251 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
1252 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
1254 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1255 new_bd_arm_EmptyReg(dbg, block),
1256 new_bd_arm_EmptyReg(dbg, block),
1257 new_bd_arm_EmptyReg(dbg, block),
1261 static ir_node *gen_Proj_Load(ir_node *node)
1263 ir_node *load = get_Proj_pred(node);
1264 ir_node *new_load = be_transform_node(load);
1265 dbg_info *dbgi = get_irn_dbg_info(node);
1266 long proj = get_Proj_proj(node);
1268 /* renumber the proj */
1269 switch (get_arm_irn_opcode(new_load)) {
1271 /* handle all gp loads equal: they have the same proj numbers. */
1272 if (proj == pn_Load_res) {
1273 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1274 } else if (proj == pn_Load_M) {
1275 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1279 if (proj == pn_Load_res) {
1280 ir_mode *mode = get_Load_mode(load);
1281 return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res);
1282 } else if (proj == pn_Load_M) {
1283 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M);
1289 panic("Unsupported Proj from Load");
1292 static ir_node *gen_Proj_CopyB(ir_node *node)
1294 ir_node *pred = get_Proj_pred(node);
1295 ir_node *new_pred = be_transform_node(pred);
1296 dbg_info *dbgi = get_irn_dbg_info(node);
1297 long proj = get_Proj_proj(node);
1301 if (is_arm_CopyB(new_pred)) {
1302 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1308 panic("Unsupported Proj from CopyB");
1311 static ir_node *gen_Proj_Quot(ir_node *node)
1313 ir_node *pred = get_Proj_pred(node);
1314 ir_node *new_pred = be_transform_node(pred);
1315 dbg_info *dbgi = get_irn_dbg_info(node);
1316 ir_mode *mode = get_irn_mode(node);
1317 long proj = get_Proj_proj(node);
1321 if (is_arm_Dvf(new_pred)) {
1322 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
1326 if (is_arm_Dvf(new_pred)) {
1327 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
1333 panic("Unsupported Proj from Quot");
1337 * Transform the Projs from a Cmp.
1339 static ir_node *gen_Proj_Cmp(ir_node *node)
1342 /* we should only be here in case of a Mux node */
1346 static ir_node *gen_Proj_Start(ir_node *node)
1348 ir_node *block = get_nodes_block(node);
1349 ir_node *new_block = be_transform_node(block);
1350 ir_node *barrier = be_transform_node(get_Proj_pred(node));
1351 long proj = get_Proj_proj(node);
1353 switch ((pn_Start) proj) {
1354 case pn_Start_X_initial_exec:
1355 /* we exchange the ProjX with a jump */
1356 return new_bd_arm_Jmp(NULL, new_block);
1359 return new_r_Proj(barrier, mode_M, 0);
1361 case pn_Start_T_args:
1364 case pn_Start_P_frame_base:
1365 return be_prolog_get_reg_value(abihelper, sp_reg);
1367 case pn_Start_P_tls:
1373 panic("unexpected start proj: %ld\n", proj);
1376 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1378 long pn = get_Proj_proj(node);
1379 ir_node *block = get_nodes_block(node);
1380 ir_node *new_block = be_transform_node(block);
1381 ir_entity *entity = get_irg_entity(current_ir_graph);
1382 ir_type *method_type = get_entity_type(entity);
1383 ir_type *param_type = get_method_param_type(method_type, pn);
1384 const reg_or_stackslot_t *param;
1386 /* Proj->Proj->Start must be a method argument */
1387 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1389 param = &cconv->parameters[pn];
1391 if (param->reg0 != NULL) {
1392 /* argument transmitted in register */
1393 ir_mode *mode = get_type_mode(param_type);
1394 ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0);
1396 if (mode_is_float(mode)) {
1397 ir_node *value1 = NULL;
1399 if (param->reg1 != NULL) {
1400 value1 = be_prolog_get_reg_value(abihelper, param->reg1);
1401 } else if (param->entity != NULL) {
1402 ir_graph *irg = get_irn_irg(node);
1403 ir_node *fp = get_irg_frame(irg);
1404 ir_node *mem = be_prolog_get_memory(abihelper);
1405 ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem,
1406 mode_gp, param->entity,
1408 value1 = new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1411 /* convert integer value to float */
1412 if (value1 == NULL) {
1413 value = int_to_float(NULL, new_block, value);
1415 value = ints_to_double(NULL, new_block, value, value1);
1420 /* argument transmitted on stack */
1421 ir_graph *irg = get_irn_irg(node);
1422 ir_node *fp = get_irg_frame(irg);
1423 ir_node *mem = be_prolog_get_memory(abihelper);
1424 ir_mode *mode = get_type_mode(param->type);
1428 if (mode_is_float(mode)) {
1429 load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode,
1430 param->entity, 0, 0, true);
1431 value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res);
1433 load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1434 param->entity, 0, 0, true);
1435 value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1437 set_irn_pinned(load, op_pin_state_floats);
1444 * Finds number of output value of a mode_T node which is constrained to
1445 * a single specific register.
1447 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1449 int n_outs = arch_irn_get_n_outs(node);
1452 for (o = 0; o < n_outs; ++o) {
1453 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1454 if (req == reg->single_req)
1460 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1462 long pn = get_Proj_proj(node);
1463 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1464 ir_node *new_call = be_transform_node(call);
1465 ir_type *function_type = get_Call_type(call);
1466 calling_convention_t *cconv = arm_decide_calling_convention(function_type);
1467 const reg_or_stackslot_t *res = &cconv->results[pn];
1471 /* TODO 64bit modes */
1472 assert(res->reg0 != NULL && res->reg1 == NULL);
1473 regn = find_out_for_reg(new_call, res->reg0);
1475 panic("Internal error in calling convention for return %+F", node);
1477 mode = res->reg0->reg_class->mode;
1479 arm_free_calling_convention(cconv);
1481 return new_r_Proj(new_call, mode, regn);
1484 static ir_node *gen_Proj_Call(ir_node *node)
1486 long pn = get_Proj_proj(node);
1487 ir_node *call = get_Proj_pred(node);
1488 ir_node *new_call = be_transform_node(call);
1490 switch ((pn_Call) pn) {
1492 return new_r_Proj(new_call, mode_M, 0);
1493 case pn_Call_X_regular:
1494 case pn_Call_X_except:
1495 case pn_Call_T_result:
1496 case pn_Call_P_value_res_base:
1500 panic("Unexpected Call proj %ld\n", pn);
1504 * Transform a Proj node.
1506 static ir_node *gen_Proj(ir_node *node)
1508 ir_node *pred = get_Proj_pred(node);
1509 long proj = get_Proj_proj(node);
1511 switch (get_irn_opcode(pred)) {
1513 if (proj == pn_Store_M) {
1514 return be_transform_node(pred);
1516 panic("Unsupported Proj from Store");
1519 return gen_Proj_Load(node);
1521 return gen_Proj_Call(node);
1523 return gen_Proj_CopyB(node);
1525 return gen_Proj_Quot(node);
1527 return gen_Proj_Cmp(node);
1529 return gen_Proj_Start(node);
1532 return be_duplicate_node(node);
1534 ir_node *pred_pred = get_Proj_pred(pred);
1535 if (is_Call(pred_pred)) {
1536 return gen_Proj_Proj_Call(node);
1537 } else if (is_Start(pred_pred)) {
1538 return gen_Proj_Proj_Start(node);
1543 panic("code selection didn't expect Proj after %+F\n", pred);
1547 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1549 static inline ir_node *create_const(ir_node **place,
1550 create_const_node_func func,
1551 const arch_register_t* reg)
1553 ir_node *block, *res;
1558 block = get_irg_start_block(env_cg->irg);
1559 res = func(NULL, block);
1560 arch_set_irn_register(res, reg);
1565 static ir_node *gen_Unknown(ir_node *node)
1567 ir_node *block = get_nodes_block(node);
1568 ir_node *new_block = be_transform_node(block);
1569 dbg_info *dbgi = get_irn_dbg_info(node);
1571 /* just produce a 0 */
1572 ir_mode *mode = get_irn_mode(node);
1573 if (mode_is_float(mode)) {
1574 tarval *tv = get_mode_null(mode);
1575 ir_node *node = new_bd_arm_fConst(dbgi, new_block, tv);
1576 be_dep_on_frame(node);
1578 } else if (mode_needs_gp_reg(mode)) {
1579 return create_const_graph_value(dbgi, new_block, 0);
1582 panic("Unexpected Unknown mode");
1586 * Produces the type which sits between the stack args and the locals on the
1587 * stack. It will contain the return address and space to store the old base
1589 * @return The Firm type modeling the ABI between type.
1591 static ir_type *arm_get_between_type(void)
1593 static ir_type *between_type = NULL;
1595 if (between_type == NULL) {
1596 between_type = new_type_class(new_id_from_str("arm_between_type"));
1597 set_type_size_bytes(between_type, 0);
1600 return between_type;
1603 static void create_stacklayout(ir_graph *irg)
1605 ir_entity *entity = get_irg_entity(irg);
1606 ir_type *function_type = get_entity_type(entity);
1607 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1612 /* calling conventions must be decided by now */
1613 assert(cconv != NULL);
1615 /* construct argument type */
1616 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1617 n_params = get_method_n_params(function_type);
1618 for (p = 0; p < n_params; ++p) {
1619 reg_or_stackslot_t *param = &cconv->parameters[p];
1623 if (param->type == NULL)
1626 snprintf(buf, sizeof(buf), "param_%d", p);
1627 id = new_id_from_str(buf);
1628 param->entity = new_entity(arg_type, id, param->type);
1629 set_entity_offset(param->entity, param->offset);
1632 /* TODO: what about external functions? we don't know most of the stack
1633 * layout for them. And probably don't need all of this... */
1634 memset(layout, 0, sizeof(*layout));
1636 layout->frame_type = get_irg_frame_type(irg);
1637 layout->between_type = arm_get_between_type();
1638 layout->arg_type = arg_type;
1639 layout->param_map = NULL; /* TODO */
1640 layout->initial_offset = 0;
1641 layout->initial_bias = 0;
1642 layout->stack_dir = -1;
1643 layout->sp_relative = true;
1645 assert(N_FRAME_TYPES == 3);
1646 layout->order[0] = layout->frame_type;
1647 layout->order[1] = layout->between_type;
1648 layout->order[2] = layout->arg_type;
1652 * transform the start node to the prolog code + initial barrier
1654 static ir_node *gen_Start(ir_node *node)
1656 ir_graph *irg = get_irn_irg(node);
1657 ir_entity *entity = get_irg_entity(irg);
1658 ir_type *function_type = get_entity_type(entity);
1659 ir_node *block = get_nodes_block(node);
1660 ir_node *new_block = be_transform_node(block);
1661 dbg_info *dbgi = get_irn_dbg_info(node);
1668 /* stackpointer is important at function prolog */
1669 be_prolog_add_reg(abihelper, sp_reg,
1670 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1671 /* function parameters in registers */
1672 for (i = 0; i < get_method_n_params(function_type); ++i) {
1673 const reg_or_stackslot_t *param = &cconv->parameters[i];
1674 if (param->reg0 != NULL)
1675 be_prolog_add_reg(abihelper, param->reg0, 0);
1676 if (param->reg1 != NULL)
1677 be_prolog_add_reg(abihelper, param->reg1, 0);
1679 /* announce that we need the values of the callee save regs */
1680 for (i = 0; i < (int) (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
1681 be_prolog_add_reg(abihelper, callee_saves[i], 0);
1684 start = be_prolog_create_start(abihelper, dbgi, new_block);
1685 sp = be_prolog_get_reg_value(abihelper, sp_reg);
1686 incsp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
1687 be_prolog_set_reg_value(abihelper, sp_reg, incsp);
1688 barrier = be_prolog_create_barrier(abihelper, new_block);
1693 static ir_node *get_stack_pointer_for(ir_node *node)
1695 /* get predecessor in stack_order list */
1696 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1697 ir_node *stack_pred_transformed;
1700 if (stack_pred == NULL) {
1701 /* first stack user in the current block. We can simply use the
1702 * initial sp_proj for it */
1703 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1707 stack_pred_transformed = be_transform_node(stack_pred);
1708 stack = pmap_get(node_to_stack, stack_pred);
1709 if (stack == NULL) {
1710 return get_stack_pointer_for(stack_pred);
1717 * transform a Return node into epilogue code + return statement
1719 static ir_node *gen_Return(ir_node *node)
1721 ir_node *block = get_nodes_block(node);
1722 ir_node *new_block = be_transform_node(block);
1723 dbg_info *dbgi = get_irn_dbg_info(node);
1724 ir_node *mem = get_Return_mem(node);
1725 ir_node *new_mem = be_transform_node(mem);
1726 int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
1727 ir_node *sp_proj = get_stack_pointer_for(node);
1728 int n_res = get_Return_n_ress(node);
1733 be_epilog_begin(abihelper);
1734 be_epilog_set_memory(abihelper, new_mem);
1735 /* connect stack pointer with initial stack pointer. fix_stack phase
1736 will later serialize all stack pointer adjusting nodes */
1737 be_epilog_add_reg(abihelper, sp_reg,
1738 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1742 for (i = 0; i < n_res; ++i) {
1743 ir_node *res_value = get_Return_res(node, i);
1744 ir_node *new_res_value = be_transform_node(res_value);
1745 const reg_or_stackslot_t *slot = &cconv->results[i];
1746 const arch_register_t *reg = slot->reg0;
1747 assert(slot->reg1 == NULL);
1748 be_epilog_add_reg(abihelper, reg, 0, new_res_value);
1751 /* connect callee saves with their values at the function begin */
1752 for (i = 0; i < n_callee_saves; ++i) {
1753 const arch_register_t *reg = callee_saves[i];
1754 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1755 be_epilog_add_reg(abihelper, reg, 0, value);
1758 /* create the barrier before the epilog code */
1759 be_epilog_create_barrier(abihelper, new_block);
1761 /* epilog code: an incsp */
1762 sp_proj = be_epilog_get_reg_value(abihelper, sp_reg);
1763 incsp = be_new_IncSP(sp_reg, new_block, sp_proj,
1764 BE_STACK_FRAME_SIZE_SHRINK, 0);
1765 be_epilog_set_reg_value(abihelper, sp_reg, incsp);
1767 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1773 static ir_node *gen_Call(ir_node *node)
1775 ir_graph *irg = get_irn_irg(node);
1776 ir_node *callee = get_Call_ptr(node);
1777 ir_node *block = get_nodes_block(node);
1778 ir_node *new_block = be_transform_node(block);
1779 ir_node *mem = get_Call_mem(node);
1780 ir_node *new_mem = be_transform_node(mem);
1781 dbg_info *dbgi = get_irn_dbg_info(node);
1782 ir_type *type = get_Call_type(node);
1783 calling_convention_t *cconv = arm_decide_calling_convention(type);
1784 int n_params = get_Call_n_params(node);
1785 int n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
1786 /* max inputs: memory, callee, register arguments */
1787 int max_inputs = 2 + n_param_regs;
1788 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1789 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1790 struct obstack *obst = be_get_be_obst(irg);
1791 const arch_register_req_t **in_req
1792 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1796 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1797 ir_entity *entity = NULL;
1798 ir_node *incsp = NULL;
1805 assert(n_params == get_method_n_params(type));
1807 /* construct arguments */
1810 in_req[in_arity] = arch_no_register_req;
1814 for (p = 0; p < n_params; ++p) {
1815 ir_node *value = get_Call_param(node, p);
1816 ir_node *new_value = be_transform_node(value);
1817 ir_node *new_value1 = NULL;
1818 const reg_or_stackslot_t *param = &cconv->parameters[p];
1819 ir_type *param_type = get_method_param_type(type, p);
1820 ir_mode *mode = get_type_mode(param_type);
1823 if (mode_is_float(mode) && param->reg0 != NULL) {
1824 unsigned size_bits = get_mode_size_bits(mode);
1825 if (size_bits == 64) {
1826 double_to_ints(dbgi, new_block, new_value, &new_value,
1829 assert(size_bits == 32);
1830 new_value = float_to_int(dbgi, new_block, new_value);
1834 /* put value into registers */
1835 if (param->reg0 != NULL) {
1836 in[in_arity] = new_value;
1837 in_req[in_arity] = param->reg0->single_req;
1839 if (new_value1 == NULL)
1842 if (param->reg1 != NULL) {
1843 assert(new_value1 != NULL);
1844 in[in_arity] = new_value1;
1845 in_req[in_arity] = param->reg1->single_req;
1850 /* we need a store if we're here */
1851 if (new_value1 != NULL) {
1852 new_value = new_value1;
1856 /* create a parameter frame if necessary */
1857 if (incsp == NULL) {
1858 ir_node *new_frame = get_stack_pointer_for(node);
1859 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1860 cconv->param_stack_size, 1);
1862 if (mode_is_float(mode)) {
1863 str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem,
1864 mode, NULL, 0, param->offset, true);
1866 str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem,
1867 mode, NULL, 0, param->offset, true);
1869 sync_ins[sync_arity++] = str;
1871 assert(in_arity <= max_inputs);
1873 /* construct memory input */
1874 if (sync_arity == 0) {
1875 in[mem_pos] = new_mem;
1876 } else if (sync_arity == 1) {
1877 in[mem_pos] = sync_ins[0];
1879 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1882 /* TODO: use a generic symconst matcher here */
1883 if (is_SymConst(callee)) {
1884 entity = get_SymConst_entity(callee);
1886 /* TODO: finish load matcher here */
1889 if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) {
1890 ir_node *load = get_Proj_pred(callee);
1891 ir_node *ptr = get_Load_ptr(load);
1892 ir_node *new_ptr = be_transform_node(ptr);
1893 ir_node *mem = get_Load_mem(load);
1894 ir_node *new_mem = be_transform_node(mem);
1895 ir_mode *mode = get_Load_mode(node);
1899 in[in_arity] = be_transform_node(callee);
1900 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1909 out_arity = 1 + n_caller_saves;
1911 if (entity != NULL) {
1912 /* TODO: use a generic symconst matcher here
1913 * so we can also handle entity+offset, etc. */
1914 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1917 * - use a proper shifter_operand matcher
1918 * - we could also use LinkLdrPC
1920 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1924 if (incsp != NULL) {
1925 /* IncSP to destroy the call stackframe */
1926 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
1928 /* if we are the last IncSP producer in a block then we have to keep
1930 * Note: This here keeps all producers which is more than necessary */
1931 add_irn_dep(incsp, res);
1934 pmap_insert(node_to_stack, node, incsp);
1937 set_arm_in_req_all(res, in_req);
1939 /* create output register reqs */
1940 arch_set_out_register_req(res, 0, arch_no_register_req);
1941 for (o = 0; o < n_caller_saves; ++o) {
1942 const arch_register_t *reg = caller_saves[o];
1943 arch_set_out_register_req(res, o+1, reg->single_req);
1946 /* copy pinned attribute */
1947 set_irn_pinned(res, get_irn_pinned(node));
1949 arm_free_calling_convention(cconv);
1953 static ir_node *gen_Sel(ir_node *node)
1955 dbg_info *dbgi = get_irn_dbg_info(node);
1956 ir_node *block = get_nodes_block(node);
1957 ir_node *new_block = be_transform_node(block);
1958 ir_node *ptr = get_Sel_ptr(node);
1959 ir_node *new_ptr = be_transform_node(ptr);
1960 ir_entity *entity = get_Sel_entity(node);
1962 /* must be the frame pointer all other sels must have been lowered
1964 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1965 /* we should not have value types from parameters anymore - they should be
1967 assert(get_entity_owner(entity) !=
1968 get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
1970 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1974 * Change some phi modes
1976 static ir_node *gen_Phi(ir_node *node)
1978 const arch_register_req_t *req;
1979 ir_node *block = be_transform_node(get_nodes_block(node));
1980 ir_graph *irg = current_ir_graph;
1981 dbg_info *dbgi = get_irn_dbg_info(node);
1982 ir_mode *mode = get_irn_mode(node);
1985 if (mode_needs_gp_reg(mode)) {
1986 /* we shouldn't have any 64bit stuff around anymore */
1987 assert(get_mode_size_bits(mode) <= 32);
1988 /* all integer operations are on 32bit registers now */
1990 req = arm_reg_classes[CLASS_arm_gp].class_req;
1992 req = arch_no_register_req;
1995 /* phi nodes allow loops, so we use the old arguments for now
1996 * and fix this later */
1997 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
1998 get_irn_in(node) + 1);
1999 copy_node_attr(irg, node, phi);
2000 be_duplicate_deps(node, phi);
2002 arch_set_out_register_req(phi, 0, req);
2004 be_enqueue_preds(node);
2011 * Enters all transform functions into the generic pointer
2013 static void arm_register_transformers(void)
2015 be_start_transform_setup();
2017 be_set_transform_function(op_Add, gen_Add);
2018 be_set_transform_function(op_And, gen_And);
2019 be_set_transform_function(op_Call, gen_Call);
2020 be_set_transform_function(op_Cmp, gen_Cmp);
2021 be_set_transform_function(op_Cond, gen_Cond);
2022 be_set_transform_function(op_Const, gen_Const);
2023 be_set_transform_function(op_Conv, gen_Conv);
2024 be_set_transform_function(op_CopyB, gen_CopyB);
2025 be_set_transform_function(op_Eor, gen_Eor);
2026 be_set_transform_function(op_Jmp, gen_Jmp);
2027 be_set_transform_function(op_Load, gen_Load);
2028 be_set_transform_function(op_Minus, gen_Minus);
2029 be_set_transform_function(op_Mul, gen_Mul);
2030 be_set_transform_function(op_Not, gen_Not);
2031 be_set_transform_function(op_Or, gen_Or);
2032 be_set_transform_function(op_Phi, gen_Phi);
2033 be_set_transform_function(op_Proj, gen_Proj);
2034 be_set_transform_function(op_Quot, gen_Quot);
2035 be_set_transform_function(op_Return, gen_Return);
2036 be_set_transform_function(op_Rotl, gen_Rotl);
2037 be_set_transform_function(op_Sel, gen_Sel);
2038 be_set_transform_function(op_Shl, gen_Shl);
2039 be_set_transform_function(op_Shr, gen_Shr);
2040 be_set_transform_function(op_Shrs, gen_Shrs);
2041 be_set_transform_function(op_Start, gen_Start);
2042 be_set_transform_function(op_Store, gen_Store);
2043 be_set_transform_function(op_Sub, gen_Sub);
2044 be_set_transform_function(op_SymConst, gen_SymConst);
2045 be_set_transform_function(op_Unknown, gen_Unknown);
2049 * Initialize fpa Immediate support.
2051 static void arm_init_fpa_immediate(void)
2053 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
2054 fpa_imm[0][fpa_null] = get_mode_null(mode_F);
2055 fpa_imm[0][fpa_one] = get_mode_one(mode_F);
2056 fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
2057 fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
2058 fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
2059 fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
2060 fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
2061 fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
2063 fpa_imm[1][fpa_null] = get_mode_null(mode_D);
2064 fpa_imm[1][fpa_one] = get_mode_one(mode_D);
2065 fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
2066 fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
2067 fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
2068 fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
2069 fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
2070 fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
2072 fpa_imm[2][fpa_null] = get_mode_null(mode_E);
2073 fpa_imm[2][fpa_one] = get_mode_one(mode_E);
2074 fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
2075 fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
2076 fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
2077 fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
2078 fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
2079 fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
2083 * Transform a Firm graph into an ARM graph.
2085 void arm_transform_graph(arm_code_gen_t *cg)
2087 static int imm_initialized = 0;
2088 ir_graph *irg = cg->irg;
2089 ir_entity *entity = get_irg_entity(irg);
2090 ir_type *frame_type;
2095 if (! imm_initialized) {
2096 arm_init_fpa_immediate();
2097 imm_initialized = 1;
2099 arm_register_transformers();
2102 node_to_stack = pmap_create();
2104 assert(abihelper == NULL);
2105 abihelper = be_abihelper_prepare(irg);
2106 be_collect_stacknodes(abihelper);
2107 assert(cconv == NULL);
2108 cconv = arm_decide_calling_convention(get_entity_type(entity));
2109 create_stacklayout(irg);
2111 be_transform_graph(cg->irg, NULL);
2113 be_abihelper_finish(abihelper);
2116 arm_free_calling_convention(cconv);
2119 frame_type = get_irg_frame_type(irg);
2120 if (get_type_state(frame_type) == layout_undefined) {
2121 default_layout_compound_type(frame_type);
2124 pmap_destroy(node_to_stack);
2125 node_to_stack = NULL;
2127 be_add_missing_keeps(irg);
2130 void arm_init_transform(void)
2132 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");