2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
41 #include "../benode.h"
43 #include "../beutil.h"
44 #include "../betranshlp.h"
45 #include "../beabihelper.h"
48 #include "bearch_arm_t.h"
49 #include "arm_nodes_attr.h"
50 #include "arm_transform.h"
51 #include "arm_optimize.h"
52 #include "arm_new_nodes.h"
53 #include "arm_map_regs.h"
54 #include "arm_cconv.h"
56 #include "gen_arm_regalloc_if.h"
60 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 /** hold the current code generator during transformation */
63 static arm_code_gen_t *env_cg;
65 static const arch_register_t *sp_reg = &arm_gp_regs[REG_SP];
66 static ir_mode *mode_gp;
67 static ir_mode *mode_fp;
68 static beabi_helper_env_t *abihelper;
69 static calling_convention_t *cconv = NULL;
71 static pmap *node_to_stack;
73 static bool mode_needs_gp_reg(ir_mode *mode)
75 return mode_is_int(mode) || mode_is_reference(mode);
79 * create firm graph for a constant
81 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
88 /* We only have 8 bit immediates. So we possibly have to combine several
89 * operations to construct the desired value.
91 * we can either create the value by adding bits to 0 or by removing bits
92 * from an register with all bits set. Try which alternative needs fewer
94 arm_gen_vals_from_word(value, &v);
95 arm_gen_vals_from_word(~value, &vn);
99 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
100 be_dep_on_frame(result);
102 for (cnt = 1; cnt < vn.ops; ++cnt) {
103 result = new_bd_arm_Bic_imm(dbgi, block, result,
104 vn.values[cnt], vn.rors[cnt]);
108 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
109 be_dep_on_frame(result);
111 for (cnt = 1; cnt < v.ops; ++cnt) {
112 result = new_bd_arm_Or_imm(dbgi, block, result,
113 v.values[cnt], v.rors[cnt]);
120 * Create a DAG constructing a given Const.
122 * @param irn a Firm const
124 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
126 tarval *tv = get_Const_tarval(irn);
127 ir_mode *mode = get_tarval_mode(tv);
130 if (mode_is_reference(mode)) {
131 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
132 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
133 tv = tarval_convert_to(tv, mode_Iu);
135 value = get_tarval_long(tv);
136 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
140 * Create an And that will zero out upper bits.
142 * @param dbgi debug info
143 * @param block the basic block
144 * @param op the original node
145 * param src_bits number of lower bits that will remain
147 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
151 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
152 } else if (src_bits == 16) {
153 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
154 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
157 panic("zero extension only supported for 8 and 16 bits");
162 * Generate code for a sign extension.
164 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
167 int shift_width = 32 - src_bits;
168 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
169 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
173 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
176 int bits = get_mode_size_bits(orig_mode);
180 if (mode_is_signed(orig_mode)) {
181 return gen_sign_extension(dbgi, block, op, bits);
183 return gen_zero_extension(dbgi, block, op, bits);
188 * returns true if it is assured, that the upper bits of a node are "clean"
189 * which means for a 16 or 8 bit value, that the upper bits in the register
190 * are 0 for unsigned and a copy of the last significant bit for signed
193 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
195 (void) transformed_node;
202 * Transforms a Conv node.
204 * @return The created ia32 Conv node
206 static ir_node *gen_Conv(ir_node *node)
208 ir_node *block = be_transform_node(get_nodes_block(node));
209 ir_node *op = get_Conv_op(node);
210 ir_node *new_op = be_transform_node(op);
211 ir_mode *src_mode = get_irn_mode(op);
212 ir_mode *dst_mode = get_irn_mode(node);
213 dbg_info *dbg = get_irn_dbg_info(node);
215 if (src_mode == dst_mode)
218 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
219 if (USE_FPA(env_cg->isa)) {
220 if (mode_is_float(src_mode)) {
221 if (mode_is_float(dst_mode)) {
222 /* from float to float */
223 return new_bd_arm_Mvf(dbg, block, new_op, dst_mode);
225 /* from float to int */
229 /* from int to float */
232 } else if (USE_VFP(env_cg->isa)) {
233 panic("VFP not supported yet");
235 panic("Softfloat not supported yet");
237 } else { /* complete in gp registers */
238 int src_bits = get_mode_size_bits(src_mode);
239 int dst_bits = get_mode_size_bits(dst_mode);
243 if (src_bits == dst_bits) {
244 /* kill unnecessary conv */
248 if (src_bits < dst_bits) {
256 if (upper_bits_clean(new_op, min_mode)) {
260 if (mode_is_signed(min_mode)) {
261 return gen_sign_extension(dbg, block, new_op, min_bits);
263 return gen_zero_extension(dbg, block, new_op, min_bits);
273 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
275 unsigned val, low_pos, high_pos;
280 val = get_tarval_long(get_Const_tarval(node));
292 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
294 So we determine the smallest even position with a bit set
295 and the highest even position with no bit set anymore.
296 If the difference between these 2 is <= 8, then we can encode the value
299 low_pos = ntz(val) & ~1u;
300 high_pos = (32-nlz(val)+1) & ~1u;
302 if (high_pos - low_pos <= 8) {
303 res->imm_8 = val >> low_pos;
304 res->rot = 32 - low_pos;
309 res->rot = 34 - high_pos;
310 val = val >> (32-res->rot) | val << (res->rot);
320 static bool is_downconv(const ir_node *node)
328 /* we only want to skip the conv when we're the only user
329 * (not optimal but for now...)
331 if (get_irn_n_edges(node) > 1)
334 src_mode = get_irn_mode(get_Conv_op(node));
335 dest_mode = get_irn_mode(node);
337 mode_needs_gp_reg(src_mode) &&
338 mode_needs_gp_reg(dest_mode) &&
339 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
342 static ir_node *arm_skip_downconv(ir_node *node)
344 while (is_downconv(node))
345 node = get_Conv_op(node);
351 MATCH_COMMUTATIVE = 1 << 0,
352 MATCH_SIZE_NEUTRAL = 1 << 1,
355 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
356 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
358 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
359 new_binop_reg_func new_reg, new_binop_imm_func new_imm)
361 ir_node *block = be_transform_node(get_nodes_block(node));
362 ir_node *op1 = get_binop_left(node);
364 ir_node *op2 = get_binop_right(node);
366 dbg_info *dbgi = get_irn_dbg_info(node);
369 if (flags & MATCH_SIZE_NEUTRAL) {
370 op1 = arm_skip_downconv(op1);
371 op2 = arm_skip_downconv(op2);
373 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
376 if (try_encode_as_immediate(op2, &imm)) {
377 ir_node *new_op1 = be_transform_node(op1);
378 return new_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
380 new_op2 = be_transform_node(op2);
381 if ((flags & MATCH_COMMUTATIVE) && try_encode_as_immediate(op1, &imm)) {
382 return new_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
384 new_op1 = be_transform_node(op1);
386 return new_reg(dbgi, block, new_op1, new_op2);
390 * Creates an ARM Add.
392 * @return the created arm Add node
394 static ir_node *gen_Add(ir_node *node)
396 ir_mode *mode = get_irn_mode(node);
398 if (mode_is_float(mode)) {
399 ir_node *block = be_transform_node(get_nodes_block(node));
400 ir_node *op1 = get_Add_left(node);
401 ir_node *op2 = get_Add_right(node);
402 dbg_info *dbgi = get_irn_dbg_info(node);
403 ir_node *new_op1 = be_transform_node(op1);
404 ir_node *new_op2 = be_transform_node(op2);
405 if (USE_FPA(env_cg->isa)) {
406 return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
407 } else if (USE_VFP(env_cg->isa)) {
408 assert(mode != mode_E && "IEEE Extended FP not supported");
409 panic("VFP not supported yet");
411 panic("Softfloat not supported yet");
416 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
418 new_op2 = get_irn_n(new_op1, 1);
419 new_op1 = get_irn_n(new_op1, 0);
421 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
423 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
425 new_op1 = get_irn_n(new_op2, 0);
426 new_op2 = get_irn_n(new_op2, 1);
428 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
432 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
433 new_bd_arm_Add_reg, new_bd_arm_Add_imm);
438 * Creates an ARM Mul.
440 * @return the created arm Mul node
442 static ir_node *gen_Mul(ir_node *node)
444 ir_node *block = be_transform_node(get_nodes_block(node));
445 ir_node *op1 = get_Mul_left(node);
446 ir_node *new_op1 = be_transform_node(op1);
447 ir_node *op2 = get_Mul_right(node);
448 ir_node *new_op2 = be_transform_node(op2);
449 ir_mode *mode = get_irn_mode(node);
450 dbg_info *dbg = get_irn_dbg_info(node);
452 if (mode_is_float(mode)) {
453 if (USE_FPA(env_cg->isa)) {
454 return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
455 } else if (USE_VFP(env_cg->isa)) {
456 assert(mode != mode_E && "IEEE Extended FP not supported");
457 panic("VFP not supported yet");
459 panic("Softfloat not supported yet");
462 assert(mode_is_data(mode));
463 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
466 static ir_node *gen_Quot(ir_node *node)
468 ir_node *block = be_transform_node(get_nodes_block(node));
469 ir_node *op1 = get_Quot_left(node);
470 ir_node *new_op1 = be_transform_node(op1);
471 ir_node *op2 = get_Quot_right(node);
472 ir_node *new_op2 = be_transform_node(op2);
473 ir_mode *mode = get_irn_mode(node);
474 dbg_info *dbg = get_irn_dbg_info(node);
476 assert(mode != mode_E && "IEEE Extended FP not supported");
478 if (USE_FPA(env_cg->isa)) {
479 return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
480 } else if (USE_VFP(env_cg->isa)) {
481 assert(mode != mode_E && "IEEE Extended FP not supported");
482 panic("VFP not supported yet");
484 panic("Softfloat not supported yet");
488 static ir_node *gen_And(ir_node *node)
490 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
491 new_bd_arm_And_reg, new_bd_arm_And_imm);
494 static ir_node *gen_Or(ir_node *node)
496 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
497 new_bd_arm_Or_reg, new_bd_arm_Or_imm);
500 static ir_node *gen_Eor(ir_node *node)
502 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL,
503 new_bd_arm_Eor_reg, new_bd_arm_Eor_imm);
506 static ir_node *gen_Sub(ir_node *node)
508 ir_node *block = be_transform_node(get_nodes_block(node));
509 ir_node *op1 = get_Sub_left(node);
510 ir_node *new_op1 = be_transform_node(op1);
511 ir_node *op2 = get_Sub_right(node);
512 ir_node *new_op2 = be_transform_node(op2);
513 ir_mode *mode = get_irn_mode(node);
514 dbg_info *dbgi = get_irn_dbg_info(node);
516 if (mode_is_float(mode)) {
517 if (USE_FPA(env_cg->isa)) {
518 return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
519 } else if (USE_VFP(env_cg->isa)) {
520 assert(mode != mode_E && "IEEE Extended FP not supported");
521 panic("VFP not supported yet");
523 panic("Softfloat not supported yet");
526 return gen_int_binop(node, MATCH_SIZE_NEUTRAL,
527 new_bd_arm_Sub_reg, new_bd_arm_Sub_imm);
532 * Checks if a given value can be used as an immediate for the given
535 static bool can_use_shift_constant(unsigned int val,
536 arm_shift_modifier_t modifier)
540 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
546 * generate an ARM shift instruction.
548 * @param node the node
549 * @param flags matching flags
550 * @param shift_modifier initial encoding of the desired shift operation
552 static ir_node *make_shift(ir_node *node, match_flags_t flags,
553 arm_shift_modifier_t shift_modifier)
555 ir_node *block = be_transform_node(get_nodes_block(node));
556 ir_node *op1 = get_binop_left(node);
557 ir_node *op2 = get_binop_right(node);
558 dbg_info *dbgi = get_irn_dbg_info(node);
562 if (flags & MATCH_SIZE_NEUTRAL) {
563 op1 = arm_skip_downconv(op1);
564 op2 = arm_skip_downconv(op2);
567 new_op1 = be_transform_node(op1);
569 tarval *tv = get_Const_tarval(op2);
570 unsigned int val = get_tarval_long(tv);
571 assert(tarval_is_long(tv));
572 if (can_use_shift_constant(val, shift_modifier)) {
573 switch (shift_modifier) {
574 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
575 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
576 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
577 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
578 default: panic("unexpected shift modifier");
580 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
581 shift_modifier, val);
585 new_op2 = be_transform_node(op2);
586 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
590 static ir_node *gen_Shl(ir_node *node)
592 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
595 static ir_node *gen_Shr(ir_node *node)
597 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
600 static ir_node *gen_Shrs(ir_node *node)
602 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
605 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
607 ir_node *block = be_transform_node(get_nodes_block(node));
608 ir_node *new_op1 = be_transform_node(op1);
609 dbg_info *dbgi = get_irn_dbg_info(node);
610 ir_node *new_op2 = be_transform_node(op2);
612 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
616 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
618 ir_node *block = be_transform_node(get_nodes_block(node));
619 ir_node *new_op1 = be_transform_node(op1);
620 dbg_info *dbgi = get_irn_dbg_info(node);
621 ir_node *new_op2 = be_transform_node(op2);
623 /* Note: there is no Rol on arm, we have to use Ror */
624 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
625 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
629 static ir_node *gen_Rotl(ir_node *node)
631 ir_node *rotate = NULL;
632 ir_node *op1 = get_Rotl_left(node);
633 ir_node *op2 = get_Rotl_right(node);
635 /* Firm has only RotL, so we are looking for a right (op2)
636 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
637 that means we can create a RotR. */
640 ir_node *right = get_Add_right(op2);
641 if (is_Const(right)) {
642 tarval *tv = get_Const_tarval(right);
643 ir_mode *mode = get_irn_mode(node);
644 long bits = get_mode_size_bits(mode);
645 ir_node *left = get_Add_left(op2);
647 if (is_Minus(left) &&
648 tarval_is_long(tv) &&
649 get_tarval_long(tv) == bits &&
651 rotate = gen_Ror(node, op1, get_Minus_op(left));
653 } else if (is_Sub(op2)) {
654 ir_node *left = get_Sub_left(op2);
655 if (is_Const(left)) {
656 tarval *tv = get_Const_tarval(left);
657 ir_mode *mode = get_irn_mode(node);
658 long bits = get_mode_size_bits(mode);
659 ir_node *right = get_Sub_right(op2);
661 if (tarval_is_long(tv) &&
662 get_tarval_long(tv) == bits &&
664 rotate = gen_Ror(node, op1, right);
666 } else if (is_Const(op2)) {
667 tarval *tv = get_Const_tarval(op2);
668 ir_mode *mode = get_irn_mode(node);
669 long bits = get_mode_size_bits(mode);
671 if (tarval_is_long(tv) && bits == 32) {
672 ir_node *block = be_transform_node(get_nodes_block(node));
673 ir_node *new_op1 = be_transform_node(op1);
674 dbg_info *dbgi = get_irn_dbg_info(node);
676 bits = (bits - get_tarval_long(tv)) & 31;
677 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
681 if (rotate == NULL) {
682 rotate = gen_Rol(node, op1, op2);
688 static ir_node *gen_Not(ir_node *node)
690 ir_node *block = be_transform_node(get_nodes_block(node));
691 ir_node *op = get_Not_op(node);
692 ir_node *new_op = be_transform_node(op);
693 dbg_info *dbgi = get_irn_dbg_info(node);
695 /* TODO: we could do alot more here with all the Mvn variations */
697 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
700 static ir_node *gen_Minus(ir_node *node)
702 ir_node *block = be_transform_node(get_nodes_block(node));
703 ir_node *op = get_Minus_op(node);
704 ir_node *new_op = be_transform_node(op);
705 dbg_info *dbgi = get_irn_dbg_info(node);
706 ir_mode *mode = get_irn_mode(node);
708 if (mode_is_float(mode)) {
709 if (USE_FPA(env_cg->isa)) {
710 return new_bd_arm_Mvf(dbgi, block, op, mode);
711 } else if (USE_VFP(env_cg->isa)) {
712 assert(mode != mode_E && "IEEE Extended FP not supported");
713 panic("VFP not supported yet");
715 panic("Softfloat not supported yet");
718 assert(mode_is_data(mode));
719 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
722 static ir_node *gen_Load(ir_node *node)
724 ir_node *block = be_transform_node(get_nodes_block(node));
725 ir_node *ptr = get_Load_ptr(node);
726 ir_node *new_ptr = be_transform_node(ptr);
727 ir_node *mem = get_Load_mem(node);
728 ir_node *new_mem = be_transform_node(mem);
729 ir_mode *mode = get_Load_mode(node);
730 dbg_info *dbgi = get_irn_dbg_info(node);
731 ir_node *new_load = NULL;
733 if (mode_is_float(mode)) {
734 if (USE_FPA(env_cg->isa)) {
735 new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
737 } else if (USE_VFP(env_cg->isa)) {
738 assert(mode != mode_E && "IEEE Extended FP not supported");
739 panic("VFP not supported yet");
741 panic("Softfloat not supported yet");
744 assert(mode_is_data(mode) && "unsupported mode for Load");
746 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
748 set_irn_pinned(new_load, get_irn_pinned(node));
750 /* check for special case: the loaded value might not be used */
751 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
752 /* add a result proj and a Keep to produce a pseudo use */
753 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
754 be_new_Keep(block, 1, &proj);
760 static ir_node *gen_Store(ir_node *node)
762 ir_node *block = be_transform_node(get_nodes_block(node));
763 ir_node *ptr = get_Store_ptr(node);
764 ir_node *new_ptr = be_transform_node(ptr);
765 ir_node *mem = get_Store_mem(node);
766 ir_node *new_mem = be_transform_node(mem);
767 ir_node *val = get_Store_value(node);
768 ir_node *new_val = be_transform_node(val);
769 ir_mode *mode = get_irn_mode(val);
770 dbg_info *dbgi = get_irn_dbg_info(node);
771 ir_node *new_store = NULL;
773 if (mode_is_float(mode)) {
774 if (USE_FPA(env_cg->isa)) {
775 new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
776 new_mem, mode, NULL, 0, 0, false);
777 } else if (USE_VFP(env_cg->isa)) {
778 assert(mode != mode_E && "IEEE Extended FP not supported");
779 panic("VFP not supported yet");
781 panic("Softfloat not supported yet");
784 assert(mode_is_data(mode) && "unsupported mode for Store");
785 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
788 set_irn_pinned(new_store, get_irn_pinned(node));
792 static ir_node *gen_Jmp(ir_node *node)
794 ir_node *block = get_nodes_block(node);
795 ir_node *new_block = be_transform_node(block);
796 dbg_info *dbgi = get_irn_dbg_info(node);
798 return new_bd_arm_Jmp(dbgi, new_block);
801 static ir_node *gen_SwitchJmp(ir_node *node)
803 ir_node *block = be_transform_node(get_nodes_block(node));
804 ir_node *selector = get_Cond_selector(node);
805 dbg_info *dbgi = get_irn_dbg_info(node);
806 ir_node *new_op = be_transform_node(selector);
807 ir_node *const_graph;
811 const ir_edge_t *edge;
818 foreach_out_edge(node, edge) {
819 proj = get_edge_src_irn(edge);
820 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
822 pn = get_Proj_proj(proj);
824 min = pn<min ? pn : min;
825 max = pn>max ? pn : max;
828 n_projs = max - translation + 1;
830 foreach_out_edge(node, edge) {
831 proj = get_edge_src_irn(edge);
832 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
834 pn = get_Proj_proj(proj) - translation;
835 set_Proj_proj(proj, pn);
838 const_graph = create_const_graph_value(dbgi, block, translation);
839 sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
840 return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
843 static ir_node *gen_Cmp(ir_node *node)
845 ir_node *block = be_transform_node(get_nodes_block(node));
846 ir_node *op1 = get_Cmp_left(node);
847 ir_node *op2 = get_Cmp_right(node);
848 ir_mode *cmp_mode = get_irn_mode(op1);
849 dbg_info *dbgi = get_irn_dbg_info(node);
854 if (mode_is_float(cmp_mode)) {
855 /* TODO: this is broken... */
856 new_op1 = be_transform_node(op1);
857 new_op2 = be_transform_node(op2);
859 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
861 panic("FloatCmp NIY");
863 ir_node *new_op2 = be_transform_node(op2);
864 /* floating point compare */
865 pn_Cmp pnc = get_Proj_proj(selector);
867 if (pnc & pn_Cmp_Uo) {
868 /* check for unordered, need cmf */
869 return new_bd_arm_CmfBra(dbgi, block, new_op1, new_op2, pnc);
871 /* Hmm: use need cmfe */
872 return new_bd_arm_CmfeBra(dbgi, block, new_op1, new_op2, pnc);
876 assert(get_irn_mode(op2) == cmp_mode);
877 is_unsigned = !mode_is_signed(cmp_mode);
879 /* compare with 0 can be done with Tst */
880 if (is_Const(op2) && tarval_is_null(get_Const_tarval(op2))) {
881 new_op1 = be_transform_node(op1);
882 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
883 return new_bd_arm_Tst_reg(dbgi, block, new_op1, new_op1, false,
886 if (is_Const(op1) && tarval_is_null(get_Const_tarval(op1))) {
887 new_op2 = be_transform_node(op2);
888 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
889 return new_bd_arm_Tst_reg(dbgi, block, new_op2, new_op2, true,
893 /* integer compare, TODO: use shifter_op in all its combinations */
894 new_op1 = be_transform_node(op1);
895 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
896 new_op2 = be_transform_node(op2);
897 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
898 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
902 static ir_node *gen_Cond(ir_node *node)
904 ir_node *selector = get_Cond_selector(node);
905 ir_mode *mode = get_irn_mode(selector);
910 if (mode != mode_b) {
911 return gen_SwitchJmp(node);
913 assert(is_Proj(selector));
915 block = be_transform_node(get_nodes_block(node));
916 dbgi = get_irn_dbg_info(node);
917 flag_node = be_transform_node(get_Proj_pred(selector));
919 return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector));
922 static tarval *fpa_imm[3][fpa_max];
926 * Check, if a floating point tarval is an fpa immediate, i.e.
927 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
929 static int is_fpa_immediate(tarval *tv)
931 ir_mode *mode = get_tarval_mode(tv);
934 switch (get_mode_size_bits(mode)) {
945 if (tarval_is_negative(tv)) {
950 for (j = 0; j < fpa_max; ++j) {
951 if (tv == fpa_imm[i][j])
958 static ir_node *gen_Const(ir_node *node)
960 ir_node *block = be_transform_node(get_nodes_block(node));
961 ir_mode *mode = get_irn_mode(node);
962 dbg_info *dbg = get_irn_dbg_info(node);
964 if (mode_is_float(mode)) {
965 if (USE_FPA(env_cg->isa)) {
966 tarval *tv = get_Const_tarval(node);
967 node = new_bd_arm_fConst(dbg, block, tv);
968 be_dep_on_frame(node);
970 } else if (USE_VFP(env_cg->isa)) {
971 assert(mode != mode_E && "IEEE Extended FP not supported");
972 panic("VFP not supported yet");
974 panic("Softfloat not supported yet");
977 return create_const_graph(node, block);
980 static ir_node *gen_SymConst(ir_node *node)
982 ir_node *block = be_transform_node(get_nodes_block(node));
983 ir_entity *entity = get_SymConst_entity(node);
984 dbg_info *dbgi = get_irn_dbg_info(node);
987 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
988 be_dep_on_frame(new_node);
992 static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0,
995 /* the good way to do this would be to use the stm (store multiple)
996 * instructions, since our input is nearly always 2 consecutive 32bit
998 ir_graph *irg = current_ir_graph;
999 ir_node *stack = get_irg_frame(irg);
1000 ir_node *nomem = new_NoMem();
1001 ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp,
1003 ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp,
1005 ir_node *in[2] = { str0, str1 };
1006 ir_node *sync = new_r_Sync(block, 2, in);
1008 set_irn_pinned(str0, op_pin_state_floats);
1009 set_irn_pinned(str1, op_pin_state_floats);
1011 ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true);
1012 set_irn_pinned(ldf, op_pin_state_floats);
1014 return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1017 static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node)
1019 ir_graph *irg = current_ir_graph;
1020 ir_node *stack = get_irg_frame(irg);
1021 ir_node *nomem = new_NoMem();
1022 ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp,
1025 set_irn_pinned(str, op_pin_state_floats);
1027 ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true);
1028 set_irn_pinned(ldf, op_pin_state_floats);
1030 return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1033 static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node)
1035 ir_graph *irg = current_ir_graph;
1036 ir_node *stack = get_irg_frame(irg);
1037 ir_node *nomem = new_NoMem();
1038 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F,
1041 set_irn_pinned(stf, op_pin_state_floats);
1043 ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1044 set_irn_pinned(ldr, op_pin_state_floats);
1046 return new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1049 static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node,
1050 ir_node **out_value0, ir_node **out_value1)
1052 ir_graph *irg = current_ir_graph;
1053 ir_node *stack = get_irg_frame(irg);
1054 ir_node *nomem = new_NoMem();
1055 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D,
1057 ir_node *ldr0, *ldr1;
1058 set_irn_pinned(stf, op_pin_state_floats);
1060 ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1061 set_irn_pinned(ldr0, op_pin_state_floats);
1062 ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true);
1063 set_irn_pinned(ldr1, op_pin_state_floats);
1065 *out_value0 = new_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
1066 *out_value1 = new_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
1069 static ir_node *gen_CopyB(ir_node *node)
1071 ir_node *block = be_transform_node(get_nodes_block(node));
1072 ir_node *src = get_CopyB_src(node);
1073 ir_node *new_src = be_transform_node(src);
1074 ir_node *dst = get_CopyB_dst(node);
1075 ir_node *new_dst = be_transform_node(dst);
1076 ir_node *mem = get_CopyB_mem(node);
1077 ir_node *new_mem = be_transform_node(mem);
1078 dbg_info *dbg = get_irn_dbg_info(node);
1079 int size = get_type_size_bytes(get_CopyB_type(node));
1083 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
1084 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
1086 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1087 new_bd_arm_EmptyReg(dbg, block),
1088 new_bd_arm_EmptyReg(dbg, block),
1089 new_bd_arm_EmptyReg(dbg, block),
1093 static ir_node *gen_Proj_Load(ir_node *node)
1095 ir_node *load = get_Proj_pred(node);
1096 ir_node *new_load = be_transform_node(load);
1097 dbg_info *dbgi = get_irn_dbg_info(node);
1098 long proj = get_Proj_proj(node);
1100 /* renumber the proj */
1101 switch (get_arm_irn_opcode(new_load)) {
1103 /* handle all gp loads equal: they have the same proj numbers. */
1104 if (proj == pn_Load_res) {
1105 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1106 } else if (proj == pn_Load_M) {
1107 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1111 if (proj == pn_Load_res) {
1112 ir_mode *mode = get_Load_mode(load);
1113 return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res);
1114 } else if (proj == pn_Load_M) {
1115 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M);
1121 panic("Unsupported Proj from Load");
1124 static ir_node *gen_Proj_CopyB(ir_node *node)
1126 ir_node *pred = get_Proj_pred(node);
1127 ir_node *new_pred = be_transform_node(pred);
1128 dbg_info *dbgi = get_irn_dbg_info(node);
1129 long proj = get_Proj_proj(node);
1133 if (is_arm_CopyB(new_pred)) {
1134 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1140 panic("Unsupported Proj from CopyB");
1143 static ir_node *gen_Proj_Quot(ir_node *node)
1145 ir_node *pred = get_Proj_pred(node);
1146 ir_node *new_pred = be_transform_node(pred);
1147 dbg_info *dbgi = get_irn_dbg_info(node);
1148 ir_mode *mode = get_irn_mode(node);
1149 long proj = get_Proj_proj(node);
1153 if (is_arm_Dvf(new_pred)) {
1154 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
1158 if (is_arm_Dvf(new_pred)) {
1159 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
1165 panic("Unsupported Proj from Quot");
1169 * Transform the Projs from a Cmp.
1171 static ir_node *gen_Proj_Cmp(ir_node *node)
1174 /* we should only be here in case of a Mux node */
1178 static ir_node *gen_Proj_Start(ir_node *node)
1180 ir_node *block = get_nodes_block(node);
1181 ir_node *new_block = be_transform_node(block);
1182 ir_node *barrier = be_transform_node(get_Proj_pred(node));
1183 long proj = get_Proj_proj(node);
1185 switch ((pn_Start) proj) {
1186 case pn_Start_X_initial_exec:
1187 /* we exchange the ProjX with a jump */
1188 return new_bd_arm_Jmp(NULL, new_block);
1191 return new_r_Proj(barrier, mode_M, 0);
1193 case pn_Start_T_args:
1196 case pn_Start_P_frame_base:
1197 return be_prolog_get_reg_value(abihelper, sp_reg);
1199 case pn_Start_P_tls:
1205 panic("unexpected start proj: %ld\n", proj);
1208 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1210 long pn = get_Proj_proj(node);
1211 ir_node *block = get_nodes_block(node);
1212 ir_node *new_block = be_transform_node(block);
1213 ir_entity *entity = get_irg_entity(current_ir_graph);
1214 ir_type *method_type = get_entity_type(entity);
1215 ir_type *param_type = get_method_param_type(method_type, pn);
1216 const reg_or_stackslot_t *param;
1218 /* Proj->Proj->Start must be a method argument */
1219 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1221 param = &cconv->parameters[pn];
1223 if (param->reg0 != NULL) {
1224 /* argument transmitted in register */
1225 ir_mode *mode = get_type_mode(param_type);
1226 ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0);
1228 if (mode_is_float(mode)) {
1229 ir_node *value1 = NULL;
1231 if (param->reg1 != NULL) {
1232 value1 = be_prolog_get_reg_value(abihelper, param->reg1);
1233 } else if (param->entity != NULL) {
1234 ir_graph *irg = get_irn_irg(node);
1235 ir_node *fp = get_irg_frame(irg);
1236 ir_node *mem = be_prolog_get_memory(abihelper);
1237 ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem,
1238 mode_gp, param->entity,
1240 value1 = new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1243 /* convert integer value to float */
1244 if (value1 == NULL) {
1245 value = int_to_float(NULL, new_block, value);
1247 value = ints_to_double(NULL, new_block, value, value1);
1252 /* argument transmitted on stack */
1253 ir_graph *irg = get_irn_irg(node);
1254 ir_node *fp = get_irg_frame(irg);
1255 ir_node *mem = be_prolog_get_memory(abihelper);
1256 ir_mode *mode = get_type_mode(param->type);
1260 if (mode_is_float(mode)) {
1261 load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode,
1262 param->entity, 0, 0, true);
1263 value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res);
1265 load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1266 param->entity, 0, 0, true);
1267 value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1269 set_irn_pinned(load, op_pin_state_floats);
1276 * Finds number of output value of a mode_T node which is constrained to
1277 * a single specific register.
1279 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1281 int n_outs = arch_irn_get_n_outs(node);
1284 for (o = 0; o < n_outs; ++o) {
1285 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1286 if (req == reg->single_req)
1292 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1294 long pn = get_Proj_proj(node);
1295 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1296 ir_node *new_call = be_transform_node(call);
1297 ir_type *function_type = get_Call_type(call);
1298 calling_convention_t *cconv = decide_calling_convention(function_type);
1299 const reg_or_stackslot_t *res = &cconv->results[pn];
1303 /* TODO 64bit modes */
1304 assert(res->reg0 != NULL && res->reg1 == NULL);
1305 regn = find_out_for_reg(new_call, res->reg0);
1307 panic("Internal error in calling convention for return %+F", node);
1309 mode = res->reg0->reg_class->mode;
1311 free_calling_convention(cconv);
1313 return new_r_Proj(new_call, mode, regn);
1316 static ir_node *gen_Proj_Call(ir_node *node)
1318 long pn = get_Proj_proj(node);
1319 ir_node *call = get_Proj_pred(node);
1320 ir_node *new_call = be_transform_node(call);
1322 switch ((pn_Call) pn) {
1324 return new_r_Proj(new_call, mode_M, 0);
1325 case pn_Call_X_regular:
1326 case pn_Call_X_except:
1327 case pn_Call_T_result:
1328 case pn_Call_P_value_res_base:
1332 panic("Unexpected Call proj %ld\n", pn);
1336 * Transform a Proj node.
1338 static ir_node *gen_Proj(ir_node *node)
1340 ir_node *pred = get_Proj_pred(node);
1341 long proj = get_Proj_proj(node);
1343 switch (get_irn_opcode(pred)) {
1345 if (proj == pn_Store_M) {
1346 return be_transform_node(pred);
1348 panic("Unsupported Proj from Store");
1351 return gen_Proj_Load(node);
1353 return gen_Proj_Call(node);
1355 return gen_Proj_CopyB(node);
1357 return gen_Proj_Quot(node);
1359 return gen_Proj_Cmp(node);
1361 return gen_Proj_Start(node);
1364 return be_duplicate_node(node);
1366 ir_node *pred_pred = get_Proj_pred(pred);
1367 if (is_Call(pred_pred)) {
1368 return gen_Proj_Proj_Call(node);
1369 } else if (is_Start(pred_pred)) {
1370 return gen_Proj_Proj_Start(node);
1375 panic("code selection didn't expect Proj after %+F\n", pred);
1379 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1381 static inline ir_node *create_const(ir_node **place,
1382 create_const_node_func func,
1383 const arch_register_t* reg)
1385 ir_node *block, *res;
1390 block = get_irg_start_block(env_cg->irg);
1391 res = func(NULL, block);
1392 arch_set_irn_register(res, reg);
1397 static ir_node *gen_Unknown(ir_node *node)
1399 ir_node *block = get_nodes_block(node);
1400 ir_node *new_block = be_transform_node(block);
1401 dbg_info *dbgi = get_irn_dbg_info(node);
1403 /* just produce a 0 */
1404 ir_mode *mode = get_irn_mode(node);
1405 if (mode_is_float(mode)) {
1406 tarval *tv = get_mode_null(mode);
1407 ir_node *node = new_bd_arm_fConst(dbgi, new_block, tv);
1408 be_dep_on_frame(node);
1410 } else if (mode_needs_gp_reg(mode)) {
1411 return create_const_graph_value(dbgi, new_block, 0);
1414 panic("Unexpected Unknown mode");
1418 * Produces the type which sits between the stack args and the locals on the
1419 * stack. It will contain the return address and space to store the old base
1421 * @return The Firm type modeling the ABI between type.
1423 static ir_type *arm_get_between_type(void)
1425 static ir_type *between_type = NULL;
1427 if (between_type == NULL) {
1428 between_type = new_type_class(new_id_from_str("arm_between_type"));
1429 set_type_size_bytes(between_type, 0);
1432 return between_type;
1435 static void create_stacklayout(ir_graph *irg)
1437 ir_entity *entity = get_irg_entity(irg);
1438 ir_type *function_type = get_entity_type(entity);
1439 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1444 /* calling conventions must be decided by now */
1445 assert(cconv != NULL);
1447 /* construct argument type */
1448 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1449 n_params = get_method_n_params(function_type);
1450 for (p = 0; p < n_params; ++p) {
1451 reg_or_stackslot_t *param = &cconv->parameters[p];
1455 if (param->type == NULL)
1458 snprintf(buf, sizeof(buf), "param_%d", p);
1459 id = new_id_from_str(buf);
1460 param->entity = new_entity(arg_type, id, param->type);
1461 set_entity_offset(param->entity, param->offset);
1464 /* TODO: what about external functions? we don't know most of the stack
1465 * layout for them. And probably don't need all of this... */
1466 memset(layout, 0, sizeof(*layout));
1468 layout->frame_type = get_irg_frame_type(irg);
1469 layout->between_type = arm_get_between_type();
1470 layout->arg_type = arg_type;
1471 layout->param_map = NULL; /* TODO */
1472 layout->initial_offset = 0;
1473 layout->initial_bias = 0;
1474 layout->stack_dir = -1;
1475 layout->sp_relative = true;
1477 assert(N_FRAME_TYPES == 3);
1478 layout->order[0] = layout->frame_type;
1479 layout->order[1] = layout->between_type;
1480 layout->order[2] = layout->arg_type;
1484 * transform the start node to the prolog code + initial barrier
1486 static ir_node *gen_Start(ir_node *node)
1488 ir_graph *irg = get_irn_irg(node);
1489 ir_entity *entity = get_irg_entity(irg);
1490 ir_type *function_type = get_entity_type(entity);
1491 ir_node *block = get_nodes_block(node);
1492 ir_node *new_block = be_transform_node(block);
1493 dbg_info *dbgi = get_irn_dbg_info(node);
1500 /* stackpointer is important at function prolog */
1501 be_prolog_add_reg(abihelper, sp_reg,
1502 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1503 /* function parameters in registers */
1504 for (i = 0; i < get_method_n_params(function_type); ++i) {
1505 const reg_or_stackslot_t *param = &cconv->parameters[i];
1506 if (param->reg0 != NULL)
1507 be_prolog_add_reg(abihelper, param->reg0, 0);
1508 if (param->reg1 != NULL)
1509 be_prolog_add_reg(abihelper, param->reg1, 0);
1511 /* announce that we need the values of the callee save regs */
1512 for (i = 0; i < (int) (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
1513 be_prolog_add_reg(abihelper, callee_saves[i], 0);
1516 start = be_prolog_create_start(abihelper, dbgi, new_block);
1517 sp = be_prolog_get_reg_value(abihelper, sp_reg);
1518 incsp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
1519 be_prolog_set_reg_value(abihelper, sp_reg, incsp);
1520 barrier = be_prolog_create_barrier(abihelper, new_block);
1525 static ir_node *get_stack_pointer_for(ir_node *node)
1527 /* get predecessor in stack_order list */
1528 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1529 ir_node *stack_pred_transformed;
1532 if (stack_pred == NULL) {
1533 /* first stack user in the current block. We can simply use the
1534 * initial sp_proj for it */
1535 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1539 stack_pred_transformed = be_transform_node(stack_pred);
1540 stack = pmap_get(node_to_stack, stack_pred);
1541 if (stack == NULL) {
1542 return get_stack_pointer_for(stack_pred);
1549 * transform a Return node into epilogue code + return statement
1551 static ir_node *gen_Return(ir_node *node)
1553 ir_node *block = get_nodes_block(node);
1554 ir_node *new_block = be_transform_node(block);
1555 dbg_info *dbgi = get_irn_dbg_info(node);
1556 ir_node *mem = get_Return_mem(node);
1557 ir_node *new_mem = be_transform_node(mem);
1558 int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
1559 ir_node *sp_proj = get_stack_pointer_for(node);
1560 int n_res = get_Return_n_ress(node);
1565 be_epilog_begin(abihelper);
1566 be_epilog_set_memory(abihelper, new_mem);
1567 /* connect stack pointer with initial stack pointer. fix_stack phase
1568 will later serialize all stack pointer adjusting nodes */
1569 be_epilog_add_reg(abihelper, sp_reg,
1570 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1574 for (i = 0; i < n_res; ++i) {
1575 ir_node *res_value = get_Return_res(node, i);
1576 ir_node *new_res_value = be_transform_node(res_value);
1577 const reg_or_stackslot_t *slot = &cconv->results[i];
1578 const arch_register_t *reg = slot->reg0;
1579 assert(slot->reg1 == NULL);
1580 be_epilog_add_reg(abihelper, reg, 0, new_res_value);
1583 /* connect callee saves with their values at the function begin */
1584 for (i = 0; i < n_callee_saves; ++i) {
1585 const arch_register_t *reg = callee_saves[i];
1586 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1587 be_epilog_add_reg(abihelper, reg, 0, value);
1590 /* create the barrier before the epilog code */
1591 be_epilog_create_barrier(abihelper, new_block);
1593 /* epilog code: an incsp */
1594 sp_proj = be_epilog_get_reg_value(abihelper, sp_reg);
1595 incsp = be_new_IncSP(sp_reg, new_block, sp_proj,
1596 BE_STACK_FRAME_SIZE_SHRINK, 0);
1597 be_epilog_set_reg_value(abihelper, sp_reg, incsp);
1599 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1605 static ir_node *gen_Call(ir_node *node)
1607 ir_graph *irg = get_irn_irg(node);
1608 ir_node *callee = get_Call_ptr(node);
1609 ir_node *block = get_nodes_block(node);
1610 ir_node *new_block = be_transform_node(block);
1611 ir_node *mem = get_Call_mem(node);
1612 ir_node *new_mem = be_transform_node(mem);
1613 dbg_info *dbgi = get_irn_dbg_info(node);
1614 ir_type *type = get_Call_type(node);
1615 calling_convention_t *cconv = decide_calling_convention(type);
1616 int n_params = get_Call_n_params(node);
1617 int n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
1618 /* max inputs: memory, callee, register arguments */
1619 int max_inputs = 2 + n_param_regs;
1620 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1621 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1622 struct obstack *obst = be_get_be_obst(irg);
1623 const arch_register_req_t **in_req
1624 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1628 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1629 ir_entity *entity = NULL;
1630 ir_node *incsp = NULL;
1637 assert(n_params == get_method_n_params(type));
1639 /* construct arguments */
1642 in_req[in_arity] = arch_no_register_req;
1646 for (p = 0; p < n_params; ++p) {
1647 ir_node *value = get_Call_param(node, p);
1648 ir_node *new_value = be_transform_node(value);
1649 ir_node *new_value1 = NULL;
1650 const reg_or_stackslot_t *param = &cconv->parameters[p];
1651 ir_type *param_type = get_method_param_type(type, p);
1652 ir_mode *mode = get_type_mode(param_type);
1655 if (mode_is_float(mode) && param->reg0 != NULL) {
1656 unsigned size_bits = get_mode_size_bits(mode);
1657 if (size_bits == 64) {
1658 double_to_ints(dbgi, new_block, new_value, &new_value,
1661 assert(size_bits == 32);
1662 new_value = float_to_int(dbgi, new_block, new_value);
1666 /* put value into registers */
1667 if (param->reg0 != NULL) {
1668 in[in_arity] = new_value;
1669 in_req[in_arity] = param->reg0->single_req;
1671 if (new_value1 == NULL)
1674 if (param->reg1 != NULL) {
1675 assert(new_value1 != NULL);
1676 in[in_arity] = new_value1;
1677 in_req[in_arity] = param->reg1->single_req;
1682 /* we need a store if we're here */
1683 if (new_value1 != NULL) {
1684 new_value = new_value1;
1688 /* create a parameter frame if necessary */
1689 if (incsp == NULL) {
1690 ir_node *new_frame = get_stack_pointer_for(node);
1691 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1692 cconv->param_stack_size, 1);
1694 if (mode_is_float(mode)) {
1695 str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem,
1696 mode, NULL, 0, param->offset, true);
1698 str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem,
1699 mode, NULL, 0, param->offset, true);
1701 sync_ins[sync_arity++] = str;
1703 assert(in_arity <= max_inputs);
1705 /* construct memory input */
1706 if (sync_arity == 0) {
1707 in[mem_pos] = new_mem;
1708 } else if (sync_arity == 1) {
1709 in[mem_pos] = sync_ins[0];
1711 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1714 /* TODO: use a generic symconst matcher here */
1715 if (is_SymConst(callee)) {
1716 entity = get_SymConst_entity(callee);
1718 /* TODO: finish load matcher here */
1721 if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) {
1722 ir_node *load = get_Proj_pred(callee);
1723 ir_node *ptr = get_Load_ptr(load);
1724 ir_node *new_ptr = be_transform_node(ptr);
1725 ir_node *mem = get_Load_mem(load);
1726 ir_node *new_mem = be_transform_node(mem);
1727 ir_mode *mode = get_Load_mode(node);
1731 in[in_arity] = be_transform_node(callee);
1732 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1741 out_arity = 1 + n_caller_saves;
1743 if (entity != NULL) {
1744 /* TODO: use a generic symconst matcher here
1745 * so we can also handle entity+offset, etc. */
1746 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1749 * - use a proper shifter_operand matcher
1750 * - we could also use LinkLdrPC
1752 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1756 if (incsp != NULL) {
1757 /* IncSP to destroy the call stackframe */
1758 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
1760 /* if we are the last IncSP producer in a block then we have to keep
1762 * Note: This here keeps all producers which is more than necessary */
1763 add_irn_dep(incsp, res);
1766 pmap_insert(node_to_stack, node, incsp);
1769 set_arm_in_req_all(res, in_req);
1771 /* create output register reqs */
1772 arch_set_out_register_req(res, 0, arch_no_register_req);
1773 for (o = 0; o < n_caller_saves; ++o) {
1774 const arch_register_t *reg = caller_saves[o];
1775 arch_set_out_register_req(res, o+1, reg->single_req);
1778 /* copy pinned attribute */
1779 set_irn_pinned(res, get_irn_pinned(node));
1781 free_calling_convention(cconv);
1785 static ir_node *gen_Sel(ir_node *node)
1787 dbg_info *dbgi = get_irn_dbg_info(node);
1788 ir_node *block = get_nodes_block(node);
1789 ir_node *new_block = be_transform_node(block);
1790 ir_node *ptr = get_Sel_ptr(node);
1791 ir_node *new_ptr = be_transform_node(ptr);
1792 ir_entity *entity = get_Sel_entity(node);
1794 /* must be the frame pointer all other sels must have been lowered
1796 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1797 /* we should not have value types from parameters anymore - they should be
1799 assert(get_entity_owner(entity) !=
1800 get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
1802 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1806 * Change some phi modes
1808 static ir_node *gen_Phi(ir_node *node)
1810 const arch_register_req_t *req;
1811 ir_node *block = be_transform_node(get_nodes_block(node));
1812 ir_graph *irg = current_ir_graph;
1813 dbg_info *dbgi = get_irn_dbg_info(node);
1814 ir_mode *mode = get_irn_mode(node);
1817 if (mode_needs_gp_reg(mode)) {
1818 /* we shouldn't have any 64bit stuff around anymore */
1819 assert(get_mode_size_bits(mode) <= 32);
1820 /* all integer operations are on 32bit registers now */
1822 req = arm_reg_classes[CLASS_arm_gp].class_req;
1824 req = arch_no_register_req;
1827 /* phi nodes allow loops, so we use the old arguments for now
1828 * and fix this later */
1829 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
1830 get_irn_in(node) + 1);
1831 copy_node_attr(irg, node, phi);
1832 be_duplicate_deps(node, phi);
1834 arch_set_out_register_req(phi, 0, req);
1836 be_enqueue_preds(node);
1843 * Enters all transform functions into the generic pointer
1845 static void arm_register_transformers(void)
1847 be_start_transform_setup();
1849 be_set_transform_function(op_Add, gen_Add);
1850 be_set_transform_function(op_And, gen_And);
1851 be_set_transform_function(op_Call, gen_Call);
1852 be_set_transform_function(op_Cmp, gen_Cmp);
1853 be_set_transform_function(op_Cond, gen_Cond);
1854 be_set_transform_function(op_Const, gen_Const);
1855 be_set_transform_function(op_Conv, gen_Conv);
1856 be_set_transform_function(op_CopyB, gen_CopyB);
1857 be_set_transform_function(op_Eor, gen_Eor);
1858 be_set_transform_function(op_Jmp, gen_Jmp);
1859 be_set_transform_function(op_Load, gen_Load);
1860 be_set_transform_function(op_Minus, gen_Minus);
1861 be_set_transform_function(op_Mul, gen_Mul);
1862 be_set_transform_function(op_Not, gen_Not);
1863 be_set_transform_function(op_Or, gen_Or);
1864 be_set_transform_function(op_Phi, gen_Phi);
1865 be_set_transform_function(op_Proj, gen_Proj);
1866 be_set_transform_function(op_Quot, gen_Quot);
1867 be_set_transform_function(op_Return, gen_Return);
1868 be_set_transform_function(op_Rotl, gen_Rotl);
1869 be_set_transform_function(op_Sel, gen_Sel);
1870 be_set_transform_function(op_Shl, gen_Shl);
1871 be_set_transform_function(op_Shr, gen_Shr);
1872 be_set_transform_function(op_Shrs, gen_Shrs);
1873 be_set_transform_function(op_Start, gen_Start);
1874 be_set_transform_function(op_Store, gen_Store);
1875 be_set_transform_function(op_Sub, gen_Sub);
1876 be_set_transform_function(op_SymConst, gen_SymConst);
1877 be_set_transform_function(op_Unknown, gen_Unknown);
1881 * Initialize fpa Immediate support.
1883 static void arm_init_fpa_immediate(void)
1885 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
1886 fpa_imm[0][fpa_null] = get_mode_null(mode_F);
1887 fpa_imm[0][fpa_one] = get_mode_one(mode_F);
1888 fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
1889 fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
1890 fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
1891 fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
1892 fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
1893 fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
1895 fpa_imm[1][fpa_null] = get_mode_null(mode_D);
1896 fpa_imm[1][fpa_one] = get_mode_one(mode_D);
1897 fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
1898 fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
1899 fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
1900 fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
1901 fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
1902 fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
1904 fpa_imm[2][fpa_null] = get_mode_null(mode_E);
1905 fpa_imm[2][fpa_one] = get_mode_one(mode_E);
1906 fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
1907 fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
1908 fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
1909 fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
1910 fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
1911 fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
1915 * Transform a Firm graph into an ARM graph.
1917 void arm_transform_graph(arm_code_gen_t *cg)
1919 static int imm_initialized = 0;
1920 ir_graph *irg = cg->irg;
1921 ir_entity *entity = get_irg_entity(irg);
1922 ir_type *frame_type;
1927 if (! imm_initialized) {
1928 arm_init_fpa_immediate();
1929 imm_initialized = 1;
1931 arm_register_transformers();
1934 node_to_stack = pmap_create();
1936 assert(abihelper == NULL);
1937 abihelper = be_abihelper_prepare(irg);
1938 be_collect_stacknodes(abihelper);
1939 assert(cconv == NULL);
1940 cconv = decide_calling_convention(get_entity_type(entity));
1941 create_stacklayout(irg);
1943 be_transform_graph(cg->irg, NULL);
1945 be_abihelper_finish(abihelper);
1948 free_calling_convention(cconv);
1951 frame_type = get_irg_frame_type(irg);
1952 if (get_type_state(frame_type) == layout_undefined) {
1953 default_layout_compound_type(frame_type);
1956 pmap_destroy(node_to_stack);
1957 node_to_stack = NULL;
1959 be_add_missing_keeps(irg);
1962 void arm_init_transform(void)
1964 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");