2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
40 #include "../benode.h"
42 #include "../beutil.h"
43 #include "../betranshlp.h"
44 #include "../beabihelper.h"
47 #include "bearch_arm_t.h"
48 #include "arm_nodes_attr.h"
49 #include "arm_transform.h"
50 #include "arm_optimize.h"
51 #include "arm_new_nodes.h"
52 #include "arm_map_regs.h"
53 #include "arm_cconv.h"
55 #include "gen_arm_regalloc_if.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static const arch_register_t *sp_reg = &arm_registers[REG_SP];
62 static ir_mode *mode_gp;
63 static ir_mode *mode_fp;
64 static beabi_helper_env_t *abihelper;
65 static calling_convention_t *cconv = NULL;
66 static arm_isa_t *isa;
68 static pmap *node_to_stack;
70 static bool mode_needs_gp_reg(ir_mode *mode)
72 return mode_is_int(mode) || mode_is_reference(mode);
76 * create firm graph for a constant
78 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
85 /* We only have 8 bit immediates. So we possibly have to combine several
86 * operations to construct the desired value.
88 * we can either create the value by adding bits to 0 or by removing bits
89 * from an register with all bits set. Try which alternative needs fewer
91 arm_gen_vals_from_word(value, &v);
92 arm_gen_vals_from_word(~value, &vn);
96 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
98 for (cnt = 1; cnt < vn.ops; ++cnt) {
99 result = new_bd_arm_Bic_imm(dbgi, block, result,
100 vn.values[cnt], vn.rors[cnt]);
104 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
106 for (cnt = 1; cnt < v.ops; ++cnt) {
107 result = new_bd_arm_Or_imm(dbgi, block, result,
108 v.values[cnt], v.rors[cnt]);
115 * Create a DAG constructing a given Const.
117 * @param irn a Firm const
119 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
121 ir_tarval *tv = get_Const_tarval(irn);
122 ir_mode *mode = get_tarval_mode(tv);
125 if (mode_is_reference(mode)) {
126 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
127 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
128 tv = tarval_convert_to(tv, mode_Iu);
130 value = get_tarval_long(tv);
131 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
135 * Create an And that will zero out upper bits.
137 * @param dbgi debug info
138 * @param block the basic block
139 * @param op the original node
140 * param src_bits number of lower bits that will remain
142 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
146 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
147 } else if (src_bits == 16) {
148 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
149 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
152 panic("zero extension only supported for 8 and 16 bits");
157 * Generate code for a sign extension.
159 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
162 int shift_width = 32 - src_bits;
163 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
164 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
168 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
171 int bits = get_mode_size_bits(orig_mode);
175 if (mode_is_signed(orig_mode)) {
176 return gen_sign_extension(dbgi, block, op, bits);
178 return gen_zero_extension(dbgi, block, op, bits);
183 * returns true if it is assured, that the upper bits of a node are "clean"
184 * which means for a 16 or 8 bit value, that the upper bits in the register
185 * are 0 for unsigned and a copy of the last significant bit for signed
188 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
190 (void) transformed_node;
197 * Transforms a Conv node.
199 * @return The created ia32 Conv node
201 static ir_node *gen_Conv(ir_node *node)
203 ir_node *block = be_transform_node(get_nodes_block(node));
204 ir_node *op = get_Conv_op(node);
205 ir_node *new_op = be_transform_node(op);
206 ir_mode *src_mode = get_irn_mode(op);
207 ir_mode *dst_mode = get_irn_mode(node);
208 dbg_info *dbg = get_irn_dbg_info(node);
210 if (src_mode == dst_mode)
213 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
215 if (mode_is_float(src_mode)) {
216 if (mode_is_float(dst_mode)) {
217 /* from float to float */
218 return new_bd_arm_Mvf(dbg, block, new_op, dst_mode);
220 /* from float to int */
224 /* from int to float */
225 if (!mode_is_signed(src_mode)) {
228 return new_bd_arm_FltX(dbg, block, new_op, dst_mode);
231 } else if (USE_VFP(isa)) {
232 panic("VFP not supported yet");
234 panic("Softfloat not supported yet");
236 } else { /* complete in gp registers */
237 int src_bits = get_mode_size_bits(src_mode);
238 int dst_bits = get_mode_size_bits(dst_mode);
242 if (src_bits == dst_bits) {
243 /* kill unnecessary conv */
247 if (src_bits < dst_bits) {
255 if (upper_bits_clean(new_op, min_mode)) {
259 if (mode_is_signed(min_mode)) {
260 return gen_sign_extension(dbg, block, new_op, min_bits);
262 return gen_zero_extension(dbg, block, new_op, min_bits);
272 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
274 unsigned val, low_pos, high_pos;
279 val = get_tarval_long(get_Const_tarval(node));
291 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
293 So we determine the smallest even position with a bit set
294 and the highest even position with no bit set anymore.
295 If the difference between these 2 is <= 8, then we can encode the value
298 low_pos = ntz(val) & ~1u;
299 high_pos = (32-nlz(val)+1) & ~1u;
301 if (high_pos - low_pos <= 8) {
302 res->imm_8 = val >> low_pos;
303 res->rot = 32 - low_pos;
308 res->rot = 34 - high_pos;
309 val = val >> (32-res->rot) | val << (res->rot);
319 static bool is_downconv(const ir_node *node)
327 /* we only want to skip the conv when we're the only user
328 * (not optimal but for now...)
330 if (get_irn_n_edges(node) > 1)
333 src_mode = get_irn_mode(get_Conv_op(node));
334 dest_mode = get_irn_mode(node);
336 mode_needs_gp_reg(src_mode) &&
337 mode_needs_gp_reg(dest_mode) &&
338 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
341 static ir_node *arm_skip_downconv(ir_node *node)
343 while (is_downconv(node))
344 node = get_Conv_op(node);
350 MATCH_COMMUTATIVE = 1 << 0, /**< commutative node */
351 MATCH_REVERSE = 1 << 1, /**< support reverse opcode */
352 MATCH_SIZE_NEUTRAL = 1 << 2,
353 MATCH_SKIP_NOT = 1 << 3, /**< skip Not on ONE input */
355 ENUM_BITSET(match_flags_t)
358 * possible binop constructors.
360 typedef struct arm_binop_factory_t {
361 /** normal reg op reg operation. */
362 ir_node *(*new_binop_reg)(dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
363 /** normal reg op imm operation. */
364 ir_node *(*new_binop_imm)(dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
365 /** barrel shifter reg op (reg shift reg operation. */
366 ir_node *(*new_binop_reg_shift_reg)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *shift, arm_shift_modifier_t shift_modifier);
367 /** barrel shifter reg op (reg shift imm operation. */
368 ir_node *(*new_binop_reg_shift_imm)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, arm_shift_modifier_t shift_modifier, unsigned shift_immediate);
369 } arm_binop_factory_t;
371 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
372 const arm_binop_factory_t *factory)
374 ir_node *block = be_transform_node(get_nodes_block(node));
375 ir_node *op1 = get_binop_left(node);
377 ir_node *op2 = get_binop_right(node);
379 dbg_info *dbgi = get_irn_dbg_info(node);
382 if (flags & MATCH_SKIP_NOT) {
384 op1 = get_Not_op(op1);
385 else if (is_Not(op2))
386 op2 = get_Not_op(op2);
388 panic("cannot execute MATCH_SKIP_NOT");
390 if (flags & MATCH_SIZE_NEUTRAL) {
391 op1 = arm_skip_downconv(op1);
392 op2 = arm_skip_downconv(op2);
394 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
397 if (try_encode_as_immediate(op2, &imm)) {
398 ir_node *new_op1 = be_transform_node(op1);
399 return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
401 new_op2 = be_transform_node(op2);
402 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && try_encode_as_immediate(op1, &imm)) {
403 if (flags & MATCH_REVERSE)
404 return factory[1].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
406 return factory[0].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
408 new_op1 = be_transform_node(op1);
410 /* check if we can fold in a Mov */
411 if (is_arm_Mov(new_op2)) {
412 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op2);
414 switch (attr->shift_modifier) {
416 case ARM_SHF_ASR_IMM:
417 case ARM_SHF_LSL_IMM:
418 case ARM_SHF_LSR_IMM:
419 case ARM_SHF_ROR_IMM:
420 if (factory->new_binop_reg_shift_imm) {
421 ir_node *mov_op = get_irn_n(new_op2, 0);
422 return factory->new_binop_reg_shift_imm(dbgi, block, new_op1, mov_op,
423 attr->shift_modifier, attr->shift_immediate);
427 case ARM_SHF_ASR_REG:
428 case ARM_SHF_LSL_REG:
429 case ARM_SHF_LSR_REG:
430 case ARM_SHF_ROR_REG:
431 if (factory->new_binop_reg_shift_reg) {
432 ir_node *mov_op = get_irn_n(new_op2, 0);
433 ir_node *mov_sft = get_irn_n(new_op2, 1);
434 return factory->new_binop_reg_shift_reg(dbgi, block, new_op1, mov_op, mov_sft,
435 attr->shift_modifier);
441 case ARM_SHF_INVALID:
442 panic("invalid shift");
445 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && is_arm_Mov(new_op1)) {
446 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op1);
447 int idx = flags & MATCH_REVERSE ? 1 : 0;
449 switch (attr->shift_modifier) {
450 ir_node *mov_op, *mov_sft;
453 case ARM_SHF_ASR_IMM:
454 case ARM_SHF_LSL_IMM:
455 case ARM_SHF_LSR_IMM:
456 case ARM_SHF_ROR_IMM:
457 if (factory[idx].new_binop_reg_shift_imm) {
458 mov_op = get_irn_n(new_op1, 0);
459 return factory[idx].new_binop_reg_shift_imm(dbgi, block, new_op2, mov_op,
460 attr->shift_modifier, attr->shift_immediate);
464 case ARM_SHF_ASR_REG:
465 case ARM_SHF_LSL_REG:
466 case ARM_SHF_LSR_REG:
467 case ARM_SHF_ROR_REG:
468 if (factory[idx].new_binop_reg_shift_reg) {
469 mov_op = get_irn_n(new_op1, 0);
470 mov_sft = get_irn_n(new_op1, 1);
471 return factory[idx].new_binop_reg_shift_reg(dbgi, block, new_op2, mov_op, mov_sft,
472 attr->shift_modifier);
479 case ARM_SHF_INVALID:
480 panic("invalid shift");
483 return factory->new_binop_reg(dbgi, block, new_op1, new_op2);
487 * Creates an ARM Add.
489 * @return the created arm Add node
491 static ir_node *gen_Add(ir_node *node)
493 static const arm_binop_factory_t add_factory = {
496 new_bd_arm_Add_reg_shift_reg,
497 new_bd_arm_Add_reg_shift_imm
500 ir_mode *mode = get_irn_mode(node);
502 if (mode_is_float(mode)) {
503 ir_node *block = be_transform_node(get_nodes_block(node));
504 ir_node *op1 = get_Add_left(node);
505 ir_node *op2 = get_Add_right(node);
506 dbg_info *dbgi = get_irn_dbg_info(node);
507 ir_node *new_op1 = be_transform_node(op1);
508 ir_node *new_op2 = be_transform_node(op2);
510 return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
511 } else if (USE_VFP(isa)) {
512 assert(mode != mode_E && "IEEE Extended FP not supported");
513 panic("VFP not supported yet");
515 panic("Softfloat not supported yet");
520 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
522 new_op2 = get_irn_n(new_op1, 1);
523 new_op1 = get_irn_n(new_op1, 0);
525 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
527 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
529 new_op1 = get_irn_n(new_op2, 0);
530 new_op2 = get_irn_n(new_op2, 1);
532 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
536 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &add_factory);
541 * Creates an ARM Mul.
543 * @return the created arm Mul node
545 static ir_node *gen_Mul(ir_node *node)
547 ir_node *block = be_transform_node(get_nodes_block(node));
548 ir_node *op1 = get_Mul_left(node);
549 ir_node *new_op1 = be_transform_node(op1);
550 ir_node *op2 = get_Mul_right(node);
551 ir_node *new_op2 = be_transform_node(op2);
552 ir_mode *mode = get_irn_mode(node);
553 dbg_info *dbg = get_irn_dbg_info(node);
555 if (mode_is_float(mode)) {
557 return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
558 } else if (USE_VFP(isa)) {
559 assert(mode != mode_E && "IEEE Extended FP not supported");
560 panic("VFP not supported yet");
562 panic("Softfloat not supported yet");
565 assert(mode_is_data(mode));
566 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
569 static ir_node *gen_Div(ir_node *node)
571 ir_node *block = be_transform_node(get_nodes_block(node));
572 ir_node *op1 = get_Div_left(node);
573 ir_node *new_op1 = be_transform_node(op1);
574 ir_node *op2 = get_Div_right(node);
575 ir_node *new_op2 = be_transform_node(op2);
576 ir_mode *mode = get_Div_resmode(node);
577 dbg_info *dbg = get_irn_dbg_info(node);
579 assert(mode != mode_E && "IEEE Extended FP not supported");
580 /* integer division should be replaced by builtin call */
581 assert(mode_is_float(mode));
584 return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
585 } else if (USE_VFP(isa)) {
586 assert(mode != mode_E && "IEEE Extended FP not supported");
587 panic("VFP not supported yet");
589 panic("Softfloat not supported yet");
593 static ir_node *gen_And(ir_node *node)
595 static const arm_binop_factory_t and_factory = {
598 new_bd_arm_And_reg_shift_reg,
599 new_bd_arm_And_reg_shift_imm
601 static const arm_binop_factory_t bic_factory = {
604 new_bd_arm_Bic_reg_shift_reg,
605 new_bd_arm_Bic_reg_shift_imm
608 /* check for and not */
609 ir_node *left = get_And_left(node);
610 ir_node *right = get_And_right(node);
612 if (is_Not(left) || is_Not(right)) {
613 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL | MATCH_SKIP_NOT,
617 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &and_factory);
620 static ir_node *gen_Or(ir_node *node)
622 static const arm_binop_factory_t or_factory = {
625 new_bd_arm_Or_reg_shift_reg,
626 new_bd_arm_Or_reg_shift_imm
629 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &or_factory);
632 static ir_node *gen_Eor(ir_node *node)
634 static const arm_binop_factory_t eor_factory = {
637 new_bd_arm_Eor_reg_shift_reg,
638 new_bd_arm_Eor_reg_shift_imm
641 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &eor_factory);
644 static ir_node *gen_Sub(ir_node *node)
646 static const arm_binop_factory_t sub_rsb_factory[2] = {
650 new_bd_arm_Sub_reg_shift_reg,
651 new_bd_arm_Sub_reg_shift_imm
656 new_bd_arm_Rsb_reg_shift_reg,
657 new_bd_arm_Rsb_reg_shift_imm
661 ir_node *block = be_transform_node(get_nodes_block(node));
662 ir_node *op1 = get_Sub_left(node);
663 ir_node *new_op1 = be_transform_node(op1);
664 ir_node *op2 = get_Sub_right(node);
665 ir_node *new_op2 = be_transform_node(op2);
666 ir_mode *mode = get_irn_mode(node);
667 dbg_info *dbgi = get_irn_dbg_info(node);
669 if (mode_is_float(mode)) {
671 return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
672 } else if (USE_VFP(isa)) {
673 assert(mode != mode_E && "IEEE Extended FP not supported");
674 panic("VFP not supported yet");
676 panic("Softfloat not supported yet");
679 return gen_int_binop(node, MATCH_SIZE_NEUTRAL | MATCH_REVERSE, sub_rsb_factory);
684 * Checks if a given value can be used as an immediate for the given
687 static bool can_use_shift_constant(unsigned int val,
688 arm_shift_modifier_t modifier)
692 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
698 * generate an ARM shift instruction.
700 * @param node the node
701 * @param flags matching flags
702 * @param shift_modifier initial encoding of the desired shift operation
704 static ir_node *make_shift(ir_node *node, match_flags_t flags,
705 arm_shift_modifier_t shift_modifier)
707 ir_node *block = be_transform_node(get_nodes_block(node));
708 ir_node *op1 = get_binop_left(node);
709 ir_node *op2 = get_binop_right(node);
710 dbg_info *dbgi = get_irn_dbg_info(node);
714 if (flags & MATCH_SIZE_NEUTRAL) {
715 op1 = arm_skip_downconv(op1);
716 op2 = arm_skip_downconv(op2);
719 new_op1 = be_transform_node(op1);
721 ir_tarval *tv = get_Const_tarval(op2);
722 unsigned int val = get_tarval_long(tv);
723 assert(tarval_is_long(tv));
724 if (can_use_shift_constant(val, shift_modifier)) {
725 switch (shift_modifier) {
726 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
727 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
728 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
729 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
730 default: panic("unexpected shift modifier");
732 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
733 shift_modifier, val);
737 new_op2 = be_transform_node(op2);
738 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
742 static ir_node *gen_Shl(ir_node *node)
744 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
747 static ir_node *gen_Shr(ir_node *node)
749 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
752 static ir_node *gen_Shrs(ir_node *node)
754 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
757 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
759 ir_node *block = be_transform_node(get_nodes_block(node));
760 ir_node *new_op1 = be_transform_node(op1);
761 dbg_info *dbgi = get_irn_dbg_info(node);
762 ir_node *new_op2 = be_transform_node(op2);
764 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
768 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
770 ir_node *block = be_transform_node(get_nodes_block(node));
771 ir_node *new_op1 = be_transform_node(op1);
772 dbg_info *dbgi = get_irn_dbg_info(node);
773 ir_node *new_op2 = be_transform_node(op2);
775 /* Note: there is no Rol on arm, we have to use Ror */
776 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
777 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
781 static ir_node *gen_Rotl(ir_node *node)
783 ir_node *rotate = NULL;
784 ir_node *op1 = get_Rotl_left(node);
785 ir_node *op2 = get_Rotl_right(node);
787 /* Firm has only RotL, so we are looking for a right (op2)
788 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
789 that means we can create a RotR. */
792 ir_node *right = get_Add_right(op2);
793 if (is_Const(right)) {
794 ir_tarval *tv = get_Const_tarval(right);
795 ir_mode *mode = get_irn_mode(node);
796 long bits = get_mode_size_bits(mode);
797 ir_node *left = get_Add_left(op2);
799 if (is_Minus(left) &&
800 tarval_is_long(tv) &&
801 get_tarval_long(tv) == bits &&
803 rotate = gen_Ror(node, op1, get_Minus_op(left));
805 } else if (is_Sub(op2)) {
806 ir_node *left = get_Sub_left(op2);
807 if (is_Const(left)) {
808 ir_tarval *tv = get_Const_tarval(left);
809 ir_mode *mode = get_irn_mode(node);
810 long bits = get_mode_size_bits(mode);
811 ir_node *right = get_Sub_right(op2);
813 if (tarval_is_long(tv) &&
814 get_tarval_long(tv) == bits &&
816 rotate = gen_Ror(node, op1, right);
818 } else if (is_Const(op2)) {
819 ir_tarval *tv = get_Const_tarval(op2);
820 ir_mode *mode = get_irn_mode(node);
821 long bits = get_mode_size_bits(mode);
823 if (tarval_is_long(tv) && bits == 32) {
824 ir_node *block = be_transform_node(get_nodes_block(node));
825 ir_node *new_op1 = be_transform_node(op1);
826 dbg_info *dbgi = get_irn_dbg_info(node);
828 bits = (bits - get_tarval_long(tv)) & 31;
829 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
833 if (rotate == NULL) {
834 rotate = gen_Rol(node, op1, op2);
840 static ir_node *gen_Not(ir_node *node)
842 ir_node *block = be_transform_node(get_nodes_block(node));
843 ir_node *op = get_Not_op(node);
844 ir_node *new_op = be_transform_node(op);
845 dbg_info *dbgi = get_irn_dbg_info(node);
847 /* check if we can fold in a Mov */
848 if (is_arm_Mov(new_op)) {
849 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op);
851 switch (attr->shift_modifier) {
852 ir_node *mov_op, *mov_sft;
855 case ARM_SHF_ASR_IMM:
856 case ARM_SHF_LSL_IMM:
857 case ARM_SHF_LSR_IMM:
858 case ARM_SHF_ROR_IMM:
859 mov_op = get_irn_n(new_op, 0);
860 return new_bd_arm_Mvn_reg_shift_imm(dbgi, block, mov_op,
861 attr->shift_modifier, attr->shift_immediate);
863 case ARM_SHF_ASR_REG:
864 case ARM_SHF_LSL_REG:
865 case ARM_SHF_LSR_REG:
866 case ARM_SHF_ROR_REG:
867 mov_op = get_irn_n(new_op, 0);
868 mov_sft = get_irn_n(new_op, 1);
869 return new_bd_arm_Mvn_reg_shift_reg(dbgi, block, mov_op, mov_sft,
870 attr->shift_modifier);
875 case ARM_SHF_INVALID:
876 panic("invalid shift");
880 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
883 static ir_node *gen_Minus(ir_node *node)
885 ir_node *block = be_transform_node(get_nodes_block(node));
886 ir_node *op = get_Minus_op(node);
887 ir_node *new_op = be_transform_node(op);
888 dbg_info *dbgi = get_irn_dbg_info(node);
889 ir_mode *mode = get_irn_mode(node);
891 if (mode_is_float(mode)) {
893 return new_bd_arm_Mvf(dbgi, block, op, mode);
894 } else if (USE_VFP(isa)) {
895 assert(mode != mode_E && "IEEE Extended FP not supported");
896 panic("VFP not supported yet");
898 panic("Softfloat not supported yet");
901 assert(mode_is_data(mode));
902 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
905 static ir_node *gen_Load(ir_node *node)
907 ir_node *block = be_transform_node(get_nodes_block(node));
908 ir_node *ptr = get_Load_ptr(node);
909 ir_node *new_ptr = be_transform_node(ptr);
910 ir_node *mem = get_Load_mem(node);
911 ir_node *new_mem = be_transform_node(mem);
912 ir_mode *mode = get_Load_mode(node);
913 dbg_info *dbgi = get_irn_dbg_info(node);
914 ir_node *new_load = NULL;
916 if (get_Load_unaligned(node) == align_non_aligned)
917 panic("arm: unaligned Loads not supported yet");
919 if (mode_is_float(mode)) {
921 new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
923 } else if (USE_VFP(isa)) {
924 assert(mode != mode_E && "IEEE Extended FP not supported");
925 panic("VFP not supported yet");
927 panic("Softfloat not supported yet");
930 assert(mode_is_data(mode) && "unsupported mode for Load");
932 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
934 set_irn_pinned(new_load, get_irn_pinned(node));
936 /* check for special case: the loaded value might not be used */
937 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
938 /* add a result proj and a Keep to produce a pseudo use */
939 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
940 be_new_Keep(block, 1, &proj);
946 static ir_node *gen_Store(ir_node *node)
948 ir_node *block = be_transform_node(get_nodes_block(node));
949 ir_node *ptr = get_Store_ptr(node);
950 ir_node *new_ptr = be_transform_node(ptr);
951 ir_node *mem = get_Store_mem(node);
952 ir_node *new_mem = be_transform_node(mem);
953 ir_node *val = get_Store_value(node);
954 ir_node *new_val = be_transform_node(val);
955 ir_mode *mode = get_irn_mode(val);
956 dbg_info *dbgi = get_irn_dbg_info(node);
957 ir_node *new_store = NULL;
959 if (get_Store_unaligned(node) == align_non_aligned)
960 panic("arm: unaligned Stores not supported yet");
962 if (mode_is_float(mode)) {
964 new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
965 new_mem, mode, NULL, 0, 0, false);
966 } else if (USE_VFP(isa)) {
967 assert(mode != mode_E && "IEEE Extended FP not supported");
968 panic("VFP not supported yet");
970 panic("Softfloat not supported yet");
973 assert(mode_is_data(mode) && "unsupported mode for Store");
974 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
977 set_irn_pinned(new_store, get_irn_pinned(node));
981 static ir_node *gen_Jmp(ir_node *node)
983 ir_node *block = get_nodes_block(node);
984 ir_node *new_block = be_transform_node(block);
985 dbg_info *dbgi = get_irn_dbg_info(node);
987 return new_bd_arm_Jmp(dbgi, new_block);
990 static ir_node *gen_SwitchJmp(ir_node *node)
992 ir_node *block = be_transform_node(get_nodes_block(node));
993 ir_node *selector = get_Cond_selector(node);
994 dbg_info *dbgi = get_irn_dbg_info(node);
995 ir_node *new_op = be_transform_node(selector);
996 ir_node *const_graph;
1000 const ir_edge_t *edge;
1007 foreach_out_edge(node, edge) {
1008 proj = get_edge_src_irn(edge);
1009 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1011 pn = get_Proj_proj(proj);
1013 min = pn<min ? pn : min;
1014 max = pn>max ? pn : max;
1017 n_projs = max - translation + 1;
1019 foreach_out_edge(node, edge) {
1020 proj = get_edge_src_irn(edge);
1021 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1023 pn = get_Proj_proj(proj) - translation;
1024 set_Proj_proj(proj, pn);
1027 const_graph = create_const_graph_value(dbgi, block, translation);
1028 sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
1029 return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
1032 static ir_node *gen_Cmp(ir_node *node)
1034 ir_node *block = be_transform_node(get_nodes_block(node));
1035 ir_node *op1 = get_Cmp_left(node);
1036 ir_node *op2 = get_Cmp_right(node);
1037 ir_mode *cmp_mode = get_irn_mode(op1);
1038 dbg_info *dbgi = get_irn_dbg_info(node);
1043 if (mode_is_float(cmp_mode)) {
1044 /* TODO: this is broken... */
1045 new_op1 = be_transform_node(op1);
1046 new_op2 = be_transform_node(op2);
1048 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
1051 assert(get_irn_mode(op2) == cmp_mode);
1052 is_unsigned = !mode_is_signed(cmp_mode);
1054 /* integer compare, TODO: use shifter_op in all its combinations */
1055 new_op1 = be_transform_node(op1);
1056 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
1057 new_op2 = be_transform_node(op2);
1058 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
1059 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
1063 static ir_node *gen_Cond(ir_node *node)
1065 ir_node *selector = get_Cond_selector(node);
1066 ir_mode *mode = get_irn_mode(selector);
1067 ir_relation relation;
1072 if (mode != mode_b) {
1073 return gen_SwitchJmp(node);
1075 assert(is_Cmp(selector));
1077 block = be_transform_node(get_nodes_block(node));
1078 dbgi = get_irn_dbg_info(node);
1079 flag_node = be_transform_node(selector);
1080 relation = get_Cmp_relation(selector);
1082 return new_bd_arm_B(dbgi, block, flag_node, relation);
1088 FPA_IMM_EXTENDED = 2,
1089 FPA_IMM_MAX = FPA_IMM_EXTENDED
1092 static ir_tarval *fpa_imm[FPA_IMM_MAX + 1][fpa_max];
1096 * Check, if a floating point tarval is an fpa immediate, i.e.
1097 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
1099 static int is_fpa_immediate(tarval *tv)
1101 ir_mode *mode = get_tarval_mode(tv);
1104 switch (get_mode_size_bits(mode)) {
1112 i = FPA_IMM_EXTENDED;
1115 if (tarval_is_negative(tv)) {
1116 tv = tarval_neg(tv);
1120 for (j = 0; j < fpa_max; ++j) {
1121 if (tv == fpa_imm[i][j])
1128 static ir_node *gen_Const(ir_node *node)
1130 ir_node *block = be_transform_node(get_nodes_block(node));
1131 ir_mode *mode = get_irn_mode(node);
1132 dbg_info *dbg = get_irn_dbg_info(node);
1134 if (mode_is_float(mode)) {
1136 ir_tarval *tv = get_Const_tarval(node);
1137 node = new_bd_arm_fConst(dbg, block, tv);
1139 } else if (USE_VFP(isa)) {
1140 assert(mode != mode_E && "IEEE Extended FP not supported");
1141 panic("VFP not supported yet");
1143 panic("Softfloat not supported yet");
1146 return create_const_graph(node, block);
1149 static ir_node *gen_SymConst(ir_node *node)
1151 ir_node *block = be_transform_node(get_nodes_block(node));
1152 ir_entity *entity = get_SymConst_entity(node);
1153 dbg_info *dbgi = get_irn_dbg_info(node);
1156 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
1160 static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0,
1163 /* the good way to do this would be to use the stm (store multiple)
1164 * instructions, since our input is nearly always 2 consecutive 32bit
1166 ir_graph *irg = current_ir_graph;
1167 ir_node *stack = get_irg_frame(irg);
1168 ir_node *nomem = get_irg_no_mem(irg);
1169 ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp,
1171 ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp,
1173 ir_node *in[2] = { str0, str1 };
1174 ir_node *sync = new_r_Sync(block, 2, in);
1176 set_irn_pinned(str0, op_pin_state_floats);
1177 set_irn_pinned(str1, op_pin_state_floats);
1179 ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true);
1180 set_irn_pinned(ldf, op_pin_state_floats);
1182 return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1185 static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node)
1187 ir_graph *irg = current_ir_graph;
1188 ir_node *stack = get_irg_frame(irg);
1189 ir_node *nomem = get_irg_no_mem(irg);
1190 ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp,
1193 set_irn_pinned(str, op_pin_state_floats);
1195 ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true);
1196 set_irn_pinned(ldf, op_pin_state_floats);
1198 return new_r_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1201 static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node)
1203 ir_graph *irg = current_ir_graph;
1204 ir_node *stack = get_irg_frame(irg);
1205 ir_node *nomem = get_irg_no_mem(irg);
1206 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F,
1209 set_irn_pinned(stf, op_pin_state_floats);
1211 ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1212 set_irn_pinned(ldr, op_pin_state_floats);
1214 return new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1217 static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node,
1218 ir_node **out_value0, ir_node **out_value1)
1220 ir_graph *irg = current_ir_graph;
1221 ir_node *stack = get_irg_frame(irg);
1222 ir_node *nomem = get_irg_no_mem(irg);
1223 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D,
1225 ir_node *ldr0, *ldr1;
1226 set_irn_pinned(stf, op_pin_state_floats);
1228 ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1229 set_irn_pinned(ldr0, op_pin_state_floats);
1230 ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true);
1231 set_irn_pinned(ldr1, op_pin_state_floats);
1233 *out_value0 = new_r_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
1234 *out_value1 = new_r_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
1237 static ir_node *gen_CopyB(ir_node *node)
1239 ir_node *block = be_transform_node(get_nodes_block(node));
1240 ir_node *src = get_CopyB_src(node);
1241 ir_node *new_src = be_transform_node(src);
1242 ir_node *dst = get_CopyB_dst(node);
1243 ir_node *new_dst = be_transform_node(dst);
1244 ir_node *mem = get_CopyB_mem(node);
1245 ir_node *new_mem = be_transform_node(mem);
1246 dbg_info *dbg = get_irn_dbg_info(node);
1247 int size = get_type_size_bytes(get_CopyB_type(node));
1251 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
1252 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
1254 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1255 new_bd_arm_EmptyReg(dbg, block),
1256 new_bd_arm_EmptyReg(dbg, block),
1257 new_bd_arm_EmptyReg(dbg, block),
1262 * Transform builtin clz.
1264 static ir_node *gen_clz(ir_node *node)
1266 ir_node *block = be_transform_node(get_nodes_block(node));
1267 dbg_info *dbg = get_irn_dbg_info(node);
1268 ir_node *op = get_irn_n(node, 1);
1269 ir_node *new_op = be_transform_node(op);
1271 /* TODO armv5 instruction, otherwise create a call */
1272 return new_bd_arm_Clz(dbg, block, new_op);
1276 * Transform Builtin node.
1278 static ir_node *gen_Builtin(ir_node *node)
1280 ir_builtin_kind kind = get_Builtin_kind(node);
1284 case ir_bk_debugbreak:
1285 case ir_bk_return_address:
1286 case ir_bk_frame_address:
1287 case ir_bk_prefetch:
1291 return gen_clz(node);
1294 case ir_bk_popcount:
1298 case ir_bk_inner_trampoline:
1301 panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
1305 * Transform Proj(Builtin) node.
1307 static ir_node *gen_Proj_Builtin(ir_node *proj)
1309 ir_node *node = get_Proj_pred(proj);
1310 ir_node *new_node = be_transform_node(node);
1311 ir_builtin_kind kind = get_Builtin_kind(node);
1314 case ir_bk_return_address:
1315 case ir_bk_frame_address:
1320 case ir_bk_popcount:
1322 assert(get_Proj_proj(proj) == pn_Builtin_1_result);
1325 case ir_bk_debugbreak:
1326 case ir_bk_prefetch:
1328 assert(get_Proj_proj(proj) == pn_Builtin_M);
1331 case ir_bk_inner_trampoline:
1334 panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
1337 static ir_node *gen_Proj_Load(ir_node *node)
1339 ir_node *load = get_Proj_pred(node);
1340 ir_node *new_load = be_transform_node(load);
1341 dbg_info *dbgi = get_irn_dbg_info(node);
1342 long proj = get_Proj_proj(node);
1344 /* renumber the proj */
1345 switch (get_arm_irn_opcode(new_load)) {
1347 /* handle all gp loads equal: they have the same proj numbers. */
1348 if (proj == pn_Load_res) {
1349 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1350 } else if (proj == pn_Load_M) {
1351 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1355 if (proj == pn_Load_res) {
1356 ir_mode *mode = get_Load_mode(load);
1357 return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res);
1358 } else if (proj == pn_Load_M) {
1359 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M);
1365 panic("Unsupported Proj from Load");
1368 static ir_node *gen_Proj_CopyB(ir_node *node)
1370 ir_node *pred = get_Proj_pred(node);
1371 ir_node *new_pred = be_transform_node(pred);
1372 dbg_info *dbgi = get_irn_dbg_info(node);
1373 long proj = get_Proj_proj(node);
1377 if (is_arm_CopyB(new_pred)) {
1378 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1384 panic("Unsupported Proj from CopyB");
1387 static ir_node *gen_Proj_Div(ir_node *node)
1389 ir_node *pred = get_Proj_pred(node);
1390 ir_node *new_pred = be_transform_node(pred);
1391 dbg_info *dbgi = get_irn_dbg_info(node);
1392 ir_mode *mode = get_irn_mode(node);
1393 long proj = get_Proj_proj(node);
1397 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
1399 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
1403 panic("Unsupported Proj from Div");
1407 * Transform the Projs from a Cmp.
1409 static ir_node *gen_Proj_Cmp(ir_node *node)
1412 /* we should only be here in case of a Mux node */
1416 static ir_node *gen_Proj_Start(ir_node *node)
1418 ir_node *block = get_nodes_block(node);
1419 ir_node *new_block = be_transform_node(block);
1420 long proj = get_Proj_proj(node);
1422 switch ((pn_Start) proj) {
1423 case pn_Start_X_initial_exec:
1424 /* we exchange the ProjX with a jump */
1425 return new_bd_arm_Jmp(NULL, new_block);
1428 return be_prolog_get_memory(abihelper);
1430 case pn_Start_T_args:
1431 return new_r_Bad(get_irn_irg(block), mode_T);
1433 case pn_Start_P_frame_base:
1434 return be_prolog_get_reg_value(abihelper, sp_reg);
1436 panic("unexpected start proj: %ld\n", proj);
1439 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1441 long pn = get_Proj_proj(node);
1442 ir_node *block = get_nodes_block(node);
1443 ir_node *new_block = be_transform_node(block);
1444 ir_entity *entity = get_irg_entity(current_ir_graph);
1445 ir_type *method_type = get_entity_type(entity);
1446 ir_type *param_type = get_method_param_type(method_type, pn);
1447 const reg_or_stackslot_t *param;
1449 /* Proj->Proj->Start must be a method argument */
1450 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1452 param = &cconv->parameters[pn];
1454 if (param->reg0 != NULL) {
1455 /* argument transmitted in register */
1456 ir_mode *mode = get_type_mode(param_type);
1457 ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0);
1459 if (mode_is_float(mode)) {
1460 ir_node *value1 = NULL;
1462 if (param->reg1 != NULL) {
1463 value1 = be_prolog_get_reg_value(abihelper, param->reg1);
1464 } else if (param->entity != NULL) {
1465 ir_graph *irg = get_irn_irg(node);
1466 ir_node *fp = get_irg_frame(irg);
1467 ir_node *mem = be_prolog_get_memory(abihelper);
1468 ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem,
1469 mode_gp, param->entity,
1471 value1 = new_r_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1474 /* convert integer value to float */
1475 if (value1 == NULL) {
1476 value = int_to_float(NULL, new_block, value);
1478 value = ints_to_double(NULL, new_block, value, value1);
1483 /* argument transmitted on stack */
1484 ir_graph *irg = get_irn_irg(node);
1485 ir_node *fp = get_irg_frame(irg);
1486 ir_node *mem = be_prolog_get_memory(abihelper);
1487 ir_mode *mode = get_type_mode(param->type);
1491 if (mode_is_float(mode)) {
1492 load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode,
1493 param->entity, 0, 0, true);
1494 value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res);
1496 load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1497 param->entity, 0, 0, true);
1498 value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1500 set_irn_pinned(load, op_pin_state_floats);
1507 * Finds number of output value of a mode_T node which is constrained to
1508 * a single specific register.
1510 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1512 int n_outs = arch_irn_get_n_outs(node);
1515 for (o = 0; o < n_outs; ++o) {
1516 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1517 if (req == reg->single_req)
1523 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1525 long pn = get_Proj_proj(node);
1526 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1527 ir_node *new_call = be_transform_node(call);
1528 ir_type *function_type = get_Call_type(call);
1529 calling_convention_t *cconv
1530 = arm_decide_calling_convention(NULL, function_type);
1531 const reg_or_stackslot_t *res = &cconv->results[pn];
1535 /* TODO 64bit modes */
1536 assert(res->reg0 != NULL && res->reg1 == NULL);
1537 regn = find_out_for_reg(new_call, res->reg0);
1539 panic("Internal error in calling convention for return %+F", node);
1541 mode = res->reg0->reg_class->mode;
1543 arm_free_calling_convention(cconv);
1545 return new_r_Proj(new_call, mode, regn);
1548 static ir_node *gen_Proj_Call(ir_node *node)
1550 long pn = get_Proj_proj(node);
1551 ir_node *call = get_Proj_pred(node);
1552 ir_node *new_call = be_transform_node(call);
1554 switch ((pn_Call) pn) {
1556 return new_r_Proj(new_call, mode_M, 0);
1557 case pn_Call_X_regular:
1558 case pn_Call_X_except:
1559 case pn_Call_T_result:
1562 panic("Unexpected Call proj %ld\n", pn);
1566 * Transform a Proj node.
1568 static ir_node *gen_Proj(ir_node *node)
1570 ir_node *pred = get_Proj_pred(node);
1571 long proj = get_Proj_proj(node);
1573 switch (get_irn_opcode(pred)) {
1575 if (proj == pn_Store_M) {
1576 return be_transform_node(pred);
1578 panic("Unsupported Proj from Store");
1581 return gen_Proj_Load(node);
1583 return gen_Proj_Call(node);
1585 return gen_Proj_CopyB(node);
1587 return gen_Proj_Div(node);
1589 return gen_Proj_Cmp(node);
1591 return gen_Proj_Start(node);
1594 return be_duplicate_node(node);
1596 ir_node *pred_pred = get_Proj_pred(pred);
1597 if (is_Call(pred_pred)) {
1598 return gen_Proj_Proj_Call(node);
1599 } else if (is_Start(pred_pred)) {
1600 return gen_Proj_Proj_Start(node);
1605 return gen_Proj_Builtin(node);
1607 panic("code selection didn't expect Proj after %+F\n", pred);
1611 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1613 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
1614 create_const_node_func func,
1615 const arch_register_t* reg)
1617 ir_node *block, *res;
1622 block = get_irg_start_block(irg);
1623 res = func(NULL, block);
1624 arch_set_irn_register(res, reg);
1629 static ir_node *gen_Unknown(ir_node *node)
1631 ir_node *block = get_nodes_block(node);
1632 ir_node *new_block = be_transform_node(block);
1633 dbg_info *dbgi = get_irn_dbg_info(node);
1635 /* just produce a 0 */
1636 ir_mode *mode = get_irn_mode(node);
1637 if (mode_is_float(mode)) {
1638 ir_tarval *tv = get_mode_null(mode);
1639 ir_node *node = new_bd_arm_fConst(dbgi, new_block, tv);
1641 } else if (mode_needs_gp_reg(mode)) {
1642 return create_const_graph_value(dbgi, new_block, 0);
1645 panic("Unexpected Unknown mode");
1649 * Produces the type which sits between the stack args and the locals on the
1650 * stack. It will contain the return address and space to store the old base
1652 * @return The Firm type modeling the ABI between type.
1654 static ir_type *arm_get_between_type(void)
1656 static ir_type *between_type = NULL;
1658 if (between_type == NULL) {
1659 between_type = new_type_class(new_id_from_str("arm_between_type"));
1660 set_type_size_bytes(between_type, 0);
1663 return between_type;
1666 static void create_stacklayout(ir_graph *irg)
1668 ir_entity *entity = get_irg_entity(irg);
1669 ir_type *function_type = get_entity_type(entity);
1670 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1675 /* calling conventions must be decided by now */
1676 assert(cconv != NULL);
1678 /* construct argument type */
1679 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1680 n_params = get_method_n_params(function_type);
1681 for (p = 0; p < n_params; ++p) {
1682 reg_or_stackslot_t *param = &cconv->parameters[p];
1686 if (param->type == NULL)
1689 snprintf(buf, sizeof(buf), "param_%d", p);
1690 id = new_id_from_str(buf);
1691 param->entity = new_entity(arg_type, id, param->type);
1692 set_entity_offset(param->entity, param->offset);
1695 /* TODO: what about external functions? we don't know most of the stack
1696 * layout for them. And probably don't need all of this... */
1697 memset(layout, 0, sizeof(*layout));
1699 layout->frame_type = get_irg_frame_type(irg);
1700 layout->between_type = arm_get_between_type();
1701 layout->arg_type = arg_type;
1702 layout->param_map = NULL; /* TODO */
1703 layout->initial_offset = 0;
1704 layout->initial_bias = 0;
1705 layout->sp_relative = true;
1707 assert(N_FRAME_TYPES == 3);
1708 layout->order[0] = layout->frame_type;
1709 layout->order[1] = layout->between_type;
1710 layout->order[2] = layout->arg_type;
1714 * transform the start node to the prolog code
1716 static ir_node *gen_Start(ir_node *node)
1718 ir_graph *irg = get_irn_irg(node);
1719 ir_entity *entity = get_irg_entity(irg);
1720 ir_type *function_type = get_entity_type(entity);
1721 ir_node *block = get_nodes_block(node);
1722 ir_node *new_block = be_transform_node(block);
1723 dbg_info *dbgi = get_irn_dbg_info(node);
1727 /* stackpointer is important at function prolog */
1728 be_prolog_add_reg(abihelper, sp_reg,
1729 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1730 /* function parameters in registers */
1731 for (i = 0; i < get_method_n_params(function_type); ++i) {
1732 const reg_or_stackslot_t *param = &cconv->parameters[i];
1733 if (param->reg0 != NULL)
1734 be_prolog_add_reg(abihelper, param->reg0, arch_register_req_type_none);
1735 if (param->reg1 != NULL)
1736 be_prolog_add_reg(abihelper, param->reg1, arch_register_req_type_none);
1738 /* announce that we need the values of the callee save regs */
1739 for (i = 0; i < (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
1740 be_prolog_add_reg(abihelper, callee_saves[i], arch_register_req_type_none);
1743 start = be_prolog_create_start(abihelper, dbgi, new_block);
1747 static ir_node *get_stack_pointer_for(ir_node *node)
1749 /* get predecessor in stack_order list */
1750 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1753 if (stack_pred == NULL) {
1754 /* first stack user in the current block. We can simply use the
1755 * initial sp_proj for it */
1756 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1760 be_transform_node(stack_pred);
1761 stack = (ir_node*)pmap_get(node_to_stack, stack_pred);
1762 if (stack == NULL) {
1763 return get_stack_pointer_for(stack_pred);
1770 * transform a Return node into epilogue code + return statement
1772 static ir_node *gen_Return(ir_node *node)
1774 ir_node *block = get_nodes_block(node);
1775 ir_node *new_block = be_transform_node(block);
1776 dbg_info *dbgi = get_irn_dbg_info(node);
1777 ir_node *mem = get_Return_mem(node);
1778 ir_node *new_mem = be_transform_node(mem);
1779 int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
1780 ir_node *sp_proj = get_stack_pointer_for(node);
1781 int n_res = get_Return_n_ress(node);
1785 be_epilog_begin(abihelper);
1786 be_epilog_set_memory(abihelper, new_mem);
1787 /* connect stack pointer with initial stack pointer. fix_stack phase
1788 will later serialize all stack pointer adjusting nodes */
1789 be_epilog_add_reg(abihelper, sp_reg,
1790 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1794 for (i = 0; i < n_res; ++i) {
1795 ir_node *res_value = get_Return_res(node, i);
1796 ir_node *new_res_value = be_transform_node(res_value);
1797 const reg_or_stackslot_t *slot = &cconv->results[i];
1798 const arch_register_t *reg = slot->reg0;
1799 assert(slot->reg1 == NULL);
1800 be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, new_res_value);
1803 /* connect callee saves with their values at the function begin */
1804 for (i = 0; i < n_callee_saves; ++i) {
1805 const arch_register_t *reg = callee_saves[i];
1806 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1807 be_epilog_add_reg(abihelper, reg, arch_register_req_type_none, value);
1810 /* epilog code: an incsp */
1811 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1816 static ir_node *gen_Call(ir_node *node)
1818 ir_graph *irg = get_irn_irg(node);
1819 ir_node *callee = get_Call_ptr(node);
1820 ir_node *block = get_nodes_block(node);
1821 ir_node *new_block = be_transform_node(block);
1822 ir_node *mem = get_Call_mem(node);
1823 ir_node *new_mem = be_transform_node(mem);
1824 dbg_info *dbgi = get_irn_dbg_info(node);
1825 ir_type *type = get_Call_type(node);
1826 calling_convention_t *cconv = arm_decide_calling_convention(NULL, type);
1827 size_t n_params = get_Call_n_params(node);
1828 size_t n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
1829 /* max inputs: memory, callee, register arguments */
1830 int max_inputs = 2 + n_param_regs;
1831 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1832 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1833 struct obstack *obst = be_get_be_obst(irg);
1834 const arch_register_req_t **in_req
1835 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1839 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1840 ir_entity *entity = NULL;
1841 ir_node *incsp = NULL;
1848 assert(n_params == get_method_n_params(type));
1850 /* construct arguments */
1853 in_req[in_arity] = arch_no_register_req;
1857 for (p = 0; p < n_params; ++p) {
1858 ir_node *value = get_Call_param(node, p);
1859 ir_node *new_value = be_transform_node(value);
1860 ir_node *new_value1 = NULL;
1861 const reg_or_stackslot_t *param = &cconv->parameters[p];
1862 ir_type *param_type = get_method_param_type(type, p);
1863 ir_mode *mode = get_type_mode(param_type);
1866 if (mode_is_float(mode) && param->reg0 != NULL) {
1867 unsigned size_bits = get_mode_size_bits(mode);
1868 if (size_bits == 64) {
1869 double_to_ints(dbgi, new_block, new_value, &new_value,
1872 assert(size_bits == 32);
1873 new_value = float_to_int(dbgi, new_block, new_value);
1877 /* put value into registers */
1878 if (param->reg0 != NULL) {
1879 in[in_arity] = new_value;
1880 in_req[in_arity] = param->reg0->single_req;
1882 if (new_value1 == NULL)
1885 if (param->reg1 != NULL) {
1886 assert(new_value1 != NULL);
1887 in[in_arity] = new_value1;
1888 in_req[in_arity] = param->reg1->single_req;
1893 /* we need a store if we're here */
1894 if (new_value1 != NULL) {
1895 new_value = new_value1;
1899 /* create a parameter frame if necessary */
1900 if (incsp == NULL) {
1901 ir_node *new_frame = get_stack_pointer_for(node);
1902 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1903 cconv->param_stack_size, 1);
1905 if (mode_is_float(mode)) {
1906 str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem,
1907 mode, NULL, 0, param->offset, true);
1909 str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem,
1910 mode, NULL, 0, param->offset, true);
1912 sync_ins[sync_arity++] = str;
1914 assert(in_arity <= max_inputs);
1916 /* construct memory input */
1917 if (sync_arity == 0) {
1918 in[mem_pos] = new_mem;
1919 } else if (sync_arity == 1) {
1920 in[mem_pos] = sync_ins[0];
1922 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1925 /* TODO: use a generic symconst matcher here */
1926 if (is_SymConst(callee)) {
1927 entity = get_SymConst_entity(callee);
1929 /* TODO: finish load matcher here */
1932 if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) {
1933 ir_node *load = get_Proj_pred(callee);
1934 ir_node *ptr = get_Load_ptr(load);
1935 ir_node *new_ptr = be_transform_node(ptr);
1936 ir_node *mem = get_Load_mem(load);
1937 ir_node *new_mem = be_transform_node(mem);
1938 ir_mode *mode = get_Load_mode(node);
1942 in[in_arity] = be_transform_node(callee);
1943 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1952 out_arity = 1 + n_caller_saves;
1954 if (entity != NULL) {
1955 /* TODO: use a generic symconst matcher here
1956 * so we can also handle entity+offset, etc. */
1957 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1960 * - use a proper shifter_operand matcher
1961 * - we could also use LinkLdrPC
1963 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1967 if (incsp != NULL) {
1968 /* IncSP to destroy the call stackframe */
1969 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
1971 /* if we are the last IncSP producer in a block then we have to keep
1973 * Note: This here keeps all producers which is more than necessary */
1974 add_irn_dep(incsp, res);
1977 pmap_insert(node_to_stack, node, incsp);
1980 arch_set_in_register_reqs(res, in_req);
1982 /* create output register reqs */
1983 arch_set_out_register_req(res, 0, arch_no_register_req);
1984 for (o = 0; o < n_caller_saves; ++o) {
1985 const arch_register_t *reg = caller_saves[o];
1986 arch_set_out_register_req(res, o+1, reg->single_req);
1989 /* copy pinned attribute */
1990 set_irn_pinned(res, get_irn_pinned(node));
1992 arm_free_calling_convention(cconv);
1996 static ir_node *gen_Sel(ir_node *node)
1998 dbg_info *dbgi = get_irn_dbg_info(node);
1999 ir_node *block = get_nodes_block(node);
2000 ir_node *new_block = be_transform_node(block);
2001 ir_node *ptr = get_Sel_ptr(node);
2002 ir_node *new_ptr = be_transform_node(ptr);
2003 ir_entity *entity = get_Sel_entity(node);
2005 /* must be the frame pointer all other sels must have been lowered
2007 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
2008 /* we should not have value types from parameters anymore - they should be
2010 assert(get_entity_owner(entity) !=
2011 get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
2013 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
2017 * Change some phi modes
2019 static ir_node *gen_Phi(ir_node *node)
2021 const arch_register_req_t *req;
2022 ir_node *block = be_transform_node(get_nodes_block(node));
2023 ir_graph *irg = current_ir_graph;
2024 dbg_info *dbgi = get_irn_dbg_info(node);
2025 ir_mode *mode = get_irn_mode(node);
2028 if (mode_needs_gp_reg(mode)) {
2029 /* we shouldn't have any 64bit stuff around anymore */
2030 assert(get_mode_size_bits(mode) <= 32);
2031 /* all integer operations are on 32bit registers now */
2033 req = arm_reg_classes[CLASS_arm_gp].class_req;
2035 req = arch_no_register_req;
2038 /* phi nodes allow loops, so we use the old arguments for now
2039 * and fix this later */
2040 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
2041 get_irn_in(node) + 1);
2042 copy_node_attr(irg, node, phi);
2043 be_duplicate_deps(node, phi);
2045 arch_set_out_register_req(phi, 0, req);
2047 be_enqueue_preds(node);
2054 * Enters all transform functions into the generic pointer
2056 static void arm_register_transformers(void)
2058 be_start_transform_setup();
2060 be_set_transform_function(op_Add, gen_Add);
2061 be_set_transform_function(op_And, gen_And);
2062 be_set_transform_function(op_Call, gen_Call);
2063 be_set_transform_function(op_Cmp, gen_Cmp);
2064 be_set_transform_function(op_Cond, gen_Cond);
2065 be_set_transform_function(op_Const, gen_Const);
2066 be_set_transform_function(op_Conv, gen_Conv);
2067 be_set_transform_function(op_CopyB, gen_CopyB);
2068 be_set_transform_function(op_Div, gen_Div);
2069 be_set_transform_function(op_Eor, gen_Eor);
2070 be_set_transform_function(op_Jmp, gen_Jmp);
2071 be_set_transform_function(op_Load, gen_Load);
2072 be_set_transform_function(op_Minus, gen_Minus);
2073 be_set_transform_function(op_Mul, gen_Mul);
2074 be_set_transform_function(op_Not, gen_Not);
2075 be_set_transform_function(op_Or, gen_Or);
2076 be_set_transform_function(op_Phi, gen_Phi);
2077 be_set_transform_function(op_Proj, gen_Proj);
2078 be_set_transform_function(op_Return, gen_Return);
2079 be_set_transform_function(op_Rotl, gen_Rotl);
2080 be_set_transform_function(op_Sel, gen_Sel);
2081 be_set_transform_function(op_Shl, gen_Shl);
2082 be_set_transform_function(op_Shr, gen_Shr);
2083 be_set_transform_function(op_Shrs, gen_Shrs);
2084 be_set_transform_function(op_Start, gen_Start);
2085 be_set_transform_function(op_Store, gen_Store);
2086 be_set_transform_function(op_Sub, gen_Sub);
2087 be_set_transform_function(op_SymConst, gen_SymConst);
2088 be_set_transform_function(op_Unknown, gen_Unknown);
2089 be_set_transform_function(op_Builtin, gen_Builtin);
2093 * Initialize fpa Immediate support.
2095 static void arm_init_fpa_immediate(void)
2097 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
2098 fpa_imm[FPA_IMM_FLOAT][fpa_null] = get_mode_null(mode_F);
2099 fpa_imm[FPA_IMM_FLOAT][fpa_one] = get_mode_one(mode_F);
2100 fpa_imm[FPA_IMM_FLOAT][fpa_two] = new_tarval_from_str("2", 1, mode_F);
2101 fpa_imm[FPA_IMM_FLOAT][fpa_three] = new_tarval_from_str("3", 1, mode_F);
2102 fpa_imm[FPA_IMM_FLOAT][fpa_four] = new_tarval_from_str("4", 1, mode_F);
2103 fpa_imm[FPA_IMM_FLOAT][fpa_five] = new_tarval_from_str("5", 1, mode_F);
2104 fpa_imm[FPA_IMM_FLOAT][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
2105 fpa_imm[FPA_IMM_FLOAT][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
2107 fpa_imm[FPA_IMM_DOUBLE][fpa_null] = get_mode_null(mode_D);
2108 fpa_imm[FPA_IMM_DOUBLE][fpa_one] = get_mode_one(mode_D);
2109 fpa_imm[FPA_IMM_DOUBLE][fpa_two] = new_tarval_from_str("2", 1, mode_D);
2110 fpa_imm[FPA_IMM_DOUBLE][fpa_three] = new_tarval_from_str("3", 1, mode_D);
2111 fpa_imm[FPA_IMM_DOUBLE][fpa_four] = new_tarval_from_str("4", 1, mode_D);
2112 fpa_imm[FPA_IMM_DOUBLE][fpa_five] = new_tarval_from_str("5", 1, mode_D);
2113 fpa_imm[FPA_IMM_DOUBLE][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
2114 fpa_imm[FPA_IMM_DOUBLE][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
2116 fpa_imm[FPA_IMM_EXTENDED][fpa_null] = get_mode_null(mode_E);
2117 fpa_imm[FPA_IMM_EXTENDED][fpa_one] = get_mode_one(mode_E);
2118 fpa_imm[FPA_IMM_EXTENDED][fpa_two] = new_tarval_from_str("2", 1, mode_E);
2119 fpa_imm[FPA_IMM_EXTENDED][fpa_three] = new_tarval_from_str("3", 1, mode_E);
2120 fpa_imm[FPA_IMM_EXTENDED][fpa_four] = new_tarval_from_str("4", 1, mode_E);
2121 fpa_imm[FPA_IMM_EXTENDED][fpa_five] = new_tarval_from_str("5", 1, mode_E);
2122 fpa_imm[FPA_IMM_EXTENDED][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
2123 fpa_imm[FPA_IMM_EXTENDED][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
2127 * Transform a Firm graph into an ARM graph.
2129 void arm_transform_graph(ir_graph *irg)
2131 static int imm_initialized = 0;
2132 ir_entity *entity = get_irg_entity(irg);
2133 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
2134 ir_type *frame_type;
2139 if (! imm_initialized) {
2140 arm_init_fpa_immediate();
2141 imm_initialized = 1;
2143 arm_register_transformers();
2145 isa = (arm_isa_t*) arch_env;
2147 node_to_stack = pmap_create();
2149 assert(abihelper == NULL);
2150 abihelper = be_abihelper_prepare(irg);
2151 be_collect_stacknodes(abihelper);
2152 assert(cconv == NULL);
2153 cconv = arm_decide_calling_convention(irg, get_entity_type(entity));
2154 create_stacklayout(irg);
2156 be_transform_graph(irg, NULL);
2158 be_abihelper_finish(abihelper);
2161 arm_free_calling_convention(cconv);
2164 frame_type = get_irg_frame_type(irg);
2165 if (get_type_state(frame_type) == layout_undefined) {
2166 default_layout_compound_type(frame_type);
2169 pmap_destroy(node_to_stack);
2170 node_to_stack = NULL;
2172 be_add_missing_keeps(irg);
2175 void arm_init_transform(void)
2177 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");