2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenerator (transform FIRM into arm FIRM)
23 * @author Matthias Braun, Oliver Richter, Tobias Gneist, Michael Beck
29 #include "irgraph_t.h"
40 #include "../benode.h"
42 #include "../beutil.h"
43 #include "../betranshlp.h"
44 #include "../beabihelper.h"
47 #include "bearch_arm_t.h"
48 #include "arm_nodes_attr.h"
49 #include "arm_transform.h"
50 #include "arm_optimize.h"
51 #include "arm_new_nodes.h"
52 #include "arm_map_regs.h"
53 #include "arm_cconv.h"
55 #include "gen_arm_regalloc_if.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 /** hold the current code generator during transformation */
62 static arm_code_gen_t *env_cg;
64 static const arch_register_t *sp_reg = &arm_gp_regs[REG_SP];
65 static ir_mode *mode_gp;
66 static ir_mode *mode_fp;
67 static beabi_helper_env_t *abihelper;
68 static calling_convention_t *cconv = NULL;
70 static pmap *node_to_stack;
72 static bool mode_needs_gp_reg(ir_mode *mode)
74 return mode_is_int(mode) || mode_is_reference(mode);
78 * create firm graph for a constant
80 static ir_node *create_const_graph_value(dbg_info *dbgi, ir_node *block,
87 /* We only have 8 bit immediates. So we possibly have to combine several
88 * operations to construct the desired value.
90 * we can either create the value by adding bits to 0 or by removing bits
91 * from an register with all bits set. Try which alternative needs fewer
93 arm_gen_vals_from_word(value, &v);
94 arm_gen_vals_from_word(~value, &vn);
98 result = new_bd_arm_Mvn_imm(dbgi, block, vn.values[0], vn.rors[0]);
99 be_dep_on_frame(result);
101 for (cnt = 1; cnt < vn.ops; ++cnt) {
102 result = new_bd_arm_Bic_imm(dbgi, block, result,
103 vn.values[cnt], vn.rors[cnt]);
107 result = new_bd_arm_Mov_imm(dbgi, block, v.values[0], v.rors[0]);
108 be_dep_on_frame(result);
110 for (cnt = 1; cnt < v.ops; ++cnt) {
111 result = new_bd_arm_Or_imm(dbgi, block, result,
112 v.values[cnt], v.rors[cnt]);
119 * Create a DAG constructing a given Const.
121 * @param irn a Firm const
123 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
125 tarval *tv = get_Const_tarval(irn);
126 ir_mode *mode = get_tarval_mode(tv);
129 if (mode_is_reference(mode)) {
130 /* ARM is 32bit, so we can safely convert a reference tarval into Iu */
131 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Iu));
132 tv = tarval_convert_to(tv, mode_Iu);
134 value = get_tarval_long(tv);
135 return create_const_graph_value(get_irn_dbg_info(irn), block, value);
139 * Create an And that will zero out upper bits.
141 * @param dbgi debug info
142 * @param block the basic block
143 * @param op the original node
144 * param src_bits number of lower bits that will remain
146 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
150 return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
151 } else if (src_bits == 16) {
152 ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
153 ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
156 panic("zero extension only supported for 8 and 16 bits");
161 * Generate code for a sign extension.
163 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
166 int shift_width = 32 - src_bits;
167 ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
168 ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
172 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
175 int bits = get_mode_size_bits(orig_mode);
179 if (mode_is_signed(orig_mode)) {
180 return gen_sign_extension(dbgi, block, op, bits);
182 return gen_zero_extension(dbgi, block, op, bits);
187 * returns true if it is assured, that the upper bits of a node are "clean"
188 * which means for a 16 or 8 bit value, that the upper bits in the register
189 * are 0 for unsigned and a copy of the last significant bit for signed
192 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
194 (void) transformed_node;
201 * Transforms a Conv node.
203 * @return The created ia32 Conv node
205 static ir_node *gen_Conv(ir_node *node)
207 ir_node *block = be_transform_node(get_nodes_block(node));
208 ir_node *op = get_Conv_op(node);
209 ir_node *new_op = be_transform_node(op);
210 ir_mode *src_mode = get_irn_mode(op);
211 ir_mode *dst_mode = get_irn_mode(node);
212 dbg_info *dbg = get_irn_dbg_info(node);
214 if (src_mode == dst_mode)
217 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
218 if (USE_FPA(env_cg->isa)) {
219 if (mode_is_float(src_mode)) {
220 if (mode_is_float(dst_mode)) {
221 /* from float to float */
222 return new_bd_arm_Mvf(dbg, block, new_op, dst_mode);
224 /* from float to int */
228 /* from int to float */
229 if (!mode_is_signed(src_mode)) {
232 return new_bd_arm_FltX(dbg, block, new_op, dst_mode);
235 } else if (USE_VFP(env_cg->isa)) {
236 panic("VFP not supported yet");
238 panic("Softfloat not supported yet");
240 } else { /* complete in gp registers */
241 int src_bits = get_mode_size_bits(src_mode);
242 int dst_bits = get_mode_size_bits(dst_mode);
246 if (src_bits == dst_bits) {
247 /* kill unnecessary conv */
251 if (src_bits < dst_bits) {
259 if (upper_bits_clean(new_op, min_mode)) {
263 if (mode_is_signed(min_mode)) {
264 return gen_sign_extension(dbg, block, new_op, min_bits);
266 return gen_zero_extension(dbg, block, new_op, min_bits);
276 static bool try_encode_as_immediate(const ir_node *node, arm_immediate_t *res)
278 unsigned val, low_pos, high_pos;
283 val = get_tarval_long(get_Const_tarval(node));
295 /* arm allows to use to rotate an 8bit immediate value by a multiple of 2
297 So we determine the smallest even position with a bit set
298 and the highest even position with no bit set anymore.
299 If the difference between these 2 is <= 8, then we can encode the value
302 low_pos = ntz(val) & ~1u;
303 high_pos = (32-nlz(val)+1) & ~1u;
305 if (high_pos - low_pos <= 8) {
306 res->imm_8 = val >> low_pos;
307 res->rot = 32 - low_pos;
312 res->rot = 34 - high_pos;
313 val = val >> (32-res->rot) | val << (res->rot);
323 static bool is_downconv(const ir_node *node)
331 /* we only want to skip the conv when we're the only user
332 * (not optimal but for now...)
334 if (get_irn_n_edges(node) > 1)
337 src_mode = get_irn_mode(get_Conv_op(node));
338 dest_mode = get_irn_mode(node);
340 mode_needs_gp_reg(src_mode) &&
341 mode_needs_gp_reg(dest_mode) &&
342 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
345 static ir_node *arm_skip_downconv(ir_node *node)
347 while (is_downconv(node))
348 node = get_Conv_op(node);
354 MATCH_COMMUTATIVE = 1 << 0, /**< commutative node */
355 MATCH_REVERSE = 1 << 1, /**< support reverse opcode */
356 MATCH_SIZE_NEUTRAL = 1 << 2,
357 MATCH_SKIP_NOT = 1 << 3, /**< skip Not on ONE input */
361 * possible binop constructors.
363 typedef struct arm_binop_factory_t {
364 /** normal reg op reg operation. */
365 ir_node *(*new_binop_reg)(dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
366 /** normal reg op imm operation. */
367 ir_node *(*new_binop_imm)(dbg_info *dbgi, ir_node *block, ir_node *op1, unsigned char imm8, unsigned char imm_rot);
368 /** barrel shifter reg op (reg shift reg operation. */
369 ir_node *(*new_binop_reg_shift_reg)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *shift, arm_shift_modifier_t shift_modifier);
370 /** barrel shifter reg op (reg shift imm operation. */
371 ir_node *(*new_binop_reg_shift_imm)(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, arm_shift_modifier_t shift_modifier, unsigned shift_immediate);
372 } arm_binop_factory_t;
374 static ir_node *gen_int_binop(ir_node *node, match_flags_t flags,
375 const arm_binop_factory_t *factory)
377 ir_node *block = be_transform_node(get_nodes_block(node));
378 ir_node *op1 = get_binop_left(node);
380 ir_node *op2 = get_binop_right(node);
382 dbg_info *dbgi = get_irn_dbg_info(node);
385 if (flags & MATCH_SKIP_NOT) {
387 op1 = get_Not_op(op1);
388 else if (is_Not(op2))
389 op2 = get_Not_op(op2);
391 panic("cannot execute MATCH_SKIP_NOT");
393 if (flags & MATCH_SIZE_NEUTRAL) {
394 op1 = arm_skip_downconv(op1);
395 op2 = arm_skip_downconv(op2);
397 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
400 if (try_encode_as_immediate(op2, &imm)) {
401 ir_node *new_op1 = be_transform_node(op1);
402 return factory->new_binop_imm(dbgi, block, new_op1, imm.imm_8, imm.rot);
404 new_op2 = be_transform_node(op2);
405 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && try_encode_as_immediate(op1, &imm)) {
406 if (flags & MATCH_REVERSE)
407 return factory[1].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
409 return factory[0].new_binop_imm(dbgi, block, new_op2, imm.imm_8, imm.rot);
411 new_op1 = be_transform_node(op1);
413 /* check if we can fold in a Mov */
414 if (is_arm_Mov(new_op2)) {
415 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op2);
417 switch (attr->shift_modifier) {
419 case ARM_SHF_ASR_IMM:
420 case ARM_SHF_LSL_IMM:
421 case ARM_SHF_LSR_IMM:
422 case ARM_SHF_ROR_IMM:
423 if (factory->new_binop_reg_shift_imm) {
424 ir_node *mov_op = get_irn_n(new_op2, 0);
425 return factory->new_binop_reg_shift_imm(dbgi, block, new_op1, mov_op,
426 attr->shift_modifier, attr->shift_immediate);
430 case ARM_SHF_ASR_REG:
431 case ARM_SHF_LSL_REG:
432 case ARM_SHF_LSR_REG:
433 case ARM_SHF_ROR_REG:
434 if (factory->new_binop_reg_shift_reg) {
435 ir_node *mov_op = get_irn_n(new_op2, 0);
436 ir_node *mov_sft = get_irn_n(new_op2, 1);
437 return factory->new_binop_reg_shift_reg(dbgi, block, new_op1, mov_op, mov_sft,
438 attr->shift_modifier);
444 case ARM_SHF_INVALID:
445 panic("invalid shift");
448 if ((flags & (MATCH_COMMUTATIVE|MATCH_REVERSE)) && is_arm_Mov(new_op1)) {
449 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op1);
450 int idx = flags & MATCH_REVERSE ? 1 : 0;
452 switch (attr->shift_modifier) {
453 ir_node *mov_op, *mov_sft;
456 case ARM_SHF_ASR_IMM:
457 case ARM_SHF_LSL_IMM:
458 case ARM_SHF_LSR_IMM:
459 case ARM_SHF_ROR_IMM:
460 if (factory[idx].new_binop_reg_shift_imm) {
461 mov_op = get_irn_n(new_op1, 0);
462 return factory[idx].new_binop_reg_shift_imm(dbgi, block, new_op2, mov_op,
463 attr->shift_modifier, attr->shift_immediate);
467 case ARM_SHF_ASR_REG:
468 case ARM_SHF_LSL_REG:
469 case ARM_SHF_LSR_REG:
470 case ARM_SHF_ROR_REG:
471 if (factory[idx].new_binop_reg_shift_reg) {
472 mov_op = get_irn_n(new_op1, 0);
473 mov_sft = get_irn_n(new_op1, 1);
474 return factory[idx].new_binop_reg_shift_reg(dbgi, block, new_op2, mov_op, mov_sft,
475 attr->shift_modifier);
482 case ARM_SHF_INVALID:
483 panic("invalid shift");
486 return factory->new_binop_reg(dbgi, block, new_op1, new_op2);
490 * Creates an ARM Add.
492 * @return the created arm Add node
494 static ir_node *gen_Add(ir_node *node)
496 static const arm_binop_factory_t add_factory = {
499 new_bd_arm_Add_reg_shift_reg,
500 new_bd_arm_Add_reg_shift_imm
503 ir_mode *mode = get_irn_mode(node);
505 if (mode_is_float(mode)) {
506 ir_node *block = be_transform_node(get_nodes_block(node));
507 ir_node *op1 = get_Add_left(node);
508 ir_node *op2 = get_Add_right(node);
509 dbg_info *dbgi = get_irn_dbg_info(node);
510 ir_node *new_op1 = be_transform_node(op1);
511 ir_node *new_op2 = be_transform_node(op2);
512 if (USE_FPA(env_cg->isa)) {
513 return new_bd_arm_Adf(dbgi, block, new_op1, new_op2, mode);
514 } else if (USE_VFP(env_cg->isa)) {
515 assert(mode != mode_E && "IEEE Extended FP not supported");
516 panic("VFP not supported yet");
518 panic("Softfloat not supported yet");
523 if (is_arm_Mul(new_op1) && get_irn_n_edges(op1) == 1) {
525 new_op2 = get_irn_n(new_op1, 1);
526 new_op1 = get_irn_n(new_op1, 0);
528 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
530 if (is_arm_Mul(new_op2) && get_irn_n_edges(op2) == 1) {
532 new_op1 = get_irn_n(new_op2, 0);
533 new_op2 = get_irn_n(new_op2, 1);
535 return new_bd_arm_Mla(dbgi, block, new_op1, new_op2, new_op3);
539 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &add_factory);
544 * Creates an ARM Mul.
546 * @return the created arm Mul node
548 static ir_node *gen_Mul(ir_node *node)
550 ir_node *block = be_transform_node(get_nodes_block(node));
551 ir_node *op1 = get_Mul_left(node);
552 ir_node *new_op1 = be_transform_node(op1);
553 ir_node *op2 = get_Mul_right(node);
554 ir_node *new_op2 = be_transform_node(op2);
555 ir_mode *mode = get_irn_mode(node);
556 dbg_info *dbg = get_irn_dbg_info(node);
558 if (mode_is_float(mode)) {
559 if (USE_FPA(env_cg->isa)) {
560 return new_bd_arm_Muf(dbg, block, new_op1, new_op2, mode);
561 } else if (USE_VFP(env_cg->isa)) {
562 assert(mode != mode_E && "IEEE Extended FP not supported");
563 panic("VFP not supported yet");
565 panic("Softfloat not supported yet");
568 assert(mode_is_data(mode));
569 return new_bd_arm_Mul(dbg, block, new_op1, new_op2);
572 static ir_node *gen_Quot(ir_node *node)
574 ir_node *block = be_transform_node(get_nodes_block(node));
575 ir_node *op1 = get_Quot_left(node);
576 ir_node *new_op1 = be_transform_node(op1);
577 ir_node *op2 = get_Quot_right(node);
578 ir_node *new_op2 = be_transform_node(op2);
579 ir_mode *mode = get_irn_mode(node);
580 dbg_info *dbg = get_irn_dbg_info(node);
582 assert(mode != mode_E && "IEEE Extended FP not supported");
584 if (USE_FPA(env_cg->isa)) {
585 return new_bd_arm_Dvf(dbg, block, new_op1, new_op2, mode);
586 } else if (USE_VFP(env_cg->isa)) {
587 assert(mode != mode_E && "IEEE Extended FP not supported");
588 panic("VFP not supported yet");
590 panic("Softfloat not supported yet");
594 static ir_node *gen_And(ir_node *node)
596 static const arm_binop_factory_t and_factory = {
599 new_bd_arm_And_reg_shift_reg,
600 new_bd_arm_And_reg_shift_imm
602 static const arm_binop_factory_t bic_factory = {
605 new_bd_arm_Bic_reg_shift_reg,
606 new_bd_arm_Bic_reg_shift_imm
609 /* check for and not */
610 ir_node *left = get_And_left(node);
611 ir_node *right = get_And_right(node);
613 if (is_Not(left) || is_Not(right)) {
614 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL | MATCH_SKIP_NOT,
618 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &and_factory);
621 static ir_node *gen_Or(ir_node *node)
623 static const arm_binop_factory_t or_factory = {
626 new_bd_arm_Or_reg_shift_reg,
627 new_bd_arm_Or_reg_shift_imm
630 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &or_factory);
633 static ir_node *gen_Eor(ir_node *node)
635 static const arm_binop_factory_t eor_factory = {
638 new_bd_arm_Eor_reg_shift_reg,
639 new_bd_arm_Eor_reg_shift_imm
642 return gen_int_binop(node, MATCH_COMMUTATIVE | MATCH_SIZE_NEUTRAL, &eor_factory);
645 static ir_node *gen_Sub(ir_node *node)
647 static const arm_binop_factory_t sub_rsb_factory[2] = {
651 new_bd_arm_Sub_reg_shift_reg,
652 new_bd_arm_Sub_reg_shift_imm
657 new_bd_arm_Rsb_reg_shift_reg,
658 new_bd_arm_Rsb_reg_shift_imm
662 ir_node *block = be_transform_node(get_nodes_block(node));
663 ir_node *op1 = get_Sub_left(node);
664 ir_node *new_op1 = be_transform_node(op1);
665 ir_node *op2 = get_Sub_right(node);
666 ir_node *new_op2 = be_transform_node(op2);
667 ir_mode *mode = get_irn_mode(node);
668 dbg_info *dbgi = get_irn_dbg_info(node);
670 if (mode_is_float(mode)) {
671 if (USE_FPA(env_cg->isa)) {
672 return new_bd_arm_Suf(dbgi, block, new_op1, new_op2, mode);
673 } else if (USE_VFP(env_cg->isa)) {
674 assert(mode != mode_E && "IEEE Extended FP not supported");
675 panic("VFP not supported yet");
677 panic("Softfloat not supported yet");
680 return gen_int_binop(node, MATCH_SIZE_NEUTRAL | MATCH_REVERSE, sub_rsb_factory);
685 * Checks if a given value can be used as an immediate for the given
688 static bool can_use_shift_constant(unsigned int val,
689 arm_shift_modifier_t modifier)
693 if (val == 32 && modifier != ARM_SHF_LSL_REG && modifier != ARM_SHF_ROR_REG)
699 * generate an ARM shift instruction.
701 * @param node the node
702 * @param flags matching flags
703 * @param shift_modifier initial encoding of the desired shift operation
705 static ir_node *make_shift(ir_node *node, match_flags_t flags,
706 arm_shift_modifier_t shift_modifier)
708 ir_node *block = be_transform_node(get_nodes_block(node));
709 ir_node *op1 = get_binop_left(node);
710 ir_node *op2 = get_binop_right(node);
711 dbg_info *dbgi = get_irn_dbg_info(node);
715 if (flags & MATCH_SIZE_NEUTRAL) {
716 op1 = arm_skip_downconv(op1);
717 op2 = arm_skip_downconv(op2);
720 new_op1 = be_transform_node(op1);
722 tarval *tv = get_Const_tarval(op2);
723 unsigned int val = get_tarval_long(tv);
724 assert(tarval_is_long(tv));
725 if (can_use_shift_constant(val, shift_modifier)) {
726 switch (shift_modifier) {
727 case ARM_SHF_LSL_REG: shift_modifier = ARM_SHF_LSL_IMM; break;
728 case ARM_SHF_LSR_REG: shift_modifier = ARM_SHF_LSR_IMM; break;
729 case ARM_SHF_ASR_REG: shift_modifier = ARM_SHF_ASR_IMM; break;
730 case ARM_SHF_ROR_REG: shift_modifier = ARM_SHF_ROR_IMM; break;
731 default: panic("unexpected shift modifier");
733 return new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1,
734 shift_modifier, val);
738 new_op2 = be_transform_node(op2);
739 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
743 static ir_node *gen_Shl(ir_node *node)
745 return make_shift(node, MATCH_SIZE_NEUTRAL, ARM_SHF_LSL_REG);
748 static ir_node *gen_Shr(ir_node *node)
750 return make_shift(node, MATCH_NONE, ARM_SHF_LSR_REG);
753 static ir_node *gen_Shrs(ir_node *node)
755 return make_shift(node, MATCH_NONE, ARM_SHF_ASR_REG);
758 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
760 ir_node *block = be_transform_node(get_nodes_block(node));
761 ir_node *new_op1 = be_transform_node(op1);
762 dbg_info *dbgi = get_irn_dbg_info(node);
763 ir_node *new_op2 = be_transform_node(op2);
765 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
769 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
771 ir_node *block = be_transform_node(get_nodes_block(node));
772 ir_node *new_op1 = be_transform_node(op1);
773 dbg_info *dbgi = get_irn_dbg_info(node);
774 ir_node *new_op2 = be_transform_node(op2);
776 /* Note: there is no Rol on arm, we have to use Ror */
777 new_op2 = new_bd_arm_Rsb_imm(dbgi, block, new_op2, 32, 0);
778 return new_bd_arm_Mov_reg_shift_reg(dbgi, block, new_op1, new_op2,
782 static ir_node *gen_Rotl(ir_node *node)
784 ir_node *rotate = NULL;
785 ir_node *op1 = get_Rotl_left(node);
786 ir_node *op2 = get_Rotl_right(node);
788 /* Firm has only RotL, so we are looking for a right (op2)
789 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
790 that means we can create a RotR. */
793 ir_node *right = get_Add_right(op2);
794 if (is_Const(right)) {
795 tarval *tv = get_Const_tarval(right);
796 ir_mode *mode = get_irn_mode(node);
797 long bits = get_mode_size_bits(mode);
798 ir_node *left = get_Add_left(op2);
800 if (is_Minus(left) &&
801 tarval_is_long(tv) &&
802 get_tarval_long(tv) == bits &&
804 rotate = gen_Ror(node, op1, get_Minus_op(left));
806 } else if (is_Sub(op2)) {
807 ir_node *left = get_Sub_left(op2);
808 if (is_Const(left)) {
809 tarval *tv = get_Const_tarval(left);
810 ir_mode *mode = get_irn_mode(node);
811 long bits = get_mode_size_bits(mode);
812 ir_node *right = get_Sub_right(op2);
814 if (tarval_is_long(tv) &&
815 get_tarval_long(tv) == bits &&
817 rotate = gen_Ror(node, op1, right);
819 } else if (is_Const(op2)) {
820 tarval *tv = get_Const_tarval(op2);
821 ir_mode *mode = get_irn_mode(node);
822 long bits = get_mode_size_bits(mode);
824 if (tarval_is_long(tv) && bits == 32) {
825 ir_node *block = be_transform_node(get_nodes_block(node));
826 ir_node *new_op1 = be_transform_node(op1);
827 dbg_info *dbgi = get_irn_dbg_info(node);
829 bits = (bits - get_tarval_long(tv)) & 31;
830 rotate = new_bd_arm_Mov_reg_shift_imm(dbgi, block, new_op1, ARM_SHF_ROR_IMM, bits);
834 if (rotate == NULL) {
835 rotate = gen_Rol(node, op1, op2);
841 static ir_node *gen_Not(ir_node *node)
843 ir_node *block = be_transform_node(get_nodes_block(node));
844 ir_node *op = get_Not_op(node);
845 ir_node *new_op = be_transform_node(op);
846 dbg_info *dbgi = get_irn_dbg_info(node);
848 /* check if we can fold in a Mov */
849 if (is_arm_Mov(new_op)) {
850 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(new_op);
852 switch (attr->shift_modifier) {
853 ir_node *mov_op, *mov_sft;
856 case ARM_SHF_ASR_IMM:
857 case ARM_SHF_LSL_IMM:
858 case ARM_SHF_LSR_IMM:
859 case ARM_SHF_ROR_IMM:
860 mov_op = get_irn_n(new_op, 0);
861 return new_bd_arm_Mvn_reg_shift_imm(dbgi, block, mov_op,
862 attr->shift_modifier, attr->shift_immediate);
864 case ARM_SHF_ASR_REG:
865 case ARM_SHF_LSL_REG:
866 case ARM_SHF_LSR_REG:
867 case ARM_SHF_ROR_REG:
868 mov_op = get_irn_n(new_op, 0);
869 mov_sft = get_irn_n(new_op, 1);
870 return new_bd_arm_Mvn_reg_shift_reg(dbgi, block, mov_op, mov_sft,
871 attr->shift_modifier);
876 case ARM_SHF_INVALID:
877 panic("invalid shift");
881 return new_bd_arm_Mvn_reg(dbgi, block, new_op);
884 static ir_node *gen_Minus(ir_node *node)
886 ir_node *block = be_transform_node(get_nodes_block(node));
887 ir_node *op = get_Minus_op(node);
888 ir_node *new_op = be_transform_node(op);
889 dbg_info *dbgi = get_irn_dbg_info(node);
890 ir_mode *mode = get_irn_mode(node);
892 if (mode_is_float(mode)) {
893 if (USE_FPA(env_cg->isa)) {
894 return new_bd_arm_Mvf(dbgi, block, op, mode);
895 } else if (USE_VFP(env_cg->isa)) {
896 assert(mode != mode_E && "IEEE Extended FP not supported");
897 panic("VFP not supported yet");
899 panic("Softfloat not supported yet");
902 assert(mode_is_data(mode));
903 return new_bd_arm_Rsb_imm(dbgi, block, new_op, 0, 0);
906 static ir_node *gen_Load(ir_node *node)
908 ir_node *block = be_transform_node(get_nodes_block(node));
909 ir_node *ptr = get_Load_ptr(node);
910 ir_node *new_ptr = be_transform_node(ptr);
911 ir_node *mem = get_Load_mem(node);
912 ir_node *new_mem = be_transform_node(mem);
913 ir_mode *mode = get_Load_mode(node);
914 dbg_info *dbgi = get_irn_dbg_info(node);
915 ir_node *new_load = NULL;
917 if (mode_is_float(mode)) {
918 if (USE_FPA(env_cg->isa)) {
919 new_load = new_bd_arm_Ldf(dbgi, block, new_ptr, new_mem, mode,
921 } else if (USE_VFP(env_cg->isa)) {
922 assert(mode != mode_E && "IEEE Extended FP not supported");
923 panic("VFP not supported yet");
925 panic("Softfloat not supported yet");
928 assert(mode_is_data(mode) && "unsupported mode for Load");
930 new_load = new_bd_arm_Ldr(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
932 set_irn_pinned(new_load, get_irn_pinned(node));
934 /* check for special case: the loaded value might not be used */
935 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
936 /* add a result proj and a Keep to produce a pseudo use */
937 ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_arm_Ldr_res);
938 be_new_Keep(block, 1, &proj);
944 static ir_node *gen_Store(ir_node *node)
946 ir_node *block = be_transform_node(get_nodes_block(node));
947 ir_node *ptr = get_Store_ptr(node);
948 ir_node *new_ptr = be_transform_node(ptr);
949 ir_node *mem = get_Store_mem(node);
950 ir_node *new_mem = be_transform_node(mem);
951 ir_node *val = get_Store_value(node);
952 ir_node *new_val = be_transform_node(val);
953 ir_mode *mode = get_irn_mode(val);
954 dbg_info *dbgi = get_irn_dbg_info(node);
955 ir_node *new_store = NULL;
957 if (mode_is_float(mode)) {
958 if (USE_FPA(env_cg->isa)) {
959 new_store = new_bd_arm_Stf(dbgi, block, new_ptr, new_val,
960 new_mem, mode, NULL, 0, 0, false);
961 } else if (USE_VFP(env_cg->isa)) {
962 assert(mode != mode_E && "IEEE Extended FP not supported");
963 panic("VFP not supported yet");
965 panic("Softfloat not supported yet");
968 assert(mode_is_data(mode) && "unsupported mode for Store");
969 new_store = new_bd_arm_Str(dbgi, block, new_ptr, new_val, new_mem, mode,
972 set_irn_pinned(new_store, get_irn_pinned(node));
976 static ir_node *gen_Jmp(ir_node *node)
978 ir_node *block = get_nodes_block(node);
979 ir_node *new_block = be_transform_node(block);
980 dbg_info *dbgi = get_irn_dbg_info(node);
982 return new_bd_arm_Jmp(dbgi, new_block);
985 static ir_node *gen_SwitchJmp(ir_node *node)
987 ir_node *block = be_transform_node(get_nodes_block(node));
988 ir_node *selector = get_Cond_selector(node);
989 dbg_info *dbgi = get_irn_dbg_info(node);
990 ir_node *new_op = be_transform_node(selector);
991 ir_node *const_graph;
995 const ir_edge_t *edge;
1002 foreach_out_edge(node, edge) {
1003 proj = get_edge_src_irn(edge);
1004 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1006 pn = get_Proj_proj(proj);
1008 min = pn<min ? pn : min;
1009 max = pn>max ? pn : max;
1012 n_projs = max - translation + 1;
1014 foreach_out_edge(node, edge) {
1015 proj = get_edge_src_irn(edge);
1016 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1018 pn = get_Proj_proj(proj) - translation;
1019 set_Proj_proj(proj, pn);
1022 const_graph = create_const_graph_value(dbgi, block, translation);
1023 sub = new_bd_arm_Sub_reg(dbgi, block, new_op, const_graph);
1024 return new_bd_arm_SwitchJmp(dbgi, block, sub, n_projs, get_Cond_default_proj(node) - translation);
1027 static ir_node *gen_Cmp(ir_node *node)
1029 ir_node *block = be_transform_node(get_nodes_block(node));
1030 ir_node *op1 = get_Cmp_left(node);
1031 ir_node *op2 = get_Cmp_right(node);
1032 ir_mode *cmp_mode = get_irn_mode(op1);
1033 dbg_info *dbgi = get_irn_dbg_info(node);
1038 if (mode_is_float(cmp_mode)) {
1039 /* TODO: this is broken... */
1040 new_op1 = be_transform_node(op1);
1041 new_op2 = be_transform_node(op2);
1043 return new_bd_arm_Cmfe(dbgi, block, new_op1, new_op2, false);
1046 assert(get_irn_mode(op2) == cmp_mode);
1047 is_unsigned = !mode_is_signed(cmp_mode);
1049 /* integer compare, TODO: use shifter_op in all its combinations */
1050 new_op1 = be_transform_node(op1);
1051 new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
1052 new_op2 = be_transform_node(op2);
1053 new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
1054 return new_bd_arm_Cmp_reg(dbgi, block, new_op1, new_op2, false,
1058 static ir_node *gen_Cond(ir_node *node)
1060 ir_node *selector = get_Cond_selector(node);
1061 ir_mode *mode = get_irn_mode(selector);
1066 if (mode != mode_b) {
1067 return gen_SwitchJmp(node);
1069 assert(is_Proj(selector));
1071 block = be_transform_node(get_nodes_block(node));
1072 dbgi = get_irn_dbg_info(node);
1073 flag_node = be_transform_node(get_Proj_pred(selector));
1075 return new_bd_arm_B(dbgi, block, flag_node, get_Proj_proj(selector));
1078 static tarval *fpa_imm[3][fpa_max];
1082 * Check, if a floating point tarval is an fpa immediate, i.e.
1083 * one of 0, 1, 2, 3, 4, 5, 10, or 0.5.
1085 static int is_fpa_immediate(tarval *tv)
1087 ir_mode *mode = get_tarval_mode(tv);
1090 switch (get_mode_size_bits(mode)) {
1101 if (tarval_is_negative(tv)) {
1102 tv = tarval_neg(tv);
1106 for (j = 0; j < fpa_max; ++j) {
1107 if (tv == fpa_imm[i][j])
1114 static ir_node *gen_Const(ir_node *node)
1116 ir_node *block = be_transform_node(get_nodes_block(node));
1117 ir_mode *mode = get_irn_mode(node);
1118 dbg_info *dbg = get_irn_dbg_info(node);
1120 if (mode_is_float(mode)) {
1121 if (USE_FPA(env_cg->isa)) {
1122 tarval *tv = get_Const_tarval(node);
1123 node = new_bd_arm_fConst(dbg, block, tv);
1124 be_dep_on_frame(node);
1126 } else if (USE_VFP(env_cg->isa)) {
1127 assert(mode != mode_E && "IEEE Extended FP not supported");
1128 panic("VFP not supported yet");
1130 panic("Softfloat not supported yet");
1133 return create_const_graph(node, block);
1136 static ir_node *gen_SymConst(ir_node *node)
1138 ir_node *block = be_transform_node(get_nodes_block(node));
1139 ir_entity *entity = get_SymConst_entity(node);
1140 dbg_info *dbgi = get_irn_dbg_info(node);
1143 new_node = new_bd_arm_SymConst(dbgi, block, entity, 0);
1144 be_dep_on_frame(new_node);
1148 static ir_node *ints_to_double(dbg_info *dbgi, ir_node *block, ir_node *node0,
1151 /* the good way to do this would be to use the stm (store multiple)
1152 * instructions, since our input is nearly always 2 consecutive 32bit
1154 ir_graph *irg = current_ir_graph;
1155 ir_node *stack = get_irg_frame(irg);
1156 ir_node *nomem = new_NoMem();
1157 ir_node *str0 = new_bd_arm_Str(dbgi, block, stack, node0, nomem, mode_gp,
1159 ir_node *str1 = new_bd_arm_Str(dbgi, block, stack, node1, nomem, mode_gp,
1161 ir_node *in[2] = { str0, str1 };
1162 ir_node *sync = new_r_Sync(block, 2, in);
1164 set_irn_pinned(str0, op_pin_state_floats);
1165 set_irn_pinned(str1, op_pin_state_floats);
1167 ldf = new_bd_arm_Ldf(dbgi, block, stack, sync, mode_D, NULL, 0, 0, true);
1168 set_irn_pinned(ldf, op_pin_state_floats);
1170 return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1173 static ir_node *int_to_float(dbg_info *dbgi, ir_node *block, ir_node *node)
1175 ir_graph *irg = current_ir_graph;
1176 ir_node *stack = get_irg_frame(irg);
1177 ir_node *nomem = new_NoMem();
1178 ir_node *str = new_bd_arm_Str(dbgi, block, stack, node, nomem, mode_gp,
1181 set_irn_pinned(str, op_pin_state_floats);
1183 ldf = new_bd_arm_Ldf(dbgi, block, stack, str, mode_F, NULL, 0, 0, true);
1184 set_irn_pinned(ldf, op_pin_state_floats);
1186 return new_Proj(ldf, mode_fp, pn_arm_Ldf_res);
1189 static ir_node *float_to_int(dbg_info *dbgi, ir_node *block, ir_node *node)
1191 ir_graph *irg = current_ir_graph;
1192 ir_node *stack = get_irg_frame(irg);
1193 ir_node *nomem = new_NoMem();
1194 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_F,
1197 set_irn_pinned(stf, op_pin_state_floats);
1199 ldr = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1200 set_irn_pinned(ldr, op_pin_state_floats);
1202 return new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1205 static void double_to_ints(dbg_info *dbgi, ir_node *block, ir_node *node,
1206 ir_node **out_value0, ir_node **out_value1)
1208 ir_graph *irg = current_ir_graph;
1209 ir_node *stack = get_irg_frame(irg);
1210 ir_node *nomem = new_NoMem();
1211 ir_node *stf = new_bd_arm_Stf(dbgi, block, stack, node, nomem, mode_D,
1213 ir_node *ldr0, *ldr1;
1214 set_irn_pinned(stf, op_pin_state_floats);
1216 ldr0 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 0, true);
1217 set_irn_pinned(ldr0, op_pin_state_floats);
1218 ldr1 = new_bd_arm_Ldr(dbgi, block, stack, stf, mode_gp, NULL, 0, 4, true);
1219 set_irn_pinned(ldr1, op_pin_state_floats);
1221 *out_value0 = new_Proj(ldr0, mode_gp, pn_arm_Ldr_res);
1222 *out_value1 = new_Proj(ldr1, mode_gp, pn_arm_Ldr_res);
1225 static ir_node *gen_CopyB(ir_node *node)
1227 ir_node *block = be_transform_node(get_nodes_block(node));
1228 ir_node *src = get_CopyB_src(node);
1229 ir_node *new_src = be_transform_node(src);
1230 ir_node *dst = get_CopyB_dst(node);
1231 ir_node *new_dst = be_transform_node(dst);
1232 ir_node *mem = get_CopyB_mem(node);
1233 ir_node *new_mem = be_transform_node(mem);
1234 dbg_info *dbg = get_irn_dbg_info(node);
1235 int size = get_type_size_bytes(get_CopyB_type(node));
1239 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_src);
1240 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], block, new_dst);
1242 return new_bd_arm_CopyB(dbg, block, dst_copy, src_copy,
1243 new_bd_arm_EmptyReg(dbg, block),
1244 new_bd_arm_EmptyReg(dbg, block),
1245 new_bd_arm_EmptyReg(dbg, block),
1250 * Transform builtin clz.
1252 static ir_node *gen_clz(ir_node *node)
1254 ir_node *block = be_transform_node(get_nodes_block(node));
1255 dbg_info *dbg = get_irn_dbg_info(node);
1256 ir_node *op = get_irn_n(node, 1);
1257 ir_node *new_op = be_transform_node(op);
1259 /* TODO armv5 instruction, otherwise create a call */
1260 return new_bd_arm_Clz(dbg, block, new_op);
1264 * Transform Builtin node.
1266 static ir_node *gen_Builtin(ir_node *node)
1268 ir_builtin_kind kind = get_Builtin_kind(node);
1272 case ir_bk_debugbreak:
1273 case ir_bk_return_address:
1274 case ir_bk_frame_address:
1275 case ir_bk_prefetch:
1279 return gen_clz(node);
1282 case ir_bk_popcount:
1286 case ir_bk_inner_trampoline:
1289 panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
1293 * Transform Proj(Builtin) node.
1295 static ir_node *gen_Proj_Builtin(ir_node *proj)
1297 ir_node *node = get_Proj_pred(proj);
1298 ir_node *new_node = be_transform_node(node);
1299 ir_builtin_kind kind = get_Builtin_kind(node);
1302 case ir_bk_return_address:
1303 case ir_bk_frame_address:
1308 case ir_bk_popcount:
1310 assert(get_Proj_proj(proj) == pn_Builtin_1_result);
1313 case ir_bk_debugbreak:
1314 case ir_bk_prefetch:
1316 assert(get_Proj_proj(proj) == pn_Builtin_M);
1319 case ir_bk_inner_trampoline:
1322 panic("Builtin %s not implemented in ARM", get_builtin_kind_name(kind));
1325 static ir_node *gen_Proj_Load(ir_node *node)
1327 ir_node *load = get_Proj_pred(node);
1328 ir_node *new_load = be_transform_node(load);
1329 dbg_info *dbgi = get_irn_dbg_info(node);
1330 long proj = get_Proj_proj(node);
1332 /* renumber the proj */
1333 switch (get_arm_irn_opcode(new_load)) {
1335 /* handle all gp loads equal: they have the same proj numbers. */
1336 if (proj == pn_Load_res) {
1337 return new_rd_Proj(dbgi, new_load, mode_Iu, pn_arm_Ldr_res);
1338 } else if (proj == pn_Load_M) {
1339 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldr_M);
1343 if (proj == pn_Load_res) {
1344 ir_mode *mode = get_Load_mode(load);
1345 return new_rd_Proj(dbgi, new_load, mode, pn_arm_Ldf_res);
1346 } else if (proj == pn_Load_M) {
1347 return new_rd_Proj(dbgi, new_load, mode_M, pn_arm_Ldf_M);
1353 panic("Unsupported Proj from Load");
1356 static ir_node *gen_Proj_CopyB(ir_node *node)
1358 ir_node *pred = get_Proj_pred(node);
1359 ir_node *new_pred = be_transform_node(pred);
1360 dbg_info *dbgi = get_irn_dbg_info(node);
1361 long proj = get_Proj_proj(node);
1365 if (is_arm_CopyB(new_pred)) {
1366 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_CopyB_M);
1372 panic("Unsupported Proj from CopyB");
1375 static ir_node *gen_Proj_Quot(ir_node *node)
1377 ir_node *pred = get_Proj_pred(node);
1378 ir_node *new_pred = be_transform_node(pred);
1379 dbg_info *dbgi = get_irn_dbg_info(node);
1380 ir_mode *mode = get_irn_mode(node);
1381 long proj = get_Proj_proj(node);
1385 if (is_arm_Dvf(new_pred)) {
1386 return new_rd_Proj(dbgi, new_pred, mode_M, pn_arm_Dvf_M);
1390 if (is_arm_Dvf(new_pred)) {
1391 return new_rd_Proj(dbgi, new_pred, mode, pn_arm_Dvf_res);
1397 panic("Unsupported Proj from Quot");
1401 * Transform the Projs from a Cmp.
1403 static ir_node *gen_Proj_Cmp(ir_node *node)
1406 /* we should only be here in case of a Mux node */
1410 static ir_node *gen_Proj_Start(ir_node *node)
1412 ir_node *block = get_nodes_block(node);
1413 ir_node *new_block = be_transform_node(block);
1414 ir_node *barrier = be_transform_node(get_Proj_pred(node));
1415 long proj = get_Proj_proj(node);
1417 switch ((pn_Start) proj) {
1418 case pn_Start_X_initial_exec:
1419 /* we exchange the ProjX with a jump */
1420 return new_bd_arm_Jmp(NULL, new_block);
1423 return new_r_Proj(barrier, mode_M, 0);
1425 case pn_Start_T_args:
1428 case pn_Start_P_frame_base:
1429 return be_prolog_get_reg_value(abihelper, sp_reg);
1431 case pn_Start_P_tls:
1437 panic("unexpected start proj: %ld\n", proj);
1440 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1442 long pn = get_Proj_proj(node);
1443 ir_node *block = get_nodes_block(node);
1444 ir_node *new_block = be_transform_node(block);
1445 ir_entity *entity = get_irg_entity(current_ir_graph);
1446 ir_type *method_type = get_entity_type(entity);
1447 ir_type *param_type = get_method_param_type(method_type, pn);
1448 const reg_or_stackslot_t *param;
1450 /* Proj->Proj->Start must be a method argument */
1451 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1453 param = &cconv->parameters[pn];
1455 if (param->reg0 != NULL) {
1456 /* argument transmitted in register */
1457 ir_mode *mode = get_type_mode(param_type);
1458 ir_node *value = be_prolog_get_reg_value(abihelper, param->reg0);
1460 if (mode_is_float(mode)) {
1461 ir_node *value1 = NULL;
1463 if (param->reg1 != NULL) {
1464 value1 = be_prolog_get_reg_value(abihelper, param->reg1);
1465 } else if (param->entity != NULL) {
1466 ir_graph *irg = get_irn_irg(node);
1467 ir_node *fp = get_irg_frame(irg);
1468 ir_node *mem = be_prolog_get_memory(abihelper);
1469 ir_node *ldr = new_bd_arm_Ldr(NULL, new_block, fp, mem,
1470 mode_gp, param->entity,
1472 value1 = new_Proj(ldr, mode_gp, pn_arm_Ldr_res);
1475 /* convert integer value to float */
1476 if (value1 == NULL) {
1477 value = int_to_float(NULL, new_block, value);
1479 value = ints_to_double(NULL, new_block, value, value1);
1484 /* argument transmitted on stack */
1485 ir_graph *irg = get_irn_irg(node);
1486 ir_node *fp = get_irg_frame(irg);
1487 ir_node *mem = be_prolog_get_memory(abihelper);
1488 ir_mode *mode = get_type_mode(param->type);
1492 if (mode_is_float(mode)) {
1493 load = new_bd_arm_Ldf(NULL, new_block, fp, mem, mode,
1494 param->entity, 0, 0, true);
1495 value = new_r_Proj(load, mode_fp, pn_arm_Ldf_res);
1497 load = new_bd_arm_Ldr(NULL, new_block, fp, mem, mode,
1498 param->entity, 0, 0, true);
1499 value = new_r_Proj(load, mode_gp, pn_arm_Ldr_res);
1501 set_irn_pinned(load, op_pin_state_floats);
1508 * Finds number of output value of a mode_T node which is constrained to
1509 * a single specific register.
1511 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1513 int n_outs = arch_irn_get_n_outs(node);
1516 for (o = 0; o < n_outs; ++o) {
1517 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1518 if (req == reg->single_req)
1524 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1526 long pn = get_Proj_proj(node);
1527 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1528 ir_node *new_call = be_transform_node(call);
1529 ir_type *function_type = get_Call_type(call);
1530 calling_convention_t *cconv = arm_decide_calling_convention(function_type);
1531 const reg_or_stackslot_t *res = &cconv->results[pn];
1535 /* TODO 64bit modes */
1536 assert(res->reg0 != NULL && res->reg1 == NULL);
1537 regn = find_out_for_reg(new_call, res->reg0);
1539 panic("Internal error in calling convention for return %+F", node);
1541 mode = res->reg0->reg_class->mode;
1543 arm_free_calling_convention(cconv);
1545 return new_r_Proj(new_call, mode, regn);
1548 static ir_node *gen_Proj_Call(ir_node *node)
1550 long pn = get_Proj_proj(node);
1551 ir_node *call = get_Proj_pred(node);
1552 ir_node *new_call = be_transform_node(call);
1554 switch ((pn_Call) pn) {
1556 return new_r_Proj(new_call, mode_M, 0);
1557 case pn_Call_X_regular:
1558 case pn_Call_X_except:
1559 case pn_Call_T_result:
1560 case pn_Call_P_value_res_base:
1564 panic("Unexpected Call proj %ld\n", pn);
1568 * Transform a Proj node.
1570 static ir_node *gen_Proj(ir_node *node)
1572 ir_node *pred = get_Proj_pred(node);
1573 long proj = get_Proj_proj(node);
1575 switch (get_irn_opcode(pred)) {
1577 if (proj == pn_Store_M) {
1578 return be_transform_node(pred);
1580 panic("Unsupported Proj from Store");
1583 return gen_Proj_Load(node);
1585 return gen_Proj_Call(node);
1587 return gen_Proj_CopyB(node);
1589 return gen_Proj_Quot(node);
1591 return gen_Proj_Cmp(node);
1593 return gen_Proj_Start(node);
1596 return be_duplicate_node(node);
1598 ir_node *pred_pred = get_Proj_pred(pred);
1599 if (is_Call(pred_pred)) {
1600 return gen_Proj_Proj_Call(node);
1601 } else if (is_Start(pred_pred)) {
1602 return gen_Proj_Proj_Start(node);
1607 return gen_Proj_Builtin(node);
1609 panic("code selection didn't expect Proj after %+F\n", pred);
1613 typedef ir_node *(*create_const_node_func)(dbg_info *db, ir_node *block);
1615 static inline ir_node *create_const(ir_node **place,
1616 create_const_node_func func,
1617 const arch_register_t* reg)
1619 ir_node *block, *res;
1624 block = get_irg_start_block(env_cg->irg);
1625 res = func(NULL, block);
1626 arch_set_irn_register(res, reg);
1631 static ir_node *gen_Unknown(ir_node *node)
1633 ir_node *block = get_nodes_block(node);
1634 ir_node *new_block = be_transform_node(block);
1635 dbg_info *dbgi = get_irn_dbg_info(node);
1637 /* just produce a 0 */
1638 ir_mode *mode = get_irn_mode(node);
1639 if (mode_is_float(mode)) {
1640 tarval *tv = get_mode_null(mode);
1641 ir_node *node = new_bd_arm_fConst(dbgi, new_block, tv);
1642 be_dep_on_frame(node);
1644 } else if (mode_needs_gp_reg(mode)) {
1645 return create_const_graph_value(dbgi, new_block, 0);
1648 panic("Unexpected Unknown mode");
1652 * Produces the type which sits between the stack args and the locals on the
1653 * stack. It will contain the return address and space to store the old base
1655 * @return The Firm type modeling the ABI between type.
1657 static ir_type *arm_get_between_type(void)
1659 static ir_type *between_type = NULL;
1661 if (between_type == NULL) {
1662 between_type = new_type_class(new_id_from_str("arm_between_type"));
1663 set_type_size_bytes(between_type, 0);
1666 return between_type;
1669 static void create_stacklayout(ir_graph *irg)
1671 ir_entity *entity = get_irg_entity(irg);
1672 ir_type *function_type = get_entity_type(entity);
1673 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1678 /* calling conventions must be decided by now */
1679 assert(cconv != NULL);
1681 /* construct argument type */
1682 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1683 n_params = get_method_n_params(function_type);
1684 for (p = 0; p < n_params; ++p) {
1685 reg_or_stackslot_t *param = &cconv->parameters[p];
1689 if (param->type == NULL)
1692 snprintf(buf, sizeof(buf), "param_%d", p);
1693 id = new_id_from_str(buf);
1694 param->entity = new_entity(arg_type, id, param->type);
1695 set_entity_offset(param->entity, param->offset);
1698 /* TODO: what about external functions? we don't know most of the stack
1699 * layout for them. And probably don't need all of this... */
1700 memset(layout, 0, sizeof(*layout));
1702 layout->frame_type = get_irg_frame_type(irg);
1703 layout->between_type = arm_get_between_type();
1704 layout->arg_type = arg_type;
1705 layout->param_map = NULL; /* TODO */
1706 layout->initial_offset = 0;
1707 layout->initial_bias = 0;
1708 layout->stack_dir = -1;
1709 layout->sp_relative = true;
1711 assert(N_FRAME_TYPES == 3);
1712 layout->order[0] = layout->frame_type;
1713 layout->order[1] = layout->between_type;
1714 layout->order[2] = layout->arg_type;
1718 * transform the start node to the prolog code + initial barrier
1720 static ir_node *gen_Start(ir_node *node)
1722 ir_graph *irg = get_irn_irg(node);
1723 ir_entity *entity = get_irg_entity(irg);
1724 ir_type *function_type = get_entity_type(entity);
1725 ir_node *block = get_nodes_block(node);
1726 ir_node *new_block = be_transform_node(block);
1727 dbg_info *dbgi = get_irn_dbg_info(node);
1734 /* stackpointer is important at function prolog */
1735 be_prolog_add_reg(abihelper, sp_reg,
1736 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1737 /* function parameters in registers */
1738 for (i = 0; i < get_method_n_params(function_type); ++i) {
1739 const reg_or_stackslot_t *param = &cconv->parameters[i];
1740 if (param->reg0 != NULL)
1741 be_prolog_add_reg(abihelper, param->reg0, 0);
1742 if (param->reg1 != NULL)
1743 be_prolog_add_reg(abihelper, param->reg1, 0);
1745 /* announce that we need the values of the callee save regs */
1746 for (i = 0; i < (int) (sizeof(callee_saves)/sizeof(callee_saves[0])); ++i) {
1747 be_prolog_add_reg(abihelper, callee_saves[i], 0);
1750 start = be_prolog_create_start(abihelper, dbgi, new_block);
1751 sp = be_prolog_get_reg_value(abihelper, sp_reg);
1752 incsp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
1753 be_prolog_set_reg_value(abihelper, sp_reg, incsp);
1754 barrier = be_prolog_create_barrier(abihelper, new_block);
1759 static ir_node *get_stack_pointer_for(ir_node *node)
1761 /* get predecessor in stack_order list */
1762 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1763 ir_node *stack_pred_transformed;
1766 if (stack_pred == NULL) {
1767 /* first stack user in the current block. We can simply use the
1768 * initial sp_proj for it */
1769 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1773 stack_pred_transformed = be_transform_node(stack_pred);
1774 stack = pmap_get(node_to_stack, stack_pred);
1775 if (stack == NULL) {
1776 return get_stack_pointer_for(stack_pred);
1783 * transform a Return node into epilogue code + return statement
1785 static ir_node *gen_Return(ir_node *node)
1787 ir_node *block = get_nodes_block(node);
1788 ir_node *new_block = be_transform_node(block);
1789 dbg_info *dbgi = get_irn_dbg_info(node);
1790 ir_node *mem = get_Return_mem(node);
1791 ir_node *new_mem = be_transform_node(mem);
1792 int n_callee_saves = sizeof(callee_saves)/sizeof(callee_saves[0]);
1793 ir_node *sp_proj = get_stack_pointer_for(node);
1794 int n_res = get_Return_n_ress(node);
1799 be_epilog_begin(abihelper);
1800 be_epilog_set_memory(abihelper, new_mem);
1801 /* connect stack pointer with initial stack pointer. fix_stack phase
1802 will later serialize all stack pointer adjusting nodes */
1803 be_epilog_add_reg(abihelper, sp_reg,
1804 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1808 for (i = 0; i < n_res; ++i) {
1809 ir_node *res_value = get_Return_res(node, i);
1810 ir_node *new_res_value = be_transform_node(res_value);
1811 const reg_or_stackslot_t *slot = &cconv->results[i];
1812 const arch_register_t *reg = slot->reg0;
1813 assert(slot->reg1 == NULL);
1814 be_epilog_add_reg(abihelper, reg, 0, new_res_value);
1817 /* connect callee saves with their values at the function begin */
1818 for (i = 0; i < n_callee_saves; ++i) {
1819 const arch_register_t *reg = callee_saves[i];
1820 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1821 be_epilog_add_reg(abihelper, reg, 0, value);
1824 /* create the barrier before the epilog code */
1825 be_epilog_create_barrier(abihelper, new_block);
1827 /* epilog code: an incsp */
1828 sp_proj = be_epilog_get_reg_value(abihelper, sp_reg);
1829 incsp = be_new_IncSP(sp_reg, new_block, sp_proj,
1830 BE_STACK_FRAME_SIZE_SHRINK, 0);
1831 be_epilog_set_reg_value(abihelper, sp_reg, incsp);
1833 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1839 static ir_node *gen_Call(ir_node *node)
1841 ir_graph *irg = get_irn_irg(node);
1842 ir_node *callee = get_Call_ptr(node);
1843 ir_node *block = get_nodes_block(node);
1844 ir_node *new_block = be_transform_node(block);
1845 ir_node *mem = get_Call_mem(node);
1846 ir_node *new_mem = be_transform_node(mem);
1847 dbg_info *dbgi = get_irn_dbg_info(node);
1848 ir_type *type = get_Call_type(node);
1849 calling_convention_t *cconv = arm_decide_calling_convention(type);
1850 int n_params = get_Call_n_params(node);
1851 int n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
1852 /* max inputs: memory, callee, register arguments */
1853 int max_inputs = 2 + n_param_regs;
1854 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1855 ir_node **sync_ins = ALLOCAN(ir_node*, max_inputs);
1856 struct obstack *obst = be_get_be_obst(irg);
1857 const arch_register_req_t **in_req
1858 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1862 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1863 ir_entity *entity = NULL;
1864 ir_node *incsp = NULL;
1871 assert(n_params == get_method_n_params(type));
1873 /* construct arguments */
1876 in_req[in_arity] = arch_no_register_req;
1880 for (p = 0; p < n_params; ++p) {
1881 ir_node *value = get_Call_param(node, p);
1882 ir_node *new_value = be_transform_node(value);
1883 ir_node *new_value1 = NULL;
1884 const reg_or_stackslot_t *param = &cconv->parameters[p];
1885 ir_type *param_type = get_method_param_type(type, p);
1886 ir_mode *mode = get_type_mode(param_type);
1889 if (mode_is_float(mode) && param->reg0 != NULL) {
1890 unsigned size_bits = get_mode_size_bits(mode);
1891 if (size_bits == 64) {
1892 double_to_ints(dbgi, new_block, new_value, &new_value,
1895 assert(size_bits == 32);
1896 new_value = float_to_int(dbgi, new_block, new_value);
1900 /* put value into registers */
1901 if (param->reg0 != NULL) {
1902 in[in_arity] = new_value;
1903 in_req[in_arity] = param->reg0->single_req;
1905 if (new_value1 == NULL)
1908 if (param->reg1 != NULL) {
1909 assert(new_value1 != NULL);
1910 in[in_arity] = new_value1;
1911 in_req[in_arity] = param->reg1->single_req;
1916 /* we need a store if we're here */
1917 if (new_value1 != NULL) {
1918 new_value = new_value1;
1922 /* create a parameter frame if necessary */
1923 if (incsp == NULL) {
1924 ir_node *new_frame = get_stack_pointer_for(node);
1925 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1926 cconv->param_stack_size, 1);
1928 if (mode_is_float(mode)) {
1929 str = new_bd_arm_Stf(dbgi, new_block, incsp, new_value, new_mem,
1930 mode, NULL, 0, param->offset, true);
1932 str = new_bd_arm_Str(dbgi, new_block, incsp, new_value, new_mem,
1933 mode, NULL, 0, param->offset, true);
1935 sync_ins[sync_arity++] = str;
1937 assert(in_arity <= max_inputs);
1939 /* construct memory input */
1940 if (sync_arity == 0) {
1941 in[mem_pos] = new_mem;
1942 } else if (sync_arity == 1) {
1943 in[mem_pos] = sync_ins[0];
1945 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1948 /* TODO: use a generic symconst matcher here */
1949 if (is_SymConst(callee)) {
1950 entity = get_SymConst_entity(callee);
1952 /* TODO: finish load matcher here */
1955 if (is_Proj(callee) && is_Load(get_Proj_pred(callee))) {
1956 ir_node *load = get_Proj_pred(callee);
1957 ir_node *ptr = get_Load_ptr(load);
1958 ir_node *new_ptr = be_transform_node(ptr);
1959 ir_node *mem = get_Load_mem(load);
1960 ir_node *new_mem = be_transform_node(mem);
1961 ir_mode *mode = get_Load_mode(node);
1965 in[in_arity] = be_transform_node(callee);
1966 in_req[in_arity] = arm_reg_classes[CLASS_arm_gp].class_req;
1975 out_arity = 1 + n_caller_saves;
1977 if (entity != NULL) {
1978 /* TODO: use a generic symconst matcher here
1979 * so we can also handle entity+offset, etc. */
1980 res = new_bd_arm_Bl(dbgi, new_block, in_arity, in, out_arity,entity, 0);
1983 * - use a proper shifter_operand matcher
1984 * - we could also use LinkLdrPC
1986 res = new_bd_arm_LinkMovPC(dbgi, new_block, in_arity, in, out_arity,
1990 if (incsp != NULL) {
1991 /* IncSP to destroy the call stackframe */
1992 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size,
1994 /* if we are the last IncSP producer in a block then we have to keep
1996 * Note: This here keeps all producers which is more than necessary */
1997 add_irn_dep(incsp, res);
2000 pmap_insert(node_to_stack, node, incsp);
2003 arch_set_in_register_reqs(res, in_req);
2005 /* create output register reqs */
2006 arch_set_out_register_req(res, 0, arch_no_register_req);
2007 for (o = 0; o < n_caller_saves; ++o) {
2008 const arch_register_t *reg = caller_saves[o];
2009 arch_set_out_register_req(res, o+1, reg->single_req);
2012 /* copy pinned attribute */
2013 set_irn_pinned(res, get_irn_pinned(node));
2015 arm_free_calling_convention(cconv);
2019 static ir_node *gen_Sel(ir_node *node)
2021 dbg_info *dbgi = get_irn_dbg_info(node);
2022 ir_node *block = get_nodes_block(node);
2023 ir_node *new_block = be_transform_node(block);
2024 ir_node *ptr = get_Sel_ptr(node);
2025 ir_node *new_ptr = be_transform_node(ptr);
2026 ir_entity *entity = get_Sel_entity(node);
2028 /* must be the frame pointer all other sels must have been lowered
2030 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
2031 /* we should not have value types from parameters anymore - they should be
2033 assert(get_entity_owner(entity) !=
2034 get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
2036 return new_bd_arm_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
2040 * Change some phi modes
2042 static ir_node *gen_Phi(ir_node *node)
2044 const arch_register_req_t *req;
2045 ir_node *block = be_transform_node(get_nodes_block(node));
2046 ir_graph *irg = current_ir_graph;
2047 dbg_info *dbgi = get_irn_dbg_info(node);
2048 ir_mode *mode = get_irn_mode(node);
2051 if (mode_needs_gp_reg(mode)) {
2052 /* we shouldn't have any 64bit stuff around anymore */
2053 assert(get_mode_size_bits(mode) <= 32);
2054 /* all integer operations are on 32bit registers now */
2056 req = arm_reg_classes[CLASS_arm_gp].class_req;
2058 req = arch_no_register_req;
2061 /* phi nodes allow loops, so we use the old arguments for now
2062 * and fix this later */
2063 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
2064 get_irn_in(node) + 1);
2065 copy_node_attr(irg, node, phi);
2066 be_duplicate_deps(node, phi);
2068 arch_set_out_register_req(phi, 0, req);
2070 be_enqueue_preds(node);
2077 * Enters all transform functions into the generic pointer
2079 static void arm_register_transformers(void)
2081 be_start_transform_setup();
2083 be_set_transform_function(op_Add, gen_Add);
2084 be_set_transform_function(op_And, gen_And);
2085 be_set_transform_function(op_Call, gen_Call);
2086 be_set_transform_function(op_Cmp, gen_Cmp);
2087 be_set_transform_function(op_Cond, gen_Cond);
2088 be_set_transform_function(op_Const, gen_Const);
2089 be_set_transform_function(op_Conv, gen_Conv);
2090 be_set_transform_function(op_CopyB, gen_CopyB);
2091 be_set_transform_function(op_Eor, gen_Eor);
2092 be_set_transform_function(op_Jmp, gen_Jmp);
2093 be_set_transform_function(op_Load, gen_Load);
2094 be_set_transform_function(op_Minus, gen_Minus);
2095 be_set_transform_function(op_Mul, gen_Mul);
2096 be_set_transform_function(op_Not, gen_Not);
2097 be_set_transform_function(op_Or, gen_Or);
2098 be_set_transform_function(op_Phi, gen_Phi);
2099 be_set_transform_function(op_Proj, gen_Proj);
2100 be_set_transform_function(op_Quot, gen_Quot);
2101 be_set_transform_function(op_Return, gen_Return);
2102 be_set_transform_function(op_Rotl, gen_Rotl);
2103 be_set_transform_function(op_Sel, gen_Sel);
2104 be_set_transform_function(op_Shl, gen_Shl);
2105 be_set_transform_function(op_Shr, gen_Shr);
2106 be_set_transform_function(op_Shrs, gen_Shrs);
2107 be_set_transform_function(op_Start, gen_Start);
2108 be_set_transform_function(op_Store, gen_Store);
2109 be_set_transform_function(op_Sub, gen_Sub);
2110 be_set_transform_function(op_SymConst, gen_SymConst);
2111 be_set_transform_function(op_Unknown, gen_Unknown);
2112 be_set_transform_function(op_Builtin, gen_Builtin);
2116 * Initialize fpa Immediate support.
2118 static void arm_init_fpa_immediate(void)
2120 /* 0, 1, 2, 3, 4, 5, 10, or 0.5. */
2121 fpa_imm[0][fpa_null] = get_mode_null(mode_F);
2122 fpa_imm[0][fpa_one] = get_mode_one(mode_F);
2123 fpa_imm[0][fpa_two] = new_tarval_from_str("2", 1, mode_F);
2124 fpa_imm[0][fpa_three] = new_tarval_from_str("3", 1, mode_F);
2125 fpa_imm[0][fpa_four] = new_tarval_from_str("4", 1, mode_F);
2126 fpa_imm[0][fpa_five] = new_tarval_from_str("5", 1, mode_F);
2127 fpa_imm[0][fpa_ten] = new_tarval_from_str("10", 2, mode_F);
2128 fpa_imm[0][fpa_half] = new_tarval_from_str("0.5", 3, mode_F);
2130 fpa_imm[1][fpa_null] = get_mode_null(mode_D);
2131 fpa_imm[1][fpa_one] = get_mode_one(mode_D);
2132 fpa_imm[1][fpa_two] = new_tarval_from_str("2", 1, mode_D);
2133 fpa_imm[1][fpa_three] = new_tarval_from_str("3", 1, mode_D);
2134 fpa_imm[1][fpa_four] = new_tarval_from_str("4", 1, mode_D);
2135 fpa_imm[1][fpa_five] = new_tarval_from_str("5", 1, mode_D);
2136 fpa_imm[1][fpa_ten] = new_tarval_from_str("10", 2, mode_D);
2137 fpa_imm[1][fpa_half] = new_tarval_from_str("0.5", 3, mode_D);
2139 fpa_imm[2][fpa_null] = get_mode_null(mode_E);
2140 fpa_imm[2][fpa_one] = get_mode_one(mode_E);
2141 fpa_imm[2][fpa_two] = new_tarval_from_str("2", 1, mode_E);
2142 fpa_imm[2][fpa_three] = new_tarval_from_str("3", 1, mode_E);
2143 fpa_imm[2][fpa_four] = new_tarval_from_str("4", 1, mode_E);
2144 fpa_imm[2][fpa_five] = new_tarval_from_str("5", 1, mode_E);
2145 fpa_imm[2][fpa_ten] = new_tarval_from_str("10", 2, mode_E);
2146 fpa_imm[2][fpa_half] = new_tarval_from_str("0.5", 3, mode_E);
2150 * Transform a Firm graph into an ARM graph.
2152 void arm_transform_graph(arm_code_gen_t *cg)
2154 static int imm_initialized = 0;
2155 ir_graph *irg = cg->irg;
2156 ir_entity *entity = get_irg_entity(irg);
2157 ir_type *frame_type;
2162 if (! imm_initialized) {
2163 arm_init_fpa_immediate();
2164 imm_initialized = 1;
2166 arm_register_transformers();
2169 node_to_stack = pmap_create();
2171 assert(abihelper == NULL);
2172 abihelper = be_abihelper_prepare(irg);
2173 be_collect_stacknodes(abihelper);
2174 assert(cconv == NULL);
2175 cconv = arm_decide_calling_convention(get_entity_type(entity));
2176 create_stacklayout(irg);
2178 be_transform_graph(cg->irg, NULL);
2180 be_abihelper_finish(abihelper);
2183 arm_free_calling_convention(cconv);
2186 frame_type = get_irg_frame_type(irg);
2187 if (get_type_state(frame_type) == layout_undefined) {
2188 default_layout_compound_type(frame_type);
2191 pmap_destroy(node_to_stack);
2192 node_to_stack = NULL;
2194 be_add_missing_keeps(irg);
2197 void arm_init_transform(void)
2199 FIRM_DBG_REGISTER(dbg, "firm.be.arm.transform");