1 /* The codegenerator (transform FIRM into arm FIRM */
20 #include "../benode_t.h"
21 #include "bearch_arm_t.h"
23 #include "arm_nodes_attr.h"
24 #include "../arch/archop.h" /* we need this for Min and Max nodes */
25 #include "arm_transform.h"
26 #include "arm_new_nodes.h"
27 #include "arm_map_regs.h"
29 #include "gen_arm_regalloc_if.h"
34 extern ir_op *get_op_Mulh(void);
38 /****************************************************************************************************
40 * | | | | / _| | | (_)
41 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
42 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
43 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
44 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
46 ****************************************************************************************************/
48 typedef struct vals_ {
50 unsigned char values[4];
51 unsigned char shifts[4];
55 static unsigned do_rol(unsigned v, unsigned rol) {
56 return (v << rol) | (v >> (32 - rol));
60 * construct 8bit values und rot amounts for a value
62 static void gen_vals_from_word(unsigned int value, vals *result)
66 memset(result, 0, sizeof(*result));
68 /* special case: we prefer shift amount 0 */
70 result->values[0] = value;
77 unsigned v = do_rol(value, 8) & 0xFFFFFF;
86 shf = (initial + shf - 8) & 0x1F;
87 result->values[result->ops] = v;
88 result->shifts[result->ops] = shf;
91 value ^= do_rol(v, shf) >> initial;
101 * Creates a arm_Const node.
103 static ir_node *create_const_node(ir_node *irn, ir_node *block, long value) {
104 tarval *tv = new_tarval_from_long(value, mode_Iu);
105 dbg_info *dbg = get_irn_dbg_info(irn);
106 return new_rd_arm_Mov_i(dbg, current_ir_graph, block, get_irn_mode(irn), tv);
110 * Creates a arm_Const_Neg node.
112 static ir_node *create_const_neg_node(ir_node *irn, ir_node *block, long value) {
113 tarval *tv = new_tarval_from_long(value, mode_Iu);
114 dbg_info *dbg = get_irn_dbg_info(irn);
115 return new_rd_arm_Mvn_i(dbg, current_ir_graph, block, get_irn_mode(irn), tv);
118 #define NEW_BINOP_NODE(opname, env, op1, op2) new_rd_arm_##opname(env->dbg, current_ir_graph, env->block, op1, op2, env->mode)
121 * Encodes an immediate with shifter operand
123 static unsigned int arm_encode_imm_w_shift(unsigned int shift, unsigned int immediate) {
124 return immediate | ((shift>>1)<<8);
128 * Decode an immediate with shifter operand
130 unsigned int arm_decode_imm_w_shift(tarval *tv) {
131 unsigned l = get_tarval_long(tv);
132 unsigned rol = (l & ~0xFF) >> 7;
134 return do_rol(l & 0xFF, rol);
138 * Creates a possible DAG for an constant.
140 static ir_node *create_const_graph_value(ir_node *irn, ir_node *block, unsigned int value) {
145 ir_mode *mode = get_irn_mode(irn);
146 dbg_info *dbg = get_irn_dbg_info(irn);
148 gen_vals_from_word(value, &v);
149 gen_vals_from_word(~value, &vn);
151 if (vn.ops < v.ops) {
153 result = create_const_neg_node(irn, block, arm_encode_imm_w_shift(vn.shifts[0], vn.values[0]));
155 for (cnt = 1; cnt < vn.ops; ++cnt) {
156 tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(vn.shifts[cnt], vn.values[cnt]), mode_Iu);
157 ir_node *bic_i_node = new_rd_arm_Bic_i(dbg, current_ir_graph, block, result, mode, tv);
163 result = create_const_node(irn, block, arm_encode_imm_w_shift(v.shifts[0], v.values[0]));
165 for (cnt = 1; cnt < v.ops; ++cnt) {
166 tarval *tv = new_tarval_from_long(arm_encode_imm_w_shift(v.shifts[cnt], v.values[cnt]), mode_Iu);
167 ir_node *orr_i_node = new_rd_arm_Or_i(dbg, current_ir_graph, block, result, mode, tv);
175 * Create a DAG constructing a given Const.
177 * @param irn a Firm const
179 static ir_node *create_const_graph(ir_node *irn, ir_node *block) {
180 int value = get_tarval_long(get_Const_tarval(irn));
181 return create_const_graph_value(irn, block, value);
186 * Creates code for a Firm Const node.
188 static ir_node *gen_Const(ir_node *irn, arm_code_gen_t *cg) {
189 ir_graph *irg = current_ir_graph;
190 ir_node *block = get_nodes_block(irn);
191 ir_mode *mode = get_irn_mode(irn);
192 dbg_info *dbg = get_irn_dbg_info(irn);
194 if (mode_is_float(mode)) {
195 if (USE_FPA(cg->isa))
196 return new_rd_arm_fpaConst(dbg, irg, block, mode, get_Const_tarval(irn));
197 else if (USE_VFP(cg->isa))
198 assert(mode != mode_E && "IEEE Extended FP not supported");
201 else if (mode_is_reference(mode))
203 return create_const_graph(irn, block);
206 static ir_node *gen_mask(ir_node *irn, ir_node *op, int result_bits) {
207 ir_node *block = get_nodes_block(irn);
208 unsigned mask_bits = (1 << result_bits) - 1;
209 ir_node *mask_node = create_const_graph_value(irn, block, mask_bits);
210 dbg_info *dbg = get_irn_dbg_info(irn);
211 return new_rd_arm_And(dbg, current_ir_graph, block, op, mask_node, get_irn_mode(irn), ARM_SHF_NONE, NULL);
214 static ir_node *gen_sign_extension(ir_node *irn, ir_node *op, int result_bits) {
215 ir_node *block = get_nodes_block(irn);
216 int shift_width = 32 - result_bits;
217 ir_graph *irg = current_ir_graph;
218 ir_node *shift_const_node = create_const_graph_value(irn, block, shift_width);
219 dbg_info *dbg = get_irn_dbg_info(irn);
220 ir_node *lshift_node = new_rd_arm_Shl(dbg, irg, block, op, shift_const_node, get_irn_mode(op));
221 ir_node *rshift_node = new_rd_arm_Shrs(dbg, irg, block, lshift_node, shift_const_node, get_irn_mode(irn));
226 * Transforms a Conv node.
228 * @param env The transformation environment
229 * @return the created arm Conv node
231 static ir_node *gen_Conv(ir_node *irn, arm_code_gen_t *cg) {
232 ir_graph *irg = current_ir_graph;
233 ir_node *block = get_nodes_block(irn);
234 ir_node *op = get_Conv_op(irn);
235 ir_mode *in_mode = get_irn_mode(op);
236 ir_mode *out_mode = get_irn_mode(irn);
237 dbg_info *dbg = get_irn_dbg_info(irn);
239 if (in_mode == out_mode)
242 if (mode_is_float(in_mode) || mode_is_float(out_mode)) {
245 if (USE_FPA(cg->isa)) {
246 if (mode_is_float(in_mode)) {
247 if (mode_is_float(out_mode)) {
248 /* from float to float */
249 return new_rd_arm_fpaMov(dbg, irg, block, op, out_mode);
252 /* from float to int */
253 return new_rd_arm_fpaFix(dbg, irg, block, op, out_mode);
257 /* from int to float */
258 return new_rd_arm_fpaFlt(dbg, irg, block, op, out_mode);
263 else { /* complete in gp registers */
264 int in_bits = get_mode_size_bits(in_mode);
265 int out_bits = get_mode_size_bits(out_mode);
266 int in_sign = get_mode_sign(in_mode);
267 int out_sign = get_mode_sign(out_mode);
271 if (in_bits == out_bits && in_bits == 32)
275 // unsigned -> unsigned
277 // unsigned -> signed
278 // sign extension (31:16)=(15)
279 // signed -> unsigned
280 // maskieren (31:16)=0
283 if (in_bits == out_bits && out_bits < 32) {
284 if (in_sign && !out_sign) {
285 return gen_mask(irn, op, out_bits);
287 return gen_sign_extension(irn, op, out_bits);
292 // unsigned -> unsigned
294 // unsigned -> signed
296 // signed -> unsigned
297 // sign extension (31:16)=(15)
299 // sign extension (31:16)=(15)
300 if (in_bits < out_bits) {
302 return gen_sign_extension(irn, op, out_bits);
309 // unsigned -> unsigned
310 // maskieren (31:16)=0
311 // unsigned -> signed
312 // maskieren (31:16)=0
313 // signed -> unsigned
314 // maskieren (31:16)=0
316 // sign extension (erledigt auch maskieren) (31:16)=(15)
317 if (in_bits > out_bits) {
318 if (in_sign && out_sign) {
319 return gen_sign_extension(irn, op, out_bits);
321 return gen_mask(irn, op, out_bits);
324 assert(0 && "recheck integer conversion logic!");
331 * Return true if an operand is a shifter operand
333 static int is_shifter_operand(ir_node *n, arm_shift_modifier *pmod) {
334 arm_shift_modifier mod = ARM_SHF_NONE;
337 mod = get_arm_shift_modifier(n);
340 if (mod != ARM_SHF_NONE) {
341 long v = get_tarval_long(get_arm_value(n));
349 * Creates an arm Add.
351 * @param env The transformation environment
352 * @return the created arm Add node
354 static ir_node *gen_Add(ir_node *irn, arm_code_gen_t *cg) {
355 ir_node *block = get_nodes_block(irn);
356 ir_node *op1 = get_Add_left(irn);
357 ir_node *op2 = get_Add_right(irn);
358 ir_mode *mode = get_irn_mode(irn);
359 ir_graph *irg = current_ir_graph;
362 arm_shift_modifier mod;
363 dbg_info *dbg = get_irn_dbg_info(irn);
365 if (mode_is_float(mode)) {
367 if (USE_FPA(cg->isa))
368 return new_rd_arm_fpaAdd(dbg, irg, block, op1, op2, mode);
369 else if (USE_VFP(cg->isa)) {
370 assert(mode != mode_E && "IEEE Extended FP not supported");
374 if (mode_is_numP(mode)) {
375 if (is_arm_Mov_i(op1))
376 return new_rd_arm_Add_i(dbg, irg, block, op2, mode, get_arm_value(op1));
377 if (is_arm_Mov_i(op2))
378 return new_rd_arm_Add_i(dbg, irg, block, op1, mode, get_arm_value(op2));
381 if (is_arm_Mul(op1) && get_irn_n_edges(op1) == 1) {
383 op2 = get_irn_n(op1, 1);
384 op1 = get_irn_n(op1, 0);
386 return new_rd_arm_Mla(dbg, irg, block, op1, op2, op3, mode);
388 if (is_arm_Mul(op2) && get_irn_n_edges(op2) == 1) {
390 op1 = get_irn_n(op2, 0);
391 op2 = get_irn_n(op2, 1);
393 return new_rd_arm_Mla(dbg, irg, block, op1, op2, op3, mode);
396 /* is the first a shifter */
397 v = is_shifter_operand(op1, &mod);
399 op1 = get_irn_n(op1, 0);
400 return new_rd_arm_Add(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu));
402 /* is the second a shifter */
403 v = is_shifter_operand(op2, &mod);
405 op2 = get_irn_n(op2, 0);
406 return new_rd_arm_Add(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu));
410 return new_rd_arm_Add(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL);
413 assert(0 && "unknown mode for add");
418 * Creates an arm Mul.
420 * @param env The transformation environment
421 * @return the created arm Mul node
423 static ir_node *gen_Mul(ir_node *irn, arm_code_gen_t *cg) {
424 ir_node *block = get_nodes_block(irn);
425 ir_node *op1 = get_Mul_left(irn);
426 ir_node *op2 = get_Mul_right(irn);
427 ir_mode *mode = get_irn_mode(irn);
428 ir_graph *irg = current_ir_graph;
429 dbg_info *dbg = get_irn_dbg_info(irn);
431 if (mode_is_float(mode)) {
433 if (USE_FPA(cg->isa))
434 return new_rd_arm_fpaMul(dbg, irg, block, op1, op2, mode);
435 else if (USE_VFP(cg->isa)) {
436 assert(mode != mode_E && "IEEE Extended FP not supported");
440 return new_rd_arm_Mul(dbg, irg, block, op1, op2, mode);
444 * Creates an arm floating point Div.
446 * @param env The transformation environment
447 * @return the created arm fDiv node
449 static ir_node *gen_Quot(ir_node *irn, arm_code_gen_t *cg) {
450 ir_node *block = get_nodes_block(irn);
451 ir_node *op1 = get_Quot_left(irn);
452 ir_node *op2 = get_Quot_right(irn);
453 ir_mode *mode = get_irn_mode(irn);
454 dbg_info *dbg = get_irn_dbg_info(irn);
456 assert(mode != mode_E && "IEEE Extended FP not supported");
459 if (USE_FPA(cg->isa))
460 return new_rd_arm_fpaDiv(dbg, current_ir_graph, block, op1, op2, mode);
461 else if (USE_VFP(cg->isa)) {
462 assert(mode != mode_E && "IEEE Extended FP not supported");
469 #define GEN_INT_OP(op) \
470 static ir_node *gen_ ## op(ir_node *irn, arm_code_gen_t *cg) { \
471 ir_graph *irg = current_ir_graph; \
472 ir_node *block = get_nodes_block(irn); \
473 ir_node *op1 = get_ ## op ## _left(irn); \
474 ir_node *op2 = get_ ## op ## _right(irn); \
476 arm_shift_modifier mod; \
477 ir_mode *mode = get_irn_mode(irn); \
478 dbg_info *dbg = get_irn_dbg_info(irn); \
480 if (is_arm_Mov_i(op1)) \
481 return new_rd_arm_ ## op ## _i(dbg, irg, block, op2, mode, get_arm_value(op1)); \
482 if (is_arm_Mov_i(op2)) \
483 return new_rd_arm_ ## op ## _i(dbg, irg, block, op1, mode, get_arm_value(op2)); \
484 /* is the first a shifter */ \
485 v = is_shifter_operand(op1, &mod); \
487 op1 = get_irn_n(op1, 0); \
488 return new_rd_arm_ ## op(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu)); \
490 /* is the second a shifter */ \
491 v = is_shifter_operand(op2, &mod); \
493 op2 = get_irn_n(op2, 0); \
494 return new_rd_arm_ ## op(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu)); \
497 return new_rd_arm_ ## op(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL); \
502 * Creates an arm And.
504 * @param env The transformation environment
505 * @return the created arm And node
507 static ir_node *gen_And(ir_node *irn, arm_code_gen_t *cg);
511 * Creates an arm Orr.
513 * @param env The transformation environment
514 * @return the created arm Or node
516 static ir_node *gen_Or(ir_node *irn, arm_code_gen_t *cg);
520 * Creates an arm Eor.
522 * @param env The transformation environment
523 * @return the created arm Eor node
525 static ir_node *gen_Eor(ir_node *irn, arm_code_gen_t *cg);
529 * Creates an arm Sub.
531 * @param env The transformation environment
532 * @return the created arm Sub node
534 static ir_node *gen_Sub(ir_node *irn, arm_code_gen_t *cg) {
535 ir_node *block = get_nodes_block(irn);
536 ir_node *op1 = get_Sub_left(irn);
537 ir_node *op2 = get_Sub_right(irn);
539 arm_shift_modifier mod;
540 ir_mode *mode = get_irn_mode(irn);
541 ir_graph *irg = current_ir_graph;
542 dbg_info *dbg = get_irn_dbg_info(irn);
544 if (mode_is_float(mode)) {
546 if (USE_FPA(cg->isa))
547 return new_rd_arm_fpaSub(dbg, irg, block, op1, op2, mode);
548 else if (USE_VFP(cg->isa)) {
549 assert(mode != mode_E && "IEEE Extended FP not supported");
553 if (mode_is_numP(mode)) {
554 if (is_arm_Mov_i(op1))
555 return new_rd_arm_Rsb_i(dbg, irg, block, op2, mode, get_arm_value(op1));
556 if (is_arm_Mov_i(op2))
557 return new_rd_arm_Sub_i(dbg, irg, block, op1, mode, get_arm_value(op2));
559 /* is the first a shifter */
560 v = is_shifter_operand(op1, &mod);
562 op1 = get_irn_n(op1, 0);
563 return new_rd_arm_Rsb(dbg, irg, block, op2, op1, mode, mod, new_tarval_from_long(v, mode_Iu));
565 /* is the second a shifter */
566 v = is_shifter_operand(op2, &mod);
568 op2 = get_irn_n(op2, 0);
569 return new_rd_arm_Sub(dbg, irg, block, op1, op2, mode, mod, new_tarval_from_long(v, mode_Iu));
572 return new_rd_arm_Sub(dbg, irg, block, op1, op2, mode, ARM_SHF_NONE, NULL);
574 assert(0 && "unknown mode for sub");
579 * Creates an arm Shl.
581 * @param env The transformation environment
582 * @return the created arm Shl node
584 static ir_node *gen_Shl(ir_node *irn, arm_code_gen_t *cg) {
586 ir_node *block = get_nodes_block(irn);
587 ir_node *op1 = get_Shl_left(irn);
588 ir_node *op2 = get_Shl_right(irn);
589 ir_mode *mode = get_irn_mode(irn);
590 ir_graph *irg = current_ir_graph;
591 dbg_info *dbg = get_irn_dbg_info(irn);
593 if (is_arm_Mov_i(op2)) {
594 result = new_rd_arm_Mov(dbg, irg, block, op1, mode, ARM_SHF_LSL, get_arm_value(op2));
596 result = new_rd_arm_Shl(dbg, irg, block, op1, op2, mode);
602 * Creates an arm Shr.
604 * @param env The transformation environment
605 * @return the created arm Shr node
607 static ir_node *gen_Shr(ir_node *irn, arm_code_gen_t *cg) {
609 ir_node *block = get_nodes_block(irn);
610 ir_node *op1 = get_Shr_left(irn);
611 ir_node *op2 = get_Shr_right(irn);
612 ir_mode *mode = get_irn_mode(irn);
613 ir_graph *irg = current_ir_graph;
614 dbg_info *dbg = get_irn_dbg_info(irn);
616 if (is_arm_Mov_i(op2)) {
617 result = new_rd_arm_Mov(dbg, irg, block, op1, mode, ARM_SHF_LSR, get_arm_value(op2));
619 result = new_rd_arm_Shr(dbg, irg, block, op1, op2, mode);
625 * Creates an arm Shrs.
627 * @param env The transformation environment
628 * @return the created arm Shrs node
630 static ir_node *gen_Shrs(ir_node *irn, arm_code_gen_t *cg) {
632 ir_node *block = get_nodes_block(irn);
633 ir_node *op1 = get_Shrs_left(irn);
634 ir_node *op2 = get_Shrs_right(irn);
635 ir_mode *mode = get_irn_mode(irn);
636 dbg_info *dbg = get_irn_dbg_info(irn);
638 if (is_arm_Mov_i(op2)) {
639 result = new_rd_arm_Mov(dbg, current_ir_graph, block, op1, mode, ARM_SHF_ASR, get_arm_value(op2));
641 result = new_rd_arm_Shrs(dbg, current_ir_graph, block, op1, op2, mode);
647 * Transforms a Not node.
649 * @param env The transformation environment
650 * @return the created arm Not node
652 static ir_node *gen_Not(ir_node *irn, arm_code_gen_t *cg) {
653 ir_node *block = get_nodes_block(irn);
654 ir_node *op = get_Not_op(irn);
656 arm_shift_modifier mod = ARM_SHF_NONE;
658 dbg_info *dbg = get_irn_dbg_info(irn);
660 v = is_shifter_operand(op, &mod);
662 op = get_irn_n(op, 0);
663 tv = new_tarval_from_long(v, mode_Iu);
665 return new_rd_arm_Mvn(dbg, current_ir_graph, block, op, get_irn_mode(irn), mod, tv);
669 * Transforms an Abs node.
671 * @param env The transformation environment
672 * @return the created arm Abs node
674 static ir_node *gen_Abs(ir_node *irn, arm_code_gen_t *cg) {
675 ir_node *block = get_nodes_block(irn);
676 ir_node *op = get_Abs_op(irn);
677 ir_mode *mode = get_irn_mode(irn);
678 dbg_info *dbg = get_irn_dbg_info(irn);
680 if (mode_is_float(mode)) {
682 if (USE_FPA(cg->isa))
683 return new_rd_arm_fpaAbs(dbg, current_ir_graph, block, op, mode);
684 else if (USE_VFP(cg->isa)) {
685 assert(mode != mode_E && "IEEE Extended FP not supported");
689 return new_rd_arm_Abs(dbg, current_ir_graph, block, op, mode);
693 * Transforms a Minus node.
695 * @param env The transformation environment
696 * @return the created arm Minus node
698 static ir_node *gen_Minus(ir_node *irn, arm_code_gen_t *cg) {
699 ir_node *block = get_nodes_block(irn);
700 ir_node *op = get_Minus_op(irn);
701 ir_mode *mode = get_irn_mode(irn);
702 ir_graph *irg = current_ir_graph;
703 dbg_info *dbg = get_irn_dbg_info(irn);
705 if (mode_is_float(mode)) {
707 if (USE_FPA(cg->isa))
708 return new_rd_arm_fpaMnv(dbg, irg, block, op, mode);
709 else if (USE_VFP(cg->isa)) {
710 assert(mode != mode_E && "IEEE Extended FP not supported");
714 return new_rd_arm_Rsb_i(dbg, irg, block, op, mode, get_mode_null(mode));
720 * @param mod the debug module
721 * @param block the block the new node should belong to
722 * @param node the ir Load node
723 * @param mode node mode
724 * @return the created arm Load node
726 static ir_node *gen_Load(ir_node *irn, arm_code_gen_t *cg) {
727 ir_node *block = get_nodes_block(irn);
728 ir_mode *mode = get_Load_mode(irn);
729 ir_graph *irg = current_ir_graph;
730 dbg_info *dbg = get_irn_dbg_info(irn);
732 if (mode_is_float(mode)) {
734 if (USE_FPA(cg->isa))
735 return new_rd_arm_fpaLdf(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn),
737 else if (USE_VFP(cg->isa)) {
738 assert(mode != mode_E && "IEEE Extended FP not supported");
742 if (mode == mode_Bu) {
743 return new_rd_arm_Loadb(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
745 if (mode == mode_Bs) {
746 return new_rd_arm_Loadbs(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
748 if (mode == mode_Hu) {
749 return new_rd_arm_Loadh(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
751 if (mode == mode_Hs) {
752 return new_rd_arm_Loadhs(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
754 if (mode_is_reference(mode)) {
755 return new_rd_arm_Load(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
757 return new_rd_arm_Load(dbg, irg, block, get_Load_ptr(irn), get_Load_mem(irn));
761 * Transforms a Store.
763 * @param mod the debug module
764 * @param block the block the new node should belong to
765 * @param node the ir Store node
766 * @param mode node mode
767 * @return the created arm Store node
769 static ir_node *gen_Store(ir_node *irn, arm_code_gen_t *cg) {
770 ir_node *block = get_nodes_block(irn);
771 ir_mode *mode = get_irn_mode(get_Store_value(irn));
772 ir_graph *irg = current_ir_graph;
773 dbg_info *dbg = get_irn_dbg_info(irn);
775 assert(mode != mode_E && "IEEE Extended FP not supported");
776 if (mode_is_float(mode)) {
778 if (USE_FPA(cg->isa))
779 return new_rd_arm_fpaStf(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn),
780 get_Store_mem(irn), get_irn_mode(get_Store_value(irn)));
781 else if (USE_VFP(cg->isa)) {
782 assert(mode != mode_E && "IEEE Extended FP not supported");
786 if (mode == mode_Bu) {
787 return new_rd_arm_Storeb(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
789 if (mode == mode_Bs) {
790 return new_rd_arm_Storebs(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
792 if (mode == mode_Hu) {
793 return new_rd_arm_Storeh(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
795 if (mode == mode_Hs) {
796 return new_rd_arm_Storehs(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
798 return new_rd_arm_Store(dbg, irg, block, get_Store_ptr(irn), get_Store_value(irn), get_Store_mem(irn));
802 static ir_node *gen_Cond(ir_node *irn, arm_code_gen_t *cg) {
803 ir_node *result = NULL;
804 ir_node *selector = get_Cond_selector(irn);
805 ir_node *block = get_nodes_block(irn);
806 ir_graph *irg = current_ir_graph;
807 dbg_info *dbg = get_irn_dbg_info(irn);
809 if ( get_irn_mode(selector) == mode_b ) {
811 ir_node *proj_node = get_Cond_selector(irn);
812 ir_node *cmp_node = get_Proj_pred(proj_node);
813 ir_node *op1 = get_Cmp_left(cmp_node);
814 ir_node *op2 = get_Cmp_right(cmp_node);
815 result = new_rd_arm_CondJmp(dbg, irg, block, op1, op2, mode_T);
816 set_arm_proj_num(result, get_Proj_proj(proj_node));
819 ir_node *op = get_irn_n(irn, 0);
820 ir_node *const_graph;
825 const ir_edge_t *edge;
835 foreach_out_edge(irn, edge) {
836 proj = get_edge_src_irn(edge);
837 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
839 pn = get_Proj_proj(proj);
841 min = pn<min ? pn : min;
842 max = pn>max ? pn : max;
845 norm_max = max - translation;
846 norm_min = min - translation;
848 n_projs = norm_max + 1;
849 projs = xcalloc(n_projs , sizeof(ir_node*));
852 foreach_out_edge(irn, edge) {
853 proj = get_edge_src_irn(edge);
854 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
856 pn = get_Proj_proj(proj) - translation;
857 set_Proj_proj(proj, pn);
861 const_node = new_rd_Const(dbg, irg, block, mode_Iu, new_tarval_from_long(translation, mode_Iu));
862 const_graph = gen_Const(const_node, cg);
863 sub = new_rd_arm_Sub(dbg, irg, block, op, const_graph, get_irn_mode(op), ARM_SHF_NONE, NULL);
864 result = new_rd_arm_SwitchJmp(dbg, irg, block, sub, mode_T);
865 set_arm_n_projs(result, n_projs);
866 set_arm_default_proj_num(result, get_Cond_defaultProj(irn)-translation);
872 * Returns the name of a SymConst.
873 * @param symc the SymConst
874 * @return name of the SymConst
876 const char *get_sc_name(ir_node *symc) {
877 if (get_irn_opcode(symc) != iro_SymConst)
880 switch (get_SymConst_kind(symc)) {
881 case symconst_addr_name:
882 return get_id_str(get_SymConst_name(symc));
884 case symconst_addr_ent:
885 return get_entity_ld_name(get_SymConst_entity(symc));
888 assert(0 && "Unsupported SymConst");
894 static ir_node *gen_SymConst(ir_node *irn, arm_code_gen_t *cg) {
895 ir_node *block = get_nodes_block(irn);
896 ir_mode *mode = get_irn_mode(irn);
897 dbg_info *dbg = get_irn_dbg_info(irn);
898 return new_rd_arm_SymConst(dbg, current_ir_graph, block, mode, get_sc_name(irn));
904 * Transforms a CopyB node.
906 * @param env The transformation environment
907 * @return The transformed node.
909 static ir_node *gen_CopyB(ir_node *irn, arm_code_gen_t *cg) {
911 dbg_info *dbg = get_irn_dbg_info(irn);
912 ir_mode *mode = get_irn_mode(irn);
913 ir_node *src = get_CopyB_src(irn);
914 ir_node *dst = get_CopyB_dst(irn);
915 ir_node *mem = get_CopyB_mem(irn);
916 ir_node *block = get_nodes_block(irn);
917 int size = get_type_size_bytes(get_CopyB_type(irn));
918 ir_graph *irg = current_ir_graph;
922 src_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, src);
923 dst_copy = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], irg, block, dst);
925 res = new_rd_arm_CopyB( dbg, irg, block, dst_copy, src_copy, new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), new_rd_arm_EmptyReg(dbg, irg, block, mode_Iu), mem, mode);
926 set_arm_value(res, new_tarval_from_long(size, mode_Iu));
935 /********************************************
938 * | |__ ___ _ __ ___ __| | ___ ___
939 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
940 * | |_) | __/ | | | (_) | (_| | __/\__ \
941 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
943 ********************************************/
946 * Return an expanding stack offset.
947 * Note that function is called in the transform phase
948 * where the stack offsets are still relative regarding
949 * the first (frame allocating) IncSP.
950 * However this is exactly what we want because frame
951 * access must be done relative the the fist IncSP ...
953 static int get_sp_expand_offset(ir_node *inc_sp) {
954 unsigned offset = be_get_IncSP_offset(inc_sp);
955 be_stack_dir_t dir = be_get_IncSP_direction(inc_sp);
957 if (offset == BE_STACK_FRAME_SIZE)
959 return dir == be_stack_dir_expand ? (int)offset : -(int)offset;
962 static ir_node *gen_StackParam(ir_node *irn, arm_code_gen_t *cg) {
964 ir_node *new_op = NULL;
965 ir_node *block = get_nodes_block(irn);
966 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
967 ir_node *mem = new_rd_NoMem(env->irg);
968 ir_node *ptr = get_irn_n(irn, 0);
969 entity *ent = be_get_frame_entity(irn);
970 ir_mode *mode = env->mode;
972 // /* If the StackParam has only one user -> */
973 // /* put it in the Block where the user resides */
974 // if (get_irn_n_edges(node) == 1) {
975 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
978 if (mode_is_float(mode)) {
979 if (USE_SSE2(env->cg))
980 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
982 env->cg->used_x87 = 1;
983 new_op = new_rd_ia32_vfld(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
987 new_op = new_rd_ia32_Load(env->dbg, env->irg, block, ptr, noreg, mem, mode_T);
990 set_ia32_frame_ent(new_op, ent);
991 set_ia32_use_frame(new_op);
993 set_ia32_am_support(new_op, ia32_am_Source);
994 set_ia32_op_type(new_op, ia32_AddrModeS);
995 set_ia32_am_flavour(new_op, ia32_B);
996 set_ia32_ls_mode(new_op, mode);
998 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1000 return new_rd_Proj(env->dbg, env->irg, block, new_op, mode, 0);
1005 * Transforms a FrameAddr into an ia32 Add.
1007 static ir_node *gen_be_FrameAddr(ir_node *irn, arm_code_gen_t *cg) {
1008 ir_node *block = get_nodes_block(irn);
1009 entity *ent = be_get_frame_entity(irn);
1010 int offset = get_entity_offset_bytes(ent);
1011 ir_node *op = get_irn_n(irn, 0);
1013 ir_mode *mode = get_irn_mode(irn);
1014 dbg_info *dbg = get_irn_dbg_info(irn);
1016 if (be_is_IncSP(op)) {
1017 /* BEWARE: we get an offset which is absolute from an offset that
1018 is relative. Both must be merged */
1019 offset += get_sp_expand_offset(op);
1021 cnst = create_const_graph_value(irn, block, (unsigned)offset);
1022 if (is_arm_Mov_i(cnst))
1023 return new_rd_arm_Add_i(dbg, current_ir_graph, block, op, mode, get_arm_value(cnst));
1024 return new_rd_arm_Add(dbg, current_ir_graph, block, op, cnst, mode, ARM_SHF_NONE, NULL);
1028 * Transforms a FrameLoad into an ia32 Load.
1030 static ir_node *gen_FrameLoad(ir_node *irn, arm_code_gen_t *cg) {
1032 ir_node *new_op = NULL;
1033 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1034 ir_node *mem = get_irn_n(irn, 0);
1035 ir_node *ptr = get_irn_n(irn, 1);
1036 entity *ent = be_get_frame_entity(irn);
1037 ir_mode *mode = get_type_mode(get_entity_type(ent));
1039 if (mode_is_float(mode)) {
1040 if (USE_SSE2(env->cg))
1041 new_op = new_rd_ia32_fLoad(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
1043 env->cg->used_x87 = 1;
1044 new_op = new_rd_ia32_vfld(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
1048 new_op = new_rd_ia32_Load(env->dbg, current_ir_graph, env->block, ptr, noreg, mem, mode_T);
1051 set_ia32_frame_ent(new_op, ent);
1052 set_ia32_use_frame(new_op);
1054 set_ia32_am_support(new_op, ia32_am_Source);
1055 set_ia32_op_type(new_op, ia32_AddrModeS);
1056 set_ia32_am_flavour(new_op, ia32_B);
1057 set_ia32_ls_mode(new_op, mode);
1059 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1067 * Transforms a FrameStore into an ia32 Store.
1069 static ir_node *gen_FrameStore(ir_node *irn, arm_code_gen_t *cg) {
1071 ir_node *new_op = NULL;
1072 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1073 ir_node *mem = get_irn_n(irn, 0);
1074 ir_node *ptr = get_irn_n(irn, 1);
1075 ir_node *val = get_irn_n(irn, 2);
1076 entity *ent = be_get_frame_entity(irn);
1077 ir_mode *mode = get_irn_mode(val);
1079 if (mode_is_float(mode)) {
1080 if (USE_SSE2(env->cg))
1081 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1083 env->cg->used_x87 = 1;
1084 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1087 else if (get_mode_size_bits(mode) == 8) {
1088 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1091 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1094 set_ia32_frame_ent(new_op, ent);
1095 set_ia32_use_frame(new_op);
1097 set_ia32_am_support(new_op, ia32_am_Dest);
1098 set_ia32_op_type(new_op, ia32_AddrModeD);
1099 set_ia32_am_flavour(new_op, ia32_B);
1100 set_ia32_ls_mode(new_op, mode);
1102 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1109 // static ir_node *gen_be_Copy(ir_node *irn, arm_code_gen_t *cg) {
1110 // return new_rd_arm_Copy(env->dbg, env->irg, env->block, op, env->mode);
1113 /*********************************************************
1116 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1117 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1118 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1119 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1121 *********************************************************/
1124 * move constants out of the start block
1126 void arm_move_consts(ir_node *node, void *env) {
1127 arm_code_gen_t *cgenv = (arm_code_gen_t *)env;
1134 for (i = get_irn_arity(node) - 1; i >= 0; --i) {
1135 ir_node *pred = get_irn_n(node,i);
1136 opcode pred_code = get_irn_opcode(pred);
1137 if (pred_code == iro_Const) {
1138 ir_node *const_graph;
1139 const_graph = create_const_graph(pred, get_nodes_block(get_irn_n(get_nodes_block(node),i)));
1140 set_irn_n(node, i, const_graph);
1142 else if (pred_code == iro_SymConst) {
1143 /* FIXME: in general, SymConst always require a load, so it
1144 might be better to place them into the first real block
1145 and let the spiller rematerialize them. */
1146 const char *str = get_sc_name(pred);
1147 ir_node *symconst_node;
1148 symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
1149 current_ir_graph, get_nodes_block(get_irn_n(get_nodes_block(node),i)),
1150 get_irn_mode(pred), str);
1151 set_irn_n(node, i, symconst_node);
1156 for (i = 0; i < get_irn_arity(node); i++) {
1157 ir_node *pred = get_irn_n(node,i);
1158 opcode pred_code = get_irn_opcode(pred);
1159 if (pred_code == iro_Const) {
1160 ir_node *const_graph;
1161 const_graph = create_const_graph(pred, get_nodes_block(node));
1162 set_irn_n(node, i, const_graph);
1163 } else if (pred_code == iro_SymConst) {
1164 const char *str = get_sc_name(pred);
1165 ir_node *symconst_node;
1166 symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
1167 current_ir_graph, get_nodes_block(node),
1168 get_irn_mode(pred), str);
1169 set_irn_n(node, i, symconst_node);
1175 /************************************************************************/
1176 /* move symbolic constants out of startblock */
1177 /************************************************************************/
1178 void arm_move_symconsts(ir_node *node, void *env) {
1184 for (i = 0; i < get_irn_arity(node); i++) {
1185 ir_node *pred = get_irn_n(node,i);
1186 opcode pred_code = get_irn_opcode(pred);
1188 if (pred_code == iro_SymConst) {
1189 const char *str = get_sc_name(pred);
1190 ir_node *symconst_node;
1192 symconst_node = new_rd_arm_SymConst(get_irn_dbg_info(pred),
1193 current_ir_graph, get_nodes_block(node), get_irn_mode(pred), str);
1194 set_irn_n(node, i, symconst_node);
1200 * the BAD transformer.
1202 static ir_node *bad_transform(ir_node *irn, arm_code_gen_t *cg) {
1203 ir_fprintf(stderr, "Not implemented: %+F\n", irn);
1209 * Enters all transform functions into the generic pointer
1211 void arm_register_transformers(void) {
1212 ir_op *op_Max, *op_Min, *op_Mulh;
1214 /* first clear the generic function pointer for all ops */
1215 clear_irp_opcodes_generic_func();
1217 #define FIRM_OP(a) op_##a->ops.generic = (op_func)gen_##a
1218 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
1221 FIRM_OP(Add); // done
1222 FIRM_OP(Mul); // done
1223 FIRM_OP(Quot); // done
1224 FIRM_OP(And); // done
1225 FIRM_OP(Or); // done
1226 FIRM_OP(Eor); // done
1228 FIRM_OP(Sub); // done
1229 FIRM_OP(Shl); // done
1230 FIRM_OP(Shr); // done
1231 FIRM_OP(Shrs); // done
1233 FIRM_OP(Minus); // done
1234 FIRM_OP(Not); // done
1235 FIRM_OP(Abs); // done
1237 FIRM_OP(CopyB); // done
1238 FIRM_OP(Const); // TODO: floating point consts
1239 FIRM_OP(Conv); // TODO: floating point conversions
1241 FIRM_OP(Load); // done
1242 FIRM_OP(Store); // done
1245 FIRM_OP(Cond); // integer done
1247 /* TODO: implement these nodes */
1249 IGN(Div); // intrinsic lowering
1250 IGN(Mod); // intrinsic lowering
1251 IGN(DivMod); // TODO: implement DivMod
1255 IGN(Cmp); // done, implemented in cond
1257 /* You probably don't need to handle the following nodes */
1269 IGN(Jmp); // emitter done
1287 FIRM_OP(be_FrameAddr);
1289 op_Max = get_op_Max();
1292 op_Min = get_op_Min();
1295 op_Mulh = get_op_Mulh();
1304 typedef ir_node *(transform_func)(ir_node *irn, arm_code_gen_t *cg);
1307 * Transforms the given firm node (and maybe some other related nodes)
1308 * into one or more assembler nodes.
1310 * @param node the firm node
1311 * @param env the debug module
1313 void arm_transform_node(ir_node *node, void *env) {
1314 arm_code_gen_t *cg = (arm_code_gen_t *)env;
1315 ir_op *op = get_irn_op(node);
1316 ir_node *asm_node = NULL;
1321 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
1323 if (op->ops.generic) {
1324 transform_func *transform = (transform_func *)op->ops.generic;
1326 asm_node = (*transform)(node, cg);
1330 exchange(node, asm_node);
1331 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
1334 DB((cg->mod, LEVEL_1, "ignored\n"));