3 # This is a template specification for the Firm-Backend
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
9 # $comment_string = 'WIRHABENKEINEKOMMENTARE';
10 $comment_string = '/*';
12 # the number of additional opcodes you want to register
13 #$additional_opcodes = 0;
15 # The node description is done as a perl hash initializer with the
16 # following structure:
21 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
22 # "irn_flags" => "R|N|I"
23 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
24 # "state" => "floats|pinned|mem_pinned|exc_pinned",
26 # { "type" => "type 1", "name" => "name 1" },
27 # { "type" => "type 2", "name" => "name 2" },
30 # "comment" => "any comment for constructor",
31 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
32 # "cmp_attr" => "c source code for comparing node attributes",
33 # "emit" => "emit code with templates",
34 # "rd_constructor" => "c source code which constructs an ir_node"
37 # ... # (all nodes you need to describe)
39 # ); # close the %nodes initializer
41 # op_flags: flags for the operation, OPTIONAL (default is "N")
42 # the op_flags correspond to the firm irop_flags:
45 # C irop_flag_commutative
46 # X irop_flag_cfopcode
47 # I irop_flag_ip_cfopcode
50 # H irop_flag_highlevel
51 # c irop_flag_constlike
54 # irn_flags: special node flags, OPTIONAL (default is 0)
55 # following irn_flags are supported:
58 # I ignore for register allocation
60 # state: state of the operation, OPTIONAL (default is "floats")
62 # arity: arity of the operation, MUST NOT BE OMITTED
64 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
65 # are always the first 3 arguments and are always autmatically
67 # If this key is missing the following arguments will be created:
68 # for i = 1 .. arity: ir_node *op_i
71 # comment: OPTIONAL comment for the node constructor
73 # rd_constructor: for every operation there will be a
74 # new_rd_<arch>_<op-name> function with the arguments from above
75 # which creates the ir_node corresponding to the defined operation
76 # you can either put the complete source code of this function here
78 # This key is OPTIONAL. If omitted, the following constructor will
80 # if (!op_<arch>_<op-name>) assert(0);
84 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
87 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
91 # 1 - caller save (register must be saved by the caller of a function)
92 # 2 - callee save (register must be saved by the called function)
93 # 4 - ignore (do not assign this register)
94 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
97 { "name" => "r0", "type" => 1 },
98 { "name" => "r1", "type" => 1 },
99 { "name" => "r2", "type" => 1 },
100 { "name" => "r3", "type" => 1 },
101 { "name" => "r4", "type" => 2 },
102 { "name" => "r5", "type" => 2 },
103 { "name" => "r6", "type" => 2 },
104 { "name" => "r7", "type" => 2 },
105 { "name" => "r8", "type" => 2 },
106 { "name" => "r9", "type" => 2 },
107 { "name" => "r10", "type" => 2 },
108 { "name" => "r11", "type" => 2 },
109 { "name" => "r12", "type" => 6 }, # reserved for linker
110 { "name" => "sp", "type" => 6 }, # this is our stack pointer
111 { "name" => "lr", "type" => 3 }, # this is our return address
112 { "name" => "pc", "type" => 6 }, # this is our program counter
113 { "name" => "rxx", "type" => 6 }, # dummy register for no_mem
114 { "mode" => "mode_Iu" }
117 { "name" => "f0", "type" => 1 },
118 { "name" => "f1", "type" => 1 },
119 { "name" => "f2", "type" => 1 },
120 { "name" => "f3", "type" => 1 },
121 { "name" => "f4", "type" => 2 },
122 { "name" => "f5", "type" => 2 },
123 { "name" => "f6", "type" => 2 },
124 { "name" => "f7", "type" => 2 },
125 { "name" => "fxx", "type" => 6 }, # dummy register for no_mem
126 { "mode" => "mode_D" }
130 #--------------------------------------------------#
133 # _ __ _____ __ _ _ __ ___ _ __ ___ #
134 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
135 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
136 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
139 #--------------------------------------------------#
143 #-----------------------------------------------------------------#
146 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
147 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
148 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
149 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
152 #-----------------------------------------------------------------#
154 # commutative operations
159 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
160 "attr" => "arm_shift_modifier mod, tarval *shf",
161 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
162 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
163 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
164 "emit" => '. ADD %D1, %S1, %S2%X0 /* Add(%S1, %S2) -> %D1, (%A1, %A2) */'
169 "comment" => "construct Add: Add(a, const) = Add(const, a) = a + const",
170 "attr" => "tarval *tv",
171 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
172 "cmp_attr" => 'return attr_a->value != attr_b->value;',
173 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
174 "emit" => '. ADD %D1, %S1, %C /* Add(%C, %S1) -> %D1, (%A1, const) */'
180 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
181 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "!in_r1" ] },
182 "emit" =>'. MUL %D1, %S1, %S2 /* Mul(%S1, %S2) -> %D1, (%A1, %A2) */'
188 "comment" => "construct Mla: Mla(a, b, c) = a * b + c",
189 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in_r1" ] },
190 "emit" =>'. MLA %D1, %S1, %S2, %S3 /* Mla(%S1, %S2, %S3) -> %D1, (%A1, %A2, %A3) */'
196 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
197 "attr" => "arm_shift_modifier mod, tarval *shf",
198 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
199 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
200 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
201 "emit" => '. AND %D1, %S1, %S2%X0 /* And(%S1, %S2) -> %D1, (%A1, %A2) */'
206 "comment" => "construct And: And(a, const) = And(const, a) = a AND const",
207 "attr" => "tarval *tv",
208 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
209 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
210 "emit" => '. AND %D1, %S1, %C /* And(%C, %S1) -> %D1, (%A1, const) */',
211 "cmp_attr" => 'return attr_a->value != attr_b->value;'
217 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
218 "attr" => "arm_shift_modifier mod, tarval *shf",
219 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
220 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
221 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
222 "emit" => '. ORR %D1, %S1, %S2%X0 /* Or(%S1, %S2) -> %D1, (%A1, %A2) */'
227 "comment" => "construct Or: Or(a, const) = Or(const, a) = a OR const",
228 "attr" => "tarval *tv",
229 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
230 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
231 "cmp_attr" => 'return attr_a->value != attr_b->value;',
232 "emit" => '. ORR %D1, %S1, %C /* Or(%C, %S1) -> %D1, (%A1, const) */'
238 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
239 "attr" => "arm_shift_modifier mod, tarval *shf",
240 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
241 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
242 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
243 "emit" => '. EOR %D1, %S1, %S2%X0 /* Xor(%S1, %S2) -> %D1, (%A1, %A2) */'
248 "comment" => "construct Eor: Eor(a, const) = Eor(const, a) = a EOR const",
249 "attr" => "tarval *tv",
250 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
251 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
252 "cmp_attr" => 'return attr_a->value != attr_b->value;',
253 "emit" => '. EOR %D1, %S1, %C /* Xor(%C, %S1) -> %D1, (%A1, const) */'
256 # not commutative operations
260 "comment" => "construct Bic: Bic(a, b) = a AND ~b",
261 "attr" => "arm_shift_modifier mod, tarval *shf",
262 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
263 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
264 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
265 "emit" => '. BIC %D1, %S1, %S2%X0 /* AndNot(%S1, %S2) -> %D1, (%A1, %A2) */'
270 "comment" => "construct Bic: Bic(a, const) = a AND ~const",
271 "attr" => "tarval *tv",
272 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
273 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
274 "emit" => '. BIC %D1, %S1, %C /* AndNot(%C, %S1) -> %D1, (%A1, const) */',
275 "cmp_attr" => 'return attr_a->value != attr_b->value;'
280 "comment" => "construct Sub: Sub(a, b) = a - b",
281 "attr" => "arm_shift_modifier mod, tarval *shf",
282 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
283 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
284 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
285 "emit" => '. SUB %D1, %S1, %S2%X0 /* Sub(%S1, %S2) -> %D1, (%A1, %A2) */'
290 "comment" => "construct Sub: Sub(a, const) = a - const",
291 "attr" => "tarval *tv",
292 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
293 "cmp_attr" => 'return attr_a->value != attr_b->value;',
294 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
295 "emit" => '. SUB %D1, %S1, %C /* Sub(%S1, %C) -> %D1, (%A1, const) */',
300 "comment" => "construct Rsb: Rsb(a, b) = b - a",
301 "attr" => "arm_shift_modifier mod, tarval *shf",
302 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
303 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
304 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
305 "emit" => '. RSB %D1, %S1, %S2%X0 /* Rsb(%S1, %S2) -> %D1, (%A1, %A2) */'
310 "comment" => "construct Rsb: Rsb(a, const) = const - a",
311 "attr" => "tarval *tv",
312 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
313 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
314 "emit" => '. RSB %D1, %S1, %C /* Rsb(%S1, %C) -> %D1, (%A1, const) */',
315 "cmp_attr" => 'return attr_a->value != attr_b->value;'
320 "comment" => "construct Shl: Shl(a, b) = a << b",
321 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
322 "emit" => '. MOV %D1, %S1, LSL %S2\t/* Shl(%S1, %S2) -> %D1, (%A1, %A2) */'
327 "comment" => "construct Shr: Shr(a, b) = a >> b",
328 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
329 "emit" => '. MOV %D1, %S1, LSR %S2 /* Shr(%S1, %S2) -> %D1, (%A1, %A2) */'
334 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
335 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
336 "emit" => '. MOV %D1, %S1, ASR %S2\t\t /* Shrs(%S1, %S2) -> %D1, (%A1, %A2) */'
340 # "irn_flags" => "R",
341 # "comment" => "construct RotR: RotR(a, b) = a ROTR b",
342 # "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
343 # "emit" => '. MOV %D1, %S1, ROR %S2 /* RotR(%S1, %S2) -> %D1, (%A1, %A2) */'
344 ## "emit" => '. ror %S1, %S2, %D1 /* RotR(%S1, %S2) -> %D1, (%A1, %A2) */'
348 # "irn_flags" => "R",
349 # "comment" => "construct RotL: RotL(a, b) = a ROTL b",
350 # "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
351 # "emit" => '. rol %S1, %S2, %D1 /* RotL(%S1, %S2) -> %D1, (%A1, %A2) */'
355 # "irn_flags" => "R",
356 # "comment" => "construct RotL: RotL(a, const) = a ROTL const",
357 # "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
358 # "emit" => '. rol %S1, %C, %D1 /* RotL(%S1, %C) -> %D1, (%A1, const) */'
363 "comment" => "construct Mov: a = b",
364 "attr" => "arm_shift_modifier mod, tarval *shf",
365 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
366 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
367 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
368 "emit" => '. MOV %D1, %S1%X0\t/* Mov(%S1%X0) -> %D1, (%A1) */'
373 "comment" => "represents an integer constant",
374 "attr" => "tarval *tv",
375 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
376 "reg_req" => { "out" => [ "gp" ] },
377 "emit" => '. MOV %D1, %C /* Mov Const into register */',
378 "cmp_attr" => 'return attr_a->value != attr_b->value;'
383 "comment" => "construct Not: Not(a) = !a",
384 "attr" => "arm_shift_modifier mod, tarval *shf",
385 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
386 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
387 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
388 "emit" => '. MVN %D1, %S1%X0 /* ~(%S1%X0) -> %D1, (%A1) */'
393 "comment" => "represents a negated integer constant",
394 "attr" => "tarval *tv",
395 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
396 "cmp_attr" => 'return attr_a->value != attr_b->value;',
397 "reg_req" => { "out" => [ "gp" ] },
398 "emit" => '. MVN %D1, %C /* Mov ~Const into register */',
403 "comment" => "construct Abs: Abs(a) = |a|",
404 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
406 '. MOVS %S1, %S1, #0 /* set condition flag */\n
407 . RSBMI %D1, %S1, #0 /* Neg(%S1) -> %D1, (%A1) */'
415 "comment" => "just to get an empty register for calculations",
416 "reg_req" => { "out" => [ "gp" ] },
417 "emit" => '. /* %D1 now available for calculations */',
418 "cmp_attr" => 'return 1;'
422 "comment" => "implements a register copy",
423 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
429 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
430 "reg_req" => { "in" => [ "!sp", "!sp", "gp", "gp", "gp", "none" ], "out" => [ "none" ] },
436 "comment" => "represents a symbolic constant",
437 "attr" => "const char *label",
438 "init_attr" => ' attr->symconst_label = label;',
439 "reg_req" => { "out" => [ "gp" ] },
440 # "emit" => '. LDR %D1, %C /* Mov Const into register */',
442 ' /* should be identical but ...*/
443 return strcmp(attr_a->symconst_label, attr_b->symconst_label);'
447 "op_flags" => "L|X|Y",
448 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
449 "cmp_attr" => " return arm_comp_condJmp(attr_a, attr_b);\n",
450 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "none", "none"] },
454 "op_flags" => "L|X|Y",
455 "comment" => "construct switch",
456 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
457 "cmp_attr" => " return 0;\n",
465 "state" => "exc_pinned",
466 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
467 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp" ] },
468 "emit" => '. LDR %D1, [%S1, #0] /* Load((%S1)) -> %D1, (%A1) */'
469 # "emit" => '. LDR %D1, %S1, %O /* Load((%S1)) -> %D1, (%A1) */'
475 "state" => "exc_pinned",
476 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
477 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp" ] },
478 "emit" => '. LDRB %D1, [%S1, #0] /* Load((%S1)) -> %D1, (%A1) */'
479 # "emit" => '. LDRB %D1, %S1, %O /* Load((%S1)) -> %D1, (%A1) */'
485 "state" => "exc_pinned",
486 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
487 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp" ] },
488 "emit" => '. LDRSB %D1, [%S1, #0] /* Load((%S1)) -> %D1, (%A1) */'
489 # "emit" => '. LDRSB %D1, %S1, %O /* Load((%S1)) -> %D1, (%A1) */'
495 "state" => "exc_pinned",
496 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
497 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp" ] },
498 "emit" => '. LDRH %D1, [%S1, #0] /* Load((%S1)) -> %D1, (%A1) */'
499 # "emit" => '. LDRH %D1, %S1, %O /* Load((%S1)) -> %D1, (%A1) */'
505 "state" => "exc_pinned",
506 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
507 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp" ] },
508 "emit" => '. LDRSH %D1, [%S1, #0] /* Load((%S1)) -> %D1, (%A1) */'
509 # "emit" => '. LDRSH %D1, %S1, %O /* Load((%S1)) -> %D1, (%A1) */'
515 "state" => "exc_pinned",
516 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
517 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
518 "emit" => '. STRB %S2, [%S1, #0] /* Store(%S2) -> (%S1), (%A1, %A2) */'
519 # "emit" => '. movl %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */'
525 "state" => "exc_pinned",
526 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
527 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
528 "emit" => '. STRSB %S2, [%S1, #0] /* Store(%S2) -> (%S1), (%A1, %A2) */'
529 # "emit" => '. movl %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */'
535 "state" => "exc_pinned",
536 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
537 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
538 "emit" => '. STRH %S2, [%S1, #0] /* Store(%S2) -> (%S1), (%A1, %A2) */'
539 # "emit" => '. movl %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */'
545 "state" => "exc_pinned",
546 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
547 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
548 "emit" => '. STRSH%S2, [%S1, #0] /* Store(%S2) -> (%S1), (%A1, %A2) */'
549 # "emit" => '. movl %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */'
555 "state" => "exc_pinned",
556 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
557 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
558 "emit" => '. STR %S2, [%S1, #0] /* Store(%S2) -> (%S1), (%A1, %A2) */'
559 # "emit" => '. movl %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */'
562 "StoreStackM4Inc" => {
565 "state" => "exc_pinned",
566 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
567 "reg_req" => { "in" => [ "sp", "gp", "gp", "gp", "gp", "none" ], "out" => [ "gp", "none" ] },
568 "emit" => '. STMFD %S1!, {%S2, %S3, %S4, %S5} /* Store multiple on Stack*/'
574 "state" => "exc_pinned",
575 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
576 "reg_req" => { "in" => [ "sp", "none" ], "out" => [ "gp", "gp", "gp", "none" ] },
577 "emit" => '. LDMFD %S1, {%D1, %D2, %D3} /* Load multiple from Stack */'
587 #--------------------------------------------------------#
590 # | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
591 # | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
592 # | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
593 # |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
594 #--------------------------------------------------------#
596 # commutative operations
601 "comment" => "construct FP Add: Add(a, b) = Add(b, a) = a + b",
602 "reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
603 "emit" => '. FADD%Mx %D1, %S1, %S2 /* FP Add(%S1, %S2) -> %D1 */'
608 "comment" => "construct FP Mul: Mul(a, b) = Mul(b, a) = a * b",
609 "reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
610 "emit" =>'. FMUL%Mx %D1, %S1, %S2 /* FP Mul(%S1, %S2) -> %D1 */'
614 "comment" => "construct FP Div: Div(a, b) = a / b",
615 "reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
616 "emit" =>'. FDIV%Mx %D1, %S1, %S2 /* FP Div(%S1, %S2) -> %D1 */'
622 "comment" => "construct FP Max: Max(a, b) = Max(b, a) = a > b ? a : b",
623 "reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
624 "emit" =>'. fmax %S1, %S2, %D1 /* FP Max(%S1, %S2) -> %D1 */'
630 "comment" => "construct FP Min: Min(a, b) = Min(b, a) = a < b ? a : b",
631 "reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
632 "emit" =>'. fmin %S1, %S2, %D1 /* FP Min(%S1, %S2) -> %D1 */'
635 # not commutative operations
639 "comment" => "construct FP Sub: Sub(a, b) = a - b",
640 "reg_req" => { "in" => [ "fp", "fp" ], "out" => [ "fp" ] },
641 "emit" => '. FSUB%Mx %D1, %S1, %S2 /* FP Sub(%S1, %S2) -> %D1 */'
646 "comment" => "construct FP Minus: Minus(a) = -a",
647 "reg_req" => { "in" => [ "fp" ], "out" => [ "fp" ] },
648 "emit" => '. fneg %S1, %D1 /* FP Minus(%S1) -> %D1 */'
653 "comment" => "construct FP Absolute value: fAbsd(a) = |a|",
654 "reg_req" => { "in" => [ "fp" ], "out" => [ "fp" ] },
655 "emit" => '. FABS%Mx %D1, %S1 /* FP Absd(%S1) -> %D1 */'
663 "comment" => "represents a FP constant",
664 "reg_req" => { "out" => [ "fp" ] },
665 "emit" => '. FMOV %D1, %C /* Mov fConst into register */',
666 "cmp_attr" => 'return attr_a->value != attr_b->value;'
671 "comment" => "convert double to single",
672 "reg_req" => { "in" => [ "fp" ], "out" => [ "fp" ] },
673 "emit" => '. FCVTSD %D1, %S1 /* Convert double to single */',
678 "comment" => "convert single to double",
679 "reg_req" => { "in" => [ "fp" ], "out" => [ "fp" ] },
680 "emit" => '. FCVTDS %D1, %S1 /* Convert single to double */',
689 "state" => "exc_pinned",
690 "comment" => "construct FP Load: Load(ptr, mem) = LD ptr",
691 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "fp" ] },
692 "emit" => '. FLD%Mx %D1, %S1 /* Load((%S1)) -> %D1 */'
698 "state" => "exc_pinned",
699 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
700 "reg_req" => { "in" => [ "gp", "fp", "none" ] },
701 "emit" => '. FST%Mx %S2, %S1 /* Store(%S2) -> (%S1), (%A1, %A2) */'