3 # This is a template specification for the Firm-Backend
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
10 # this strings mark the beginning and the end of a comment in emit
11 $comment_string = "/*";
12 $comment_string_end = "*/";
14 # the number of additional opcodes you want to register
15 #$additional_opcodes = 0;
17 # The node description is done as a perl hash initializer with the
18 # following structure:
23 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
24 # "irn_flags" => "R|N|I"
25 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
26 # "state" => "floats|pinned|mem_pinned|exc_pinned",
28 # { "type" => "type 1", "name" => "name 1" },
29 # { "type" => "type 2", "name" => "name 2" },
32 # "comment" => "any comment for constructor",
33 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
34 # "cmp_attr" => "c source code for comparing node attributes",
35 # "emit" => "emit code with templates",
36 # "attr" => "attitional attribute arguments for constructor"
37 # "init_attr" => "emit attribute initialization template"
38 # "rd_constructor" => "c source code which constructs an ir_node"
41 # ... # (all nodes you need to describe)
43 # ); # close the %nodes initializer
45 # op_flags: flags for the operation, OPTIONAL (default is "N")
46 # the op_flags correspond to the firm irop_flags:
49 # C irop_flag_commutative
50 # X irop_flag_cfopcode
51 # I irop_flag_ip_cfopcode
54 # H irop_flag_highlevel
55 # c irop_flag_constlike
58 # irn_flags: special node flags, OPTIONAL (default is 0)
59 # following irn_flags are supported:
62 # I ignore for register allocation
64 # state: state of the operation, OPTIONAL (default is "floats")
66 # arity: arity of the operation, MUST NOT BE OMITTED
68 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
69 # are always the first 3 arguments and are always autmatically
71 # If this key is missing the following arguments will be created:
72 # for i = 1 .. arity: ir_node *op_i
75 # outs: if a node defines more than one output, the names of the projections
76 # nodes having outs having automatically the mode mode_T
78 # comment: OPTIONAL comment for the node constructor
80 # rd_constructor: for every operation there will be a
81 # new_rd_<arch>_<op-name> function with the arguments from above
82 # which creates the ir_node corresponding to the defined operation
83 # you can either put the complete source code of this function here
85 # This key is OPTIONAL. If omitted, the following constructor will
87 # if (!op_<arch>_<op-name>) assert(0);
91 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
94 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
98 # 1 - caller save (register must be saved by the caller of a function)
99 # 2 - callee save (register must be saved by the called function)
100 # 4 - ignore (do not assign this register)
101 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
104 { "name" => "r0", "type" => 1 },
105 { "name" => "r1", "type" => 1 },
106 { "name" => "r2", "type" => 1 },
107 { "name" => "r3", "type" => 1 },
108 { "name" => "r4", "type" => 2 },
109 { "name" => "r5", "type" => 2 },
110 { "name" => "r6", "type" => 2 },
111 { "name" => "r7", "type" => 2 },
112 { "name" => "r8", "type" => 2 },
113 { "name" => "r9", "type" => 2 },
114 { "name" => "r10", "type" => 2 },
115 { "name" => "r11", "type" => 2 },
116 { "name" => "r12", "type" => 6 }, # reserved for linker
117 { "name" => "sp", "realname" => "r13", "type" => 6 }, # this is our stack pointer
118 { "name" => "lr", "realname" => "r14", "type" => 3 }, # this is our return address
119 { "name" => "pc", "realname" => "r15", "type" => 6 }, # this is our program counter
120 { "mode" => "mode_Iu" }
123 { "name" => "f0", "type" => 1 },
124 { "name" => "f1", "type" => 1 },
125 { "name" => "f2", "type" => 1 },
126 { "name" => "f3", "type" => 1 },
127 { "name" => "f4", "type" => 2 },
128 { "name" => "f5", "type" => 2 },
129 { "name" => "f6", "type" => 2 },
130 { "name" => "f7", "type" => 2 },
131 { "mode" => "mode_E" }
136 M => "${arch}_emit_mode(env, node);",
137 X => "${arch}_emit_shift(env, node);",
138 S1 => "${arch}_emit_source_register(env, node, 0);",
139 S2 => "${arch}_emit_source_register(env, node, 1);",
140 S3 => "${arch}_emit_source_register(env, node, 2);",
141 S4 => "${arch}_emit_source_register(env, node, 3);",
142 S5 => "${arch}_emit_source_register(env, node, 4);",
143 D1 => "${arch}_emit_dest_register(env, node, 0);",
144 D2 => "${arch}_emit_dest_register(env, node, 1);",
145 D3 => "${arch}_emit_dest_register(env, node, 2);",
146 C => "${arch}_emit_immediate(env, node);",
147 O => "${arch}_emit_offset(env, mode);",
148 JumpTarget => "${arch}_emit_jump_target(env, node);",
149 JumpTarget1 => "${arch}_emit_jump_target_proj(env, node, 1);",
152 #--------------------------------------------------#
155 # _ __ _____ __ _ _ __ ___ _ __ ___ #
156 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
157 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
158 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
161 #--------------------------------------------------#
165 #-----------------------------------------------------------------#
168 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
169 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
170 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
171 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
174 #-----------------------------------------------------------------#
176 # commutative operations
181 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
182 "attr" => "arm_shift_modifier mod, tarval *shf",
183 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
184 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
185 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
186 "emit" => '. add %D1, %S1, %S2%X'
191 "comment" => "construct Add: Add(a, const) = Add(const, a) = a + const",
192 "attr" => "tarval *tv",
193 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
194 "cmp_attr" => 'return attr_a->value != attr_b->value;',
195 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
196 "emit" => '. add %D1, %S1, %C'
202 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
203 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "!in_r1" ] },
204 "emit" =>'. mul %D1, %S1, %S2'
210 "comment" => "construct signed 64bit Mul: Mul(a, b) = Mul(b, a) = a * b",
211 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp", "gp" ] },
212 "emit" =>'. smull %D1, %D2, %S1, %S2',
213 "outs" => [ "low", "high" ],
219 "comment" => "construct unsigned 64bit Mul: Mul(a, b) = Mul(b, a) = a * b",
220 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp", "gp" ] },
221 "emit" =>'. umull %D1, %D2, %S1, %S2',
222 "outs" => [ "low", "high" ],
228 "comment" => "construct Mla: Mla(a, b, c) = a * b + c",
229 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in_r1" ] },
230 "emit" =>'. mla %D1, %S1, %S2, %S3'
236 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
237 "attr" => "arm_shift_modifier mod, tarval *shf",
238 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
239 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
240 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
241 "emit" => '. and %D1, %S1, %S2%X'
246 "comment" => "construct And: And(a, const) = And(const, a) = a AND const",
247 "attr" => "tarval *tv",
248 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
249 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
250 "emit" => '. and %D1, %S1, %C',
251 "cmp_attr" => 'return attr_a->value != attr_b->value;'
257 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
258 "attr" => "arm_shift_modifier mod, tarval *shf",
259 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
260 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
261 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
262 "emit" => '. orr %D1, %S1, %S2%X'
267 "comment" => "construct Or: Or(a, const) = Or(const, a) = a OR const",
268 "attr" => "tarval *tv",
269 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
270 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
271 "cmp_attr" => 'return attr_a->value != attr_b->value;',
272 "emit" => '. orr %D1, %S1, %C'
278 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
279 "attr" => "arm_shift_modifier mod, tarval *shf",
280 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
281 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
282 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
283 "emit" => '. eor %D1, %S1, %S2%X'
288 "comment" => "construct Eor: Eor(a, const) = Eor(const, a) = a EOR const",
289 "attr" => "tarval *tv",
290 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
291 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
292 "cmp_attr" => 'return attr_a->value != attr_b->value;',
293 "emit" => '. eor %D1, %S1, %C'
296 # not commutative operations
300 "comment" => "construct Bic: Bic(a, b) = a AND ~b",
301 "attr" => "arm_shift_modifier mod, tarval *shf",
302 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
303 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
304 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
305 "emit" => '. bic %D1, %S1, %S2%X'
310 "comment" => "construct Bic: Bic(a, const) = a AND ~const",
311 "attr" => "tarval *tv",
312 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
313 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
314 "emit" => '. bic %D1, %S1, %C',
315 "cmp_attr" => 'return attr_a->value != attr_b->value;'
320 "comment" => "construct Sub: Sub(a, b) = a - b",
321 "attr" => "arm_shift_modifier mod, tarval *shf",
322 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
323 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
324 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
325 "emit" => '. sub %D1, %S1, %S2%X'
330 "comment" => "construct Sub: Sub(a, const) = a - const",
331 "attr" => "tarval *tv",
332 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
333 "cmp_attr" => 'return attr_a->value != attr_b->value;',
334 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
335 "emit" => '. sub %D1, %S1, %C',
340 "comment" => "construct Rsb: Rsb(a, b) = b - a",
341 "attr" => "arm_shift_modifier mod, tarval *shf",
342 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
343 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
344 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
345 "emit" => '. rsb %D1, %S1, %S2%X'
350 "comment" => "construct Rsb: Rsb(a, const) = const - a",
351 "attr" => "tarval *tv",
352 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
353 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
354 "emit" => '. rsb %D1, %S1, %C',
355 "cmp_attr" => 'return attr_a->value != attr_b->value;'
360 "comment" => "construct Shl: Shl(a, b) = a << b",
361 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
362 "emit" => '. mov %D1, %S1, lsl %S2'
367 "comment" => "construct Shr: Shr(a, b) = a >> b",
368 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
369 "emit" => '. mov %D1, %S1, lsr %S2'
374 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
375 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
376 "emit" => '. mov %D1, %S1, asr %S2'
380 # "irn_flags" => "R",
381 # "comment" => "construct RotR: RotR(a, b) = a ROTR b",
382 # "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
383 # "emit" => '. mov %D1, %S1, ror %S2 /* RotR(%S1, %S2) -> %D1, (%A1, %A2) */'
384 ## "emit" => '. ror %S1, %S2, %D1'
388 # "irn_flags" => "R",
389 # "comment" => "construct RotL: RotL(a, b) = a ROTL b",
390 # "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
391 # "emit" => '. rol %S1, %S2, %D1'
395 # "irn_flags" => "R",
396 # "comment" => "construct RotL: RotL(a, const) = a ROTL const",
397 # "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
398 # "emit" => '. rol %S1, %C, %D1'
403 "comment" => "construct Mov: a = b",
404 "attr" => "arm_shift_modifier mod, tarval *shf",
405 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
406 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
407 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
408 "emit" => '. mov %D1, %S1%X'
413 "comment" => "represents an integer constant",
414 "attr" => "tarval *tv",
415 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
416 "reg_req" => { "out" => [ "gp" ] },
417 "emit" => '. mov %D1, %C',
418 "cmp_attr" => 'return attr_a->value != attr_b->value;'
423 "comment" => "construct Not: Not(a) = !a",
424 "attr" => "arm_shift_modifier mod, tarval *shf",
425 "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
426 "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
427 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
428 "emit" => '. mvn %D1, %S1%X'
433 "comment" => "represents a negated integer constant",
434 "attr" => "tarval *tv",
435 "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
436 "cmp_attr" => 'return attr_a->value != attr_b->value;',
437 "reg_req" => { "out" => [ "gp" ] },
438 "emit" => '. mvn %D1, %C',
443 "comment" => "construct Abs: Abs(a) = |a|",
444 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
446 '. movs %S1, %S1, #0 /* set condition flag */\n
447 . rsbmi %D1, %S1, #0'
455 "comment" => "allocate an empty register for calculations",
456 "reg_req" => { "out" => [ "gp" ] },
457 "emit" => '. /* %D1 now available for calculations */',
458 "cmp_attr" => 'return 1;'
462 "comment" => "implements a register copy",
463 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
469 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
470 "reg_req" => { "in" => [ "!sp", "!sp", "gp", "gp", "gp", "none" ], "out" => [ "none" ] },
476 "comment" => "represents a symbolic constant",
477 "attr" => "const char *label",
478 "init_attr" => ' attr->symconst_label = label;',
479 "reg_req" => { "out" => [ "gp" ] },
481 ' /* should be identical but ...*/
482 return strcmp(attr_a->symconst_label, attr_b->symconst_label);'
486 "op_flags" => "L|X|Y",
487 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
488 "cmp_attr" => " return arm_comp_condJmp(attr_a, attr_b);\n",
489 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "none", "none"] },
493 "op_flags" => "L|X|Y",
494 "comment" => "construct switch",
495 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
496 "cmp_attr" => " return 0;\n",
504 "state" => "exc_pinned",
505 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
506 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp", "none" ] },
507 "emit" => '. ldr %D1, [%S1, #0]',
508 "outs" => [ "res", "M" ],
514 "state" => "exc_pinned",
515 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
516 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp", "none" ] },
517 "emit" => '. ldrb %D1, [%S1, #0]',
518 "outs" => [ "res", "M" ],
524 "state" => "exc_pinned",
525 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
526 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp", "none" ] },
527 "emit" => '. ldrsb %D1, [%S1, #0]',
528 "outs" => [ "res", "M" ],
534 "state" => "exc_pinned",
535 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
536 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp", "none" ] },
537 "emit" => '. ldrh %D1, [%S1, #0]',
538 "outs" => [ "res", "M" ],
544 "state" => "exc_pinned",
545 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
546 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp", "none" ] },
547 "emit" => '. ldrsh %D1, [%S1, #0]',
548 "outs" => [ "res", "M" ],
554 "state" => "exc_pinned",
555 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
556 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
557 "emit" => '. strb %S2, [%S1, #0]',
564 "state" => "exc_pinned",
565 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
566 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
567 "emit" => '. strsb %S2, [%S1, #0]',
574 "state" => "exc_pinned",
575 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
576 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
577 "emit" => '. strh %S2, [%S1, #0]',
584 "state" => "exc_pinned",
585 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
586 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
587 "emit" => '. strhs %S2, [%S1, #0]',
594 "state" => "exc_pinned",
595 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
596 "reg_req" => { "in" => [ "gp", "gp", "none" ] },
597 "emit" => '. str %S2, [%S1, #0]',
601 "StoreStackM4Inc" => {
604 "state" => "exc_pinned",
605 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
606 "reg_req" => { "in" => [ "sp", "gp", "gp", "gp", "gp", "none" ], "out" => [ "gp", "none" ] },
607 "emit" => '. stmfd %S1!, {%S2, %S3, %S4, %S5}',
608 "outs" => [ "ptr", "M" ],
614 "state" => "exc_pinned",
615 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
616 "reg_req" => { "in" => [ "sp", "none" ], "out" => [ "gp", "gp", "gp", "none" ] },
617 "emit" => '. ldmfd %S1, {%D1, %D2, %D3}',
618 "outs" => [ "res0", "res1", "res2", "M" ],
622 #---------------------------------------------------#
625 # | |_ _ __ __ _ _ __ ___ __| | ___ ___ #
626 # | _| '_ \ / _` | | '_ \ / _ \ / _` |/ _ \/ __| #
627 # | | | |_) | (_| | | | | | (_) | (_| | __/\__ \ #
628 # |_| | .__/ \__,_| |_| |_|\___/ \__,_|\___||___/ #
631 #---------------------------------------------------#
633 # commutative operations
638 "comment" => "construct FPA Add: Add(a, b) = Add(b, a) = a + b",
639 "reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
640 "emit" => '. adf%M %D1, %S1, %S2',
645 "comment" => "construct FPA Mul: Mul(a, b) = Mul(b, a) = a * b",
646 "reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
647 "emit" =>'. muf%M %D1, %S1, %S2',
652 "comment" => "construct FPA Fast Mul: Mul(a, b) = Mul(b, a) = a * b",
653 "reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
654 "emit" =>'. fml%M %D1, %S1, %S2',
660 "comment" => "construct FPA Max: Max(a, b) = Max(b, a) = a > b ? a : b",
661 "reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
662 "emit" =>'. fmax %S1, %S2, %D1',
668 "comment" => "construct FPA Min: Min(a, b) = Min(b, a) = a < b ? a : b",
669 "reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
670 "emit" =>'. fmin %S1, %S2, %D1',
673 # not commutative operations
677 "comment" => "construct FPA Sub: Sub(a, b) = a - b",
678 "reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
679 "emit" => '. suf%M %D1, %S1, %S2'
684 "comment" => "construct FPA reverse Sub: Sub(a, b) = b - a",
685 "reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
686 "emit" => '. rsf%M %D1, %S1, %S2'
690 "comment" => "construct FPA Div: Div(a, b) = a / b",
691 "reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
692 "emit" =>'. dvf%M %D1, %S1, %S2',
696 "comment" => "construct FPA reverse Div: Div(a, b) = b / a",
697 "reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
698 "emit" =>'. rdf%M %D1, %S1, %S2',
702 "comment" => "construct FPA Fast Div: Div(a, b) = a / b",
703 "reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
704 "emit" =>'. fdv%M %D1, %S1, %S2',
708 "comment" => "construct FPA Fast reverse Div: Div(a, b) = b / a",
709 "reg_req" => { "in" => [ "fpa", "fpa" ], "out" => [ "fpa" ] },
710 "emit" =>'. frd%M %D1, %S1, %S2',
715 "comment" => "construct FPA Move: b = a",
716 "reg_req" => { "in" => [ "fpa" ], "out" => [ "fpa" ] },
717 "emit" => '. mvf%M %S1, %D1',
722 "comment" => "construct FPA Move Negated: b = -a",
723 "reg_req" => { "in" => [ "fpa" ], "out" => [ "fpa" ] },
724 "emit" => '. mnf%M %S1, %D1',
729 "comment" => "construct FPA Absolute value: fAbsd(a) = |a|",
730 "reg_req" => { "in" => [ "fpa" ], "out" => [ "fpa" ] },
731 "emit" => '. abs%M %D1, %S1',
739 "comment" => "represents a FPA constant",
740 "attr" => "tarval *val",
741 "init_attr" => 'attr->value = val;',
742 "reg_req" => { "out" => [ "fpa" ] },
743 "emit" => '. fmov %D1, %C',
744 "cmp_attr" => 'return attr_a->value != attr_b->value;',
749 "comment" => "construct a FPA integer->float conversion",
750 "reg_req" => { "in" => ["gp"], "out" => [ "fpa" ] },
751 "emit" => '. flt%M %D1, %S1',
756 "comment" => "construct a FPA float->integer conversion",
757 "reg_req" => { "in" => ["fpa"], "out" => [ "gp" ] },
758 "emit" => '. fix %D1, %S1',
766 "state" => "exc_pinned",
767 "comment" => "construct FPA Load: Load(ptr, mem) = LD ptr",
768 "attr" => "ir_mode *op_mode",
769 "init_attr" => "attr->op_mode = op_mode;",
770 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "fpa", "none" ] },
771 "emit" => '. ldf%M %D1, [%S1, #0]',
772 "outs" => [ "res", "M" ],
778 "state" => "exc_pinned",
779 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
780 "attr" => "ir_mode *op_mode",
781 "init_attr" => "attr->op_mode = op_mode;",
782 "reg_req" => { "in" => [ "gp", "fpa", "none" ] },
783 "emit" => '. stf%M [%S2, #0], %S1',
790 "state" => "exc_pinned",
791 "comment" => "construct fp double to 2 gp register transfer",
792 "reg_req" => { "in" => [ "fpa", "none" ], "out" => [ "gp", "gp" ] },
793 "outs" => [ "low", "high", "M" ],
797 #---------------------------------------------------#
800 # __ _| |_ _ __ _ __ ___ __| | ___ ___ #
801 # \ \ / / _| '_ \ | '_ \ / _ \ / _` |/ _ \/ __| #
802 # \ V /| | | |_) | | | | | (_) | (_| | __/\__ \ #
803 # \_/ |_| | .__/ |_| |_|\___/ \__,_|\___||___/ #
806 #---------------------------------------------------#