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4 * This file is part of libFirm.
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15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for ARM.
23 * @author Michael Beck
35 #include "bepeephole.h"
38 #include "arm_optimize.h"
39 #include "gen_arm_regalloc_if.h"
40 #include "gen_arm_new_nodes.h"
42 static const arch_env_t *arch_env;
43 static arm_code_gen_t *cg;
45 /** Execute ARM ROL. */
46 static unsigned arm_rol(unsigned v, unsigned rol) {
47 return (v << rol) | (v >> (32 - rol));
51 * construct 8bit values and rot amounts for a value.
53 void arm_gen_vals_from_word(unsigned int value, arm_vals *result)
57 memset(result, 0, sizeof(*result));
59 /* special case: we prefer shift amount 0 */
61 result->values[0] = value;
68 unsigned v = arm_rol(value, 8) & 0xFFFFFF;
77 shf = (initial + shf - 8) & 0x1F;
78 result->values[result->ops] = v;
79 result->shifts[result->ops] = shf;
82 value ^= arm_rol(v, shf) >> initial;
92 * Encodes an immediate with shifter operand
94 unsigned int arm_encode_imm_w_shift(unsigned int shift, unsigned int immediate) {
95 return immediate | ((shift>>1)<<8);
99 * Decode an immediate with shifter operand
101 unsigned int arm_decode_imm_w_shift(long imm_value) {
102 unsigned l = (unsigned)imm_value;
103 unsigned rol = (l & ~0xFF) >> 7;
105 return arm_rol(l & 0xFF, rol);
109 * Returns non.zero if the given offset can be directly encoded into an ARM instruction.
111 static int allowed_arm_immediate(int offset, arm_vals *result) {
112 arm_gen_vals_from_word(offset, result);
113 return result->ops <= 1;
117 * Fix an IncSP node if the offset gets too big
119 static void peephole_be_IncSP(ir_node *node) {
122 int offset, cnt, align, sign = 1;
125 /* first optimize incsp->incsp combinations */
126 node = be_peephole_IncSP_IncSP(node);
128 offset = be_get_IncSP_offset(node);
129 /* can be transformed into Add OR Sub */
134 if (allowed_arm_immediate(offset, &v))
137 be_set_IncSP_offset(node, (int)arm_rol(v.values[0], v.shifts[0]) * sign);
139 irg = current_ir_graph;
140 block = get_nodes_block(node);
141 align = be_get_IncSP_align(node);
142 for (cnt = 1; cnt < v.ops; ++cnt) {
143 int value = (int)arm_rol(v.values[cnt], v.shifts[cnt]);
144 ir_node *next = be_new_IncSP(&arm_gp_regs[REG_SP], irg, block, node, value * sign, align);
145 sched_add_after(node, next);
151 * creates the address by Adds
153 static ir_node *gen_ptr_add(ir_node *node, ir_node *frame, arm_vals *v)
155 ir_graph *irg = current_ir_graph;
156 dbg_info *dbg = get_irn_dbg_info(node);
157 ir_node *block = get_nodes_block(node);
161 ptr = new_rd_arm_Add_i(dbg, irg, block, frame, mode_Iu, arm_encode_imm_w_shift(v->shifts[0], v->values[0]));
162 arch_set_irn_register(arch_env, ptr, &arm_gp_regs[REG_R12]);
163 sched_add_before(node, ptr);
165 for (cnt = 1; cnt < v->ops; ++cnt) {
166 long value = arm_encode_imm_w_shift(v->shifts[cnt], v->values[cnt]);
167 ir_node *next = new_rd_arm_Add_i(dbg, irg, block, ptr, mode_Iu, value);
168 arch_set_irn_register(arch_env, next, &arm_gp_regs[REG_R12]);
169 sched_add_before(node, next);
176 * creates the address by Subs
178 static ir_node *gen_ptr_sub(ir_node *node, ir_node *frame, arm_vals *v)
180 ir_graph *irg = current_ir_graph;
181 dbg_info *dbg = get_irn_dbg_info(node);
182 ir_node *block = get_nodes_block(node);
186 ptr = new_rd_arm_Sub_i(dbg, irg, block, frame, mode_Iu, arm_encode_imm_w_shift(v->shifts[0], v->values[0]));
187 arch_set_irn_register(arch_env, ptr, &arm_gp_regs[REG_R12]);
188 sched_add_before(node, ptr);
190 for (cnt = 1; cnt < v->ops; ++cnt) {
191 long value = arm_encode_imm_w_shift(v->shifts[cnt], v->values[cnt]);
192 ir_node *next = new_rd_arm_Sub_i(dbg, irg, block, ptr, mode_Iu, value);
193 arch_set_irn_register(arch_env, next, &arm_gp_regs[REG_R12]);
194 sched_add_before(node, next);
201 * Fix an be_Spill node if the offset gets too big
203 static void peephole_be_Spill(ir_node *node) {
204 ir_entity *ent = be_get_frame_entity(node);
205 int use_add = 1, offset = get_entity_offset(ent);
206 ir_node *block, *ptr, *frame, *value, *store;
212 if (allowed_arm_immediate(offset, &v))
219 frame = be_get_Spill_frame(node);
221 ptr = gen_ptr_add(node, frame, &v);
223 ptr = gen_ptr_sub(node, frame, &v);
226 value = be_get_Spill_val(node);
227 mode = get_irn_mode(value);
228 irg = current_ir_graph;
229 dbg = get_irn_dbg_info(node);
230 block = get_nodes_block(node);
232 if (mode_is_float(mode)) {
233 if (USE_FPA(cg->isa)) {
234 /* transform into fpaStf */
235 store = new_rd_arm_fpaStf(dbg, irg, block, ptr, value, get_irg_no_mem(irg), mode);
236 sched_add_before(node, store);
238 panic("peephole_be_Spill: spill not supported for this mode");
240 } else if (mode_is_dataM(mode)) {
241 /* transform into Store */;
242 store = new_rd_arm_Store(dbg, irg, block, ptr, value, get_irg_no_mem(irg));
243 sched_add_before(node, store);
245 panic("peephole_be_Spill: spill not supported for this mode");
248 be_peephole_exchange(node, store);
252 * Fix an be_Reload node if the offset gets too big
254 static void peephole_be_Reload(ir_node *node) {
255 ir_entity *ent = be_get_frame_entity(node);
256 int use_add = 1, offset = get_entity_offset(ent);
257 ir_node *block, *ptr, *frame, *load, *mem, *proj;
262 const arch_register_t *reg;
264 if (allowed_arm_immediate(offset, &v))
271 frame = be_get_Reload_frame(node);
273 ptr = gen_ptr_add(node, frame, &v);
275 ptr = gen_ptr_sub(node, frame, &v);
278 reg = arch_get_irn_register(arch_env, node);
279 mem = be_get_Reload_mem(node);
280 mode = get_irn_mode(node);
281 irg = current_ir_graph;
282 dbg = get_irn_dbg_info(node);
283 block = get_nodes_block(node);
285 if (mode_is_float(mode)) {
286 if (USE_FPA(cg->isa)) {
287 /* transform into fpaLdf */
288 load = new_rd_arm_fpaLdf(dbg, irg, block, ptr, mem, mode);
289 sched_add_before(node, load);
290 proj = new_rd_Proj(dbg, irg, block, load, mode, pn_arm_fpaLdf_res);
291 arch_set_irn_register(arch_env, proj, reg);
293 panic("peephole_be_Spill: spill not supported for this mode");
295 } else if (mode_is_dataM(mode)) {
296 /* transform into Store */;
297 load = new_rd_arm_Load(dbg, irg, block, ptr, mem);
298 sched_add_before(node, load);
299 proj = new_rd_Proj(dbg, irg, block, load, mode_Iu, pn_arm_Load_res);
300 arch_set_irn_register(arch_env, proj, reg);
302 panic("peephole_be_Spill: spill not supported for this mode");
305 be_peephole_exchange(node, proj);
309 * Register a peephole optimization function.
311 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
312 assert(op->ops.generic == NULL);
313 op->ops.generic = (op_func)func;
316 /* Perform peephole-optimizations. */
317 void arm_peephole_optimization(arm_code_gen_t *new_cg)
320 arch_env = cg->arch_env;
322 /* register peephole optimizations */
323 clear_irp_opcodes_generic_func();
324 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
325 register_peephole_optimisation(op_be_Spill, peephole_be_Spill);
326 register_peephole_optimisation(op_be_Reload, peephole_be_Reload);
328 be_peephole_opt(cg->birg);