2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for ARM.
23 * @author Michael Beck
33 #include "bepeephole.h"
36 #include "arm_optimize.h"
37 #include "gen_arm_regalloc_if.h"
38 #include "gen_arm_new_nodes.h"
40 static arm_code_gen_t *cg;
42 /** Execute ARM ROL. */
43 static unsigned arm_rol(unsigned v, unsigned rol) {
44 return (v << rol) | (v >> (32 - rol));
48 * construct 8bit values and rot amounts for a value.
50 void arm_gen_vals_from_word(unsigned int value, arm_vals *result)
54 memset(result, 0, sizeof(*result));
56 /* special case: we prefer shift amount 0 */
58 result->values[0] = value;
65 unsigned v = arm_rol(value, 8) & 0xFFFFFF;
74 shf = (initial + shf - 8) & 0x1F;
75 result->values[result->ops] = v;
76 result->shifts[result->ops] = shf;
79 value ^= arm_rol(v, shf) >> initial;
89 * Encodes an immediate with shifter operand
91 unsigned int arm_encode_imm_w_shift(unsigned int shift, unsigned int immediate) {
92 return immediate | ((shift>>1)<<8);
96 * Decode an immediate with shifter operand
98 unsigned int arm_decode_imm_w_shift(long imm_value) {
99 unsigned l = (unsigned)imm_value;
100 unsigned rol = (l & ~0xFF) >> 7;
102 return arm_rol(l & 0xFF, rol);
106 * Returns non.zero if the given offset can be directly encoded into an ARM instruction.
108 static int allowed_arm_immediate(int offset, arm_vals *result) {
109 arm_gen_vals_from_word(offset, result);
110 return result->ops <= 1;
114 * Fix an IncSP node if the offset gets too big
116 static void peephole_be_IncSP(ir_node *node) {
118 int offset, cnt, align, sign = 1;
121 /* first optimize incsp->incsp combinations */
122 node = be_peephole_IncSP_IncSP(node);
124 offset = be_get_IncSP_offset(node);
125 /* can be transformed into Add OR Sub */
130 if (allowed_arm_immediate(offset, &v))
133 be_set_IncSP_offset(node, (int)arm_rol(v.values[0], v.shifts[0]) * sign);
135 block = get_nodes_block(node);
136 align = be_get_IncSP_align(node);
137 for (cnt = 1; cnt < v.ops; ++cnt) {
138 int value = (int)arm_rol(v.values[cnt], v.shifts[cnt]);
139 ir_node *next = be_new_IncSP(&arm_gp_regs[REG_SP], block, node, value * sign, align);
140 sched_add_after(node, next);
146 * creates the address by Adds
148 static ir_node *gen_ptr_add(ir_node *node, ir_node *frame, arm_vals *v)
150 dbg_info *dbg = get_irn_dbg_info(node);
151 ir_node *block = get_nodes_block(node);
155 ptr = new_bd_arm_Add_i(dbg, block, frame, mode_Iu, arm_encode_imm_w_shift(v->shifts[0], v->values[0]));
156 arch_set_irn_register(ptr, &arm_gp_regs[REG_R12]);
157 sched_add_before(node, ptr);
159 for (cnt = 1; cnt < v->ops; ++cnt) {
160 long value = arm_encode_imm_w_shift(v->shifts[cnt], v->values[cnt]);
161 ir_node *next = new_bd_arm_Add_i(dbg, block, ptr, mode_Iu, value);
162 arch_set_irn_register(next, &arm_gp_regs[REG_R12]);
163 sched_add_before(node, next);
170 * creates the address by Subs
172 static ir_node *gen_ptr_sub(ir_node *node, ir_node *frame, arm_vals *v)
174 dbg_info *dbg = get_irn_dbg_info(node);
175 ir_node *block = get_nodes_block(node);
179 ptr = new_bd_arm_Sub_i(dbg, block, frame, mode_Iu, arm_encode_imm_w_shift(v->shifts[0], v->values[0]));
180 arch_set_irn_register(ptr, &arm_gp_regs[REG_R12]);
181 sched_add_before(node, ptr);
183 for (cnt = 1; cnt < v->ops; ++cnt) {
184 long value = arm_encode_imm_w_shift(v->shifts[cnt], v->values[cnt]);
185 ir_node *next = new_bd_arm_Sub_i(dbg, block, ptr, mode_Iu, value);
186 arch_set_irn_register(next, &arm_gp_regs[REG_R12]);
187 sched_add_before(node, next);
194 * Fix an be_Spill node if the offset gets too big
196 static void peephole_be_Spill(ir_node *node) {
197 ir_entity *ent = be_get_frame_entity(node);
198 int use_add = 1, offset = get_entity_offset(ent);
199 ir_node *block, *ptr, *frame, *value, *store;
205 if (allowed_arm_immediate(offset, &v))
212 frame = be_get_Spill_frame(node);
214 ptr = gen_ptr_add(node, frame, &v);
216 ptr = gen_ptr_sub(node, frame, &v);
219 value = be_get_Spill_val(node);
220 mode = get_irn_mode(value);
221 irg = current_ir_graph;
222 dbg = get_irn_dbg_info(node);
223 block = get_nodes_block(node);
225 if (mode_is_float(mode)) {
226 if (USE_FPA(cg->isa)) {
227 /* transform into fpaStf */
228 store = new_bd_arm_fpaStf(dbg, block, ptr, value, get_irg_no_mem(irg), mode);
229 sched_add_before(node, store);
231 panic("peephole_be_Spill: spill not supported for this mode");
233 } else if (mode_is_dataM(mode)) {
234 /* transform into Store */;
235 store = new_bd_arm_Store(dbg, block, ptr, value, get_irg_no_mem(irg));
236 sched_add_before(node, store);
238 panic("peephole_be_Spill: spill not supported for this mode");
241 be_peephole_exchange(node, store);
245 * Fix an be_Reload node if the offset gets too big
247 static void peephole_be_Reload(ir_node *node) {
248 ir_entity *ent = be_get_frame_entity(node);
249 int use_add = 1, offset = get_entity_offset(ent);
250 ir_node *block, *ptr, *frame, *load, *mem, *proj;
254 const arch_register_t *reg;
256 if (allowed_arm_immediate(offset, &v))
263 frame = be_get_Reload_frame(node);
265 ptr = gen_ptr_add(node, frame, &v);
267 ptr = gen_ptr_sub(node, frame, &v);
270 reg = arch_get_irn_register(node);
271 mem = be_get_Reload_mem(node);
272 mode = get_irn_mode(node);
273 dbg = get_irn_dbg_info(node);
274 block = get_nodes_block(node);
276 if (mode_is_float(mode)) {
277 if (USE_FPA(cg->isa)) {
278 /* transform into fpaLdf */
279 load = new_bd_arm_fpaLdf(dbg, block, ptr, mem, mode);
280 sched_add_before(node, load);
281 proj = new_rd_Proj(dbg, block, load, mode, pn_arm_fpaLdf_res);
282 arch_set_irn_register(proj, reg);
284 panic("peephole_be_Spill: spill not supported for this mode");
286 } else if (mode_is_dataM(mode)) {
287 /* transform into Store */;
288 load = new_bd_arm_Load(dbg, block, ptr, mem);
289 sched_add_before(node, load);
290 proj = new_rd_Proj(dbg, block, load, mode_Iu, pn_arm_Load_res);
291 arch_set_irn_register(proj, reg);
293 panic("peephole_be_Spill: spill not supported for this mode");
296 be_peephole_exchange(node, proj);
300 * Register a peephole optimization function.
302 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
303 assert(op->ops.generic == NULL);
304 op->ops.generic = (op_func)func;
307 /* Perform peephole-optimizations. */
308 void arm_peephole_optimization(arm_code_gen_t *new_cg)
312 /* register peephole optimizations */
313 clear_irp_opcodes_generic_func();
314 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
315 register_peephole_optimisation(op_be_Spill, peephole_be_Spill);
316 register_peephole_optimisation(op_be_Reload, peephole_be_Reload);
318 be_peephole_opt(cg->birg);