2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the creation of the architecture specific firm
23 * opcodes and the corresponding node constructors for the arm
25 * @author Oliver Richter, Tobias Gneist
35 #include "irgraph_t.h"
41 #include "firm_common_t.h"
46 #include "../bearch_t.h"
48 #include "arm_nodes_attr.h"
49 #include "arm_new_nodes.h"
52 #include "bearch_arm_t.h"
55 * Returns the shift modifier string.
57 const char *arm_shf_mod_name(arm_shift_modifier mod) {
58 static const char *names[] = { NULL, NULL, "asr", "lsl", "lsr", "ror", "rrx" };
62 /***********************************************************************************
65 * __| |_ _ _ __ ___ _ __ ___ _ __ _ _ __ | |_ ___ _ __| |_ __ _ ___ ___
66 * / _` | | | | '_ ` _ \| '_ \ / _ \ '__| | | '_ \| __/ _ \ '__| _/ _` |/ __/ _ \
67 * | (_| | |_| | | | | | | |_) | __/ | | | | | | || __/ | | || (_| | (_| __/
68 * \__,_|\__,_|_| |_| |_| .__/ \___|_| |_|_| |_|\__\___|_| |_| \__,_|\___\___|
71 ***********************************************************************************/
74 * Dumps the register requirements for either in or out.
76 static void dump_reg_req(FILE *F, const ir_node *node,
77 const arch_register_req_t **reqs, int inout) {
78 char *dir = inout ? "out" : "in";
79 int max = inout ? get_arm_n_res(node) : get_irn_arity(node);
83 memset(buf, 0, sizeof(buf));
86 for (i = 0; i < max; i++) {
87 fprintf(F, "%sreq #%d =", dir, i);
89 if (reqs[i]->type == arch_register_req_type_none) {
93 if (reqs[i]->type & arch_register_req_type_normal) {
94 fprintf(F, " %s", reqs[i]->cls->name);
97 if (reqs[i]->type & arch_register_req_type_limited) {
99 arch_register_req_format(buf, sizeof(buf), reqs[i], node));
102 if (reqs[i]->type & arch_register_req_type_should_be_same) {
103 const unsigned other = reqs[i]->other_same;
106 ir_fprintf(F, " same as");
107 for (i = 0; 1U << i <= other; ++i) {
108 if (other & (1U << i)) {
109 ir_fprintf(F, " %+F", get_irn_n(node, i));
114 if (reqs[i]->type & arch_register_req_type_should_be_different) {
115 const unsigned other = reqs[i]->other_different;
118 ir_fprintf(F, " different from");
119 for (i = 0; 1U << i <= other; ++i) {
120 if (other & (1U << i)) {
121 ir_fprintf(F, " %+F", get_irn_n(node, i));
131 fprintf(F, "%sreq = N/A\n", dir);
136 * Dumper interface for dumping arm nodes in vcg.
137 * @param n the node to dump
138 * @param F the output file
139 * @param reason indicates which kind of information should be dumped
140 * @return 0 on success or != 0 on failure
142 static int arm_dump_node(ir_node *n, FILE *F, dump_reason_t reason) {
143 ir_mode *mode = NULL;
146 arm_attr_t *attr = get_arm_attr(n);
147 const arch_register_req_t **reqs;
148 const arch_register_t **slots;
149 arm_shift_modifier mod;
152 case dump_node_opcode_txt:
153 fprintf(F, "%s", get_irn_opname(n));
156 case dump_node_mode_txt:
157 mode = get_irn_mode(n);
160 fprintf(F, "[%s]", get_mode_name(mode));
163 fprintf(F, "[?NOMODE?]");
167 case dump_node_nodeattr_txt:
168 mod = ARM_GET_SHF_MOD(attr);
169 if (ARM_HAS_SHIFT(mod)) {
170 fprintf(F, "[%s #%ld]", arm_shf_mod_name(mod), get_tarval_long(attr->value));
172 else if (mod == ARM_SHF_IMM) {
174 fprintf(F, "[#0x%X]", arm_decode_imm_w_shift(attr->value));
178 case dump_node_info_txt:
179 fprintf(F, "=== arm attr begin ===\n");
181 /* dump IN requirements */
182 if (get_irn_arity(n) > 0) {
183 reqs = get_arm_in_req_all(n);
184 dump_reg_req(F, n, reqs, 0);
187 /* dump OUT requirements */
188 if (ARR_LEN(attr->slots) > 0) {
189 reqs = get_arm_out_req_all(n);
190 dump_reg_req(F, n, reqs, 1);
193 /* dump assigned registers */
194 slots = get_arm_slots(n);
195 if (slots && ARR_LEN(attr->slots) > 0) {
196 for (i = 0; i < ARR_LEN(attr->slots); i++) {
198 fprintf(F, "reg #%d = %s\n", i, slots[i]->name);
201 fprintf(F, "reg #%d = n/a\n", i);
208 fprintf(F, "n_res = %d\n", get_arm_n_res(n));
211 fprintf(F, "flags =");
212 if (attr->flags == arch_irn_flags_none) {
216 if (attr->flags & arch_irn_flags_dont_spill) {
217 fprintf(F, " unspillable");
219 if (attr->flags & arch_irn_flags_rematerializable) {
220 fprintf(F, " remat");
222 if (attr->flags & arch_irn_flags_ignore) {
223 fprintf(F, " ignore");
226 fprintf(F, " (%d)\n", attr->flags);
228 if (get_arm_value(n)) {
229 if (is_arm_CopyB(n)) {
230 fprintf(F, "size = %lu\n", get_tarval_long(get_arm_value(n)));
232 if (mode_is_float(get_irn_mode(n))) {
233 fprintf(F, "float value = (%f)\n", (double) get_tarval_double(get_arm_value(n)));
234 } else if (mode_is_int(get_irn_mode(n))) {
235 long v = get_tarval_long(get_arm_value(n));
236 fprintf(F, "long value = %ld (0x%08lx)\n", v, v);
237 } else if (mode_is_reference(get_irn_mode(n))) {
238 fprintf(F, "pointer\n");
240 assert(0 && "unbehandelter Typ im const-Knoten");
244 if (is_arm_CmpBra(n) && get_arm_CondJmp_proj_num(n) >= 0) {
245 fprintf(F, "proj_num = (%d)\n", get_arm_CondJmp_proj_num(n));
247 /* TODO: dump all additional attributes */
249 fprintf(F, "=== arm attr end ===\n");
250 /* end of: case dump_node_info_txt */
258 /***************************************************************************************************
260 * | | | | | | / / | | | | | | | |
261 * __ _| |_| |_ _ __ ___ ___| |_ / /_ _ ___| |_ _ __ ___ ___| |_| |__ ___ __| |___
262 * / _` | __| __| '__| / __|/ _ \ __| / / _` |/ _ \ __| | '_ ` _ \ / _ \ __| '_ \ / _ \ / _` / __|
263 * | (_| | |_| |_| | \__ \ __/ |_ / / (_| | __/ |_ | | | | | | __/ |_| | | | (_) | (_| \__ \
264 * \__,_|\__|\__|_| |___/\___|\__/_/ \__, |\___|\__| |_| |_| |_|\___|\__|_| |_|\___/ \__,_|___/
267 ***************************************************************************************************/
269 /* Returns the attributes of a generic Arm node. */
270 arm_attr_t *get_arm_attr(ir_node *node) {
271 assert(is_arm_irn(node) && "need arm node to get attributes");
272 return get_irn_generic_attr(node);
275 const arm_attr_t *get_arm_attr_const(const ir_node *node) {
276 assert(is_arm_irn(node) && "need arm node to get attributes");
277 return get_irn_generic_attr_const(node);
281 * Returns the attributes of an ARM SymConst node.
283 arm_SymConst_attr_t *get_arm_SymConst_attr(ir_node *node) {
284 assert(is_arm_SymConst(node));
285 return get_irn_generic_attr(node);
288 const arm_SymConst_attr_t *get_arm_SymConst_attr_const(const ir_node *node) {
289 assert(is_arm_SymConst(node));
290 return get_irn_generic_attr_const(node);
293 static int is_arm_CondJmp(const ir_node *node) {
294 int code = get_arm_irn_opcode(node);
296 return (code == iro_arm_CmpBra || code == iro_arm_fpaCmfBra ||
297 code == iro_arm_fpaCnfBra || iro_arm_fpaCmfeBra ||
298 code == iro_arm_fpaCnfeBra);
301 /* Returns the attributes of a CondJmp node. */
302 arm_CondJmp_attr_t *get_arm_CondJmp_attr(ir_node *node) {
303 assert(is_arm_CondJmp(node));
304 return get_irn_generic_attr(node);
307 const arm_CondJmp_attr_t *get_arm_CondJmp_attr_const(const ir_node *node) {
308 assert(is_arm_CondJmp(node));
309 return get_irn_generic_attr_const(node);
312 /* Returns the attributes of a SwitchJmp node. */
313 arm_SwitchJmp_attr_t *get_arm_SwitchJmp_attr(ir_node *node) {
314 assert(is_arm_SwitchJmp(node));
315 return get_irn_generic_attr(node);
318 const arm_SwitchJmp_attr_t *get_arm_SwitchJmp_attr_const(const ir_node *node) {
319 assert(is_arm_SwitchJmp(node));
320 return get_irn_generic_attr_const(node);
324 * Returns the argument register requirements of a arm node.
326 const arch_register_req_t **get_arm_in_req_all(const ir_node *node) {
327 const arm_attr_t *attr = get_arm_attr_const(node);
332 * Returns the result register requirements of an arm node.
334 const arch_register_req_t **get_arm_out_req_all(const ir_node *node) {
335 const arm_attr_t *attr = get_arm_attr_const(node);
336 return attr->out_req;
340 * Returns the argument register requirement at position pos of an arm node.
342 const arch_register_req_t *get_arm_in_req(const ir_node *node, int pos) {
343 const arm_attr_t *attr = get_arm_attr_const(node);
344 return attr->in_req[pos];
348 * Returns the result register requirement at position pos of an arm node.
350 const arch_register_req_t *get_arm_out_req(const ir_node *node, int pos) {
351 const arm_attr_t *attr = get_arm_attr_const(node);
352 return attr->out_req[pos];
356 * Sets the OUT register requirements at position pos.
358 void set_arm_req_out(ir_node *node, const arch_register_req_t *req, int pos) {
359 arm_attr_t *attr = get_arm_attr(node);
360 attr->out_req[pos] = req;
364 * Sets the complete OUT requirements of node.
366 void set_arm_req_out_all(ir_node *node, const arch_register_req_t **reqs) {
367 arm_attr_t *attr = get_arm_attr(node);
368 attr->out_req = reqs;
372 * Sets the IN register requirements at position pos.
374 void set_arm_req_in(ir_node *node, const arch_register_req_t *req, int pos) {
375 arm_attr_t *attr = get_arm_attr(node);
376 attr->in_req[pos] = req;
380 * Returns the register flag of an arm node.
382 arch_irn_flags_t get_arm_flags(const ir_node *node) {
383 const arm_attr_t *attr = get_arm_attr_const(node);
388 * Sets the register flag of an arm node.
390 void set_arm_flags(ir_node *node, arch_irn_flags_t flags) {
391 arm_attr_t *attr = get_arm_attr(node);
396 * Returns the result register slots of an arm node.
398 const arch_register_t **get_arm_slots(const ir_node *node) {
399 const arm_attr_t *attr = get_arm_attr_const(node);
404 * Returns the name of the OUT register at position pos.
406 const char *get_arm_out_reg_name(const ir_node *node, int pos) {
407 const arm_attr_t *attr = get_arm_attr_const(node);
409 assert(is_arm_irn(node) && "Not an arm node.");
410 assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
411 assert(attr->slots[pos] && "No register assigned");
413 return arch_register_get_name(attr->slots[pos]);
417 * Returns the index of the OUT register at position pos within its register class.
419 int get_arm_out_regnr(const ir_node *node, int pos) {
420 const arm_attr_t *attr = get_arm_attr_const(node);
422 assert(is_arm_irn(node) && "Not an arm node.");
423 assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
424 assert(attr->slots[pos] && "No register assigned");
426 return arch_register_get_index(attr->slots[pos]);
430 * Returns the OUT register at position pos.
432 const arch_register_t *get_arm_out_reg(const ir_node *node, int pos) {
433 const arm_attr_t *attr = get_arm_attr_const(node);
435 assert(is_arm_irn(node) && "Not an arm node.");
436 assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
437 assert(attr->slots[pos] && "No register assigned");
439 return attr->slots[pos];
443 * Sets the flags for the n'th out.
445 void set_arm_out_flags(ir_node *node, arch_irn_flags_t flags, int pos) {
446 arm_attr_t *attr = get_arm_attr(node);
447 assert(pos < ARR_LEN(attr->out_flags) && "Invalid OUT position.");
448 attr->out_flags[pos] = flags;
452 * Gets the flags for the n'th out.
454 arch_irn_flags_t get_arm_out_flags(const ir_node *node, int pos) {
455 const arm_attr_t *attr = get_arm_attr_const(node);
456 assert(pos < ARR_LEN(attr->out_flags) && "Invalid OUT position.");
457 return attr->out_flags[pos];
461 * Returns the number of results.
463 int get_arm_n_res(const ir_node *node) {
464 const arm_attr_t *attr = get_arm_attr_const(node);
465 return ARR_LEN(attr->slots);
468 * Returns the tarvalue
470 tarval *get_arm_value(const ir_node *node) {
471 const arm_attr_t *attr = get_arm_attr_const(node);
478 void set_arm_value(ir_node *node, tarval *tv) {
479 arm_attr_t *attr = get_arm_attr(node);
484 * Returns the proj num
486 int get_arm_CondJmp_proj_num(const ir_node *node) {
487 const arm_CondJmp_attr_t *attr = get_arm_CondJmp_attr_const(node);
488 return attr->proj_num;
494 void set_arm_CondJmp_proj_num(ir_node *node, int proj_num) {
495 arm_CondJmp_attr_t *attr = get_arm_CondJmp_attr(node);
496 attr->proj_num = proj_num;
500 * Returns the SymConst label
502 ident *get_arm_symconst_id(const ir_node *node) {
503 const arm_SymConst_attr_t *attr = get_arm_SymConst_attr_const(node);
504 return attr->symconst_id;
508 * Sets the SymConst label
510 void set_arm_symconst_id(ir_node *node, ident *symconst_id) {
511 arm_SymConst_attr_t *attr = get_arm_SymConst_attr(node);
512 attr->symconst_id = symconst_id;
516 * Returns the number of projs of a SwitchJmp.
518 int get_arm_SwitchJmp_n_projs(const ir_node *node) {
519 const arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr_const(node);
520 return attr->n_projs;
524 * Sets the number of projs.
526 void set_arm_SwitchJmp_n_projs(ir_node *node, int n_projs) {
527 arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr(node);
528 attr->n_projs = n_projs;
532 * Returns the default_proj_num.
534 long get_arm_SwitchJmp_default_proj_num(const ir_node *node) {
535 const arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr_const(node);
536 return attr->default_proj_num;
540 * Sets the default_proj_num.
542 void set_arm_SwitchJmp_default_proj_num(ir_node *node, long default_proj_num) {
543 arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr(node);
544 attr->default_proj_num = default_proj_num;
548 * Gets the shift modifier attribute.
550 arm_shift_modifier get_arm_shift_modifier(const ir_node *node) {
551 const arm_attr_t *attr = get_arm_attr_const(node);
552 return ARM_GET_SHF_MOD(attr);
555 /* Set the ARM machine node attributes to default values. */
556 static void init_arm_attributes(ir_node *node, int flags,
557 const arch_register_req_t ** in_reqs,
558 const arch_register_req_t ** out_reqs,
559 const be_execution_unit_t ***execution_units,
561 ir_graph *irg = get_irn_irg(node);
562 struct obstack *obst = get_irg_obstack(irg);
563 arm_attr_t *attr = get_arm_attr(node);
564 (void) execution_units;
566 attr->in_req = in_reqs;
567 attr->out_req = out_reqs;
569 attr->instr_fl = (ARM_COND_AL << 3) | ARM_SHF_NONE;
572 attr->out_flags = NEW_ARR_D(int, obst, n_res);
573 memset(attr->out_flags, 0, n_res * sizeof(attr->out_flags[0]));
575 attr->slots = NEW_ARR_D(const arch_register_t*, obst, n_res);
576 memset(attr->slots, 0, n_res * sizeof(attr->slots[0]));
579 /************************************************
581 * / _ \ _ __ | |_(_)_ __ ___ (_)_______ _ __ *
582 * | | | | '_ \| __| | '_ ` _ \| |_ / _ \ '__| *
583 * | |_| | |_) | |_| | | | | | | |/ / __/ | *
584 * \___/| .__/ \__|_|_| |_| |_|_/___\___|_| *
586 ************************************************/
588 typedef struct _opt_tuple {
589 ir_op *op_imm_left; /**< immediate is left */
590 ir_op *op_imm_right; /**< immediate is right */
591 ir_op *op_shf_left; /**< shift operand on left */
592 ir_op *op_shf_right; /**< shift operand on right */
595 //static const opt_tuple *opt_ops[iro_arm_last];
597 void arm_set_optimizers(void) {
599 #define STD(op) p_##op = { op_arm_##op##_i, op_arm_##op##_i, op_arm_##op, op_arm_##op }
600 #define LEFT(op) p_##op = { op_arm_##op##_i, NULL, op_arm_##op, NULL }
601 #define SET(op) opt_ops[iro_arm_##op] = &p_##op;
603 static const opt_tuple
612 p_Sub = { op_arm_Sub_i, op_arm_Rsb_i, op_arm_Sub, op_arm_Rsb },
614 memset(opt_ops, 0, sizeof(opt_ops));
627 static int cmp_attr_arm_SymConst(ir_node *a, ir_node *b) {
628 const arm_SymConst_attr_t *attr_a = get_irn_generic_attr_const(a);
629 const arm_SymConst_attr_t *attr_b = get_irn_generic_attr_const(b);
630 return attr_a->symconst_id != attr_b->symconst_id;
633 static int cmp_attr_arm(ir_node *a, ir_node *b) {
634 arm_attr_t *attr_a = get_irn_generic_attr(a);
635 arm_attr_t *attr_b = get_irn_generic_attr(b);
636 return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);
639 static int cmp_attr_arm_CondJmp(ir_node *a, ir_node *b) {
642 /* never identical */
646 static int cmp_attr_arm_SwitchJmp(ir_node *a, ir_node *b) {
649 /* never identical */
653 /** copies the ARM attributes of a node. */
654 static void arm_copy_attr(const ir_node *old_node, ir_node *new_node) {
655 ir_graph *irg = get_irn_irg(new_node);
656 struct obstack *obst = get_irg_obstack(irg);
657 const arm_attr_t *attr_old = get_arm_attr_const(old_node);
658 arm_attr_t *attr_new = get_arm_attr(new_node);
660 /* copy the attributes */
661 memcpy(attr_new, attr_old, get_op_attr_size(get_irn_op(old_node)));
664 attr_new->out_flags =
665 DUP_ARR_D(int, obst, attr_old->out_flags);
666 /* copy register assignments */
668 DUP_ARR_D(arch_register_t*, obst, attr_old->slots);
673 /* Include the generated constructor functions */
674 #include "gen_arm_new_nodes.c.inl"