2 * This file implements the creation of the achitecture specific firm opcodes
3 * and the coresponding node constructors for the arm assembler irg.
19 #include "irgraph_t.h"
25 #include "firm_common_t.h"
29 #include "../bearch.h"
31 #include "arm_nodes_attr.h"
32 #include "arm_new_nodes.h"
33 #include "gen_arm_regalloc_if.h"
36 #include "bearch_arm_t.h"
39 /***********************************************************************************
42 * __| |_ _ _ __ ___ _ __ ___ _ __ _ _ __ | |_ ___ _ __| |_ __ _ ___ ___
43 * / _` | | | | '_ ` _ \| '_ \ / _ \ '__| | | '_ \| __/ _ \ '__| _/ _` |/ __/ _ \
44 * | (_| | |_| | | | | | | |_) | __/ | | | | | | || __/ | | || (_| | (_| __/
45 * \__,_|\__,_|_| |_| |_| .__/ \___|_| |_|_| |_|\__\___|_| |_| \__,_|\___\___|
48 ***********************************************************************************/
51 * Returns a string containing the names of all registers within the limited bitset
53 static char *get_limited_regs(const arch_register_req_t *req, char *buf, int max) {
54 bitset_t *bs = bitset_alloca(req->cls->n_regs);
59 req->limited(NULL, bs);
61 for (i = 0; i < req->cls->n_regs; i++) {
62 if (bitset_is_set(bs, i)) {
63 cnt = snprintf(p, max - size, " %s", req->cls->regs[i].name);
65 fprintf(stderr, "dumper problem, exiting\n");
81 * Dumps the register requirements for either in or out.
83 static void dump_reg_req(FILE *F, ir_node *n, const arm_register_req_t **reqs, int inout) {
84 char *dir = inout ? "out" : "in";
85 int max = inout ? get_arm_n_res(n) : get_irn_arity(n);
86 char *buf = alloca(1024);
92 for (i = 0; i < max; i++) {
93 fprintf(F, "%sreq #%d =", dir, i);
95 if (reqs[i]->req.type == arch_register_req_type_none) {
99 if (reqs[i]->req.type & arch_register_req_type_normal) {
100 fprintf(F, " %s", reqs[i]->req.cls->name);
103 if (reqs[i]->req.type & arch_register_req_type_limited) {
104 fprintf(F, " %s", get_limited_regs(&reqs[i]->req, buf, 1024));
107 if (reqs[i]->req.type & arch_register_req_type_should_be_same) {
108 ir_fprintf(F, " same as %+F", get_irn_n(n, reqs[i]->same_pos));
111 if (reqs[i]->req.type & arch_register_req_type_should_be_different) {
112 ir_fprintf(F, " different from %+F", get_irn_n(n, reqs[i]->different_pos));
121 fprintf(F, "%sreq = N/A\n", dir);
127 * Dumper interface for dumping arm nodes in vcg.
128 * @param n the node to dump
129 * @param F the output file
130 * @param reason indicates which kind of information should be dumped
131 * @return 0 on success or != 0 on failure
133 static int dump_node_arm(ir_node *n, FILE *F, dump_reason_t reason) {
134 ir_mode *mode = NULL;
138 const arm_register_req_t **reqs;
139 const arch_register_t **slots;
142 case dump_node_opcode_txt:
143 fprintf(F, "%s", get_irn_opname(n));
146 case dump_node_mode_txt:
147 mode = get_irn_mode(n);
150 fprintf(F, "[%s]", get_mode_name(mode));
153 fprintf(F, "[?NOMODE?]");
157 case dump_node_nodeattr_txt:
159 /* TODO: dump some attributes which should show up */
160 /* in node name in dump (e.g. consts or the like) */
164 case dump_node_info_txt:
165 attr = get_arm_attr(n);
166 fprintf(F, "=== arm attr begin ===\n");
168 /* dump IN requirements */
169 if (get_irn_arity(n) > 0) {
170 reqs = get_arm_in_req_all(n);
171 dump_reg_req(F, n, reqs, 0);
174 /* dump OUT requirements */
175 if (attr->n_res > 0) {
176 reqs = get_arm_out_req_all(n);
177 dump_reg_req(F, n, reqs, 1);
180 /* dump assigned registers */
181 slots = get_arm_slots(n);
182 if (slots && attr->n_res > 0) {
183 for (i = 0; i < attr->n_res; i++) {
185 fprintf(F, "reg #%d = %s\n", i, slots[i]->name);
188 fprintf(F, "reg #%d = n/a\n", i);
195 fprintf(F, "n_res = %d\n", get_arm_n_res(n));
198 fprintf(F, "flags =");
199 if (attr->flags == arch_irn_flags_none) {
203 if (attr->flags & arch_irn_flags_dont_spill) {
204 fprintf(F, " unspillable");
206 if (attr->flags & arch_irn_flags_rematerializable) {
207 fprintf(F, " remat");
209 if (attr->flags & arch_irn_flags_ignore) {
210 fprintf(F, " ignore");
213 fprintf(F, " (%d)\n", attr->flags);
215 if (get_arm_value(n)) {
216 if (is_arm_CopyB(n)) {
217 fprintf(F, "size = %u\n", get_tarval_long(get_arm_value(n)));
219 if (mode_is_float(get_irn_mode(n))) {
220 fprintf(F, "float value = (%lf)\n", get_tarval_double(get_arm_value(n)));
221 } else if (mode_is_int(get_irn_mode(n))) {
222 long v = get_tarval_long(get_arm_value(n));
223 fprintf(F, "long value = %ld (0x%08lx)\n", v, v);
224 } else if (mode_is_reference(get_irn_mode(n))) {
225 fprintf(F, "pointer\n");
227 assert(0 && "unbehandelter Typ im const-Knoten");
231 if (get_arm_proj_num(n) >= 0) {
232 fprintf(F, "proj_num = (%d)\n", get_arm_proj_num(n));
234 /* TODO: dump all additional attributes */
236 fprintf(F, "=== arm attr end ===\n");
237 /* end of: case dump_node_info_txt */
247 /***************************************************************************************************
249 * | | | | | | / / | | | | | | | |
250 * __ _| |_| |_ _ __ ___ ___| |_ / /_ _ ___| |_ _ __ ___ ___| |_| |__ ___ __| |___
251 * / _` | __| __| '__| / __|/ _ \ __| / / _` |/ _ \ __| | '_ ` _ \ / _ \ __| '_ \ / _ \ / _` / __|
252 * | (_| | |_| |_| | \__ \ __/ |_ / / (_| | __/ |_ | | | | | | __/ |_| | | | (_) | (_| \__ \
253 * \__,_|\__|\__|_| |___/\___|\__/_/ \__, |\___|\__| |_| |_| |_|\___|\__|_| |_|\___/ \__,_|___/
256 ***************************************************************************************************/
259 * Wraps get_irn_generic_attr() as it takes no const ir_node, so we need to do a cast.
260 * Firm was made by people hating const :-(
262 arm_attr_t *get_arm_attr(const ir_node *node) {
263 assert(is_arm_irn(node) && "need arm node to get attributes");
264 return (arm_attr_t *)get_irn_generic_attr((ir_node *)node);
268 * Returns the argument register requirements of a arm node.
270 const arm_register_req_t **get_arm_in_req_all(const ir_node *node) {
271 arm_attr_t *attr = get_arm_attr(node);
276 * Returns the result register requirements of an arm node.
278 const arm_register_req_t **get_arm_out_req_all(const ir_node *node) {
279 arm_attr_t *attr = get_arm_attr(node);
280 return attr->out_req;
284 * Returns the argument register requirement at position pos of an arm node.
286 const arm_register_req_t *get_arm_in_req(const ir_node *node, int pos) {
287 arm_attr_t *attr = get_arm_attr(node);
288 return attr->in_req[pos];
292 * Returns the result register requirement at position pos of an arm node.
294 const arm_register_req_t *get_arm_out_req(const ir_node *node, int pos) {
295 arm_attr_t *attr = get_arm_attr(node);
296 return attr->out_req[pos];
300 * Sets the OUT register requirements at position pos.
302 void set_arm_req_out(ir_node *node, const arm_register_req_t *req, int pos) {
303 arm_attr_t *attr = get_arm_attr(node);
304 attr->out_req[pos] = req;
308 * Sets the complete OUT requirements of node.
310 void set_arm_req_out_all(ir_node *node, const arm_register_req_t **reqs) {
311 arm_attr_t *attr = get_arm_attr(node);
312 attr->out_req = reqs;
316 * Sets the IN register requirements at position pos.
318 void set_arm_req_in(ir_node *node, const arm_register_req_t *req, int pos) {
319 arm_attr_t *attr = get_arm_attr(node);
320 attr->in_req[pos] = req;
324 * Returns the register flag of an arm node.
326 arch_irn_flags_t get_arm_flags(const ir_node *node) {
327 arm_attr_t *attr = get_arm_attr(node);
332 * Sets the register flag of an arm node.
334 void set_arm_flags(const ir_node *node, arch_irn_flags_t flags) {
335 arm_attr_t *attr = get_arm_attr(node);
340 * Returns the result register slots of an arm node.
342 const arch_register_t **get_arm_slots(const ir_node *node) {
343 arm_attr_t *attr = get_arm_attr(node);
348 * Returns the name of the OUT register at position pos.
350 const char *get_arm_out_reg_name(const ir_node *node, int pos) {
351 arm_attr_t *attr = get_arm_attr(node);
353 assert(is_arm_irn(node) && "Not an arm node.");
354 assert(pos < attr->n_res && "Invalid OUT position.");
355 assert(attr->slots[pos] && "No register assigned");
357 return arch_register_get_name(attr->slots[pos]);
361 * Returns the index of the OUT register at position pos within its register class.
363 int get_arm_out_regnr(const ir_node *node, int pos) {
364 arm_attr_t *attr = get_arm_attr(node);
366 assert(is_arm_irn(node) && "Not an arm node.");
367 assert(pos < attr->n_res && "Invalid OUT position.");
368 assert(attr->slots[pos] && "No register assigned");
370 return arch_register_get_index(attr->slots[pos]);
374 * Returns the OUT register at position pos.
376 const arch_register_t *get_arm_out_reg(const ir_node *node, int pos) {
377 arm_attr_t *attr = get_arm_attr(node);
379 assert(is_arm_irn(node) && "Not an arm node.");
380 assert(pos < attr->n_res && "Invalid OUT position.");
381 assert(attr->slots[pos] && "No register assigned");
383 return attr->slots[pos];
387 * Sets the number of results.
389 void set_arm_n_res(ir_node *node, int n_res) {
390 arm_attr_t *attr = get_arm_attr(node);
395 * Returns the number of results.
397 int get_arm_n_res(const ir_node *node) {
398 arm_attr_t *attr = get_arm_attr(node);
402 * Returns the tarvalue
404 tarval *get_arm_value(const ir_node *node) {
405 arm_attr_t *attr = get_arm_attr(node);
412 void set_arm_value(ir_node *node, tarval *tv) {
413 arm_attr_t *attr = get_arm_attr(node);
418 * Returns the proj num
420 int get_arm_proj_num(const ir_node *node) {
421 arm_attr_t *attr = get_arm_attr(node);
422 return attr->proj_num;
428 void set_arm_proj_num(ir_node *node, int proj_num) {
429 arm_attr_t *attr = get_arm_attr(node);
430 attr->proj_num = proj_num;
434 * Returns the SymConst label
436 const char *get_arm_symconst_label(ir_node *node) {
437 arm_attr_t *attr = get_arm_attr(node);
438 return attr->symconst_label;
442 * Sets the SymConst label
444 void set_arm_symconst_label(ir_node *node, const char *symconst_label) {
445 arm_attr_t *attr = get_arm_attr(node);
446 attr->symconst_label = symconst_label;
451 * Returns the number of projs.
453 int get_arm_n_projs(ir_node *node) {
454 arm_attr_t *attr = get_arm_attr(node);
455 return attr->n_projs;
459 * Sets the number of projs.
461 void set_arm_n_projs(ir_node *node, int n_projs) {
462 arm_attr_t *attr = get_arm_attr(node);
463 attr->n_projs = n_projs;
467 * Returns the default_proj_num.
469 long get_arm_default_proj_num(ir_node *node) {
470 arm_attr_t *attr = get_arm_attr(node);
471 return attr->default_proj_num;
475 * Sets the default_proj_num.
477 void set_arm_default_proj_num(ir_node *node, long default_proj_num) {
478 arm_attr_t *attr = get_arm_attr(node);
479 attr->default_proj_num = default_proj_num;
484 void init_arm_attributes(ir_node *node, int flags, const arm_register_req_t ** in_reqs,
485 const arm_register_req_t ** out_reqs, int n_res) {
486 arm_attr_t *attr = get_arm_attr(node);
487 attr->in_req = in_reqs;
488 attr->out_req = out_reqs;
491 attr->slots = xcalloc(n_res, sizeof(attr->slots[0]));
493 attr->proj_num = -42;
494 attr->symconst_label = NULL;
496 attr->default_proj_num = 0;
499 static int arm_comp_condJmp(arm_attr_t *attr_a, arm_attr_t *attr_b) {
503 ir_node *arm_new_NoReg_gp(arm_code_gen_t *cg) {
504 return be_abi_get_callee_save_irn(cg->birg->abi, &arm_general_purpose_regs[REG_RXX]);
507 ir_node *arm_new_NoReg_fp(arm_code_gen_t *cg) {
508 return be_abi_get_callee_save_irn(cg->birg->abi, &arm_floating_point_regs[REG_FXX]);
514 /***************************************************************************************
517 * _ __ ___ __| | ___ ___ ___ _ __ ___| |_ _ __ _ _ ___| |_ ___ _ __ ___
518 * | '_ \ / _ \ / _` |/ _ \ / __/ _ \| '_ \/ __| __| '__| | | |/ __| __/ _ \| '__/ __|
519 * | | | | (_) | (_| | __/ | (_| (_) | | | \__ \ |_| | | |_| | (__| || (_) | | \__ \
520 * |_| |_|\___/ \__,_|\___| \___\___/|_| |_|___/\__|_| \__,_|\___|\__\___/|_| |___/
522 ***************************************************************************************/
524 /* limit the possible registers for sp in arm_StoreStackM4Inc */
525 static void limit_reg_arm_StoreStackM4Inc_sp(void *_unused, bitset_t *bs) {
526 bs = bitset_clear_all(bs); /* disallow all register (positive constraints given) */
527 bitset_set(bs, 14); /* allow r13 */
528 bitset_clear(bs, 13); /* disallow ignore reg r12 */
529 bitset_clear(bs, 14); /* disallow ignore reg r13 */
530 bitset_clear(bs, 15); /* disallow ignore reg r15 */
531 bitset_clear(bs, 16); /* disallow ignore reg rxx */
532 bitset_clear(bs, 17); /* disallow ignore reg MURX */
535 static const arm_register_req_t _arm_req_sp = {
537 arch_register_req_type_limited,
538 &arm_reg_classes[CLASS_arm_general_purpose],
539 limit_reg_arm_StoreStackM4Inc_sp,
540 NULL, /* limit environment */
541 NULL, /* same node */
542 NULL /* different node */
548 /* construct Store: Store(ptr, val, mem) = ST ptr,val */
549 ir_node *new_r_arm_StoreStackMInc(ir_graph *irg, ir_node *block, ir_node *mem, ir_node *sp,
550 int n_regs, ir_node **regs, ir_mode *mode) {
554 static const arm_register_req_t *_in_req_arm_StoreStackM4Inc[] =
556 &arm_default_req_none,
558 &arm_default_req_arm_general_purpose,
559 &arm_default_req_arm_general_purpose,
560 &arm_default_req_arm_general_purpose,
561 &arm_default_req_arm_general_purpose,
562 &arm_default_req_arm_general_purpose,
563 &arm_default_req_arm_general_purpose,
564 &arm_default_req_arm_general_purpose,
565 &arm_default_req_arm_general_purpose,
566 &arm_default_req_arm_general_purpose,
567 &arm_default_req_arm_general_purpose,
568 &arm_default_req_arm_general_purpose,
569 &arm_default_req_arm_general_purpose,
570 &arm_default_req_arm_general_purpose,
571 &arm_default_req_arm_general_purpose,
574 assert(n_regs <= 15);
578 memcpy(&in[2], regs, n_regs * sizeof(in[0]));
579 res = new_ir_node(NULL, irg, block, op_arm_StoreStackM4Inc, mode, 2 + n_regs, in);
580 flags |= arch_irn_flags_rematerializable; /* op can be easily recalculated */
582 /* init node attributes */
583 init_arm_attributes(res, flags, _in_req_arm_StoreStackM4Inc, NULL, 0);
585 res = optimize_node(res);
586 irn_vrfy_irg(res, irg);
592 * Register additional opcodes here.
594 static void arm_register_additional_opcodes(int cur_opcode) {
598 /* Include the generated constructor functions */
599 #include "gen_arm_new_nodes.c.inl"