2 * This file implements the creation of the architecture specific firm opcodes
3 * and the corresponding node constructors for the arm assembler irg.
21 #include "irgraph_t.h"
27 #include "firm_common_t.h"
31 #include "../bearch.h"
33 #include "arm_nodes_attr.h"
34 #include "arm_new_nodes.h"
35 #include "gen_arm_regalloc_if.h"
38 #include "bearch_arm_t.h"
41 * Returns the shift modifier string.
43 const char *arm_shf_mod_name(arm_shift_modifier mod) {
44 static const char *names[] = { NULL, NULL, "ASR", "LSL", "LSR", "ROR", "RRX" };
48 /***********************************************************************************
51 * __| |_ _ _ __ ___ _ __ ___ _ __ _ _ __ | |_ ___ _ __| |_ __ _ ___ ___
52 * / _` | | | | '_ ` _ \| '_ \ / _ \ '__| | | '_ \| __/ _ \ '__| _/ _` |/ __/ _ \
53 * | (_| | |_| | | | | | | |_) | __/ | | | | | | || __/ | | || (_| | (_| __/
54 * \__,_|\__,_|_| |_| |_| .__/ \___|_| |_|_| |_|\__\___|_| |_| \__,_|\___\___|
57 ***********************************************************************************/
60 * Returns a string containing the names of all registers within the limited bitset
62 static char *get_limited_regs(const arch_register_req_t *req, char *buf, int max) {
63 bitset_t *bs = bitset_alloca(req->cls->n_regs);
68 req->limited(NULL, bs);
70 for (i = 0; i < req->cls->n_regs; i++) {
71 if (bitset_is_set(bs, i)) {
72 cnt = snprintf(p, max - size, " %s", req->cls->regs[i].name);
74 fprintf(stderr, "dumper problem, exiting\n");
90 * Dumps the register requirements for either in or out.
92 static void dump_reg_req(FILE *F, ir_node *n, const arm_register_req_t **reqs, int inout) {
93 char *dir = inout ? "out" : "in";
94 int max = inout ? get_arm_n_res(n) : get_irn_arity(n);
95 char *buf = alloca(1024);
101 for (i = 0; i < max; i++) {
102 fprintf(F, "%sreq #%d =", dir, i);
104 if (reqs[i]->req.type == arch_register_req_type_none) {
108 if (reqs[i]->req.type & arch_register_req_type_normal) {
109 fprintf(F, " %s", reqs[i]->req.cls->name);
112 if (reqs[i]->req.type & arch_register_req_type_limited) {
113 fprintf(F, " %s", get_limited_regs(&reqs[i]->req, buf, 1024));
116 if (reqs[i]->req.type & arch_register_req_type_should_be_same) {
117 ir_fprintf(F, " same as %+F", get_irn_n(n, reqs[i]->same_pos));
120 if (reqs[i]->req.type & arch_register_req_type_should_be_different) {
121 ir_fprintf(F, " different from %+F", get_irn_n(n, reqs[i]->different_pos));
130 fprintf(F, "%sreq = N/A\n", dir);
136 * Dumper interface for dumping arm nodes in vcg.
137 * @param n the node to dump
138 * @param F the output file
139 * @param reason indicates which kind of information should be dumped
140 * @return 0 on success or != 0 on failure
142 static int dump_node_arm(ir_node *n, FILE *F, dump_reason_t reason) {
143 ir_mode *mode = NULL;
146 arm_attr_t *attr = get_arm_attr(n);
147 const arm_register_req_t **reqs;
148 const arch_register_t **slots;
149 arm_shift_modifier mod;
152 case dump_node_opcode_txt:
153 fprintf(F, "%s", get_irn_opname(n));
156 case dump_node_mode_txt:
157 mode = get_irn_mode(n);
160 fprintf(F, "[%s]", get_mode_name(mode));
163 fprintf(F, "[?NOMODE?]");
167 case dump_node_nodeattr_txt:
168 mod = ARM_GET_SHF_MOD(attr);
169 if (ARM_HAS_SHIFT(mod)) {
170 fprintf(F, "[%s #%ld]", arm_shf_mod_name(mod), get_tarval_long(attr->value));
172 else if (mod == ARM_SHF_IMM) {
174 fprintf(F, "[#0x%X]", arm_decode_imm_w_shift(attr->value));
178 case dump_node_info_txt:
179 fprintf(F, "=== arm attr begin ===\n");
181 /* dump IN requirements */
182 if (get_irn_arity(n) > 0) {
183 reqs = get_arm_in_req_all(n);
184 dump_reg_req(F, n, reqs, 0);
187 /* dump OUT requirements */
188 if (attr->n_res > 0) {
189 reqs = get_arm_out_req_all(n);
190 dump_reg_req(F, n, reqs, 1);
193 /* dump assigned registers */
194 slots = get_arm_slots(n);
195 if (slots && attr->n_res > 0) {
196 for (i = 0; i < attr->n_res; i++) {
198 fprintf(F, "reg #%d = %s\n", i, slots[i]->name);
201 fprintf(F, "reg #%d = n/a\n", i);
208 fprintf(F, "n_res = %d\n", get_arm_n_res(n));
211 fprintf(F, "flags =");
212 if (attr->flags == arch_irn_flags_none) {
216 if (attr->flags & arch_irn_flags_dont_spill) {
217 fprintf(F, " unspillable");
219 if (attr->flags & arch_irn_flags_rematerializable) {
220 fprintf(F, " remat");
222 if (attr->flags & arch_irn_flags_ignore) {
223 fprintf(F, " ignore");
226 fprintf(F, " (%d)\n", attr->flags);
228 if (get_arm_value(n)) {
229 if (is_arm_CopyB(n)) {
230 fprintf(F, "size = %u\n", get_tarval_long(get_arm_value(n)));
232 if (mode_is_float(get_irn_mode(n))) {
233 fprintf(F, "float value = (%lf)\n", get_tarval_double(get_arm_value(n)));
234 } else if (mode_is_int(get_irn_mode(n))) {
235 long v = get_tarval_long(get_arm_value(n));
236 fprintf(F, "long value = %ld (0x%08lx)\n", v, v);
237 } else if (mode_is_reference(get_irn_mode(n))) {
238 fprintf(F, "pointer\n");
240 assert(0 && "unbehandelter Typ im const-Knoten");
244 if (get_arm_proj_num(n) >= 0) {
245 fprintf(F, "proj_num = (%d)\n", get_arm_proj_num(n));
247 /* TODO: dump all additional attributes */
249 fprintf(F, "=== arm attr end ===\n");
250 /* end of: case dump_node_info_txt */
258 /***************************************************************************************************
260 * | | | | | | / / | | | | | | | |
261 * __ _| |_| |_ _ __ ___ ___| |_ / /_ _ ___| |_ _ __ ___ ___| |_| |__ ___ __| |___
262 * / _` | __| __| '__| / __|/ _ \ __| / / _` |/ _ \ __| | '_ ` _ \ / _ \ __| '_ \ / _ \ / _` / __|
263 * | (_| | |_| |_| | \__ \ __/ |_ / / (_| | __/ |_ | | | | | | __/ |_| | | | (_) | (_| \__ \
264 * \__,_|\__|\__|_| |___/\___|\__/_/ \__, |\___|\__| |_| |_| |_|\___|\__|_| |_|\___/ \__,_|___/
267 ***************************************************************************************************/
270 * Wraps get_irn_generic_attr() as it takes no const ir_node, so we need to do a cast.
271 * Firm was made by people hating const :-(
273 arm_attr_t *get_arm_attr(const ir_node *node) {
274 assert(is_arm_irn(node) && "need arm node to get attributes");
275 return (arm_attr_t *)get_irn_generic_attr((ir_node *)node);
279 * Returns the argument register requirements of a arm node.
281 const arm_register_req_t **get_arm_in_req_all(const ir_node *node) {
282 arm_attr_t *attr = get_arm_attr(node);
287 * Returns the result register requirements of an arm node.
289 const arm_register_req_t **get_arm_out_req_all(const ir_node *node) {
290 arm_attr_t *attr = get_arm_attr(node);
291 return attr->out_req;
295 * Returns the argument register requirement at position pos of an arm node.
297 const arm_register_req_t *get_arm_in_req(const ir_node *node, int pos) {
298 arm_attr_t *attr = get_arm_attr(node);
299 return attr->in_req[pos];
303 * Returns the result register requirement at position pos of an arm node.
305 const arm_register_req_t *get_arm_out_req(const ir_node *node, int pos) {
306 arm_attr_t *attr = get_arm_attr(node);
307 return attr->out_req[pos];
311 * Sets the OUT register requirements at position pos.
313 void set_arm_req_out(ir_node *node, const arm_register_req_t *req, int pos) {
314 arm_attr_t *attr = get_arm_attr(node);
315 attr->out_req[pos] = req;
319 * Sets the complete OUT requirements of node.
321 void set_arm_req_out_all(ir_node *node, const arm_register_req_t **reqs) {
322 arm_attr_t *attr = get_arm_attr(node);
323 attr->out_req = reqs;
327 * Sets the IN register requirements at position pos.
329 void set_arm_req_in(ir_node *node, const arm_register_req_t *req, int pos) {
330 arm_attr_t *attr = get_arm_attr(node);
331 attr->in_req[pos] = req;
335 * Returns the register flag of an arm node.
337 arch_irn_flags_t get_arm_flags(const ir_node *node) {
338 arm_attr_t *attr = get_arm_attr(node);
343 * Sets the register flag of an arm node.
345 void set_arm_flags(const ir_node *node, arch_irn_flags_t flags) {
346 arm_attr_t *attr = get_arm_attr(node);
351 * Returns the result register slots of an arm node.
353 const arch_register_t **get_arm_slots(const ir_node *node) {
354 arm_attr_t *attr = get_arm_attr(node);
359 * Returns the name of the OUT register at position pos.
361 const char *get_arm_out_reg_name(const ir_node *node, int pos) {
362 arm_attr_t *attr = get_arm_attr(node);
364 assert(is_arm_irn(node) && "Not an arm node.");
365 assert(pos < attr->n_res && "Invalid OUT position.");
366 assert(attr->slots[pos] && "No register assigned");
368 return arch_register_get_name(attr->slots[pos]);
372 * Returns the index of the OUT register at position pos within its register class.
374 int get_arm_out_regnr(const ir_node *node, int pos) {
375 arm_attr_t *attr = get_arm_attr(node);
377 assert(is_arm_irn(node) && "Not an arm node.");
378 assert(pos < attr->n_res && "Invalid OUT position.");
379 assert(attr->slots[pos] && "No register assigned");
381 return arch_register_get_index(attr->slots[pos]);
385 * Returns the OUT register at position pos.
387 const arch_register_t *get_arm_out_reg(const ir_node *node, int pos) {
388 arm_attr_t *attr = get_arm_attr(node);
390 assert(is_arm_irn(node) && "Not an arm node.");
391 assert(pos < attr->n_res && "Invalid OUT position.");
392 assert(attr->slots[pos] && "No register assigned");
394 return attr->slots[pos];
398 * Sets the number of results.
400 void set_arm_n_res(ir_node *node, int n_res) {
401 arm_attr_t *attr = get_arm_attr(node);
406 * Returns the number of results.
408 int get_arm_n_res(const ir_node *node) {
409 arm_attr_t *attr = get_arm_attr(node);
413 * Returns the tarvalue
415 tarval *get_arm_value(const ir_node *node) {
416 arm_attr_t *attr = get_arm_attr(node);
423 void set_arm_value(ir_node *node, tarval *tv) {
424 arm_attr_t *attr = get_arm_attr(node);
429 * Returns the proj num
431 int get_arm_proj_num(const ir_node *node) {
432 arm_attr_t *attr = get_arm_attr(node);
433 return attr->proj_num;
439 void set_arm_proj_num(ir_node *node, int proj_num) {
440 arm_attr_t *attr = get_arm_attr(node);
441 attr->proj_num = proj_num;
445 * Returns the SymConst label
447 const char *get_arm_symconst_label(ir_node *node) {
448 arm_attr_t *attr = get_arm_attr(node);
449 return attr->symconst_label;
453 * Sets the SymConst label
455 void set_arm_symconst_label(ir_node *node, const char *symconst_label) {
456 arm_attr_t *attr = get_arm_attr(node);
457 attr->symconst_label = symconst_label;
462 * Returns the number of projs.
464 int get_arm_n_projs(ir_node *node) {
465 arm_attr_t *attr = get_arm_attr(node);
466 return attr->n_projs;
470 * Sets the number of projs.
472 void set_arm_n_projs(ir_node *node, int n_projs) {
473 arm_attr_t *attr = get_arm_attr(node);
474 attr->n_projs = n_projs;
478 * Returns the default_proj_num.
480 long get_arm_default_proj_num(ir_node *node) {
481 arm_attr_t *attr = get_arm_attr(node);
482 return attr->default_proj_num;
486 * Sets the default_proj_num.
488 void set_arm_default_proj_num(ir_node *node, long default_proj_num) {
489 arm_attr_t *attr = get_arm_attr(node);
490 attr->default_proj_num = default_proj_num;
494 * Gets the shift modifier attribute.
496 arm_shift_modifier get_arm_shift_modifier(ir_node *node) {
497 arm_attr_t *attr = get_arm_attr(node);
498 return ARM_GET_SHF_MOD(attr);
501 /* Set the ARM machine node attributes to default values. */
502 void init_arm_attributes(ir_node *node, int flags, const arm_register_req_t ** in_reqs,
503 const arm_register_req_t ** out_reqs, int n_res) {
504 arm_attr_t *attr = get_arm_attr(node);
505 attr->in_req = in_reqs;
506 attr->out_req = out_reqs;
509 attr->slots = xcalloc(n_res, sizeof(attr->slots[0]));
510 attr->instr_fl = (ARM_COND_AL << 3) | ARM_SHF_NONE;
512 attr->proj_num = -42;
513 attr->symconst_label = NULL;
515 attr->default_proj_num = 0;
518 static int arm_comp_condJmp(arm_attr_t *attr_a, arm_attr_t *attr_b) {
522 ir_node *arm_new_NoReg_gp(arm_code_gen_t *cg) {
523 return be_abi_get_callee_save_irn(cg->birg->abi, &arm_gp_regs[REG_RXX]);
526 ir_node *arm_new_NoReg_fp(arm_code_gen_t *cg) {
527 return be_abi_get_callee_save_irn(cg->birg->abi, &arm_fp_regs[REG_FXX]);
533 /***************************************************************************************
536 * _ __ ___ __| | ___ ___ ___ _ __ ___| |_ _ __ _ _ ___| |_ ___ _ __ ___
537 * | '_ \ / _ \ / _` |/ _ \ / __/ _ \| '_ \/ __| __| '__| | | |/ __| __/ _ \| '__/ __|
538 * | | | | (_) | (_| | __/ | (_| (_) | | | \__ \ |_| | | |_| | (__| || (_) | | \__ \
539 * |_| |_|\___/ \__,_|\___| \___\___/|_| |_|___/\__|_| \__,_|\___|\__\___/|_| |___/
541 ***************************************************************************************/
543 /* limit the possible registers for sp in arm_StoreStackM4Inc */
544 static void limit_reg_arm_StoreStackM4Inc_sp(void *_unused, bitset_t *bs) {
545 bs = bitset_clear_all(bs); /* disallow all register (positive constraints given) */
546 bitset_set(bs, 14); /* allow r13 */
547 bitset_clear(bs, 13); /* disallow ignore reg r12 */
548 bitset_clear(bs, 14); /* disallow ignore reg r13 */
549 bitset_clear(bs, 15); /* disallow ignore reg r15 */
550 bitset_clear(bs, 16); /* disallow ignore reg rxx */
553 static const arm_register_req_t _arm_req_sp = {
555 arch_register_req_type_limited,
556 &arm_reg_classes[CLASS_arm_gp],
557 limit_reg_arm_StoreStackM4Inc_sp,
558 NULL, /* limit environment */
559 NULL, /* same node */
560 NULL /* different node */
566 /* construct Store: Store(ptr, val, mem) = ST ptr,val */
567 ir_node *new_r_arm_StoreStackMInc(ir_graph *irg, ir_node *block, ir_node *mem, ir_node *sp,
568 int n_regs, ir_node **regs, ir_mode *mode) {
572 static const arm_register_req_t *_in_req_arm_StoreStackM4Inc[] =
574 &arm_default_req_none,
576 &arm_default_req_arm_gp,
577 &arm_default_req_arm_gp,
578 &arm_default_req_arm_gp,
579 &arm_default_req_arm_gp,
580 &arm_default_req_arm_gp,
581 &arm_default_req_arm_gp,
582 &arm_default_req_arm_gp,
583 &arm_default_req_arm_gp,
584 &arm_default_req_arm_gp,
585 &arm_default_req_arm_gp,
586 &arm_default_req_arm_gp,
587 &arm_default_req_arm_gp,
588 &arm_default_req_arm_gp,
589 &arm_default_req_arm_gp,
592 assert(n_regs <= 15);
596 memcpy(&in[2], regs, n_regs * sizeof(in[0]));
597 res = new_ir_node(NULL, irg, block, op_arm_StoreStackM4Inc, mode, 2 + n_regs, in);
598 flags |= arch_irn_flags_rematerializable; /* op can be easily recalculated */
600 /* init node attributes */
601 init_arm_attributes(res, flags, _in_req_arm_StoreStackM4Inc, NULL, 0);
603 res = optimize_node(res);
604 irn_vrfy_irg(res, irg);
609 /************************************************
611 * / _ \ _ __ | |_(_)_ __ ___ (_)_______ _ __ *
612 * | | | | '_ \| __| | '_ ` _ \| |_ / _ \ '__| *
613 * | |_| | |_) | |_| | | | | | | |/ / __/ | *
614 * \___/| .__/ \__|_|_| |_| |_|_/___\___|_| *
616 ************************************************/
618 typedef struct _opt_tuple {
619 ir_op *op_imm_left; /**< immediate is left */
620 ir_op *op_imm_right; /**< immediate is right */
621 ir_op *op_shf_left; /**< shift operand on left */
622 ir_op *op_shf_right; /**< shift operand on right */
625 static const opt_tuple *opt_ops[iro_arm_last];
627 void arm_set_optimizers(void) {
629 #define STD(op) p_##op = { op_arm_##op##_i, op_arm_##op##_i, op_arm_##op, op_arm_##op }
630 #define LEFT(op) p_##op = { op_arm_##op##_i, NULL, op_arm_##op, NULL }
631 #define SET(op) opt_ops[iro_arm_##op] = &p_##op;
633 static const opt_tuple
642 p_Sub = { op_arm_Sub_i, op_arm_Rsb_i, op_arm_Sub, op_arm_Rsb },
644 memset(opt_ops, 0, sizeof(opt_ops));
658 /* Include the generated constructor functions */
659 #include "gen_arm_new_nodes.c.inl"