2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the creation of the architecture specific firm
23 * opcodes and the corresponding node constructors for the arm
25 * @author Oliver Richter, Tobias Gneist
35 #include "irgraph_t.h"
41 #include "firm_common_t.h"
46 #include "../bearch_t.h"
48 #include "arm_nodes_attr.h"
49 #include "arm_new_nodes.h"
50 #include "gen_arm_regalloc_if_t.h"
53 #include "bearch_arm_t.h"
56 * Returns the shift modifier string.
58 const char *arm_shf_mod_name(arm_shift_modifier mod) {
59 static const char *names[] = { NULL, NULL, "asr", "lsl", "lsr", "ror", "rrx" };
63 /***********************************************************************************
66 * __| |_ _ _ __ ___ _ __ ___ _ __ _ _ __ | |_ ___ _ __| |_ __ _ ___ ___
67 * / _` | | | | '_ ` _ \| '_ \ / _ \ '__| | | '_ \| __/ _ \ '__| _/ _` |/ __/ _ \
68 * | (_| | |_| | | | | | | |_) | __/ | | | | | | || __/ | | || (_| | (_| __/
69 * \__,_|\__,_|_| |_| |_| .__/ \___|_| |_|_| |_|\__\___|_| |_| \__,_|\___\___|
72 ***********************************************************************************/
75 * Dumps the register requirements for either in or out.
77 static void dump_reg_req(FILE *F, const ir_node *node,
78 const arch_register_req_t **reqs, int inout) {
79 char *dir = inout ? "out" : "in";
80 int max = inout ? get_arm_n_res(node) : get_irn_arity(node);
84 memset(buf, 0, sizeof(buf));
87 for (i = 0; i < max; i++) {
88 fprintf(F, "%sreq #%d =", dir, i);
90 if (reqs[i]->type == arch_register_req_type_none) {
94 if (reqs[i]->type & arch_register_req_type_normal) {
95 fprintf(F, " %s", reqs[i]->cls->name);
98 if (reqs[i]->type & arch_register_req_type_limited) {
100 arch_register_req_format(buf, sizeof(buf), reqs[i], node));
103 if (reqs[i]->type & arch_register_req_type_should_be_same) {
104 ir_fprintf(F, " same as %+F", get_irn_n(node, reqs[i]->other_same));
107 if (reqs[i]->type & arch_register_req_type_should_be_different) {
108 ir_fprintf(F, " different from %+F", get_irn_n(node, reqs[i]->other_different));
116 fprintf(F, "%sreq = N/A\n", dir);
121 * Dumper interface for dumping arm nodes in vcg.
122 * @param n the node to dump
123 * @param F the output file
124 * @param reason indicates which kind of information should be dumped
125 * @return 0 on success or != 0 on failure
127 static int arm_dump_node(ir_node *n, FILE *F, dump_reason_t reason) {
128 ir_mode *mode = NULL;
131 arm_attr_t *attr = get_arm_attr(n);
132 const arch_register_req_t **reqs;
133 const arch_register_t **slots;
134 arm_shift_modifier mod;
137 case dump_node_opcode_txt:
138 fprintf(F, "%s", get_irn_opname(n));
141 case dump_node_mode_txt:
142 mode = get_irn_mode(n);
145 fprintf(F, "[%s]", get_mode_name(mode));
148 fprintf(F, "[?NOMODE?]");
152 case dump_node_nodeattr_txt:
153 mod = ARM_GET_SHF_MOD(attr);
154 if (ARM_HAS_SHIFT(mod)) {
155 fprintf(F, "[%s #%ld]", arm_shf_mod_name(mod), get_tarval_long(attr->value));
157 else if (mod == ARM_SHF_IMM) {
159 fprintf(F, "[#0x%X]", arm_decode_imm_w_shift(attr->value));
163 case dump_node_info_txt:
164 fprintf(F, "=== arm attr begin ===\n");
166 /* dump IN requirements */
167 if (get_irn_arity(n) > 0) {
168 reqs = get_arm_in_req_all(n);
169 dump_reg_req(F, n, reqs, 0);
172 /* dump OUT requirements */
173 if (ARR_LEN(attr->slots) > 0) {
174 reqs = get_arm_out_req_all(n);
175 dump_reg_req(F, n, reqs, 1);
178 /* dump assigned registers */
179 slots = get_arm_slots(n);
180 if (slots && ARR_LEN(attr->slots) > 0) {
181 for (i = 0; i < ARR_LEN(attr->slots); i++) {
183 fprintf(F, "reg #%d = %s\n", i, slots[i]->name);
186 fprintf(F, "reg #%d = n/a\n", i);
193 fprintf(F, "n_res = %d\n", get_arm_n_res(n));
196 fprintf(F, "flags =");
197 if (attr->flags == arch_irn_flags_none) {
201 if (attr->flags & arch_irn_flags_dont_spill) {
202 fprintf(F, " unspillable");
204 if (attr->flags & arch_irn_flags_rematerializable) {
205 fprintf(F, " remat");
207 if (attr->flags & arch_irn_flags_ignore) {
208 fprintf(F, " ignore");
211 fprintf(F, " (%d)\n", attr->flags);
213 if (get_arm_value(n)) {
214 if (is_arm_CopyB(n)) {
215 fprintf(F, "size = %lu\n", get_tarval_long(get_arm_value(n)));
217 if (mode_is_float(get_irn_mode(n))) {
218 fprintf(F, "float value = (%f)\n", (double) get_tarval_double(get_arm_value(n)));
219 } else if (mode_is_int(get_irn_mode(n))) {
220 long v = get_tarval_long(get_arm_value(n));
221 fprintf(F, "long value = %ld (0x%08lx)\n", v, v);
222 } else if (mode_is_reference(get_irn_mode(n))) {
223 fprintf(F, "pointer\n");
225 assert(0 && "unbehandelter Typ im const-Knoten");
229 if (is_arm_CondJmp(n) && get_arm_CondJmp_proj_num(n) >= 0) {
230 fprintf(F, "proj_num = (%d)\n", get_arm_CondJmp_proj_num(n));
232 /* TODO: dump all additional attributes */
234 fprintf(F, "=== arm attr end ===\n");
235 /* end of: case dump_node_info_txt */
243 /***************************************************************************************************
245 * | | | | | | / / | | | | | | | |
246 * __ _| |_| |_ _ __ ___ ___| |_ / /_ _ ___| |_ _ __ ___ ___| |_| |__ ___ __| |___
247 * / _` | __| __| '__| / __|/ _ \ __| / / _` |/ _ \ __| | '_ ` _ \ / _ \ __| '_ \ / _ \ / _` / __|
248 * | (_| | |_| |_| | \__ \ __/ |_ / / (_| | __/ |_ | | | | | | __/ |_| | | | (_) | (_| \__ \
249 * \__,_|\__|\__|_| |___/\___|\__/_/ \__, |\___|\__| |_| |_| |_|\___|\__|_| |_|\___/ \__,_|___/
252 ***************************************************************************************************/
254 /* Returns the attributes of a generic Arm node. */
255 arm_attr_t *get_arm_attr(ir_node *node) {
256 assert(is_arm_irn(node) && "need arm node to get attributes");
257 return get_irn_generic_attr(node);
260 const arm_attr_t *get_arm_attr_const(const ir_node *node) {
261 assert(is_arm_irn(node) && "need arm node to get attributes");
262 return get_irn_generic_attr_const(node);
266 * Returns the attributes of an ARM SymConst node.
268 arm_SymConst_attr_t *get_arm_SymConst_attr(ir_node *node) {
269 assert(is_arm_SymConst(node));
270 return get_irn_generic_attr(node);
273 const arm_SymConst_attr_t *get_arm_SymConst_attr_const(const ir_node *node) {
274 assert(is_arm_SymConst(node));
275 return get_irn_generic_attr_const(node);
278 /* Returns the attributes of a CondJmp node. */
279 arm_CondJmp_attr_t *get_arm_CondJmp_attr(ir_node *node) {
280 assert(is_arm_CondJmp(node));
281 return get_irn_generic_attr(node);
284 const arm_CondJmp_attr_t *get_arm_CondJmp_attr_const(const ir_node *node) {
285 assert(is_arm_CondJmp(node));
286 return get_irn_generic_attr_const(node);
289 /* Returns the attributes of a SwitchJmp node. */
290 arm_SwitchJmp_attr_t *get_arm_SwitchJmp_attr(ir_node *node) {
291 assert(is_arm_SwitchJmp(node));
292 return get_irn_generic_attr(node);
295 const arm_SwitchJmp_attr_t *get_arm_SwitchJmp_attr_const(const ir_node *node) {
296 assert(is_arm_SwitchJmp(node));
297 return get_irn_generic_attr_const(node);
301 * Returns the argument register requirements of a arm node.
303 const arch_register_req_t **get_arm_in_req_all(const ir_node *node) {
304 const arm_attr_t *attr = get_arm_attr_const(node);
309 * Returns the result register requirements of an arm node.
311 const arch_register_req_t **get_arm_out_req_all(const ir_node *node) {
312 const arm_attr_t *attr = get_arm_attr_const(node);
313 return attr->out_req;
317 * Returns the argument register requirement at position pos of an arm node.
319 const arch_register_req_t *get_arm_in_req(const ir_node *node, int pos) {
320 const arm_attr_t *attr = get_arm_attr_const(node);
321 return attr->in_req[pos];
325 * Returns the result register requirement at position pos of an arm node.
327 const arch_register_req_t *get_arm_out_req(const ir_node *node, int pos) {
328 const arm_attr_t *attr = get_arm_attr_const(node);
329 return attr->out_req[pos];
333 * Sets the OUT register requirements at position pos.
335 void set_arm_req_out(ir_node *node, const arch_register_req_t *req, int pos) {
336 arm_attr_t *attr = get_arm_attr(node);
337 attr->out_req[pos] = req;
341 * Sets the complete OUT requirements of node.
343 void set_arm_req_out_all(ir_node *node, const arch_register_req_t **reqs) {
344 arm_attr_t *attr = get_arm_attr(node);
345 attr->out_req = reqs;
349 * Sets the IN register requirements at position pos.
351 void set_arm_req_in(ir_node *node, const arch_register_req_t *req, int pos) {
352 arm_attr_t *attr = get_arm_attr(node);
353 attr->in_req[pos] = req;
357 * Returns the register flag of an arm node.
359 arch_irn_flags_t get_arm_flags(const ir_node *node) {
360 const arm_attr_t *attr = get_arm_attr_const(node);
365 * Sets the register flag of an arm node.
367 void set_arm_flags(ir_node *node, arch_irn_flags_t flags) {
368 arm_attr_t *attr = get_arm_attr(node);
373 * Returns the result register slots of an arm node.
375 const arch_register_t **get_arm_slots(const ir_node *node) {
376 const arm_attr_t *attr = get_arm_attr_const(node);
381 * Returns the name of the OUT register at position pos.
383 const char *get_arm_out_reg_name(const ir_node *node, int pos) {
384 const arm_attr_t *attr = get_arm_attr_const(node);
386 assert(is_arm_irn(node) && "Not an arm node.");
387 assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
388 assert(attr->slots[pos] && "No register assigned");
390 return arch_register_get_name(attr->slots[pos]);
394 * Returns the index of the OUT register at position pos within its register class.
396 int get_arm_out_regnr(const ir_node *node, int pos) {
397 const arm_attr_t *attr = get_arm_attr_const(node);
399 assert(is_arm_irn(node) && "Not an arm node.");
400 assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
401 assert(attr->slots[pos] && "No register assigned");
403 return arch_register_get_index(attr->slots[pos]);
407 * Returns the OUT register at position pos.
409 const arch_register_t *get_arm_out_reg(const ir_node *node, int pos) {
410 const arm_attr_t *attr = get_arm_attr_const(node);
412 assert(is_arm_irn(node) && "Not an arm node.");
413 assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
414 assert(attr->slots[pos] && "No register assigned");
416 return attr->slots[pos];
420 * Sets the flags for the n'th out.
422 void set_arm_out_flags(ir_node *node, arch_irn_flags_t flags, int pos) {
423 arm_attr_t *attr = get_arm_attr(node);
424 assert(pos < ARR_LEN(attr->out_flags) && "Invalid OUT position.");
425 attr->out_flags[pos] = flags;
429 * Gets the flags for the n'th out.
431 arch_irn_flags_t get_arm_out_flags(const ir_node *node, int pos) {
432 const arm_attr_t *attr = get_arm_attr_const(node);
433 assert(pos < ARR_LEN(attr->out_flags) && "Invalid OUT position.");
434 return attr->out_flags[pos];
438 * Returns the number of results.
440 int get_arm_n_res(const ir_node *node) {
441 const arm_attr_t *attr = get_arm_attr_const(node);
442 return ARR_LEN(attr->slots);
445 * Returns the tarvalue
447 tarval *get_arm_value(const ir_node *node) {
448 const arm_attr_t *attr = get_arm_attr_const(node);
455 void set_arm_value(ir_node *node, tarval *tv) {
456 arm_attr_t *attr = get_arm_attr(node);
461 * Returns the proj num
463 int get_arm_CondJmp_proj_num(const ir_node *node) {
464 const arm_CondJmp_attr_t *attr = get_arm_CondJmp_attr_const(node);
465 return attr->proj_num;
471 void set_arm_CondJmp_proj_num(ir_node *node, int proj_num) {
472 arm_CondJmp_attr_t *attr = get_arm_CondJmp_attr(node);
473 attr->proj_num = proj_num;
477 * Returns the SymConst label
479 ident *get_arm_symconst_id(const ir_node *node) {
480 const arm_SymConst_attr_t *attr = get_arm_SymConst_attr_const(node);
481 return attr->symconst_id;
485 * Sets the SymConst label
487 void set_arm_symconst_id(ir_node *node, ident *symconst_id) {
488 arm_SymConst_attr_t *attr = get_arm_SymConst_attr(node);
489 attr->symconst_id = symconst_id;
493 * Returns the number of projs of a SwitchJmp.
495 int get_arm_SwitchJmp_n_projs(const ir_node *node) {
496 const arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr_const(node);
497 return attr->n_projs;
501 * Sets the number of projs.
503 void set_arm_SwitchJmp_n_projs(ir_node *node, int n_projs) {
504 arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr(node);
505 attr->n_projs = n_projs;
509 * Returns the default_proj_num.
511 long get_arm_SwitchJmp_default_proj_num(const ir_node *node) {
512 const arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr_const(node);
513 return attr->default_proj_num;
517 * Sets the default_proj_num.
519 void set_arm_SwitchJmp_default_proj_num(ir_node *node, long default_proj_num) {
520 arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr(node);
521 attr->default_proj_num = default_proj_num;
525 * Gets the shift modifier attribute.
527 arm_shift_modifier get_arm_shift_modifier(const ir_node *node) {
528 const arm_attr_t *attr = get_arm_attr_const(node);
529 return ARM_GET_SHF_MOD(attr);
532 /* Set the ARM machine node attributes to default values. */
533 void init_arm_attributes(ir_node *node, int flags, const arch_register_req_t ** in_reqs,
534 const arch_register_req_t ** out_reqs, const be_execution_unit_t ***execution_units,
535 int n_res, unsigned latency) {
536 ir_graph *irg = get_irn_irg(node);
537 struct obstack *obst = get_irg_obstack(irg);
538 arm_attr_t *attr = get_arm_attr(node);
540 attr->in_req = in_reqs;
541 attr->out_req = out_reqs;
543 attr->instr_fl = (ARM_COND_AL << 3) | ARM_SHF_NONE;
546 attr->out_flags = NEW_ARR_D(int, obst, n_res);
547 memset(attr->out_flags, 0, n_res * sizeof(attr->out_flags[0]));
549 attr->slots = NEW_ARR_D(const arch_register_t*, obst, n_res);
550 memset((arch_register_t **)attr->slots, 0, n_res * sizeof(attr->slots[0]));
553 /***************************************************************************************
556 * _ __ ___ __| | ___ ___ ___ _ __ ___| |_ _ __ _ _ ___| |_ ___ _ __ ___
557 * | '_ \ / _ \ / _` |/ _ \ / __/ _ \| '_ \/ __| __| '__| | | |/ __| __/ _ \| '__/ __|
558 * | | | | (_) | (_| | __/ | (_| (_) | | | \__ \ |_| | | |_| | (__| || (_) | | \__ \
559 * |_| |_|\___/ \__,_|\___| \___\___/|_| |_|___/\__|_| \__,_|\___|\__\___/|_| |___/
561 ***************************************************************************************/
566 #define BIT(x) (1 << (x % 32))
568 static unsigned arm_req_sp_limited[] = { BIT(REG_SP) };
569 static const arch_register_req_t _arm_req_sp = {
570 arch_register_req_type_limited,
571 &arm_reg_classes[CLASS_arm_gp],
577 /* construct Store: Store(ptr, val, mem) = ST ptr,val */
578 ir_node *new_r_arm_StoreStackMInc(ir_graph *irg, ir_node *block, ir_node *mem,
579 ir_node *sp, int n_regs, ir_node **regs,
584 static const arch_register_req_t *_in_req_arm_StoreStackM4Inc[] =
586 &arm_StoreStackM4Inc_reg_req_in_0,
587 &arm_StoreStackM4Inc_reg_req_in_1,
588 &arm_StoreStackM4Inc_reg_req_in_2,
589 &arm_StoreStackM4Inc_reg_req_in_2,
590 &arm_StoreStackM4Inc_reg_req_in_2,
591 &arm_StoreStackM4Inc_reg_req_in_2,
592 &arm_StoreStackM4Inc_reg_req_in_2,
593 &arm_StoreStackM4Inc_reg_req_in_2,
594 &arm_StoreStackM4Inc_reg_req_in_2,
595 &arm_StoreStackM4Inc_reg_req_in_2,
596 &arm_StoreStackM4Inc_reg_req_in_2,
597 &arm_StoreStackM4Inc_reg_req_in_2,
598 &arm_StoreStackM4Inc_reg_req_in_2,
599 &arm_StoreStackM4Inc_reg_req_in_2,
600 &arm_StoreStackM4Inc_reg_req_in_2,
601 &arm_StoreStackM4Inc_reg_req_in_2,
602 &arm_StoreStackM4Inc_reg_req_in_2,
605 assert(n_regs <= 15);
609 memcpy(&in[2], regs, n_regs * sizeof(in[0]));
610 res = new_ir_node(NULL, irg, block, op_arm_StoreStackM4Inc, mode, 2 + n_regs, in);
611 flags |= arch_irn_flags_rematerializable; /* op can be easily recalculated */
613 /* init node attributes */
614 init_arm_attributes(res, flags, _in_req_arm_StoreStackM4Inc, NULL, NULL, 0, 1);
616 res = optimize_node(res);
617 irn_vrfy_irg(res, irg);
622 /************************************************
624 * / _ \ _ __ | |_(_)_ __ ___ (_)_______ _ __ *
625 * | | | | '_ \| __| | '_ ` _ \| |_ / _ \ '__| *
626 * | |_| | |_) | |_| | | | | | | |/ / __/ | *
627 * \___/| .__/ \__|_|_| |_| |_|_/___\___|_| *
629 ************************************************/
631 typedef struct _opt_tuple {
632 ir_op *op_imm_left; /**< immediate is left */
633 ir_op *op_imm_right; /**< immediate is right */
634 ir_op *op_shf_left; /**< shift operand on left */
635 ir_op *op_shf_right; /**< shift operand on right */
638 //static const opt_tuple *opt_ops[iro_arm_last];
640 void arm_set_optimizers(void) {
642 #define STD(op) p_##op = { op_arm_##op##_i, op_arm_##op##_i, op_arm_##op, op_arm_##op }
643 #define LEFT(op) p_##op = { op_arm_##op##_i, NULL, op_arm_##op, NULL }
644 #define SET(op) opt_ops[iro_arm_##op] = &p_##op;
646 static const opt_tuple
655 p_Sub = { op_arm_Sub_i, op_arm_Rsb_i, op_arm_Sub, op_arm_Rsb },
657 memset(opt_ops, 0, sizeof(opt_ops));
670 static int cmp_attr_arm_SymConst(ir_node *a, ir_node *b) {
671 const arm_SymConst_attr_t *attr_a = get_irn_generic_attr_const(a);
672 const arm_SymConst_attr_t *attr_b = get_irn_generic_attr_const(b);
673 return attr_a->symconst_id != attr_b->symconst_id;
676 static int cmp_attr_arm(ir_node *a, ir_node *b) {
677 arm_attr_t *attr_a = get_irn_generic_attr(a);
678 arm_attr_t *attr_b = get_irn_generic_attr(b);
679 return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);
682 static int cmp_attr_arm_CondJmp(ir_node *a, ir_node *b) {
683 /* never identical */
687 static int cmp_attr_arm_SwitchJmp(ir_node *a, ir_node *b) {
688 /* never identical */
692 /** copies the ARM attributes of a node. */
693 static void arm_copy_attr(const ir_node *old_node, ir_node *new_node) {
694 ir_graph *irg = get_irn_irg(new_node);
695 struct obstack *obst = get_irg_obstack(irg);
696 const arm_attr_t *attr_old = get_arm_attr_const(old_node);
697 arm_attr_t *attr_new = get_arm_attr(new_node);
699 /* copy the attributes */
700 memcpy(attr_new, attr_old, get_op_attr_size(get_irn_op(old_node)));
703 attr_new->out_flags =
704 DUP_ARR_D(int, obst, attr_old->out_flags);
705 /* copy register assignments */
707 DUP_ARR_D(arch_register_t*, obst, attr_old->slots);
712 /* Include the generated constructor functions */
713 #include "gen_arm_new_nodes.c.inl"
716 * Registers the arm_copy_attr function for all ARM opcodes.
718 void arm_register_copy_attr_func(void) {
721 for (i = get_irp_n_opcodes() - 1; i >= 0; --i) {
722 ir_op *op = get_irp_opcode(i);
724 op->ops.copy_attr = arm_copy_attr;