2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
45 #include "raw_bitset.h"
48 #include "../besched.h"
49 #include "../beblocksched.h"
50 #include "../beirg_t.h"
51 #include "../begnuas.h"
52 #include "../be_dbgout.h"
54 #include "arm_emitter.h"
55 #include "arm_optimize.h"
56 #include "gen_arm_emitter.h"
57 #include "arm_nodes_attr.h"
58 #include "arm_new_nodes.h"
59 #include "arm_map_regs.h"
60 #include "gen_arm_regalloc_if.h"
62 #include "../benode_t.h"
64 #define BLOCK_PREFIX ".L"
66 #define SNPRINTF_BUF_LEN 128
68 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
70 static const arch_env_t *arch_env = NULL;
71 static const arm_code_gen_t *cg;
72 static const arm_isa_t *isa;
73 static set *sym_or_tv;
76 * Returns the register at in position pos.
78 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
80 const arch_register_t *reg = NULL;
82 assert(get_irn_arity(irn) > pos && "Invalid IN position");
84 /* The out register of the operator at position pos is the
85 in register we need. */
86 op = get_irn_n(irn, pos);
88 reg = arch_get_irn_register(arch_env, op);
90 assert(reg && "no in register found");
92 /* in case of a joker register: just return a valid register */
93 if (arch_register_type_is(reg, joker)) {
94 const arch_register_req_t *req = arch_get_register_req(irn, pos);
96 if (arch_register_req_is(req, limited)) {
97 /* in case of limited requirements: get the first allowed register */
98 unsigned idx = rbitset_next(req->limited, 0, 1);
99 reg = arch_register_for_index(req->cls, idx);
101 /* otherwise get first register in class */
102 reg = arch_register_for_index(req->cls, 0);
110 * Returns the register at out position pos.
112 static const arch_register_t *get_out_reg(const ir_node *node, int pos)
115 const arch_register_t *reg = NULL;
117 /* 1st case: irn is not of mode_T, so it has only */
118 /* one OUT register -> good */
119 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
120 /* Proj with the corresponding projnum for the register */
122 if (get_irn_mode(node) != mode_T) {
123 reg = arch_get_irn_register(arch_env, node);
124 } else if (is_arm_irn(node)) {
125 reg = get_arm_out_reg(node, pos);
127 const ir_edge_t *edge;
129 foreach_out_edge(node, edge) {
130 proj = get_edge_src_irn(edge);
131 assert(is_Proj(proj) && "non-Proj from mode_T node");
132 if (get_Proj_proj(proj) == pos) {
133 reg = arch_get_irn_register(arch_env, proj);
139 assert(reg && "no out register found");
143 /*************************************************************
145 * (_) | | / _| | | | |
146 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
147 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
148 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
149 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
152 *************************************************************/
155 * Emit the name of the source register at given input position.
157 void arm_emit_source_register(const ir_node *node, int pos) {
158 const arch_register_t *reg = get_in_reg(node, pos);
159 be_emit_string(arch_register_get_name(reg));
163 * Emit the name of the destination register at given output position.
165 void arm_emit_dest_register(const ir_node *node, int pos) {
166 const arch_register_t *reg = get_out_reg(node, pos);
167 be_emit_string(arch_register_get_name(reg));
171 * Emit a node's offset.
173 void arm_emit_offset(const ir_node *node) {
175 ir_opcode opc = get_irn_opcode(node);
177 if (opc == beo_Reload || opc == beo_Spill) {
178 ir_entity *ent = be_get_frame_entity(node);
179 offset = get_entity_offset(ent);
181 assert(!"unimplemented arm_emit_offset for this node type");
182 panic("unimplemented arm_emit_offset for this node type");
184 be_emit_irprintf("%d", offset);
188 * Emit the arm fpa instruction suffix depending on the mode.
190 static void arm_emit_fpa_postfix(const ir_mode *mode) {
191 int bits = get_mode_size_bits(mode);
202 * Emit the instruction suffix depending on the mode.
204 void arm_emit_mode(const ir_node *node) {
207 if (is_arm_irn(node)) {
208 const arm_attr_t *attr = get_arm_attr_const(node);
209 mode = attr->op_mode ? attr->op_mode : get_irn_mode(node);
211 mode = get_irn_mode(node);
213 arm_emit_fpa_postfix(mode);
217 * Emit a const or SymConst value.
219 void arm_emit_immediate(const ir_node *node) {
220 const arm_attr_t *attr = get_arm_attr_const(node);
222 if (ARM_GET_SHF_MOD(attr) == ARM_SHF_IMM) {
223 be_emit_irprintf("#0x%X", arm_decode_imm_w_shift(get_arm_imm_value(node)));
224 } else if (ARM_GET_FPA_IMM(attr)) {
225 be_emit_irprintf("#%s", arm_get_fpa_imm_name(get_arm_imm_value(node)));
226 } else if (is_arm_SymConst(node))
227 be_emit_ident(get_arm_symconst_id(node));
229 assert(!"not a Constant");
234 * Returns the tarval or offset of an arm node as a string.
236 void arm_emit_shift(const ir_node *node) {
237 arm_shift_modifier mod;
239 mod = get_arm_shift_modifier(node);
240 if (ARM_HAS_SHIFT(mod)) {
241 int v = get_arm_imm_value(node);
243 be_emit_irprintf(", %s #%d", arm_shf_mod_name(mod), v);
247 /** An entry in the sym_or_tv set. */
248 typedef struct sym_or_tv_t {
250 ident *id; /**< An ident. */
251 tarval *tv; /**< A tarval. */
252 const void *generic; /**< For generic compare. */
254 unsigned label; /**< the associated label. */
255 char is_ident; /**< Non-zero if an ident is stored. */
259 * Returns a unique label. This number will not be used a second time.
261 static unsigned get_unique_label(void) {
262 static unsigned id = 0;
269 static void emit_arm_SymConst(const ir_node *irn) {
270 sym_or_tv_t key, *entry;
273 key.u.id = get_arm_symconst_id(irn);
276 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
277 if (entry->label == 0) {
278 /* allocate a label */
279 entry->label = get_unique_label();
281 label = entry->label;
283 /* load the symbol indirect */
284 be_emit_cstring("\tldr ");
285 arm_emit_dest_register(irn, 0);
286 be_emit_irprintf(", .L%u", label);
287 be_emit_finish_line_gas(irn);
291 * Emit a floating point fpa constant.
293 static void emit_arm_fpaConst(const ir_node *irn) {
294 sym_or_tv_t key, *entry;
298 key.u.tv = get_fpaConst_value(irn);
301 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
302 if (entry->label == 0) {
303 /* allocate a label */
304 entry->label = get_unique_label();
306 label = entry->label;
308 /* load the tarval indirect */
309 mode = get_irn_mode(irn);
310 be_emit_cstring("\tldf");
311 arm_emit_fpa_postfix(mode);
314 arm_emit_dest_register(irn, 0);
315 be_emit_irprintf(", .L%u", label);
316 be_emit_finish_line_gas(irn);
320 * Returns the next block in a block schedule.
322 static ir_node *sched_next_block(const ir_node *block) {
323 return get_irn_link(block);
327 * Returns the target block for a control flow node.
329 static ir_node *get_cfop_target_block(const ir_node *irn) {
330 return get_irn_link(irn);
334 * Emits a block label for the given block.
336 static void arm_emit_block_name(const ir_node *block) {
337 if (has_Block_label(block)) {
338 be_emit_string(be_gas_block_label_prefix());
339 be_emit_irprintf("%lu", get_Block_label(block));
341 be_emit_cstring(BLOCK_PREFIX);
342 be_emit_irprintf("%d", get_irn_node_nr(block));
347 * Emit the target label for a control flow node.
349 static void arm_emit_cfop_target(const ir_node *irn) {
350 ir_node *block = get_cfop_target_block(irn);
352 arm_emit_block_name(block);
356 * Emit a Compare with conditional branch.
358 static void emit_arm_CmpBra(const ir_node *irn) {
359 const ir_edge_t *edge;
360 const ir_node *proj_true = NULL;
361 const ir_node *proj_false = NULL;
362 const ir_node *block;
363 const ir_node *next_block;
364 ir_node *op1 = get_irn_n(irn, 0);
365 ir_mode *opmode = get_irn_mode(op1);
367 int proj_num = get_arm_CondJmp_proj_num(irn);
369 foreach_out_edge(irn, edge) {
370 ir_node *proj = get_edge_src_irn(edge);
371 long nr = get_Proj_proj(proj);
372 if (nr == pn_Cond_true) {
379 /* for now, the code works for scheduled and non-schedules blocks */
380 block = get_nodes_block(irn);
382 /* we have a block schedule */
383 next_block = sched_next_block(block);
385 if (proj_num == pn_Cmp_False) {
386 /* always false: should not happen */
387 be_emit_cstring("\tb ");
388 arm_emit_cfop_target(proj_false);
389 be_emit_finish_line_gas(proj_false);
390 } else if (proj_num == pn_Cmp_True) {
391 /* always true: should not happen */
392 be_emit_cstring("\tb ");
393 arm_emit_cfop_target(proj_true);
394 be_emit_finish_line_gas(proj_true);
396 if (mode_is_float(opmode)) {
397 suffix = "ICHWILLIMPLEMENTIERTWERDEN";
399 be_emit_cstring("\tfcmp ");
400 arm_emit_source_register(irn, 0);
401 be_emit_cstring(", ");
402 arm_emit_source_register(irn, 1);
403 be_emit_finish_line_gas(irn);
405 be_emit_cstring("\tfmstat");
406 be_emit_pad_comment();
407 be_emit_cstring("/* FCSPR -> CPSR */");
408 be_emit_finish_line_gas(NULL);
410 if (get_cfop_target_block(proj_true) == next_block) {
411 /* exchange both proj's so the second one can be omitted */
412 const ir_node *t = proj_true;
414 proj_true = proj_false;
416 proj_num = get_negated_pnc(proj_num, mode_Iu);
419 case pn_Cmp_Eq: suffix = "eq"; break;
420 case pn_Cmp_Lt: suffix = "lt"; break;
421 case pn_Cmp_Le: suffix = "le"; break;
422 case pn_Cmp_Gt: suffix = "gt"; break;
423 case pn_Cmp_Ge: suffix = "ge"; break;
424 case pn_Cmp_Lg: suffix = "ne"; break;
425 case pn_Cmp_Leg: suffix = "al"; break;
426 default: assert(!"Cmp unsupported"); suffix = "al";
428 be_emit_cstring("\tcmp ");
429 arm_emit_source_register(irn, 0);
430 be_emit_cstring(", ");
431 arm_emit_source_register(irn, 1);
432 be_emit_finish_line_gas(irn);
435 /* emit the true proj */
436 be_emit_irprintf("\tb%s ", suffix);
437 arm_emit_cfop_target(proj_true);
438 be_emit_finish_line_gas(proj_true);
440 if (get_cfop_target_block(proj_false) == next_block) {
441 be_emit_cstring("\t/* fallthrough to ");
442 arm_emit_cfop_target(proj_false);
443 be_emit_cstring(" */");
444 be_emit_finish_line_gas(proj_false);
446 be_emit_cstring("b ");
447 arm_emit_cfop_target(proj_false);
448 be_emit_finish_line_gas(proj_false);
455 * Emit a Tst with conditional branch.
457 static void emit_arm_TstBra(const ir_node *irn)
459 const ir_edge_t *edge;
460 const ir_node *proj_true = NULL;
461 const ir_node *proj_false = NULL;
462 const ir_node *block;
463 const ir_node *next_block;
465 int proj_num = get_arm_CondJmp_proj_num(irn);
467 foreach_out_edge(irn, edge) {
468 ir_node *proj = get_edge_src_irn(edge);
469 long nr = get_Proj_proj(proj);
470 if (nr == pn_Cond_true) {
477 /* for now, the code works for scheduled and non-schedules blocks */
478 block = get_nodes_block(irn);
480 /* we have a block schedule */
481 next_block = sched_next_block(block);
483 assert(proj_num != pn_Cmp_False);
484 assert(proj_num != pn_Cmp_True);
486 if (get_cfop_target_block(proj_true) == next_block) {
487 /* exchange both proj's so the second one can be omitted */
488 const ir_node *t = proj_true;
490 proj_true = proj_false;
492 proj_num = get_negated_pnc(proj_num, mode_Iu);
495 case pn_Cmp_Eq: suffix = "eq"; break;
496 case pn_Cmp_Lt: suffix = "lt"; break;
497 case pn_Cmp_Le: suffix = "le"; break;
498 case pn_Cmp_Gt: suffix = "gt"; break;
499 case pn_Cmp_Ge: suffix = "ge"; break;
500 case pn_Cmp_Lg: suffix = "ne"; break;
501 case pn_Cmp_Leg: suffix = "al"; break;
502 default: assert(!"Cmp unsupported"); suffix = "al";
504 be_emit_cstring("\ttst ");
505 arm_emit_source_register(irn, 0);
506 be_emit_cstring(", ");
507 arm_emit_source_register(irn, 1);
508 be_emit_finish_line_gas(irn);
510 /* emit the true proj */
511 be_emit_irprintf("\tb%s ", suffix);
512 arm_emit_cfop_target(proj_true);
513 be_emit_finish_line_gas(proj_true);
515 if (get_cfop_target_block(proj_false) == next_block) {
516 be_emit_cstring("\t/* fallthrough to ");
517 arm_emit_cfop_target(proj_false);
518 be_emit_cstring(" */");
519 be_emit_finish_line_gas(proj_false);
521 be_emit_cstring("b ");
522 arm_emit_cfop_target(proj_false);
523 be_emit_finish_line_gas(proj_false);
528 * Emit a Compare with conditional branch.
530 static void emit_arm_fpaCmfBra(const ir_node *irn) {
535 * Emit a Compare with conditional branch.
537 static void emit_arm_fpaCmfeBra(const ir_node *irn) {
541 /** Sort register in ascending order. */
542 static int reg_cmp(const void *a, const void *b) {
543 const arch_register_t * const *ra = a;
544 const arch_register_t * const *rb = b;
546 return *ra < *rb ? -1 : (*ra != *rb);
550 * Create the CopyB instruction sequence.
552 static void emit_arm_CopyB(const ir_node *irn) {
553 unsigned size = (unsigned)get_arm_imm_value(irn);
555 const char *tgt = arch_register_get_name(get_in_reg(irn, 0));
556 const char *src = arch_register_get_name(get_in_reg(irn, 1));
557 const char *t0, *t1, *t2, *t3;
559 const arch_register_t *tmpregs[4];
561 /* collect the temporary registers and sort them, we need ascending order */
562 tmpregs[0] = get_in_reg(irn, 2);
563 tmpregs[1] = get_in_reg(irn, 3);
564 tmpregs[2] = get_in_reg(irn, 4);
565 tmpregs[3] = &arm_gp_regs[REG_R12];
567 /* Note: R12 is always the last register because the RA did not assign higher ones */
568 qsort((void *)tmpregs, 3, sizeof(tmpregs[0]), reg_cmp);
570 /* need ascending order */
571 t0 = arch_register_get_name(tmpregs[0]);
572 t1 = arch_register_get_name(tmpregs[1]);
573 t2 = arch_register_get_name(tmpregs[2]);
574 t3 = arch_register_get_name(tmpregs[3]);
576 be_emit_cstring("/* MemCopy (");
578 be_emit_cstring(")->(");
579 arm_emit_source_register(irn, 0);
580 be_emit_irprintf(" [%u bytes], Uses ", size);
582 be_emit_cstring(", ");
584 be_emit_cstring(", ");
586 be_emit_cstring(", and ");
588 be_emit_cstring("*/");
589 be_emit_finish_line_gas(NULL);
591 assert(size > 0 && "CopyB needs size > 0" );
594 assert(!"strange hack enabled: copy more bytes than needed!");
603 be_emit_cstring("\tldr ");
605 be_emit_cstring(", [");
607 be_emit_cstring(", #0]");
608 be_emit_finish_line_gas(NULL);
610 be_emit_cstring("\tstr ");
612 be_emit_cstring(", [");
614 be_emit_cstring(", #0]");
615 be_emit_finish_line_gas(irn);
618 be_emit_cstring("\tldmia ");
620 be_emit_cstring("!, {");
622 be_emit_cstring(", ");
625 be_emit_finish_line_gas(NULL);
627 be_emit_cstring("\tstmia ");
629 be_emit_cstring("!, {");
631 be_emit_cstring(", ");
634 be_emit_finish_line_gas(irn);
637 be_emit_cstring("\tldmia ");
639 be_emit_cstring("!, {");
641 be_emit_cstring(", ");
643 be_emit_cstring(", ");
646 be_emit_finish_line_gas(NULL);
648 be_emit_cstring("\tstmia ");
650 be_emit_cstring("!, {");
652 be_emit_cstring(", ");
654 be_emit_cstring(", ");
657 be_emit_finish_line_gas(irn);
662 be_emit_cstring("\tldmia ");
664 be_emit_cstring("!, {");
666 be_emit_cstring(", ");
668 be_emit_cstring(", ");
670 be_emit_cstring(", ");
673 be_emit_finish_line_gas(NULL);
675 be_emit_cstring("\tstmia ");
677 be_emit_cstring("!, {");
679 be_emit_cstring(", ");
681 be_emit_cstring(", ");
683 be_emit_cstring(", ");
686 be_emit_finish_line_gas(irn);
691 static void emit_arm_SwitchJmp(const ir_node *irn) {
692 const ir_edge_t *edge;
698 ir_node *default_proj = NULL;
700 block_nr = get_irn_node_nr(irn);
701 n_projs = get_arm_SwitchJmp_n_projs(irn);
703 projs = XMALLOCNZ(ir_node*, n_projs);
705 foreach_out_edge(irn, edge) {
706 proj = get_edge_src_irn(edge);
707 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
709 if (get_Proj_proj(proj) == get_arm_SwitchJmp_default_proj_num(irn))
712 projs[get_Proj_proj(proj)] = proj;
714 assert(default_proj != NULL && "SwitchJmp should have a Default Proj");
721 be_emit_cstring("\tcmp ");
722 arm_emit_source_register(irn, 0);
723 be_emit_irprintf(", #%u", n_projs - 1);
724 be_emit_finish_line_gas(irn);
726 be_emit_cstring("\tbhi ");
727 arm_emit_cfop_target(default_proj);
728 be_emit_finish_line_gas(default_proj);
731 LDR %r12, .TABLE_X_START
732 ADD %r12, %r12, [%1S, LSL #2]
736 be_emit_irprintf("\tldr %%r12, TABLE_%d_START", block_nr);
737 be_emit_finish_line_gas(NULL);
739 be_emit_irprintf("\tadd %%r12, %%r12, ");
740 arm_emit_source_register(irn, 0);
741 be_emit_cstring(", LSL #2");
742 be_emit_finish_line_gas(NULL);
744 be_emit_cstring("\tldr %r15, [%r12, #0]");
745 be_emit_finish_line_gas(NULL);
747 be_emit_irprintf("TABLE_%d_START:\n\t.word\tTABLE_%d", block_nr, block_nr);
748 be_emit_finish_line_gas(NULL);
749 be_emit_irprintf("\t.align 2");
750 be_emit_finish_line_gas(NULL);
751 be_emit_irprintf("TABLE_%d:", block_nr);
752 be_emit_finish_line_gas(NULL);
754 for (i = 0; i < n_projs; ++i) {
757 proj = projs[get_arm_SwitchJmp_default_proj_num(irn)];
759 be_emit_cstring("\t.word\t");
760 arm_emit_cfop_target(proj);
761 be_emit_finish_line_gas(proj);
763 be_emit_irprintf("\t.align 2\n");
764 be_emit_finish_line_gas(NULL);
768 /************************************************************************/
770 /************************************************************************/
772 static void emit_be_Call(const ir_node *irn) {
773 ir_entity *ent = be_Call_get_entity(irn);
775 be_emit_cstring("\tbl ");
777 set_entity_backend_marked(ent, 1);
778 be_emit_ident(get_entity_ld_ident(ent));
780 arm_emit_source_register(irn, be_pos_Call_ptr);
782 be_emit_finish_line_gas(irn);
785 /** Emit an IncSP node */
786 static void emit_be_IncSP(const ir_node *irn) {
787 int offs = -be_get_IncSP_offset(irn);
791 be_emit_cstring("\tsub ");
794 be_emit_cstring("\tadd ");
796 arm_emit_dest_register(irn, 0);
797 be_emit_cstring(", ");
798 arm_emit_source_register(irn, 0);
799 be_emit_irprintf(", #0x%X", offs);
801 /* omitted IncSP(0) */
804 be_emit_finish_line_gas(irn);
807 static void emit_be_Copy(const ir_node *irn) {
808 ir_mode *mode = get_irn_mode(irn);
810 if (get_in_reg(irn, 0) == get_out_reg(irn, 0)) {
815 if (mode_is_float(mode)) {
817 be_emit_cstring("\tmvf");
820 arm_emit_dest_register(irn, 0);
821 be_emit_cstring(", ");
822 arm_emit_source_register(irn, 0);
823 be_emit_finish_line_gas(irn);
825 assert(0 && "move not supported for this mode");
826 panic("emit_be_Copy: move not supported for this mode");
828 } else if (mode_is_data(mode)) {
829 be_emit_cstring("\tmov ");
830 arm_emit_dest_register(irn, 0);
831 be_emit_cstring(", ");
832 arm_emit_source_register(irn, 0);
833 be_emit_finish_line_gas(irn);
835 assert(0 && "move not supported for this mode");
836 panic("emit_be_Copy: move not supported for this mode");
841 * Emit code for a Spill.
843 static void emit_be_Spill(const ir_node *irn) {
844 ir_mode *mode = get_irn_mode(be_get_Spill_val(irn));
846 if (mode_is_float(mode)) {
847 if (USE_FPA(cg->isa)) {
848 be_emit_cstring("\tstf");
849 arm_emit_fpa_postfix(mode);
852 assert(0 && "spill not supported for this mode");
853 panic("emit_be_Spill: spill not supported for this mode");
855 } else if (mode_is_dataM(mode)) {
856 be_emit_cstring("\tstr ");
858 assert(0 && "spill not supported for this mode");
859 panic("emit_be_Spill: spill not supported for this mode");
861 arm_emit_source_register(irn, 1);
862 be_emit_cstring(", [");
863 arm_emit_source_register(irn, 0);
864 be_emit_cstring(", #");
865 arm_emit_offset(irn);
867 be_emit_finish_line_gas(irn);
871 * Emit code for a Reload.
873 static void emit_be_Reload(const ir_node *irn) {
874 ir_mode *mode = get_irn_mode(irn);
876 if (mode_is_float(mode)) {
877 if (USE_FPA(cg->isa)) {
878 be_emit_cstring("\tldf");
879 arm_emit_fpa_postfix(mode);
882 assert(0 && "reload not supported for this mode");
883 panic("emit_be_Reload: reload not supported for this mode");
885 } else if (mode_is_dataM(mode)) {
886 be_emit_cstring("\tldr ");
888 assert(0 && "reload not supported for this mode");
889 panic("emit_be_Reload: reload not supported for this mode");
891 arm_emit_dest_register(irn, 0);
892 be_emit_cstring(", [");
893 arm_emit_source_register(irn, 0);
894 be_emit_cstring(", #");
895 arm_emit_offset(irn);
897 be_emit_finish_line_gas(irn);
900 static void emit_be_Perm(const ir_node *irn) {
901 be_emit_cstring("\teor ");
902 arm_emit_source_register(irn, 0);
903 be_emit_cstring(", ");
904 arm_emit_source_register(irn, 0);
905 be_emit_cstring(", ");
906 arm_emit_source_register(irn, 1);
907 be_emit_finish_line_gas(NULL);
909 be_emit_cstring("\teor ");
910 arm_emit_source_register(irn, 1);
911 be_emit_cstring(", ");
912 arm_emit_source_register(irn, 0);
913 be_emit_cstring(", ");
914 arm_emit_source_register(irn, 1);
915 be_emit_finish_line_gas(NULL);
917 be_emit_cstring("\teor ");
918 arm_emit_source_register(irn, 0);
919 be_emit_cstring(", ");
920 arm_emit_source_register(irn, 0);
921 be_emit_cstring(", ");
922 arm_emit_source_register(irn, 1);
923 be_emit_finish_line_gas(irn);
926 /************************************************************************/
928 /************************************************************************/
930 static void emit_Jmp(const ir_node *node) {
931 ir_node *block, *next_block;
933 /* for now, the code works for scheduled and non-schedules blocks */
934 block = get_nodes_block(node);
936 /* we have a block schedule */
937 next_block = sched_next_block(block);
938 if (get_cfop_target_block(node) != next_block) {
939 be_emit_cstring("\tb ");
940 arm_emit_cfop_target(node);
942 be_emit_cstring("\t/* fallthrough to ");
943 arm_emit_cfop_target(node);
944 be_emit_cstring(" */");
946 be_emit_finish_line_gas(node);
949 static void emit_arm_fpaDbl2GP(const ir_node *irn) {
950 be_emit_cstring("\tstfd ");
951 arm_emit_source_register(irn, 0);
952 be_emit_cstring(", [sp, #-8]!");
953 be_emit_pad_comment();
954 be_emit_cstring("/* Push fp to stack */");
955 be_emit_finish_line_gas(NULL);
957 be_emit_cstring("\tldmfd sp!, {");
958 arm_emit_dest_register(irn, 1);
959 be_emit_cstring(", ");
960 arm_emit_dest_register(irn, 0);
962 be_emit_pad_comment();
963 be_emit_cstring("/* Pop destination */");
964 be_emit_finish_line_gas(irn);
967 static void emit_arm_LdTls(const ir_node *irn) {
969 panic("TLS not supported for this target");
970 /* Er... our gcc does not support it... Install a newer toolchain. */
973 /***********************************************************************************
976 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
977 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
978 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
979 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
981 ***********************************************************************************/
983 static void emit_silence(const ir_node *irn) {
989 * The type of a emitter function.
991 typedef void (emit_func)(const ir_node *irn);
994 * Set a node emitter. Make it a bit more type safe.
996 static INLINE void set_emitter(ir_op *op, emit_func arm_emit_node) {
997 op->ops.generic = (op_func)arm_emit_node;
1001 * Enters the emitter functions for handled nodes into the generic
1002 * pointer of an opcode.
1004 static void arm_register_emitters(void) {
1006 #define ARM_EMIT(a) set_emitter(op_arm_##a, emit_arm_##a)
1007 #define EMIT(a) set_emitter(op_##a, emit_##a)
1008 #define BE_EMIT(a) set_emitter(op_be_##a, emit_be_##a)
1009 #define SILENCE(a) set_emitter(op_##a, emit_silence)
1011 /* first clear the generic function pointer for all ops */
1012 clear_irp_opcodes_generic_func();
1014 /* register all emitter functions defined in spec */
1015 arm_register_spec_emitters();
1017 /* other emitter functions */
1020 ARM_EMIT(fpaCmfBra);
1021 ARM_EMIT(fpaCmfeBra);
1023 // ARM_EMIT(CopyB_i);
1026 ARM_EMIT(SwitchJmp);
1027 ARM_EMIT(fpaDbl2GP);
1031 /* benode emitter */
1048 SILENCE(be_CopyKeep);
1049 SILENCE(be_RegParams);
1050 SILENCE(be_Barrier);
1061 * Emits code for a node.
1063 static void arm_emit_node(const ir_node *irn) {
1064 ir_op *op = get_irn_op(irn);
1066 if (op->ops.generic) {
1067 emit_func *emit = (emit_func *)op->ops.generic;
1068 be_dbg_set_dbg_info(get_irn_dbg_info(irn));
1071 be_emit_cstring("\t/* TODO */");
1072 be_emit_finish_line_gas(irn);
1077 * emit the block label if needed.
1079 static void arm_emit_block_header(ir_node *block, ir_node *prev)
1084 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1087 n_cfgpreds = get_Block_n_cfgpreds(block);
1088 if (n_cfgpreds == 1) {
1089 ir_node *pred = get_Block_cfgpred(block, 0);
1090 ir_node *pred_block = get_nodes_block(pred);
1092 /* we don't need labels for fallthrough blocks, however switch-jmps
1093 * are no fallthroughs */
1094 if (pred_block == prev &&
1095 !(is_Proj(pred) && is_arm_SwitchJmp(get_Proj_pred(pred)))) {
1105 arm_emit_block_name(block);
1108 be_emit_pad_comment();
1109 be_emit_cstring(" /* preds:");
1111 /* emit list of pred blocks in comment */
1112 arity = get_irn_arity(block);
1113 for (i = 0; i < arity; ++i) {
1114 ir_node *predblock = get_Block_cfgpred_block(block, i);
1115 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1118 be_emit_cstring("\t/* ");
1119 arm_emit_block_name(block);
1120 be_emit_cstring(": ");
1122 if (exec_freq != NULL) {
1123 be_emit_irprintf(" freq: %f",
1124 get_block_execfreq(exec_freq, block));
1126 be_emit_cstring(" */\n");
1127 be_emit_write_line();
1131 * Walks over the nodes in a block connected by scheduling edges
1132 * and emits code for each node.
1134 static void arm_gen_block(ir_node *block, ir_node *prev_block) {
1137 arm_emit_block_header(block, prev_block);
1138 be_dbg_set_dbg_info(get_irn_dbg_info(block));
1139 sched_foreach(block, irn) {
1145 * Emits code for function start.
1147 void arm_func_prolog(ir_graph *irg) {
1148 ir_entity *ent = get_irg_entity(irg);
1149 const char *irg_name = get_entity_ld_name(ent);
1151 be_emit_write_line();
1152 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1153 be_emit_cstring("\t.align 2\n");
1155 if (get_entity_visibility(ent) == visibility_external_visible)
1156 be_emit_irprintf("\t.global %s\n", irg_name);
1157 be_emit_irprintf("%s:\n", irg_name);
1161 * Emits code for function end
1163 void arm_emit_end(FILE *F, ir_graph *irg) {
1165 fprintf(F, "\t.ident \"firmcc\"\n");
1170 * Sets labels for control flow nodes (jump target)
1172 static void arm_gen_labels(ir_node *block, void *env) {
1174 int n = get_Block_n_cfgpreds(block);
1177 for (n--; n >= 0; n--) {
1178 pred = get_Block_cfgpred(block, n);
1179 set_irn_link(pred, block);
1184 * Compare two entries of the symbol or tarval set.
1186 static int cmp_sym_or_tv(const void *elt, const void *key, size_t size) {
1187 const sym_or_tv_t *p1 = elt;
1188 const sym_or_tv_t *p2 = key;
1191 /* as an identifier NEVER can point to a tarval, it's enough
1192 to compare it this way */
1193 return p1->u.generic != p2->u.generic;
1197 * Main driver. Emits the code for one routine.
1199 void arm_gen_routine(const arm_code_gen_t *arm_cg, ir_graph *irg) {
1200 ir_node **blk_sched;
1202 ir_node *last_block = NULL;
1203 ir_entity *entity = get_irg_entity(irg);
1206 isa = (const arm_isa_t *)cg->arch_env;
1207 arch_env = cg->arch_env;
1208 sym_or_tv = new_set(cmp_sym_or_tv, 8);
1210 arm_register_emitters();
1212 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
1214 /* create the block schedule. For now, we don't need it earlier. */
1215 blk_sched = be_create_block_schedule(cg->irg, cg->birg->exec_freq);
1217 arm_func_prolog(irg);
1218 irg_block_walk_graph(irg, arm_gen_labels, NULL, NULL);
1220 n = ARR_LEN(blk_sched);
1221 for (i = 0; i < n;) {
1222 ir_node *block, *next_bl;
1224 block = blk_sched[i];
1226 next_bl = i < n ? blk_sched[i] : NULL;
1228 /* set here the link. the emitter expects to find the next block here */
1229 set_irn_link(block, next_bl);
1230 arm_gen_block(block, last_block);
1234 be_dbg_method_end();
1236 /* emit SymConst values */
1237 if (set_count(sym_or_tv) > 0) {
1240 be_emit_cstring("\t.align 2\n");
1242 foreach_set(sym_or_tv, entry) {
1243 be_emit_irprintf(".L%u:\n", entry->label);
1245 if (entry->is_ident) {
1246 be_emit_cstring("\t.word\t");
1247 be_emit_ident(entry->u.id);
1249 be_emit_write_line();
1251 tarval *tv = entry->u.tv;
1252 int i, size = get_mode_size_bytes(get_tarval_mode(tv));
1255 /* beware: ARM fpa uses big endian format */
1256 for (i = ((size + 3) & ~3) - 4; i >= 0; i -= 4) {
1258 v = get_tarval_sub_bits(tv, i+3);
1259 v = (v << 8) | get_tarval_sub_bits(tv, i+2);
1260 v = (v << 8) | get_tarval_sub_bits(tv, i+1);
1261 v = (v << 8) | get_tarval_sub_bits(tv, i+0);
1262 be_emit_irprintf("\t.word\t%u\n", v);
1263 be_emit_write_line();
1268 be_emit_write_line();
1273 void arm_init_emitter(void)
1275 FIRM_DBG_REGISTER(dbg, "firm.be.arm.emit");