2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
45 #include "raw_bitset.h"
48 #include "../besched.h"
49 #include "../beblocksched.h"
50 #include "../beirg_t.h"
51 #include "../begnuas.h"
52 #include "../be_dbgout.h"
54 #include "arm_emitter.h"
55 #include "arm_optimize.h"
56 #include "gen_arm_emitter.h"
57 #include "arm_nodes_attr.h"
58 #include "arm_new_nodes.h"
59 #include "arm_map_regs.h"
60 #include "gen_arm_regalloc_if.h"
62 #include "../benode_t.h"
64 #define BLOCK_PREFIX ".L"
66 #define SNPRINTF_BUF_LEN 128
68 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
70 static const arm_code_gen_t *cg;
71 static const arm_isa_t *isa;
72 static set *sym_or_tv;
75 * Returns the register at in position pos.
77 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
79 const arch_register_t *reg = NULL;
81 assert(get_irn_arity(irn) > pos && "Invalid IN position");
83 /* The out register of the operator at position pos is the
84 in register we need. */
85 op = get_irn_n(irn, pos);
87 reg = arch_get_irn_register(op);
89 assert(reg && "no in register found");
91 /* in case of a joker register: just return a valid register */
92 if (arch_register_type_is(reg, joker)) {
93 const arch_register_req_t *req = arch_get_register_req(irn, pos);
95 if (arch_register_req_is(req, limited)) {
96 /* in case of limited requirements: get the first allowed register */
97 unsigned idx = rbitset_next(req->limited, 0, 1);
98 reg = arch_register_for_index(req->cls, idx);
100 /* otherwise get first register in class */
101 reg = arch_register_for_index(req->cls, 0);
109 * Returns the register at out position pos.
111 static const arch_register_t *get_out_reg(const ir_node *node, int pos)
114 const arch_register_t *reg = NULL;
116 /* 1st case: irn is not of mode_T, so it has only */
117 /* one OUT register -> good */
118 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
119 /* Proj with the corresponding projnum for the register */
121 if (get_irn_mode(node) != mode_T) {
122 reg = arch_get_irn_register(node);
123 } else if (is_arm_irn(node)) {
124 reg = get_arm_out_reg(node, pos);
126 const ir_edge_t *edge;
128 foreach_out_edge(node, edge) {
129 proj = get_edge_src_irn(edge);
130 assert(is_Proj(proj) && "non-Proj from mode_T node");
131 if (get_Proj_proj(proj) == pos) {
132 reg = arch_get_irn_register(proj);
138 assert(reg && "no out register found");
142 /*************************************************************
144 * (_) | | / _| | | | |
145 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
146 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
147 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
148 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
151 *************************************************************/
154 * Emit the name of the source register at given input position.
156 void arm_emit_source_register(const ir_node *node, int pos) {
157 const arch_register_t *reg = get_in_reg(node, pos);
158 be_emit_string(arch_register_get_name(reg));
162 * Emit the name of the destination register at given output position.
164 void arm_emit_dest_register(const ir_node *node, int pos) {
165 const arch_register_t *reg = get_out_reg(node, pos);
166 be_emit_string(arch_register_get_name(reg));
170 * Emit a node's offset.
172 void arm_emit_offset(const ir_node *node) {
174 ir_opcode opc = get_irn_opcode(node);
176 if (opc == beo_Reload || opc == beo_Spill) {
177 ir_entity *ent = be_get_frame_entity(node);
178 offset = get_entity_offset(ent);
180 assert(!"unimplemented arm_emit_offset for this node type");
181 panic("unimplemented arm_emit_offset for this node type");
183 be_emit_irprintf("%d", offset);
187 * Emit the arm fpa instruction suffix depending on the mode.
189 static void arm_emit_fpa_postfix(const ir_mode *mode) {
190 int bits = get_mode_size_bits(mode);
201 * Emit the instruction suffix depending on the mode.
203 void arm_emit_mode(const ir_node *node) {
206 if (is_arm_irn(node)) {
207 const arm_attr_t *attr = get_arm_attr_const(node);
208 mode = attr->op_mode ? attr->op_mode : get_irn_mode(node);
210 mode = get_irn_mode(node);
212 arm_emit_fpa_postfix(mode);
216 * Emit a const or SymConst value.
218 void arm_emit_immediate(const ir_node *node) {
219 const arm_attr_t *attr = get_arm_attr_const(node);
221 if (ARM_GET_SHF_MOD(attr) == ARM_SHF_IMM) {
222 be_emit_irprintf("#0x%X", arm_decode_imm_w_shift(get_arm_imm_value(node)));
223 } else if (ARM_GET_FPA_IMM(attr)) {
224 be_emit_irprintf("#%s", arm_get_fpa_imm_name(get_arm_imm_value(node)));
225 } else if (is_arm_SymConst(node))
226 be_emit_ident(get_arm_symconst_id(node));
228 assert(!"not a Constant");
233 * Returns the tarval or offset of an arm node as a string.
235 void arm_emit_shift(const ir_node *node) {
236 arm_shift_modifier mod;
238 mod = get_arm_shift_modifier(node);
239 if (ARM_HAS_SHIFT(mod)) {
240 int v = get_arm_imm_value(node);
242 be_emit_irprintf(", %s #%d", arm_shf_mod_name(mod), v);
246 /** An entry in the sym_or_tv set. */
247 typedef struct sym_or_tv_t {
249 ident *id; /**< An ident. */
250 tarval *tv; /**< A tarval. */
251 const void *generic; /**< For generic compare. */
253 unsigned label; /**< the associated label. */
254 char is_ident; /**< Non-zero if an ident is stored. */
258 * Returns a unique label. This number will not be used a second time.
260 static unsigned get_unique_label(void) {
261 static unsigned id = 0;
268 static void emit_arm_SymConst(const ir_node *irn) {
269 sym_or_tv_t key, *entry;
272 key.u.id = get_arm_symconst_id(irn);
275 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
276 if (entry->label == 0) {
277 /* allocate a label */
278 entry->label = get_unique_label();
280 label = entry->label;
282 /* load the symbol indirect */
283 be_emit_cstring("\tldr ");
284 arm_emit_dest_register(irn, 0);
285 be_emit_irprintf(", .L%u", label);
286 be_emit_finish_line_gas(irn);
290 * Emit a floating point fpa constant.
292 static void emit_arm_fpaConst(const ir_node *irn) {
293 sym_or_tv_t key, *entry;
297 key.u.tv = get_fpaConst_value(irn);
300 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
301 if (entry->label == 0) {
302 /* allocate a label */
303 entry->label = get_unique_label();
305 label = entry->label;
307 /* load the tarval indirect */
308 mode = get_irn_mode(irn);
309 be_emit_cstring("\tldf");
310 arm_emit_fpa_postfix(mode);
313 arm_emit_dest_register(irn, 0);
314 be_emit_irprintf(", .L%u", label);
315 be_emit_finish_line_gas(irn);
319 * Returns the next block in a block schedule.
321 static ir_node *sched_next_block(const ir_node *block) {
322 return get_irn_link(block);
326 * Returns the target block for a control flow node.
328 static ir_node *get_cfop_target_block(const ir_node *irn) {
329 return get_irn_link(irn);
333 * Emits a block label for the given block.
335 static void arm_emit_block_name(const ir_node *block) {
336 if (has_Block_label(block)) {
337 be_emit_string(be_gas_block_label_prefix());
338 be_emit_irprintf("%lu", get_Block_label(block));
340 be_emit_cstring(BLOCK_PREFIX);
341 be_emit_irprintf("%d", get_irn_node_nr(block));
346 * Emit the target label for a control flow node.
348 static void arm_emit_cfop_target(const ir_node *irn) {
349 ir_node *block = get_cfop_target_block(irn);
351 arm_emit_block_name(block);
355 * Emit a Compare with conditional branch.
357 static void emit_arm_CmpBra(const ir_node *irn) {
358 const ir_edge_t *edge;
359 const ir_node *proj_true = NULL;
360 const ir_node *proj_false = NULL;
361 const ir_node *block;
362 const ir_node *next_block;
363 ir_node *op1 = get_irn_n(irn, 0);
364 ir_mode *opmode = get_irn_mode(op1);
366 int proj_num = get_arm_CondJmp_proj_num(irn);
368 foreach_out_edge(irn, edge) {
369 ir_node *proj = get_edge_src_irn(edge);
370 long nr = get_Proj_proj(proj);
371 if (nr == pn_Cond_true) {
378 /* for now, the code works for scheduled and non-schedules blocks */
379 block = get_nodes_block(irn);
381 /* we have a block schedule */
382 next_block = sched_next_block(block);
384 if (proj_num == pn_Cmp_False) {
385 /* always false: should not happen */
386 be_emit_cstring("\tb ");
387 arm_emit_cfop_target(proj_false);
388 be_emit_finish_line_gas(proj_false);
389 } else if (proj_num == pn_Cmp_True) {
390 /* always true: should not happen */
391 be_emit_cstring("\tb ");
392 arm_emit_cfop_target(proj_true);
393 be_emit_finish_line_gas(proj_true);
395 if (mode_is_float(opmode)) {
396 suffix = "ICHWILLIMPLEMENTIERTWERDEN";
398 be_emit_cstring("\tfcmp ");
399 arm_emit_source_register(irn, 0);
400 be_emit_cstring(", ");
401 arm_emit_source_register(irn, 1);
402 be_emit_finish_line_gas(irn);
404 be_emit_cstring("\tfmstat");
405 be_emit_pad_comment();
406 be_emit_cstring("/* FCSPR -> CPSR */");
407 be_emit_finish_line_gas(NULL);
409 if (get_cfop_target_block(proj_true) == next_block) {
410 /* exchange both proj's so the second one can be omitted */
411 const ir_node *t = proj_true;
413 proj_true = proj_false;
415 proj_num = get_negated_pnc(proj_num, mode_Iu);
418 case pn_Cmp_Eq: suffix = "eq"; break;
419 case pn_Cmp_Lt: suffix = "lt"; break;
420 case pn_Cmp_Le: suffix = "le"; break;
421 case pn_Cmp_Gt: suffix = "gt"; break;
422 case pn_Cmp_Ge: suffix = "ge"; break;
423 case pn_Cmp_Lg: suffix = "ne"; break;
424 case pn_Cmp_Leg: suffix = "al"; break;
425 default: assert(!"Cmp unsupported"); suffix = "al";
427 be_emit_cstring("\tcmp ");
428 arm_emit_source_register(irn, 0);
429 be_emit_cstring(", ");
430 arm_emit_source_register(irn, 1);
431 be_emit_finish_line_gas(irn);
434 /* emit the true proj */
435 be_emit_irprintf("\tb%s ", suffix);
436 arm_emit_cfop_target(proj_true);
437 be_emit_finish_line_gas(proj_true);
439 if (get_cfop_target_block(proj_false) == next_block) {
440 be_emit_cstring("\t/* fallthrough to ");
441 arm_emit_cfop_target(proj_false);
442 be_emit_cstring(" */");
443 be_emit_finish_line_gas(proj_false);
445 be_emit_cstring("b ");
446 arm_emit_cfop_target(proj_false);
447 be_emit_finish_line_gas(proj_false);
454 * Emit a Tst with conditional branch.
456 static void emit_arm_TstBra(const ir_node *irn)
458 const ir_edge_t *edge;
459 const ir_node *proj_true = NULL;
460 const ir_node *proj_false = NULL;
461 const ir_node *block;
462 const ir_node *next_block;
464 int proj_num = get_arm_CondJmp_proj_num(irn);
466 foreach_out_edge(irn, edge) {
467 ir_node *proj = get_edge_src_irn(edge);
468 long nr = get_Proj_proj(proj);
469 if (nr == pn_Cond_true) {
476 /* for now, the code works for scheduled and non-schedules blocks */
477 block = get_nodes_block(irn);
479 /* we have a block schedule */
480 next_block = sched_next_block(block);
482 assert(proj_num != pn_Cmp_False);
483 assert(proj_num != pn_Cmp_True);
485 if (get_cfop_target_block(proj_true) == next_block) {
486 /* exchange both proj's so the second one can be omitted */
487 const ir_node *t = proj_true;
489 proj_true = proj_false;
491 proj_num = get_negated_pnc(proj_num, mode_Iu);
494 case pn_Cmp_Eq: suffix = "eq"; break;
495 case pn_Cmp_Lt: suffix = "lt"; break;
496 case pn_Cmp_Le: suffix = "le"; break;
497 case pn_Cmp_Gt: suffix = "gt"; break;
498 case pn_Cmp_Ge: suffix = "ge"; break;
499 case pn_Cmp_Lg: suffix = "ne"; break;
500 case pn_Cmp_Leg: suffix = "al"; break;
501 default: assert(!"Cmp unsupported"); suffix = "al";
503 be_emit_cstring("\ttst ");
504 arm_emit_source_register(irn, 0);
505 be_emit_cstring(", ");
506 arm_emit_source_register(irn, 1);
507 be_emit_finish_line_gas(irn);
509 /* emit the true proj */
510 be_emit_irprintf("\tb%s ", suffix);
511 arm_emit_cfop_target(proj_true);
512 be_emit_finish_line_gas(proj_true);
514 if (get_cfop_target_block(proj_false) == next_block) {
515 be_emit_cstring("\t/* fallthrough to ");
516 arm_emit_cfop_target(proj_false);
517 be_emit_cstring(" */");
518 be_emit_finish_line_gas(proj_false);
520 be_emit_cstring("b ");
521 arm_emit_cfop_target(proj_false);
522 be_emit_finish_line_gas(proj_false);
527 * Emit a Compare with conditional branch.
529 static void emit_arm_fpaCmfBra(const ir_node *irn) {
534 * Emit a Compare with conditional branch.
536 static void emit_arm_fpaCmfeBra(const ir_node *irn) {
540 /** Sort register in ascending order. */
541 static int reg_cmp(const void *a, const void *b) {
542 const arch_register_t * const *ra = a;
543 const arch_register_t * const *rb = b;
545 return *ra < *rb ? -1 : (*ra != *rb);
549 * Create the CopyB instruction sequence.
551 static void emit_arm_CopyB(const ir_node *irn) {
552 unsigned size = (unsigned)get_arm_imm_value(irn);
554 const char *tgt = arch_register_get_name(get_in_reg(irn, 0));
555 const char *src = arch_register_get_name(get_in_reg(irn, 1));
556 const char *t0, *t1, *t2, *t3;
558 const arch_register_t *tmpregs[4];
560 /* collect the temporary registers and sort them, we need ascending order */
561 tmpregs[0] = get_in_reg(irn, 2);
562 tmpregs[1] = get_in_reg(irn, 3);
563 tmpregs[2] = get_in_reg(irn, 4);
564 tmpregs[3] = &arm_gp_regs[REG_R12];
566 /* Note: R12 is always the last register because the RA did not assign higher ones */
567 qsort((void *)tmpregs, 3, sizeof(tmpregs[0]), reg_cmp);
569 /* need ascending order */
570 t0 = arch_register_get_name(tmpregs[0]);
571 t1 = arch_register_get_name(tmpregs[1]);
572 t2 = arch_register_get_name(tmpregs[2]);
573 t3 = arch_register_get_name(tmpregs[3]);
575 be_emit_cstring("/* MemCopy (");
577 be_emit_cstring(")->(");
578 arm_emit_source_register(irn, 0);
579 be_emit_irprintf(" [%u bytes], Uses ", size);
581 be_emit_cstring(", ");
583 be_emit_cstring(", ");
585 be_emit_cstring(", and ");
587 be_emit_cstring("*/");
588 be_emit_finish_line_gas(NULL);
590 assert(size > 0 && "CopyB needs size > 0" );
593 assert(!"strange hack enabled: copy more bytes than needed!");
602 be_emit_cstring("\tldr ");
604 be_emit_cstring(", [");
606 be_emit_cstring(", #0]");
607 be_emit_finish_line_gas(NULL);
609 be_emit_cstring("\tstr ");
611 be_emit_cstring(", [");
613 be_emit_cstring(", #0]");
614 be_emit_finish_line_gas(irn);
617 be_emit_cstring("\tldmia ");
619 be_emit_cstring("!, {");
621 be_emit_cstring(", ");
624 be_emit_finish_line_gas(NULL);
626 be_emit_cstring("\tstmia ");
628 be_emit_cstring("!, {");
630 be_emit_cstring(", ");
633 be_emit_finish_line_gas(irn);
636 be_emit_cstring("\tldmia ");
638 be_emit_cstring("!, {");
640 be_emit_cstring(", ");
642 be_emit_cstring(", ");
645 be_emit_finish_line_gas(NULL);
647 be_emit_cstring("\tstmia ");
649 be_emit_cstring("!, {");
651 be_emit_cstring(", ");
653 be_emit_cstring(", ");
656 be_emit_finish_line_gas(irn);
661 be_emit_cstring("\tldmia ");
663 be_emit_cstring("!, {");
665 be_emit_cstring(", ");
667 be_emit_cstring(", ");
669 be_emit_cstring(", ");
672 be_emit_finish_line_gas(NULL);
674 be_emit_cstring("\tstmia ");
676 be_emit_cstring("!, {");
678 be_emit_cstring(", ");
680 be_emit_cstring(", ");
682 be_emit_cstring(", ");
685 be_emit_finish_line_gas(irn);
690 static void emit_arm_SwitchJmp(const ir_node *irn) {
691 const ir_edge_t *edge;
697 ir_node *default_proj = NULL;
699 block_nr = get_irn_node_nr(irn);
700 n_projs = get_arm_SwitchJmp_n_projs(irn);
702 projs = XMALLOCNZ(ir_node*, n_projs);
704 foreach_out_edge(irn, edge) {
705 proj = get_edge_src_irn(edge);
706 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
708 if (get_Proj_proj(proj) == get_arm_SwitchJmp_default_proj_num(irn))
711 projs[get_Proj_proj(proj)] = proj;
713 assert(default_proj != NULL && "SwitchJmp should have a Default Proj");
720 be_emit_cstring("\tcmp ");
721 arm_emit_source_register(irn, 0);
722 be_emit_irprintf(", #%u", n_projs - 1);
723 be_emit_finish_line_gas(irn);
725 be_emit_cstring("\tbhi ");
726 arm_emit_cfop_target(default_proj);
727 be_emit_finish_line_gas(default_proj);
730 LDR %r12, .TABLE_X_START
731 ADD %r12, %r12, [%1S, LSL #2]
735 be_emit_irprintf("\tldr %%r12, TABLE_%d_START", block_nr);
736 be_emit_finish_line_gas(NULL);
738 be_emit_irprintf("\tadd %%r12, %%r12, ");
739 arm_emit_source_register(irn, 0);
740 be_emit_cstring(", LSL #2");
741 be_emit_finish_line_gas(NULL);
743 be_emit_cstring("\tldr %r15, [%r12, #0]");
744 be_emit_finish_line_gas(NULL);
746 be_emit_irprintf("TABLE_%d_START:\n\t.word\tTABLE_%d", block_nr, block_nr);
747 be_emit_finish_line_gas(NULL);
748 be_emit_irprintf("\t.align 2");
749 be_emit_finish_line_gas(NULL);
750 be_emit_irprintf("TABLE_%d:", block_nr);
751 be_emit_finish_line_gas(NULL);
753 for (i = 0; i < n_projs; ++i) {
756 proj = projs[get_arm_SwitchJmp_default_proj_num(irn)];
758 be_emit_cstring("\t.word\t");
759 arm_emit_cfop_target(proj);
760 be_emit_finish_line_gas(proj);
762 be_emit_irprintf("\t.align 2\n");
763 be_emit_finish_line_gas(NULL);
767 /************************************************************************/
769 /************************************************************************/
771 static void emit_be_Call(const ir_node *irn) {
772 ir_entity *ent = be_Call_get_entity(irn);
774 be_emit_cstring("\tbl ");
776 set_entity_backend_marked(ent, 1);
777 be_emit_ident(get_entity_ld_ident(ent));
779 arm_emit_source_register(irn, be_pos_Call_ptr);
781 be_emit_finish_line_gas(irn);
784 /** Emit an IncSP node */
785 static void emit_be_IncSP(const ir_node *irn) {
786 int offs = -be_get_IncSP_offset(irn);
790 be_emit_cstring("\tsub ");
793 be_emit_cstring("\tadd ");
795 arm_emit_dest_register(irn, 0);
796 be_emit_cstring(", ");
797 arm_emit_source_register(irn, 0);
798 be_emit_irprintf(", #0x%X", offs);
800 /* omitted IncSP(0) */
803 be_emit_finish_line_gas(irn);
806 static void emit_be_Copy(const ir_node *irn) {
807 ir_mode *mode = get_irn_mode(irn);
809 if (get_in_reg(irn, 0) == get_out_reg(irn, 0)) {
814 if (mode_is_float(mode)) {
816 be_emit_cstring("\tmvf");
819 arm_emit_dest_register(irn, 0);
820 be_emit_cstring(", ");
821 arm_emit_source_register(irn, 0);
822 be_emit_finish_line_gas(irn);
824 assert(0 && "move not supported for this mode");
825 panic("emit_be_Copy: move not supported for this mode");
827 } else if (mode_is_data(mode)) {
828 be_emit_cstring("\tmov ");
829 arm_emit_dest_register(irn, 0);
830 be_emit_cstring(", ");
831 arm_emit_source_register(irn, 0);
832 be_emit_finish_line_gas(irn);
834 assert(0 && "move not supported for this mode");
835 panic("emit_be_Copy: move not supported for this mode");
840 * Emit code for a Spill.
842 static void emit_be_Spill(const ir_node *irn) {
843 ir_mode *mode = get_irn_mode(be_get_Spill_val(irn));
845 if (mode_is_float(mode)) {
846 if (USE_FPA(cg->isa)) {
847 be_emit_cstring("\tstf");
848 arm_emit_fpa_postfix(mode);
851 assert(0 && "spill not supported for this mode");
852 panic("emit_be_Spill: spill not supported for this mode");
854 } else if (mode_is_dataM(mode)) {
855 be_emit_cstring("\tstr ");
857 assert(0 && "spill not supported for this mode");
858 panic("emit_be_Spill: spill not supported for this mode");
860 arm_emit_source_register(irn, 1);
861 be_emit_cstring(", [");
862 arm_emit_source_register(irn, 0);
863 be_emit_cstring(", #");
864 arm_emit_offset(irn);
866 be_emit_finish_line_gas(irn);
870 * Emit code for a Reload.
872 static void emit_be_Reload(const ir_node *irn) {
873 ir_mode *mode = get_irn_mode(irn);
875 if (mode_is_float(mode)) {
876 if (USE_FPA(cg->isa)) {
877 be_emit_cstring("\tldf");
878 arm_emit_fpa_postfix(mode);
881 assert(0 && "reload not supported for this mode");
882 panic("emit_be_Reload: reload not supported for this mode");
884 } else if (mode_is_dataM(mode)) {
885 be_emit_cstring("\tldr ");
887 assert(0 && "reload not supported for this mode");
888 panic("emit_be_Reload: reload not supported for this mode");
890 arm_emit_dest_register(irn, 0);
891 be_emit_cstring(", [");
892 arm_emit_source_register(irn, 0);
893 be_emit_cstring(", #");
894 arm_emit_offset(irn);
896 be_emit_finish_line_gas(irn);
899 static void emit_be_Perm(const ir_node *irn) {
900 be_emit_cstring("\teor ");
901 arm_emit_source_register(irn, 0);
902 be_emit_cstring(", ");
903 arm_emit_source_register(irn, 0);
904 be_emit_cstring(", ");
905 arm_emit_source_register(irn, 1);
906 be_emit_finish_line_gas(NULL);
908 be_emit_cstring("\teor ");
909 arm_emit_source_register(irn, 1);
910 be_emit_cstring(", ");
911 arm_emit_source_register(irn, 0);
912 be_emit_cstring(", ");
913 arm_emit_source_register(irn, 1);
914 be_emit_finish_line_gas(NULL);
916 be_emit_cstring("\teor ");
917 arm_emit_source_register(irn, 0);
918 be_emit_cstring(", ");
919 arm_emit_source_register(irn, 0);
920 be_emit_cstring(", ");
921 arm_emit_source_register(irn, 1);
922 be_emit_finish_line_gas(irn);
925 /************************************************************************/
927 /************************************************************************/
929 static void emit_Jmp(const ir_node *node) {
930 ir_node *block, *next_block;
932 /* for now, the code works for scheduled and non-schedules blocks */
933 block = get_nodes_block(node);
935 /* we have a block schedule */
936 next_block = sched_next_block(block);
937 if (get_cfop_target_block(node) != next_block) {
938 be_emit_cstring("\tb ");
939 arm_emit_cfop_target(node);
941 be_emit_cstring("\t/* fallthrough to ");
942 arm_emit_cfop_target(node);
943 be_emit_cstring(" */");
945 be_emit_finish_line_gas(node);
948 static void emit_arm_fpaDbl2GP(const ir_node *irn) {
949 be_emit_cstring("\tstfd ");
950 arm_emit_source_register(irn, 0);
951 be_emit_cstring(", [sp, #-8]!");
952 be_emit_pad_comment();
953 be_emit_cstring("/* Push fp to stack */");
954 be_emit_finish_line_gas(NULL);
956 be_emit_cstring("\tldmfd sp!, {");
957 arm_emit_dest_register(irn, 1);
958 be_emit_cstring(", ");
959 arm_emit_dest_register(irn, 0);
961 be_emit_pad_comment();
962 be_emit_cstring("/* Pop destination */");
963 be_emit_finish_line_gas(irn);
966 static void emit_arm_LdTls(const ir_node *irn) {
968 panic("TLS not supported for this target");
969 /* Er... our gcc does not support it... Install a newer toolchain. */
972 /***********************************************************************************
975 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
976 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
977 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
978 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
980 ***********************************************************************************/
982 static void emit_silence(const ir_node *irn) {
988 * The type of a emitter function.
990 typedef void (emit_func)(const ir_node *irn);
993 * Set a node emitter. Make it a bit more type safe.
995 static INLINE void set_emitter(ir_op *op, emit_func arm_emit_node) {
996 op->ops.generic = (op_func)arm_emit_node;
1000 * Enters the emitter functions for handled nodes into the generic
1001 * pointer of an opcode.
1003 static void arm_register_emitters(void) {
1005 #define ARM_EMIT(a) set_emitter(op_arm_##a, emit_arm_##a)
1006 #define EMIT(a) set_emitter(op_##a, emit_##a)
1007 #define BE_EMIT(a) set_emitter(op_be_##a, emit_be_##a)
1008 #define SILENCE(a) set_emitter(op_##a, emit_silence)
1010 /* first clear the generic function pointer for all ops */
1011 clear_irp_opcodes_generic_func();
1013 /* register all emitter functions defined in spec */
1014 arm_register_spec_emitters();
1016 /* other emitter functions */
1019 ARM_EMIT(fpaCmfBra);
1020 ARM_EMIT(fpaCmfeBra);
1022 // ARM_EMIT(CopyB_i);
1025 ARM_EMIT(SwitchJmp);
1026 ARM_EMIT(fpaDbl2GP);
1030 /* benode emitter */
1047 SILENCE(be_CopyKeep);
1048 SILENCE(be_RegParams);
1049 SILENCE(be_Barrier);
1060 * Emits code for a node.
1062 static void arm_emit_node(const ir_node *irn) {
1063 ir_op *op = get_irn_op(irn);
1065 if (op->ops.generic) {
1066 emit_func *emit = (emit_func *)op->ops.generic;
1067 be_dbg_set_dbg_info(get_irn_dbg_info(irn));
1070 be_emit_cstring("\t/* TODO */");
1071 be_emit_finish_line_gas(irn);
1076 * emit the block label if needed.
1078 static void arm_emit_block_header(ir_node *block, ir_node *prev)
1083 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1086 n_cfgpreds = get_Block_n_cfgpreds(block);
1087 if (n_cfgpreds == 1) {
1088 ir_node *pred = get_Block_cfgpred(block, 0);
1089 ir_node *pred_block = get_nodes_block(pred);
1091 /* we don't need labels for fallthrough blocks, however switch-jmps
1092 * are no fallthroughs */
1093 if (pred_block == prev &&
1094 !(is_Proj(pred) && is_arm_SwitchJmp(get_Proj_pred(pred)))) {
1104 arm_emit_block_name(block);
1107 be_emit_pad_comment();
1108 be_emit_cstring(" /* preds:");
1110 /* emit list of pred blocks in comment */
1111 arity = get_irn_arity(block);
1112 for (i = 0; i < arity; ++i) {
1113 ir_node *predblock = get_Block_cfgpred_block(block, i);
1114 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1117 be_emit_cstring("\t/* ");
1118 arm_emit_block_name(block);
1119 be_emit_cstring(": ");
1121 if (exec_freq != NULL) {
1122 be_emit_irprintf(" freq: %f",
1123 get_block_execfreq(exec_freq, block));
1125 be_emit_cstring(" */\n");
1126 be_emit_write_line();
1130 * Walks over the nodes in a block connected by scheduling edges
1131 * and emits code for each node.
1133 static void arm_gen_block(ir_node *block, ir_node *prev_block) {
1136 arm_emit_block_header(block, prev_block);
1137 be_dbg_set_dbg_info(get_irn_dbg_info(block));
1138 sched_foreach(block, irn) {
1144 * Emits code for function start.
1146 void arm_func_prolog(ir_graph *irg) {
1147 ir_entity *ent = get_irg_entity(irg);
1148 const char *irg_name = get_entity_ld_name(ent);
1150 be_emit_write_line();
1151 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1152 be_emit_cstring("\t.align 2\n");
1154 if (get_entity_visibility(ent) == visibility_external_visible)
1155 be_emit_irprintf("\t.global %s\n", irg_name);
1156 be_emit_irprintf("%s:\n", irg_name);
1160 * Emits code for function end
1162 void arm_emit_end(FILE *F, ir_graph *irg) {
1164 fprintf(F, "\t.ident \"firmcc\"\n");
1169 * Sets labels for control flow nodes (jump target)
1171 static void arm_gen_labels(ir_node *block, void *env) {
1173 int n = get_Block_n_cfgpreds(block);
1176 for (n--; n >= 0; n--) {
1177 pred = get_Block_cfgpred(block, n);
1178 set_irn_link(pred, block);
1183 * Compare two entries of the symbol or tarval set.
1185 static int cmp_sym_or_tv(const void *elt, const void *key, size_t size) {
1186 const sym_or_tv_t *p1 = elt;
1187 const sym_or_tv_t *p2 = key;
1190 /* as an identifier NEVER can point to a tarval, it's enough
1191 to compare it this way */
1192 return p1->u.generic != p2->u.generic;
1196 * Main driver. Emits the code for one routine.
1198 void arm_gen_routine(const arm_code_gen_t *arm_cg, ir_graph *irg) {
1199 ir_node **blk_sched;
1201 ir_node *last_block = NULL;
1202 ir_entity *entity = get_irg_entity(irg);
1205 isa = (const arm_isa_t *)cg->arch_env;
1206 sym_or_tv = new_set(cmp_sym_or_tv, 8);
1208 arm_register_emitters();
1210 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
1212 /* create the block schedule. For now, we don't need it earlier. */
1213 blk_sched = be_create_block_schedule(cg->irg, cg->birg->exec_freq);
1215 arm_func_prolog(irg);
1216 irg_block_walk_graph(irg, arm_gen_labels, NULL, NULL);
1218 n = ARR_LEN(blk_sched);
1219 for (i = 0; i < n;) {
1220 ir_node *block, *next_bl;
1222 block = blk_sched[i];
1224 next_bl = i < n ? blk_sched[i] : NULL;
1226 /* set here the link. the emitter expects to find the next block here */
1227 set_irn_link(block, next_bl);
1228 arm_gen_block(block, last_block);
1232 be_dbg_method_end();
1234 /* emit SymConst values */
1235 if (set_count(sym_or_tv) > 0) {
1238 be_emit_cstring("\t.align 2\n");
1240 foreach_set(sym_or_tv, entry) {
1241 be_emit_irprintf(".L%u:\n", entry->label);
1243 if (entry->is_ident) {
1244 be_emit_cstring("\t.word\t");
1245 be_emit_ident(entry->u.id);
1247 be_emit_write_line();
1249 tarval *tv = entry->u.tv;
1250 int i, size = get_mode_size_bytes(get_tarval_mode(tv));
1253 /* beware: ARM fpa uses big endian format */
1254 for (i = ((size + 3) & ~3) - 4; i >= 0; i -= 4) {
1256 v = get_tarval_sub_bits(tv, i+3);
1257 v = (v << 8) | get_tarval_sub_bits(tv, i+2);
1258 v = (v << 8) | get_tarval_sub_bits(tv, i+1);
1259 v = (v << 8) | get_tarval_sub_bits(tv, i+0);
1260 be_emit_irprintf("\t.word\t%u\n", v);
1261 be_emit_write_line();
1266 be_emit_write_line();
1271 void arm_init_emitter(void)
1273 FIRM_DBG_REGISTER(dbg, "firm.be.arm.emit");