2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
42 #include "raw_bitset.h"
45 #include "../besched.h"
46 #include "../beblocksched.h"
48 #include "../begnuas.h"
49 #include "../be_dbgout.h"
51 #include "arm_emitter.h"
52 #include "arm_optimize.h"
53 #include "gen_arm_emitter.h"
54 #include "arm_nodes_attr.h"
55 #include "arm_new_nodes.h"
56 #include "arm_map_regs.h"
57 #include "gen_arm_regalloc_if.h"
59 #include "../benode.h"
61 #define SNPRINTF_BUF_LEN 128
63 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
65 static const arm_code_gen_t *cg;
66 static set *sym_or_tv;
69 * Returns the register at in position pos.
71 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
74 const arch_register_t *reg = NULL;
76 assert(get_irn_arity(irn) > pos && "Invalid IN position");
78 /* The out register of the operator at position pos is the
79 in register we need. */
80 op = get_irn_n(irn, pos);
82 reg = arch_get_irn_register(op);
84 assert(reg && "no in register found");
86 /* in case of a joker register: just return a valid register */
87 if (arch_register_type_is(reg, joker)) {
88 const arch_register_req_t *req = arch_get_register_req(irn, pos);
90 if (arch_register_req_is(req, limited)) {
91 /* in case of limited requirements: get the first allowed register */
92 unsigned idx = rbitset_next(req->limited, 0, 1);
93 reg = arch_register_for_index(req->cls, idx);
95 /* otherwise get first register in class */
96 reg = arch_register_for_index(req->cls, 0);
104 * Returns the register at out position pos.
106 static const arch_register_t *get_out_reg(const ir_node *node, int pos)
109 const arch_register_t *reg = NULL;
111 /* 1st case: irn is not of mode_T, so it has only */
112 /* one OUT register -> good */
113 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
114 /* Proj with the corresponding projnum for the register */
116 if (get_irn_mode(node) != mode_T) {
117 reg = arch_get_irn_register(node);
118 } else if (is_arm_irn(node)) {
119 reg = arch_irn_get_register(node, pos);
121 const ir_edge_t *edge;
123 foreach_out_edge(node, edge) {
124 proj = get_edge_src_irn(edge);
125 assert(is_Proj(proj) && "non-Proj from mode_T node");
126 if (get_Proj_proj(proj) == pos) {
127 reg = arch_get_irn_register(proj);
133 assert(reg && "no out register found");
138 * Emit the name of the source register at given input position.
140 void arm_emit_source_register(const ir_node *node, int pos)
142 const arch_register_t *reg = get_in_reg(node, pos);
143 be_emit_string(arch_register_get_name(reg));
147 * Emit the name of the destination register at given output position.
149 void arm_emit_dest_register(const ir_node *node, int pos)
151 const arch_register_t *reg = get_out_reg(node, pos);
152 be_emit_string(arch_register_get_name(reg));
156 * Emit a node's offset.
158 void arm_emit_offset(const ir_node *node)
160 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
161 assert(attr->base.is_load_store);
163 be_emit_irprintf("0x%X", attr->offset);
167 * Emit the arm fpa instruction suffix depending on the mode.
169 static void arm_emit_fpa_postfix(const ir_mode *mode)
171 int bits = get_mode_size_bits(mode);
182 * Emit the instruction suffix depending on the mode.
184 void arm_emit_mode(const ir_node *node)
188 if (is_arm_irn(node)) {
189 const arm_attr_t *attr = get_arm_attr_const(node);
190 mode = attr->op_mode ? attr->op_mode : get_irn_mode(node);
192 mode = get_irn_mode(node);
194 arm_emit_fpa_postfix(mode);
197 void arm_emit_symconst(const ir_node *node)
199 const arm_SymConst_attr_t *symconst = get_arm_SymConst_attr_const(node);
200 ir_entity *entity = symconst->entity;
202 be_gas_emit_entity(entity);
204 /* TODO do something with offset */
207 void arm_emit_load_mode(const ir_node *node)
209 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
210 ir_mode *mode = attr->load_store_mode;
211 int bits = get_mode_size_bits(mode);
212 bool is_signed = mode_is_signed(mode);
214 be_emit_string(is_signed ? "sh" : "h");
215 } else if (bits == 8) {
216 be_emit_string(is_signed ? "sb" : "b");
222 void arm_emit_store_mode(const ir_node *node)
224 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
225 ir_mode *mode = attr->load_store_mode;
226 int bits = get_mode_size_bits(mode);
228 be_emit_cstring("h");
229 } else if (bits == 8) {
230 be_emit_cstring("b");
237 static void emit_shf_mod_name(arm_shift_modifier_t mod)
240 case ARM_SHF_ASR_REG:
241 case ARM_SHF_ASR_IMM:
242 be_emit_cstring("asr");
244 case ARM_SHF_LSL_REG:
245 case ARM_SHF_LSL_IMM:
246 be_emit_cstring("lsl");
248 case ARM_SHF_LSR_REG:
249 case ARM_SHF_LSR_IMM:
250 be_emit_cstring("lsr");
252 case ARM_SHF_ROR_REG:
253 case ARM_SHF_ROR_IMM:
254 be_emit_cstring("ror");
259 panic("can't emit this shf_mod_name %d", (int) mod);
262 void arm_emit_shifter_operand(const ir_node *node)
264 const arm_shifter_operand_t *attr = get_irn_generic_attr_const(node);
266 switch (attr->shift_modifier) {
268 arm_emit_source_register(node, get_irn_arity(node) - 1);
271 unsigned val = attr->immediate_value;
272 val = (val >> attr->shift_immediate)
273 | (val << (32-attr->shift_immediate));
275 be_emit_irprintf("#0x%X", val);
278 case ARM_SHF_ASR_IMM:
279 case ARM_SHF_LSL_IMM:
280 case ARM_SHF_LSR_IMM:
281 case ARM_SHF_ROR_IMM:
282 arm_emit_source_register(node, get_irn_arity(node) - 1);
283 be_emit_cstring(", ");
284 emit_shf_mod_name(attr->shift_modifier);
285 be_emit_irprintf(" #0x%X", attr->shift_immediate);
288 case ARM_SHF_ASR_REG:
289 case ARM_SHF_LSL_REG:
290 case ARM_SHF_LSR_REG:
291 case ARM_SHF_ROR_REG:
292 arm_emit_source_register(node, get_irn_arity(node) - 2);
293 be_emit_cstring(", ");
294 emit_shf_mod_name(attr->shift_modifier);
295 be_emit_cstring(" ");
296 arm_emit_source_register(node, get_irn_arity(node) - 1);
300 arm_emit_source_register(node, get_irn_arity(node) - 1);
301 panic("RRX shifter emitter TODO");
303 case ARM_SHF_INVALID:
306 panic("Invalid shift_modifier while emitting %+F", node);
309 /** An entry in the sym_or_tv set. */
310 typedef struct sym_or_tv_t {
312 ir_entity *entity; /**< An entity. */
313 tarval *tv; /**< A tarval. */
314 const void *generic; /**< For generic compare. */
316 unsigned label; /**< the associated label. */
317 bool is_entity; /**< true if an entity is stored. */
321 * Returns a unique label. This number will not be used a second time.
323 static unsigned get_unique_label(void)
325 static unsigned id = 0;
332 static void emit_arm_SymConst(const ir_node *irn)
334 const arm_SymConst_attr_t *attr = get_arm_SymConst_attr_const(irn);
335 sym_or_tv_t key, *entry;
338 key.u.entity = attr->entity;
339 key.is_entity = true;
341 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
342 if (entry->label == 0) {
343 /* allocate a label */
344 entry->label = get_unique_label();
346 label = entry->label;
348 /* load the symbol indirect */
349 be_emit_cstring("\tldr ");
350 arm_emit_dest_register(irn, 0);
351 be_emit_irprintf(", %s%u", be_gas_get_private_prefix(), label);
352 be_emit_finish_line_gas(irn);
355 static void emit_arm_FrameAddr(const ir_node *irn)
357 const arm_SymConst_attr_t *attr = get_irn_generic_attr_const(irn);
359 be_emit_cstring("\tadd ");
360 arm_emit_dest_register(irn, 0);
361 be_emit_cstring(", ");
362 arm_emit_source_register(irn, 0);
363 be_emit_cstring(", ");
364 be_emit_irprintf("#0x%X", attr->fp_offset);
365 be_emit_finish_line_gas(irn);
369 * Emit a floating point fpa constant.
371 static void emit_arm_fpaConst(const ir_node *irn)
373 sym_or_tv_t key, *entry;
377 key.u.tv = get_fpaConst_value(irn);
378 key.is_entity = false;
380 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
381 if (entry->label == 0) {
382 /* allocate a label */
383 entry->label = get_unique_label();
385 label = entry->label;
387 /* load the tarval indirect */
388 mode = get_irn_mode(irn);
389 be_emit_cstring("\tldf");
390 arm_emit_fpa_postfix(mode);
393 arm_emit_dest_register(irn, 0);
394 be_emit_irprintf(", %s%u", be_gas_get_private_prefix(), label);
395 be_emit_finish_line_gas(irn);
399 * Returns the next block in a block schedule.
401 static ir_node *sched_next_block(const ir_node *block)
403 return get_irn_link(block);
407 * Returns the target block for a control flow node.
409 static ir_node *get_cfop_target_block(const ir_node *irn)
411 return get_irn_link(irn);
415 * Emit the target label for a control flow node.
417 static void arm_emit_cfop_target(const ir_node *irn)
419 ir_node *block = get_cfop_target_block(irn);
421 be_gas_emit_block_name(block);
425 * Emit a Compare with conditional branch.
427 static void emit_arm_B(const ir_node *irn)
429 const ir_edge_t *edge;
430 const ir_node *proj_true = NULL;
431 const ir_node *proj_false = NULL;
432 const ir_node *block;
433 const ir_node *next_block;
434 ir_node *op1 = get_irn_n(irn, 0);
436 pn_Cmp pnc = get_arm_CondJmp_pnc(irn);
437 const arm_cmp_attr_t *cmp_attr = get_irn_generic_attr_const(op1);
438 bool is_signed = !cmp_attr->is_unsigned;
440 assert(is_arm_Cmp(op1) || is_arm_Tst(op1));
442 foreach_out_edge(irn, edge) {
443 ir_node *proj = get_edge_src_irn(edge);
444 long nr = get_Proj_proj(proj);
445 if (nr == pn_Cond_true) {
452 if (cmp_attr->ins_permuted) {
453 pnc = get_mirrored_pnc(pnc);
456 /* for now, the code works for scheduled and non-schedules blocks */
457 block = get_nodes_block(irn);
459 /* we have a block schedule */
460 next_block = sched_next_block(block);
462 assert(pnc != pn_Cmp_False);
463 assert(pnc != pn_Cmp_True);
465 if (get_cfop_target_block(proj_true) == next_block) {
466 /* exchange both proj's so the second one can be omitted */
467 const ir_node *t = proj_true;
469 proj_true = proj_false;
471 pnc = get_negated_pnc(pnc, mode_Iu);
475 case pn_Cmp_Eq: suffix = "eq"; break;
476 case pn_Cmp_Lt: suffix = is_signed ? "lt" : "lo"; break;
477 case pn_Cmp_Le: suffix = is_signed ? "le" : "ls"; break;
478 case pn_Cmp_Gt: suffix = is_signed ? "gt" : "hi"; break;
479 case pn_Cmp_Ge: suffix = is_signed ? "ge" : "hs"; break;
480 case pn_Cmp_Lg: suffix = "ne"; break;
481 case pn_Cmp_Leg: suffix = "al"; break;
482 default: panic("Cmp has unsupported pnc");
485 /* emit the true proj */
486 be_emit_irprintf("\tb%s ", suffix);
487 arm_emit_cfop_target(proj_true);
488 be_emit_finish_line_gas(proj_true);
490 if (get_cfop_target_block(proj_false) == next_block) {
491 be_emit_cstring("\t/* fallthrough to ");
492 arm_emit_cfop_target(proj_false);
493 be_emit_cstring(" */");
494 be_emit_finish_line_gas(proj_false);
496 be_emit_cstring("\tb ");
497 arm_emit_cfop_target(proj_false);
498 be_emit_finish_line_gas(proj_false);
502 /** Sort register in ascending order. */
503 static int reg_cmp(const void *a, const void *b)
505 const arch_register_t * const *ra = a;
506 const arch_register_t * const *rb = b;
508 return *ra < *rb ? -1 : (*ra != *rb);
512 * Create the CopyB instruction sequence.
514 static void emit_arm_CopyB(const ir_node *irn)
516 const arm_CopyB_attr_t *attr = get_irn_generic_attr_const(irn);
517 unsigned size = attr->size;
519 const char *tgt = arch_register_get_name(get_in_reg(irn, 0));
520 const char *src = arch_register_get_name(get_in_reg(irn, 1));
521 const char *t0, *t1, *t2, *t3;
523 const arch_register_t *tmpregs[4];
525 /* collect the temporary registers and sort them, we need ascending order */
526 tmpregs[0] = get_in_reg(irn, 2);
527 tmpregs[1] = get_in_reg(irn, 3);
528 tmpregs[2] = get_in_reg(irn, 4);
529 tmpregs[3] = &arm_gp_regs[REG_R12];
531 /* Note: R12 is always the last register because the RA did not assign higher ones */
532 qsort((void *)tmpregs, 3, sizeof(tmpregs[0]), reg_cmp);
534 /* need ascending order */
535 t0 = arch_register_get_name(tmpregs[0]);
536 t1 = arch_register_get_name(tmpregs[1]);
537 t2 = arch_register_get_name(tmpregs[2]);
538 t3 = arch_register_get_name(tmpregs[3]);
540 be_emit_cstring("/* MemCopy (");
542 be_emit_cstring(")->(");
543 arm_emit_source_register(irn, 0);
544 be_emit_irprintf(" [%u bytes], Uses ", size);
546 be_emit_cstring(", ");
548 be_emit_cstring(", ");
550 be_emit_cstring(", and ");
552 be_emit_cstring("*/");
553 be_emit_finish_line_gas(NULL);
555 assert(size > 0 && "CopyB needs size > 0" );
558 fprintf(stderr, "strange hack enabled: copy more bytes than needed!");
567 be_emit_cstring("\tldr ");
569 be_emit_cstring(", [");
571 be_emit_cstring(", #0]");
572 be_emit_finish_line_gas(NULL);
574 be_emit_cstring("\tstr ");
576 be_emit_cstring(", [");
578 be_emit_cstring(", #0]");
579 be_emit_finish_line_gas(irn);
582 be_emit_cstring("\tldmia ");
584 be_emit_cstring("!, {");
586 be_emit_cstring(", ");
589 be_emit_finish_line_gas(NULL);
591 be_emit_cstring("\tstmia ");
593 be_emit_cstring("!, {");
595 be_emit_cstring(", ");
598 be_emit_finish_line_gas(irn);
601 be_emit_cstring("\tldmia ");
603 be_emit_cstring("!, {");
605 be_emit_cstring(", ");
607 be_emit_cstring(", ");
610 be_emit_finish_line_gas(NULL);
612 be_emit_cstring("\tstmia ");
614 be_emit_cstring("!, {");
616 be_emit_cstring(", ");
618 be_emit_cstring(", ");
621 be_emit_finish_line_gas(irn);
626 be_emit_cstring("\tldmia ");
628 be_emit_cstring("!, {");
630 be_emit_cstring(", ");
632 be_emit_cstring(", ");
634 be_emit_cstring(", ");
637 be_emit_finish_line_gas(NULL);
639 be_emit_cstring("\tstmia ");
641 be_emit_cstring("!, {");
643 be_emit_cstring(", ");
645 be_emit_cstring(", ");
647 be_emit_cstring(", ");
650 be_emit_finish_line_gas(irn);
655 static void emit_arm_SwitchJmp(const ir_node *irn)
657 const ir_edge_t *edge;
663 ir_node *default_proj = NULL;
665 block_nr = get_irn_node_nr(irn);
666 n_projs = get_arm_SwitchJmp_n_projs(irn);
668 projs = XMALLOCNZ(ir_node*, n_projs);
670 foreach_out_edge(irn, edge) {
671 proj = get_edge_src_irn(edge);
672 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
674 if (get_Proj_proj(proj) == get_arm_SwitchJmp_default_proj_num(irn))
677 projs[get_Proj_proj(proj)] = proj;
679 assert(default_proj != NULL && "SwitchJmp should have a Default Proj");
686 be_emit_cstring("\tcmp ");
687 arm_emit_source_register(irn, 0);
688 be_emit_irprintf(", #%u", n_projs - 1);
689 be_emit_finish_line_gas(irn);
691 be_emit_cstring("\tbhi ");
692 arm_emit_cfop_target(default_proj);
693 be_emit_finish_line_gas(default_proj);
696 LDR %r12, .TABLE_X_START
697 ADD %r12, %r12, [%1S, LSL #2]
701 be_emit_irprintf("\tldr %%r12, TABLE_%d_START", block_nr);
702 be_emit_finish_line_gas(NULL);
704 be_emit_irprintf("\tadd %%r12, %%r12, ");
705 arm_emit_source_register(irn, 0);
706 be_emit_cstring(", LSL #2");
707 be_emit_finish_line_gas(NULL);
709 be_emit_cstring("\tldr %r15, [%r12, #0]");
710 be_emit_finish_line_gas(NULL);
712 be_emit_irprintf("TABLE_%d_START:\n\t.word\tTABLE_%d", block_nr, block_nr);
713 be_emit_finish_line_gas(NULL);
714 be_emit_irprintf("\t.align 2");
715 be_emit_finish_line_gas(NULL);
716 be_emit_irprintf("TABLE_%d:", block_nr);
717 be_emit_finish_line_gas(NULL);
719 for (i = 0; i < n_projs; ++i) {
722 proj = projs[get_arm_SwitchJmp_default_proj_num(irn)];
724 be_emit_cstring("\t.word\t");
725 arm_emit_cfop_target(proj);
726 be_emit_finish_line_gas(proj);
728 be_emit_irprintf("\t.align 2\n");
729 be_emit_finish_line_gas(NULL);
734 static void arm_emit_entity(ir_entity *entity)
736 be_emit_ident(get_entity_ld_ident(entity));
739 static void emit_be_Call(const ir_node *irn)
741 ir_entity *entity = be_Call_get_entity(irn);
743 if (entity != NULL) {
744 be_emit_cstring("\tbl ");
745 arm_emit_entity(entity);
746 be_emit_finish_line_gas(irn);
748 be_emit_cstring("\tmov lr, pc");
749 be_emit_finish_line_gas(irn);
750 be_emit_cstring("\tmov pc, ");
751 arm_emit_source_register(irn, be_pos_Call_ptr);
752 be_emit_finish_line_gas(irn);
756 /** Emit an IncSP node */
757 static void emit_be_IncSP(const ir_node *irn)
759 int offs = -be_get_IncSP_offset(irn);
763 be_emit_cstring("\tsub ");
766 be_emit_cstring("\tadd ");
768 arm_emit_dest_register(irn, 0);
769 be_emit_cstring(", ");
770 arm_emit_source_register(irn, 0);
771 be_emit_irprintf(", #0x%X", offs);
773 /* omitted IncSP(0) */
776 be_emit_finish_line_gas(irn);
779 static void emit_be_Copy(const ir_node *irn)
781 ir_mode *mode = get_irn_mode(irn);
783 if (get_in_reg(irn, 0) == get_out_reg(irn, 0)) {
788 if (mode_is_float(mode)) {
789 if (USE_FPA(cg->isa)) {
790 be_emit_cstring("\tmvf");
793 arm_emit_dest_register(irn, 0);
794 be_emit_cstring(", ");
795 arm_emit_source_register(irn, 0);
796 be_emit_finish_line_gas(irn);
798 panic("emit_be_Copy: move not supported for this mode");
800 } else if (mode_is_data(mode)) {
801 be_emit_cstring("\tmov ");
802 arm_emit_dest_register(irn, 0);
803 be_emit_cstring(", ");
804 arm_emit_source_register(irn, 0);
805 be_emit_finish_line_gas(irn);
807 panic("emit_be_Copy: move not supported for this mode");
811 static void emit_be_Perm(const ir_node *irn)
813 be_emit_cstring("\teor ");
814 arm_emit_source_register(irn, 0);
815 be_emit_cstring(", ");
816 arm_emit_source_register(irn, 0);
817 be_emit_cstring(", ");
818 arm_emit_source_register(irn, 1);
819 be_emit_finish_line_gas(NULL);
821 be_emit_cstring("\teor ");
822 arm_emit_source_register(irn, 1);
823 be_emit_cstring(", ");
824 arm_emit_source_register(irn, 0);
825 be_emit_cstring(", ");
826 arm_emit_source_register(irn, 1);
827 be_emit_finish_line_gas(NULL);
829 be_emit_cstring("\teor ");
830 arm_emit_source_register(irn, 0);
831 be_emit_cstring(", ");
832 arm_emit_source_register(irn, 0);
833 be_emit_cstring(", ");
834 arm_emit_source_register(irn, 1);
835 be_emit_finish_line_gas(irn);
838 static void emit_be_MemPerm(const ir_node *node)
844 /* TODO: this implementation is slower than necessary.
845 The longterm goal is however to avoid the memperm node completely */
847 memperm_arity = be_get_MemPerm_entity_arity(node);
848 if (memperm_arity > 12)
849 panic("memperm with more than 12 inputs not supported yet");
851 for (i = 0; i < memperm_arity; ++i) {
853 ir_entity *entity = be_get_MemPerm_in_entity(node, i);
856 be_emit_irprintf("\tstr r%d, [sp, #-4]!", i);
857 be_emit_finish_line_gas(node);
859 /* load from entity */
860 offset = get_entity_offset(entity) + sp_change;
861 be_emit_irprintf("\tldr r%d, [sp, #%d]", i, offset);
862 be_emit_finish_line_gas(node);
865 for (i = memperm_arity-1; i >= 0; --i) {
867 ir_entity *entity = be_get_MemPerm_out_entity(node, i);
869 /* store to new entity */
870 offset = get_entity_offset(entity) + sp_change;
871 be_emit_irprintf("\tstr r%d, [sp, #%d]", i, offset);
872 be_emit_finish_line_gas(node);
873 /* restore register */
874 be_emit_irprintf("\tldr r%d, [sp], #4", i);
876 be_emit_finish_line_gas(node);
878 assert(sp_change == 0);
881 static void emit_be_Return(const ir_node *node)
883 be_emit_cstring("\tmov pc, lr");
884 be_emit_finish_line_gas(node);
888 static void emit_arm_Jmp(const ir_node *node)
890 ir_node *block, *next_block;
892 /* for now, the code works for scheduled and non-schedules blocks */
893 block = get_nodes_block(node);
895 /* we have a block schedule */
896 next_block = sched_next_block(block);
897 if (get_cfop_target_block(node) != next_block) {
898 be_emit_cstring("\tb ");
899 arm_emit_cfop_target(node);
901 be_emit_cstring("\t/* fallthrough to ");
902 arm_emit_cfop_target(node);
903 be_emit_cstring(" */");
905 be_emit_finish_line_gas(node);
908 static void emit_arm_fpaDbl2GP(const ir_node *irn)
910 be_emit_cstring("\tstfd ");
911 arm_emit_source_register(irn, 0);
912 be_emit_cstring(", [sp, #-8]!");
913 be_emit_pad_comment();
914 be_emit_cstring("/* Push fp to stack */");
915 be_emit_finish_line_gas(NULL);
917 be_emit_cstring("\tldmfd sp!, {");
918 arm_emit_dest_register(irn, 1);
919 be_emit_cstring(", ");
920 arm_emit_dest_register(irn, 0);
922 be_emit_pad_comment();
923 be_emit_cstring("/* Pop destination */");
924 be_emit_finish_line_gas(irn);
927 static void emit_arm_LdTls(const ir_node *irn)
930 panic("TLS not supported for this target");
931 /* Er... our gcc does not support it... Install a newer toolchain. */
934 static void emit_nothing(const ir_node *irn)
940 * The type of a emitter function.
942 typedef void (emit_func)(const ir_node *irn);
945 * Set a node emitter. Make it a bit more type safe.
947 static inline void set_emitter(ir_op *op, emit_func arm_emit_node)
949 op->ops.generic = (op_func)arm_emit_node;
953 * Enters the emitter functions for handled nodes into the generic
954 * pointer of an opcode.
956 static void arm_register_emitters(void)
958 /* first clear the generic function pointer for all ops */
959 clear_irp_opcodes_generic_func();
961 /* register all emitter functions defined in spec */
962 arm_register_spec_emitters();
965 set_emitter(op_arm_B, emit_arm_B);
966 set_emitter(op_arm_CopyB, emit_arm_CopyB);
967 set_emitter(op_arm_fpaConst, emit_arm_fpaConst);
968 set_emitter(op_arm_fpaDbl2GP, emit_arm_fpaDbl2GP);
969 set_emitter(op_arm_FrameAddr, emit_arm_FrameAddr);
970 set_emitter(op_arm_Jmp, emit_arm_Jmp);
971 set_emitter(op_arm_LdTls, emit_arm_LdTls);
972 set_emitter(op_arm_SwitchJmp, emit_arm_SwitchJmp);
973 set_emitter(op_arm_SymConst, emit_arm_SymConst);
974 set_emitter(op_be_Call, emit_be_Call);
975 set_emitter(op_be_Copy, emit_be_Copy);
976 set_emitter(op_be_CopyKeep, emit_be_Copy);
977 set_emitter(op_be_IncSP, emit_be_IncSP);
978 set_emitter(op_be_MemPerm, emit_be_MemPerm);
979 set_emitter(op_be_Perm, emit_be_Perm);
980 set_emitter(op_be_Return, emit_be_Return);
982 /* no need to emit anything for the following nodes */
983 set_emitter(op_Phi, emit_nothing);
984 set_emitter(op_be_Keep, emit_nothing);
985 set_emitter(op_be_Start, emit_nothing);
986 set_emitter(op_be_Barrier, emit_nothing);
990 * Emits code for a node.
992 static void arm_emit_node(const ir_node *irn)
994 ir_op *op = get_irn_op(irn);
996 if (op->ops.generic) {
997 emit_func *emit = (emit_func *)op->ops.generic;
998 be_dbg_set_dbg_info(get_irn_dbg_info(irn));
1001 panic("Error: No emit handler for node %+F (graph %+F)\n",
1002 irn, current_ir_graph);
1007 * emit the block label if needed.
1009 static void arm_emit_block_header(ir_node *block, ir_node *prev)
1014 ir_exec_freq *exec_freq = be_get_irg_exec_freq(cg->irg);
1017 n_cfgpreds = get_Block_n_cfgpreds(block);
1018 if (n_cfgpreds == 1) {
1019 ir_node *pred = get_Block_cfgpred(block, 0);
1020 ir_node *pred_block = get_nodes_block(pred);
1022 /* we don't need labels for fallthrough blocks, however switch-jmps
1023 * are no fallthroughs */
1024 if (pred_block == prev &&
1025 !(is_Proj(pred) && is_arm_SwitchJmp(get_Proj_pred(pred)))) {
1035 be_gas_emit_block_name(block);
1038 be_emit_pad_comment();
1039 be_emit_cstring(" /* preds:");
1041 /* emit list of pred blocks in comment */
1042 arity = get_irn_arity(block);
1043 for (i = 0; i < arity; ++i) {
1044 ir_node *predblock = get_Block_cfgpred_block(block, i);
1045 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1048 be_emit_cstring("\t/* ");
1049 be_gas_emit_block_name(block);
1050 be_emit_cstring(": ");
1052 if (exec_freq != NULL) {
1053 be_emit_irprintf(" freq: %f",
1054 get_block_execfreq(exec_freq, block));
1056 be_emit_cstring(" */\n");
1057 be_emit_write_line();
1061 * Walks over the nodes in a block connected by scheduling edges
1062 * and emits code for each node.
1064 static void arm_gen_block(ir_node *block, ir_node *prev_block)
1068 arm_emit_block_header(block, prev_block);
1069 be_dbg_set_dbg_info(get_irn_dbg_info(block));
1070 sched_foreach(block, irn) {
1077 * Sets labels for control flow nodes (jump target)
1079 static void arm_gen_labels(ir_node *block, void *env)
1082 int n = get_Block_n_cfgpreds(block);
1085 for (n--; n >= 0; n--) {
1086 pred = get_Block_cfgpred(block, n);
1087 set_irn_link(pred, block);
1092 * Compare two entries of the symbol or tarval set.
1094 static int cmp_sym_or_tv(const void *elt, const void *key, size_t size)
1096 const sym_or_tv_t *p1 = elt;
1097 const sym_or_tv_t *p2 = key;
1100 /* as an identifier NEVER can point to a tarval, it's enough
1101 to compare it this way */
1102 return p1->u.generic != p2->u.generic;
1106 * Main driver. Emits the code for one routine.
1108 void arm_gen_routine(const arm_code_gen_t *arm_cg, ir_graph *irg)
1110 ir_node **blk_sched;
1112 ir_node *last_block = NULL;
1113 ir_entity *entity = get_irg_entity(irg);
1116 sym_or_tv = new_set(cmp_sym_or_tv, 8);
1118 be_gas_elf_type_char = '%';
1120 arm_register_emitters();
1122 be_dbg_method_begin(entity);
1124 /* create the block schedule */
1125 blk_sched = be_create_block_schedule(irg);
1127 be_gas_emit_function_prolog(entity, 4);
1129 irg_block_walk_graph(irg, arm_gen_labels, NULL, NULL);
1131 n = ARR_LEN(blk_sched);
1132 for (i = 0; i < n;) {
1133 ir_node *block, *next_bl;
1135 block = blk_sched[i];
1137 next_bl = i < n ? blk_sched[i] : NULL;
1139 /* set here the link. the emitter expects to find the next block here */
1140 set_irn_link(block, next_bl);
1141 arm_gen_block(block, last_block);
1145 be_gas_emit_function_epilog(entity);
1146 be_dbg_method_end();
1148 /* emit SymConst values */
1149 if (set_count(sym_or_tv) > 0) {
1152 be_emit_cstring("\t.align 2\n");
1154 foreach_set(sym_or_tv, entry) {
1155 be_emit_irprintf("%s%u:\n", be_gas_get_private_prefix(),
1158 if (entry->is_entity) {
1159 be_emit_cstring("\t.word\t");
1160 be_gas_emit_entity(entry->u.entity);
1162 be_emit_write_line();
1164 tarval *tv = entry->u.tv;
1165 int i, size = get_mode_size_bytes(get_tarval_mode(tv));
1168 /* beware: ARM fpa uses big endian format */
1169 for (i = ((size + 3) & ~3) - 4; i >= 0; i -= 4) {
1171 v = get_tarval_sub_bits(tv, i+3);
1172 v = (v << 8) | get_tarval_sub_bits(tv, i+2);
1173 v = (v << 8) | get_tarval_sub_bits(tv, i+1);
1174 v = (v << 8) | get_tarval_sub_bits(tv, i+0);
1175 be_emit_irprintf("\t.word\t%u\n", v);
1176 be_emit_write_line();
1181 be_emit_write_line();
1186 void arm_init_emitter(void)
1188 FIRM_DBG_REGISTER(dbg, "firm.be.arm.emit");