2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
43 #include "raw_bitset.h"
46 #include "../besched.h"
47 #include "../beblocksched.h"
48 #include "../beirg_t.h"
49 #include "../begnuas.h"
50 #include "../be_dbgout.h"
52 #include "arm_emitter.h"
53 #include "arm_optimize.h"
54 #include "gen_arm_emitter.h"
55 #include "arm_nodes_attr.h"
56 #include "arm_new_nodes.h"
57 #include "arm_map_regs.h"
58 #include "gen_arm_regalloc_if.h"
60 #include "../benode_t.h"
62 #define BLOCK_PREFIX ".L"
64 #define SNPRINTF_BUF_LEN 128
66 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
68 static const arm_code_gen_t *cg;
69 static const arm_isa_t *isa;
70 static set *sym_or_tv;
73 * Returns the register at in position pos.
75 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
77 const arch_register_t *reg = NULL;
79 assert(get_irn_arity(irn) > pos && "Invalid IN position");
81 /* The out register of the operator at position pos is the
82 in register we need. */
83 op = get_irn_n(irn, pos);
85 reg = arch_get_irn_register(op);
87 assert(reg && "no in register found");
89 /* in case of a joker register: just return a valid register */
90 if (arch_register_type_is(reg, joker)) {
91 const arch_register_req_t *req = arch_get_register_req(irn, pos);
93 if (arch_register_req_is(req, limited)) {
94 /* in case of limited requirements: get the first allowed register */
95 unsigned idx = rbitset_next(req->limited, 0, 1);
96 reg = arch_register_for_index(req->cls, idx);
98 /* otherwise get first register in class */
99 reg = arch_register_for_index(req->cls, 0);
107 * Returns the register at out position pos.
109 static const arch_register_t *get_out_reg(const ir_node *node, int pos)
112 const arch_register_t *reg = NULL;
114 /* 1st case: irn is not of mode_T, so it has only */
115 /* one OUT register -> good */
116 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
117 /* Proj with the corresponding projnum for the register */
119 if (get_irn_mode(node) != mode_T) {
120 reg = arch_get_irn_register(node);
121 } else if (is_arm_irn(node)) {
122 reg = get_arm_out_reg(node, pos);
124 const ir_edge_t *edge;
126 foreach_out_edge(node, edge) {
127 proj = get_edge_src_irn(edge);
128 assert(is_Proj(proj) && "non-Proj from mode_T node");
129 if (get_Proj_proj(proj) == pos) {
130 reg = arch_get_irn_register(proj);
136 assert(reg && "no out register found");
140 /*************************************************************
142 * (_) | | / _| | | | |
143 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
144 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
145 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
146 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
149 *************************************************************/
152 * Emit the name of the source register at given input position.
154 void arm_emit_source_register(const ir_node *node, int pos) {
155 const arch_register_t *reg = get_in_reg(node, pos);
156 be_emit_string(arch_register_get_name(reg));
160 * Emit the name of the destination register at given output position.
162 void arm_emit_dest_register(const ir_node *node, int pos) {
163 const arch_register_t *reg = get_out_reg(node, pos);
164 be_emit_string(arch_register_get_name(reg));
168 * Emit a node's offset.
170 void arm_emit_offset(const ir_node *node) {
172 ir_opcode opc = get_irn_opcode(node);
174 if (opc == beo_Reload || opc == beo_Spill) {
175 ir_entity *ent = be_get_frame_entity(node);
176 offset = get_entity_offset(ent);
178 assert(!"unimplemented arm_emit_offset for this node type");
179 panic("unimplemented arm_emit_offset for this node type");
181 be_emit_irprintf("%d", offset);
185 * Emit the arm fpa instruction suffix depending on the mode.
187 static void arm_emit_fpa_postfix(const ir_mode *mode) {
188 int bits = get_mode_size_bits(mode);
199 * Emit the instruction suffix depending on the mode.
201 void arm_emit_mode(const ir_node *node) {
204 if (is_arm_irn(node)) {
205 const arm_attr_t *attr = get_arm_attr_const(node);
206 mode = attr->op_mode ? attr->op_mode : get_irn_mode(node);
208 mode = get_irn_mode(node);
210 arm_emit_fpa_postfix(mode);
214 * Emit a const or SymConst value.
216 void arm_emit_immediate(const ir_node *node) {
217 const arm_attr_t *attr = get_arm_attr_const(node);
219 if (ARM_GET_SHF_MOD(attr) == ARM_SHF_IMM) {
220 be_emit_irprintf("#0x%X", arm_decode_imm_w_shift(get_arm_imm_value(node)));
221 } else if (ARM_GET_FPA_IMM(attr)) {
222 be_emit_irprintf("#%s", arm_get_fpa_imm_name(get_arm_imm_value(node)));
223 } else if (is_arm_SymConst(node))
224 be_emit_ident(get_arm_symconst_id(node));
226 assert(!"not a Constant");
231 * Returns the tarval or offset of an arm node as a string.
233 void arm_emit_shift(const ir_node *node) {
234 arm_shift_modifier mod;
236 mod = get_arm_shift_modifier(node);
237 if (ARM_HAS_SHIFT(mod)) {
238 int v = get_arm_imm_value(node);
240 be_emit_irprintf(", %s #%d", arm_shf_mod_name(mod), v);
244 /** An entry in the sym_or_tv set. */
245 typedef struct sym_or_tv_t {
247 ident *id; /**< An ident. */
248 tarval *tv; /**< A tarval. */
249 const void *generic; /**< For generic compare. */
251 unsigned label; /**< the associated label. */
252 char is_ident; /**< Non-zero if an ident is stored. */
256 * Returns a unique label. This number will not be used a second time.
258 static unsigned get_unique_label(void) {
259 static unsigned id = 0;
266 static void emit_arm_SymConst(const ir_node *irn) {
267 sym_or_tv_t key, *entry;
270 key.u.id = get_arm_symconst_id(irn);
273 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
274 if (entry->label == 0) {
275 /* allocate a label */
276 entry->label = get_unique_label();
278 label = entry->label;
280 /* load the symbol indirect */
281 be_emit_cstring("\tldr ");
282 arm_emit_dest_register(irn, 0);
283 be_emit_irprintf(", .L%u", label);
284 be_emit_finish_line_gas(irn);
288 * Emit a floating point fpa constant.
290 static void emit_arm_fpaConst(const ir_node *irn) {
291 sym_or_tv_t key, *entry;
295 key.u.tv = get_fpaConst_value(irn);
298 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
299 if (entry->label == 0) {
300 /* allocate a label */
301 entry->label = get_unique_label();
303 label = entry->label;
305 /* load the tarval indirect */
306 mode = get_irn_mode(irn);
307 be_emit_cstring("\tldf");
308 arm_emit_fpa_postfix(mode);
311 arm_emit_dest_register(irn, 0);
312 be_emit_irprintf(", .L%u", label);
313 be_emit_finish_line_gas(irn);
317 * Returns the next block in a block schedule.
319 static ir_node *sched_next_block(const ir_node *block) {
320 return get_irn_link(block);
324 * Returns the target block for a control flow node.
326 static ir_node *get_cfop_target_block(const ir_node *irn) {
327 return get_irn_link(irn);
331 * Emits a block label for the given block.
333 static void arm_emit_block_name(const ir_node *block) {
334 if (has_Block_label(block)) {
335 be_emit_string(be_gas_block_label_prefix());
336 be_emit_irprintf("%lu", get_Block_label(block));
338 be_emit_cstring(BLOCK_PREFIX);
339 be_emit_irprintf("%d", get_irn_node_nr(block));
344 * Emit the target label for a control flow node.
346 static void arm_emit_cfop_target(const ir_node *irn) {
347 ir_node *block = get_cfop_target_block(irn);
349 arm_emit_block_name(block);
353 * Emit a Compare with conditional branch.
355 static void emit_arm_CmpBra(const ir_node *irn) {
356 const ir_edge_t *edge;
357 const ir_node *proj_true = NULL;
358 const ir_node *proj_false = NULL;
359 const ir_node *block;
360 const ir_node *next_block;
361 ir_node *op1 = get_irn_n(irn, 0);
362 ir_mode *opmode = get_irn_mode(op1);
364 int proj_num = get_arm_CondJmp_proj_num(irn);
366 foreach_out_edge(irn, edge) {
367 ir_node *proj = get_edge_src_irn(edge);
368 long nr = get_Proj_proj(proj);
369 if (nr == pn_Cond_true) {
376 /* for now, the code works for scheduled and non-schedules blocks */
377 block = get_nodes_block(irn);
379 /* we have a block schedule */
380 next_block = sched_next_block(block);
382 if (proj_num == pn_Cmp_False) {
383 /* always false: should not happen */
384 be_emit_cstring("\tb ");
385 arm_emit_cfop_target(proj_false);
386 be_emit_finish_line_gas(proj_false);
387 } else if (proj_num == pn_Cmp_True) {
388 /* always true: should not happen */
389 be_emit_cstring("\tb ");
390 arm_emit_cfop_target(proj_true);
391 be_emit_finish_line_gas(proj_true);
393 if (mode_is_float(opmode)) {
394 suffix = "ICHWILLIMPLEMENTIERTWERDEN";
396 be_emit_cstring("\tfcmp ");
397 arm_emit_source_register(irn, 0);
398 be_emit_cstring(", ");
399 arm_emit_source_register(irn, 1);
400 be_emit_finish_line_gas(irn);
402 be_emit_cstring("\tfmstat");
403 be_emit_pad_comment();
404 be_emit_cstring("/* FCSPR -> CPSR */");
405 be_emit_finish_line_gas(NULL);
407 if (get_cfop_target_block(proj_true) == next_block) {
408 /* exchange both proj's so the second one can be omitted */
409 const ir_node *t = proj_true;
411 proj_true = proj_false;
413 proj_num = get_negated_pnc(proj_num, mode_Iu);
416 case pn_Cmp_Eq: suffix = "eq"; break;
417 case pn_Cmp_Lt: suffix = "lt"; break;
418 case pn_Cmp_Le: suffix = "le"; break;
419 case pn_Cmp_Gt: suffix = "gt"; break;
420 case pn_Cmp_Ge: suffix = "ge"; break;
421 case pn_Cmp_Lg: suffix = "ne"; break;
422 case pn_Cmp_Leg: suffix = "al"; break;
423 default: assert(!"Cmp unsupported"); suffix = "al";
425 be_emit_cstring("\tcmp ");
426 arm_emit_source_register(irn, 0);
427 be_emit_cstring(", ");
428 arm_emit_source_register(irn, 1);
429 be_emit_finish_line_gas(irn);
432 /* emit the true proj */
433 be_emit_irprintf("\tb%s ", suffix);
434 arm_emit_cfop_target(proj_true);
435 be_emit_finish_line_gas(proj_true);
437 if (get_cfop_target_block(proj_false) == next_block) {
438 be_emit_cstring("\t/* fallthrough to ");
439 arm_emit_cfop_target(proj_false);
440 be_emit_cstring(" */");
441 be_emit_finish_line_gas(proj_false);
443 be_emit_cstring("b ");
444 arm_emit_cfop_target(proj_false);
445 be_emit_finish_line_gas(proj_false);
452 * Emit a Tst with conditional branch.
454 static void emit_arm_TstBra(const ir_node *irn)
456 const ir_edge_t *edge;
457 const ir_node *proj_true = NULL;
458 const ir_node *proj_false = NULL;
459 const ir_node *block;
460 const ir_node *next_block;
462 int proj_num = get_arm_CondJmp_proj_num(irn);
464 foreach_out_edge(irn, edge) {
465 ir_node *proj = get_edge_src_irn(edge);
466 long nr = get_Proj_proj(proj);
467 if (nr == pn_Cond_true) {
474 /* for now, the code works for scheduled and non-schedules blocks */
475 block = get_nodes_block(irn);
477 /* we have a block schedule */
478 next_block = sched_next_block(block);
480 assert(proj_num != pn_Cmp_False);
481 assert(proj_num != pn_Cmp_True);
483 if (get_cfop_target_block(proj_true) == next_block) {
484 /* exchange both proj's so the second one can be omitted */
485 const ir_node *t = proj_true;
487 proj_true = proj_false;
489 proj_num = get_negated_pnc(proj_num, mode_Iu);
492 case pn_Cmp_Eq: suffix = "eq"; break;
493 case pn_Cmp_Lt: suffix = "lt"; break;
494 case pn_Cmp_Le: suffix = "le"; break;
495 case pn_Cmp_Gt: suffix = "gt"; break;
496 case pn_Cmp_Ge: suffix = "ge"; break;
497 case pn_Cmp_Lg: suffix = "ne"; break;
498 case pn_Cmp_Leg: suffix = "al"; break;
499 default: assert(!"Cmp unsupported"); suffix = "al";
501 be_emit_cstring("\ttst ");
502 arm_emit_source_register(irn, 0);
503 be_emit_cstring(", ");
504 arm_emit_source_register(irn, 1);
505 be_emit_finish_line_gas(irn);
507 /* emit the true proj */
508 be_emit_irprintf("\tb%s ", suffix);
509 arm_emit_cfop_target(proj_true);
510 be_emit_finish_line_gas(proj_true);
512 if (get_cfop_target_block(proj_false) == next_block) {
513 be_emit_cstring("\t/* fallthrough to ");
514 arm_emit_cfop_target(proj_false);
515 be_emit_cstring(" */");
516 be_emit_finish_line_gas(proj_false);
518 be_emit_cstring("b ");
519 arm_emit_cfop_target(proj_false);
520 be_emit_finish_line_gas(proj_false);
525 * Emit a Compare with conditional branch.
527 static void emit_arm_fpaCmfBra(const ir_node *irn) {
532 * Emit a Compare with conditional branch.
534 static void emit_arm_fpaCmfeBra(const ir_node *irn) {
538 /** Sort register in ascending order. */
539 static int reg_cmp(const void *a, const void *b) {
540 const arch_register_t * const *ra = a;
541 const arch_register_t * const *rb = b;
543 return *ra < *rb ? -1 : (*ra != *rb);
547 * Create the CopyB instruction sequence.
549 static void emit_arm_CopyB(const ir_node *irn) {
550 unsigned size = (unsigned)get_arm_imm_value(irn);
552 const char *tgt = arch_register_get_name(get_in_reg(irn, 0));
553 const char *src = arch_register_get_name(get_in_reg(irn, 1));
554 const char *t0, *t1, *t2, *t3;
556 const arch_register_t *tmpregs[4];
558 /* collect the temporary registers and sort them, we need ascending order */
559 tmpregs[0] = get_in_reg(irn, 2);
560 tmpregs[1] = get_in_reg(irn, 3);
561 tmpregs[2] = get_in_reg(irn, 4);
562 tmpregs[3] = &arm_gp_regs[REG_R12];
564 /* Note: R12 is always the last register because the RA did not assign higher ones */
565 qsort((void *)tmpregs, 3, sizeof(tmpregs[0]), reg_cmp);
567 /* need ascending order */
568 t0 = arch_register_get_name(tmpregs[0]);
569 t1 = arch_register_get_name(tmpregs[1]);
570 t2 = arch_register_get_name(tmpregs[2]);
571 t3 = arch_register_get_name(tmpregs[3]);
573 be_emit_cstring("/* MemCopy (");
575 be_emit_cstring(")->(");
576 arm_emit_source_register(irn, 0);
577 be_emit_irprintf(" [%u bytes], Uses ", size);
579 be_emit_cstring(", ");
581 be_emit_cstring(", ");
583 be_emit_cstring(", and ");
585 be_emit_cstring("*/");
586 be_emit_finish_line_gas(NULL);
588 assert(size > 0 && "CopyB needs size > 0" );
591 assert(!"strange hack enabled: copy more bytes than needed!");
600 be_emit_cstring("\tldr ");
602 be_emit_cstring(", [");
604 be_emit_cstring(", #0]");
605 be_emit_finish_line_gas(NULL);
607 be_emit_cstring("\tstr ");
609 be_emit_cstring(", [");
611 be_emit_cstring(", #0]");
612 be_emit_finish_line_gas(irn);
615 be_emit_cstring("\tldmia ");
617 be_emit_cstring("!, {");
619 be_emit_cstring(", ");
622 be_emit_finish_line_gas(NULL);
624 be_emit_cstring("\tstmia ");
626 be_emit_cstring("!, {");
628 be_emit_cstring(", ");
631 be_emit_finish_line_gas(irn);
634 be_emit_cstring("\tldmia ");
636 be_emit_cstring("!, {");
638 be_emit_cstring(", ");
640 be_emit_cstring(", ");
643 be_emit_finish_line_gas(NULL);
645 be_emit_cstring("\tstmia ");
647 be_emit_cstring("!, {");
649 be_emit_cstring(", ");
651 be_emit_cstring(", ");
654 be_emit_finish_line_gas(irn);
659 be_emit_cstring("\tldmia ");
661 be_emit_cstring("!, {");
663 be_emit_cstring(", ");
665 be_emit_cstring(", ");
667 be_emit_cstring(", ");
670 be_emit_finish_line_gas(NULL);
672 be_emit_cstring("\tstmia ");
674 be_emit_cstring("!, {");
676 be_emit_cstring(", ");
678 be_emit_cstring(", ");
680 be_emit_cstring(", ");
683 be_emit_finish_line_gas(irn);
688 static void emit_arm_SwitchJmp(const ir_node *irn) {
689 const ir_edge_t *edge;
695 ir_node *default_proj = NULL;
697 block_nr = get_irn_node_nr(irn);
698 n_projs = get_arm_SwitchJmp_n_projs(irn);
700 projs = XMALLOCNZ(ir_node*, n_projs);
702 foreach_out_edge(irn, edge) {
703 proj = get_edge_src_irn(edge);
704 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
706 if (get_Proj_proj(proj) == get_arm_SwitchJmp_default_proj_num(irn))
709 projs[get_Proj_proj(proj)] = proj;
711 assert(default_proj != NULL && "SwitchJmp should have a Default Proj");
718 be_emit_cstring("\tcmp ");
719 arm_emit_source_register(irn, 0);
720 be_emit_irprintf(", #%u", n_projs - 1);
721 be_emit_finish_line_gas(irn);
723 be_emit_cstring("\tbhi ");
724 arm_emit_cfop_target(default_proj);
725 be_emit_finish_line_gas(default_proj);
728 LDR %r12, .TABLE_X_START
729 ADD %r12, %r12, [%1S, LSL #2]
733 be_emit_irprintf("\tldr %%r12, TABLE_%d_START", block_nr);
734 be_emit_finish_line_gas(NULL);
736 be_emit_irprintf("\tadd %%r12, %%r12, ");
737 arm_emit_source_register(irn, 0);
738 be_emit_cstring(", LSL #2");
739 be_emit_finish_line_gas(NULL);
741 be_emit_cstring("\tldr %r15, [%r12, #0]");
742 be_emit_finish_line_gas(NULL);
744 be_emit_irprintf("TABLE_%d_START:\n\t.word\tTABLE_%d", block_nr, block_nr);
745 be_emit_finish_line_gas(NULL);
746 be_emit_irprintf("\t.align 2");
747 be_emit_finish_line_gas(NULL);
748 be_emit_irprintf("TABLE_%d:", block_nr);
749 be_emit_finish_line_gas(NULL);
751 for (i = 0; i < n_projs; ++i) {
754 proj = projs[get_arm_SwitchJmp_default_proj_num(irn)];
756 be_emit_cstring("\t.word\t");
757 arm_emit_cfop_target(proj);
758 be_emit_finish_line_gas(proj);
760 be_emit_irprintf("\t.align 2\n");
761 be_emit_finish_line_gas(NULL);
765 /************************************************************************/
767 /************************************************************************/
769 static void emit_be_Call(const ir_node *irn) {
770 ir_entity *ent = be_Call_get_entity(irn);
772 be_emit_cstring("\tbl ");
774 set_entity_backend_marked(ent, 1);
775 be_emit_ident(get_entity_ld_ident(ent));
777 arm_emit_source_register(irn, be_pos_Call_ptr);
779 be_emit_finish_line_gas(irn);
782 /** Emit an IncSP node */
783 static void emit_be_IncSP(const ir_node *irn) {
784 int offs = -be_get_IncSP_offset(irn);
788 be_emit_cstring("\tsub ");
791 be_emit_cstring("\tadd ");
793 arm_emit_dest_register(irn, 0);
794 be_emit_cstring(", ");
795 arm_emit_source_register(irn, 0);
796 be_emit_irprintf(", #0x%X", offs);
798 /* omitted IncSP(0) */
801 be_emit_finish_line_gas(irn);
804 static void emit_be_Copy(const ir_node *irn) {
805 ir_mode *mode = get_irn_mode(irn);
807 if (get_in_reg(irn, 0) == get_out_reg(irn, 0)) {
812 if (mode_is_float(mode)) {
814 be_emit_cstring("\tmvf");
817 arm_emit_dest_register(irn, 0);
818 be_emit_cstring(", ");
819 arm_emit_source_register(irn, 0);
820 be_emit_finish_line_gas(irn);
822 assert(0 && "move not supported for this mode");
823 panic("emit_be_Copy: move not supported for this mode");
825 } else if (mode_is_data(mode)) {
826 be_emit_cstring("\tmov ");
827 arm_emit_dest_register(irn, 0);
828 be_emit_cstring(", ");
829 arm_emit_source_register(irn, 0);
830 be_emit_finish_line_gas(irn);
832 assert(0 && "move not supported for this mode");
833 panic("emit_be_Copy: move not supported for this mode");
838 * Emit code for a Spill.
840 static void emit_be_Spill(const ir_node *irn) {
841 ir_mode *mode = get_irn_mode(be_get_Spill_val(irn));
843 if (mode_is_float(mode)) {
844 if (USE_FPA(cg->isa)) {
845 be_emit_cstring("\tstf");
846 arm_emit_fpa_postfix(mode);
849 assert(0 && "spill not supported for this mode");
850 panic("emit_be_Spill: spill not supported for this mode");
852 } else if (mode_is_dataM(mode)) {
853 be_emit_cstring("\tstr ");
855 assert(0 && "spill not supported for this mode");
856 panic("emit_be_Spill: spill not supported for this mode");
858 arm_emit_source_register(irn, 1);
859 be_emit_cstring(", [");
860 arm_emit_source_register(irn, 0);
861 be_emit_cstring(", #");
862 arm_emit_offset(irn);
864 be_emit_finish_line_gas(irn);
868 * Emit code for a Reload.
870 static void emit_be_Reload(const ir_node *irn) {
871 ir_mode *mode = get_irn_mode(irn);
873 if (mode_is_float(mode)) {
874 if (USE_FPA(cg->isa)) {
875 be_emit_cstring("\tldf");
876 arm_emit_fpa_postfix(mode);
879 assert(0 && "reload not supported for this mode");
880 panic("emit_be_Reload: reload not supported for this mode");
882 } else if (mode_is_dataM(mode)) {
883 be_emit_cstring("\tldr ");
885 assert(0 && "reload not supported for this mode");
886 panic("emit_be_Reload: reload not supported for this mode");
888 arm_emit_dest_register(irn, 0);
889 be_emit_cstring(", [");
890 arm_emit_source_register(irn, 0);
891 be_emit_cstring(", #");
892 arm_emit_offset(irn);
894 be_emit_finish_line_gas(irn);
897 static void emit_be_Perm(const ir_node *irn) {
898 be_emit_cstring("\teor ");
899 arm_emit_source_register(irn, 0);
900 be_emit_cstring(", ");
901 arm_emit_source_register(irn, 0);
902 be_emit_cstring(", ");
903 arm_emit_source_register(irn, 1);
904 be_emit_finish_line_gas(NULL);
906 be_emit_cstring("\teor ");
907 arm_emit_source_register(irn, 1);
908 be_emit_cstring(", ");
909 arm_emit_source_register(irn, 0);
910 be_emit_cstring(", ");
911 arm_emit_source_register(irn, 1);
912 be_emit_finish_line_gas(NULL);
914 be_emit_cstring("\teor ");
915 arm_emit_source_register(irn, 0);
916 be_emit_cstring(", ");
917 arm_emit_source_register(irn, 0);
918 be_emit_cstring(", ");
919 arm_emit_source_register(irn, 1);
920 be_emit_finish_line_gas(irn);
923 /************************************************************************/
925 /************************************************************************/
927 static void emit_Jmp(const ir_node *node) {
928 ir_node *block, *next_block;
930 /* for now, the code works for scheduled and non-schedules blocks */
931 block = get_nodes_block(node);
933 /* we have a block schedule */
934 next_block = sched_next_block(block);
935 if (get_cfop_target_block(node) != next_block) {
936 be_emit_cstring("\tb ");
937 arm_emit_cfop_target(node);
939 be_emit_cstring("\t/* fallthrough to ");
940 arm_emit_cfop_target(node);
941 be_emit_cstring(" */");
943 be_emit_finish_line_gas(node);
946 static void emit_arm_fpaDbl2GP(const ir_node *irn) {
947 be_emit_cstring("\tstfd ");
948 arm_emit_source_register(irn, 0);
949 be_emit_cstring(", [sp, #-8]!");
950 be_emit_pad_comment();
951 be_emit_cstring("/* Push fp to stack */");
952 be_emit_finish_line_gas(NULL);
954 be_emit_cstring("\tldmfd sp!, {");
955 arm_emit_dest_register(irn, 1);
956 be_emit_cstring(", ");
957 arm_emit_dest_register(irn, 0);
959 be_emit_pad_comment();
960 be_emit_cstring("/* Pop destination */");
961 be_emit_finish_line_gas(irn);
964 static void emit_arm_LdTls(const ir_node *irn) {
966 panic("TLS not supported for this target");
967 /* Er... our gcc does not support it... Install a newer toolchain. */
970 /***********************************************************************************
973 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
974 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
975 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
976 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
978 ***********************************************************************************/
980 static void emit_silence(const ir_node *irn) {
986 * The type of a emitter function.
988 typedef void (emit_func)(const ir_node *irn);
991 * Set a node emitter. Make it a bit more type safe.
993 static INLINE void set_emitter(ir_op *op, emit_func arm_emit_node) {
994 op->ops.generic = (op_func)arm_emit_node;
998 * Enters the emitter functions for handled nodes into the generic
999 * pointer of an opcode.
1001 static void arm_register_emitters(void) {
1003 #define ARM_EMIT(a) set_emitter(op_arm_##a, emit_arm_##a)
1004 #define EMIT(a) set_emitter(op_##a, emit_##a)
1005 #define BE_EMIT(a) set_emitter(op_be_##a, emit_be_##a)
1006 #define SILENCE(a) set_emitter(op_##a, emit_silence)
1008 /* first clear the generic function pointer for all ops */
1009 clear_irp_opcodes_generic_func();
1011 /* register all emitter functions defined in spec */
1012 arm_register_spec_emitters();
1014 /* other emitter functions */
1017 ARM_EMIT(fpaCmfBra);
1018 ARM_EMIT(fpaCmfeBra);
1020 // ARM_EMIT(CopyB_i);
1023 ARM_EMIT(SwitchJmp);
1024 ARM_EMIT(fpaDbl2GP);
1028 /* benode emitter */
1045 SILENCE(be_CopyKeep);
1046 SILENCE(be_RegParams);
1047 SILENCE(be_Barrier);
1058 * Emits code for a node.
1060 static void arm_emit_node(const ir_node *irn) {
1061 ir_op *op = get_irn_op(irn);
1063 if (op->ops.generic) {
1064 emit_func *emit = (emit_func *)op->ops.generic;
1065 be_dbg_set_dbg_info(get_irn_dbg_info(irn));
1068 be_emit_cstring("\t/* TODO */");
1069 be_emit_finish_line_gas(irn);
1074 * emit the block label if needed.
1076 static void arm_emit_block_header(ir_node *block, ir_node *prev)
1081 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1084 n_cfgpreds = get_Block_n_cfgpreds(block);
1085 if (n_cfgpreds == 1) {
1086 ir_node *pred = get_Block_cfgpred(block, 0);
1087 ir_node *pred_block = get_nodes_block(pred);
1089 /* we don't need labels for fallthrough blocks, however switch-jmps
1090 * are no fallthroughs */
1091 if (pred_block == prev &&
1092 !(is_Proj(pred) && is_arm_SwitchJmp(get_Proj_pred(pred)))) {
1102 arm_emit_block_name(block);
1105 be_emit_pad_comment();
1106 be_emit_cstring(" /* preds:");
1108 /* emit list of pred blocks in comment */
1109 arity = get_irn_arity(block);
1110 for (i = 0; i < arity; ++i) {
1111 ir_node *predblock = get_Block_cfgpred_block(block, i);
1112 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1115 be_emit_cstring("\t/* ");
1116 arm_emit_block_name(block);
1117 be_emit_cstring(": ");
1119 if (exec_freq != NULL) {
1120 be_emit_irprintf(" freq: %f",
1121 get_block_execfreq(exec_freq, block));
1123 be_emit_cstring(" */\n");
1124 be_emit_write_line();
1128 * Walks over the nodes in a block connected by scheduling edges
1129 * and emits code for each node.
1131 static void arm_gen_block(ir_node *block, ir_node *prev_block) {
1134 arm_emit_block_header(block, prev_block);
1135 be_dbg_set_dbg_info(get_irn_dbg_info(block));
1136 sched_foreach(block, irn) {
1142 * Emits code for function start.
1144 void arm_func_prolog(ir_graph *irg) {
1145 ir_entity *ent = get_irg_entity(irg);
1146 const char *irg_name = get_entity_ld_name(ent);
1148 be_emit_write_line();
1149 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1150 be_emit_cstring("\t.align 2\n");
1152 if (get_entity_visibility(ent) == visibility_external_visible)
1153 be_emit_irprintf("\t.global %s\n", irg_name);
1154 be_emit_irprintf("%s:\n", irg_name);
1158 * Emits code for function end
1160 void arm_emit_end(FILE *F, ir_graph *irg) {
1162 fprintf(F, "\t.ident \"firmcc\"\n");
1167 * Sets labels for control flow nodes (jump target)
1169 static void arm_gen_labels(ir_node *block, void *env) {
1171 int n = get_Block_n_cfgpreds(block);
1174 for (n--; n >= 0; n--) {
1175 pred = get_Block_cfgpred(block, n);
1176 set_irn_link(pred, block);
1181 * Compare two entries of the symbol or tarval set.
1183 static int cmp_sym_or_tv(const void *elt, const void *key, size_t size) {
1184 const sym_or_tv_t *p1 = elt;
1185 const sym_or_tv_t *p2 = key;
1188 /* as an identifier NEVER can point to a tarval, it's enough
1189 to compare it this way */
1190 return p1->u.generic != p2->u.generic;
1194 * Main driver. Emits the code for one routine.
1196 void arm_gen_routine(const arm_code_gen_t *arm_cg, ir_graph *irg) {
1197 ir_node **blk_sched;
1199 ir_node *last_block = NULL;
1200 ir_entity *entity = get_irg_entity(irg);
1204 sym_or_tv = new_set(cmp_sym_or_tv, 8);
1206 arm_register_emitters();
1208 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
1210 /* create the block schedule. For now, we don't need it earlier. */
1211 blk_sched = be_create_block_schedule(cg->irg, cg->birg->exec_freq);
1213 arm_func_prolog(irg);
1214 irg_block_walk_graph(irg, arm_gen_labels, NULL, NULL);
1216 n = ARR_LEN(blk_sched);
1217 for (i = 0; i < n;) {
1218 ir_node *block, *next_bl;
1220 block = blk_sched[i];
1222 next_bl = i < n ? blk_sched[i] : NULL;
1224 /* set here the link. the emitter expects to find the next block here */
1225 set_irn_link(block, next_bl);
1226 arm_gen_block(block, last_block);
1230 be_dbg_method_end();
1232 /* emit SymConst values */
1233 if (set_count(sym_or_tv) > 0) {
1236 be_emit_cstring("\t.align 2\n");
1238 foreach_set(sym_or_tv, entry) {
1239 be_emit_irprintf(".L%u:\n", entry->label);
1241 if (entry->is_ident) {
1242 be_emit_cstring("\t.word\t");
1243 be_emit_ident(entry->u.id);
1245 be_emit_write_line();
1247 tarval *tv = entry->u.tv;
1248 int i, size = get_mode_size_bytes(get_tarval_mode(tv));
1251 /* beware: ARM fpa uses big endian format */
1252 for (i = ((size + 3) & ~3) - 4; i >= 0; i -= 4) {
1254 v = get_tarval_sub_bits(tv, i+3);
1255 v = (v << 8) | get_tarval_sub_bits(tv, i+2);
1256 v = (v << 8) | get_tarval_sub_bits(tv, i+1);
1257 v = (v << 8) | get_tarval_sub_bits(tv, i+0);
1258 be_emit_irprintf("\t.word\t%u\n", v);
1259 be_emit_write_line();
1264 be_emit_write_line();
1269 void arm_init_emitter(void)
1271 FIRM_DBG_REGISTER(dbg, "firm.be.arm.emit");