2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
42 #include "raw_bitset.h"
45 #include "../besched.h"
46 #include "../beblocksched.h"
48 #include "../begnuas.h"
49 #include "../be_dbgout.h"
51 #include "arm_emitter.h"
52 #include "arm_optimize.h"
53 #include "gen_arm_emitter.h"
54 #include "arm_nodes_attr.h"
55 #include "arm_new_nodes.h"
56 #include "arm_map_regs.h"
57 #include "gen_arm_regalloc_if.h"
59 #include "../benode.h"
61 #define SNPRINTF_BUF_LEN 128
63 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
65 static const arm_code_gen_t *cg;
66 static set *sym_or_tv;
69 * Returns the register at in position pos.
71 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
74 const arch_register_t *reg = NULL;
76 assert(get_irn_arity(irn) > pos && "Invalid IN position");
78 /* The out register of the operator at position pos is the
79 in register we need. */
80 op = get_irn_n(irn, pos);
82 reg = arch_get_irn_register(op);
84 assert(reg && "no in register found");
86 /* in case of a joker register: just return a valid register */
87 if (arch_register_type_is(reg, joker)) {
88 const arch_register_req_t *req = arch_get_register_req(irn, pos);
90 if (arch_register_req_is(req, limited)) {
91 /* in case of limited requirements: get the first allowed register */
92 unsigned idx = rbitset_next(req->limited, 0, 1);
93 reg = arch_register_for_index(req->cls, idx);
95 /* otherwise get first register in class */
96 reg = arch_register_for_index(req->cls, 0);
104 * Returns the register at out position pos.
106 static const arch_register_t *get_out_reg(const ir_node *node, int pos)
109 const arch_register_t *reg = NULL;
111 /* 1st case: irn is not of mode_T, so it has only */
112 /* one OUT register -> good */
113 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
114 /* Proj with the corresponding projnum for the register */
116 if (get_irn_mode(node) != mode_T) {
117 reg = arch_get_irn_register(node);
118 } else if (is_arm_irn(node)) {
119 reg = arch_irn_get_register(node, pos);
121 const ir_edge_t *edge;
123 foreach_out_edge(node, edge) {
124 proj = get_edge_src_irn(edge);
125 assert(is_Proj(proj) && "non-Proj from mode_T node");
126 if (get_Proj_proj(proj) == pos) {
127 reg = arch_get_irn_register(proj);
133 assert(reg && "no out register found");
137 void arm_emit_source_register(const ir_node *node, int pos)
139 const arch_register_t *reg = get_in_reg(node, pos);
140 be_emit_string(arch_register_get_name(reg));
143 void arm_emit_dest_register(const ir_node *node, int pos)
145 const arch_register_t *reg = get_out_reg(node, pos);
146 be_emit_string(arch_register_get_name(reg));
149 void arm_emit_offset(const ir_node *node)
151 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
152 assert(attr->base.is_load_store);
154 be_emit_irprintf("0x%X", attr->offset);
158 * Emit the arm fpa instruction suffix depending on the mode.
160 static void arm_emit_fpa_postfix(const ir_mode *mode)
162 int bits = get_mode_size_bits(mode);
172 void arm_emit_float_load_store_mode(const ir_node *node)
174 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
175 arm_emit_fpa_postfix(attr->load_store_mode);
178 void arm_emit_float_arithmetic_mode(const ir_node *node)
180 const arm_farith_attr_t *attr = get_arm_farith_attr_const(node);
181 arm_emit_fpa_postfix(attr->mode);
184 void arm_emit_symconst(const ir_node *node)
186 const arm_SymConst_attr_t *symconst = get_arm_SymConst_attr_const(node);
187 ir_entity *entity = symconst->entity;
189 be_gas_emit_entity(entity);
191 /* TODO do something with offset */
194 void arm_emit_load_mode(const ir_node *node)
196 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
197 ir_mode *mode = attr->load_store_mode;
198 int bits = get_mode_size_bits(mode);
199 bool is_signed = mode_is_signed(mode);
201 be_emit_string(is_signed ? "sh" : "h");
202 } else if (bits == 8) {
203 be_emit_string(is_signed ? "sb" : "b");
209 void arm_emit_store_mode(const ir_node *node)
211 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
212 ir_mode *mode = attr->load_store_mode;
213 int bits = get_mode_size_bits(mode);
215 be_emit_cstring("h");
216 } else if (bits == 8) {
217 be_emit_cstring("b");
224 static void emit_shf_mod_name(arm_shift_modifier_t mod)
227 case ARM_SHF_ASR_REG:
228 case ARM_SHF_ASR_IMM:
229 be_emit_cstring("asr");
231 case ARM_SHF_LSL_REG:
232 case ARM_SHF_LSL_IMM:
233 be_emit_cstring("lsl");
235 case ARM_SHF_LSR_REG:
236 case ARM_SHF_LSR_IMM:
237 be_emit_cstring("lsr");
239 case ARM_SHF_ROR_REG:
240 case ARM_SHF_ROR_IMM:
241 be_emit_cstring("ror");
246 panic("can't emit this shf_mod_name %d", (int) mod);
249 void arm_emit_shifter_operand(const ir_node *node)
251 const arm_shifter_operand_t *attr = get_irn_generic_attr_const(node);
253 switch (attr->shift_modifier) {
255 arm_emit_source_register(node, get_irn_arity(node) - 1);
258 unsigned val = attr->immediate_value;
259 val = (val >> attr->shift_immediate)
260 | (val << (32-attr->shift_immediate));
262 be_emit_irprintf("#0x%X", val);
265 case ARM_SHF_ASR_IMM:
266 case ARM_SHF_LSL_IMM:
267 case ARM_SHF_LSR_IMM:
268 case ARM_SHF_ROR_IMM:
269 arm_emit_source_register(node, get_irn_arity(node) - 1);
270 be_emit_cstring(", ");
271 emit_shf_mod_name(attr->shift_modifier);
272 be_emit_irprintf(" #0x%X", attr->shift_immediate);
275 case ARM_SHF_ASR_REG:
276 case ARM_SHF_LSL_REG:
277 case ARM_SHF_LSR_REG:
278 case ARM_SHF_ROR_REG:
279 arm_emit_source_register(node, get_irn_arity(node) - 2);
280 be_emit_cstring(", ");
281 emit_shf_mod_name(attr->shift_modifier);
282 be_emit_cstring(" ");
283 arm_emit_source_register(node, get_irn_arity(node) - 1);
287 arm_emit_source_register(node, get_irn_arity(node) - 1);
288 panic("RRX shifter emitter TODO");
290 case ARM_SHF_INVALID:
293 panic("Invalid shift_modifier while emitting %+F", node);
296 /** An entry in the sym_or_tv set. */
297 typedef struct sym_or_tv_t {
299 ir_entity *entity; /**< An entity. */
300 tarval *tv; /**< A tarval. */
301 const void *generic; /**< For generic compare. */
303 unsigned label; /**< the associated label. */
304 bool is_entity; /**< true if an entity is stored. */
308 * Returns a unique label. This number will not be used a second time.
310 static unsigned get_unique_label(void)
312 static unsigned id = 0;
316 static void emit_constant_name(const sym_or_tv_t *entry)
318 be_emit_irprintf("%sC%u", be_gas_get_private_prefix(), entry->label);
324 static void emit_arm_SymConst(const ir_node *irn)
326 const arm_SymConst_attr_t *attr = get_arm_SymConst_attr_const(irn);
327 sym_or_tv_t key, *entry;
330 key.u.entity = attr->entity;
331 key.is_entity = true;
333 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
334 if (entry->label == 0) {
335 /* allocate a label */
336 entry->label = get_unique_label();
338 label = entry->label;
340 /* load the symbol indirect */
341 be_emit_cstring("\tldr ");
342 arm_emit_dest_register(irn, 0);
343 be_emit_cstring(", ");
344 emit_constant_name(entry);
345 be_emit_finish_line_gas(irn);
348 static void emit_arm_FrameAddr(const ir_node *irn)
350 const arm_SymConst_attr_t *attr = get_irn_generic_attr_const(irn);
352 be_emit_cstring("\tadd ");
353 arm_emit_dest_register(irn, 0);
354 be_emit_cstring(", ");
355 arm_emit_source_register(irn, 0);
356 be_emit_cstring(", ");
357 be_emit_irprintf("#0x%X", attr->fp_offset);
358 be_emit_finish_line_gas(irn);
362 * Emit a floating point fpa constant.
364 static void emit_arm_fConst(const ir_node *irn)
366 sym_or_tv_t key, *entry;
370 key.u.tv = get_fConst_value(irn);
371 key.is_entity = false;
373 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
374 if (entry->label == 0) {
375 /* allocate a label */
376 entry->label = get_unique_label();
378 label = entry->label;
380 /* load the tarval indirect */
381 mode = get_irn_mode(irn);
382 be_emit_cstring("\tldf");
383 arm_emit_fpa_postfix(mode);
386 arm_emit_dest_register(irn, 0);
387 be_emit_cstring(", ");
388 emit_constant_name(entry);
389 be_emit_finish_line_gas(irn);
393 * Returns the next block in a block schedule.
395 static ir_node *sched_next_block(const ir_node *block)
397 return get_irn_link(block);
401 * Returns the target block for a control flow node.
403 static ir_node *get_cfop_target_block(const ir_node *irn)
405 return get_irn_link(irn);
409 * Emit the target label for a control flow node.
411 static void arm_emit_cfop_target(const ir_node *irn)
413 ir_node *block = get_cfop_target_block(irn);
415 be_gas_emit_block_name(block);
419 * Emit a Compare with conditional branch.
421 static void emit_arm_B(const ir_node *irn)
423 const ir_edge_t *edge;
424 const ir_node *proj_true = NULL;
425 const ir_node *proj_false = NULL;
426 const ir_node *block;
427 const ir_node *next_block;
428 ir_node *op1 = get_irn_n(irn, 0);
430 pn_Cmp pnc = get_arm_CondJmp_pnc(irn);
431 const arm_cmp_attr_t *cmp_attr = get_irn_generic_attr_const(op1);
432 bool is_signed = !cmp_attr->is_unsigned;
434 assert(is_arm_Cmp(op1) || is_arm_Tst(op1));
436 foreach_out_edge(irn, edge) {
437 ir_node *proj = get_edge_src_irn(edge);
438 long nr = get_Proj_proj(proj);
439 if (nr == pn_Cond_true) {
446 if (cmp_attr->ins_permuted) {
447 pnc = get_mirrored_pnc(pnc);
450 /* for now, the code works for scheduled and non-schedules blocks */
451 block = get_nodes_block(irn);
453 /* we have a block schedule */
454 next_block = sched_next_block(block);
456 assert(pnc != pn_Cmp_False);
457 assert(pnc != pn_Cmp_True);
459 if (get_cfop_target_block(proj_true) == next_block) {
460 /* exchange both proj's so the second one can be omitted */
461 const ir_node *t = proj_true;
463 proj_true = proj_false;
465 pnc = get_negated_pnc(pnc, mode_Iu);
469 case pn_Cmp_Eq: suffix = "eq"; break;
470 case pn_Cmp_Lt: suffix = is_signed ? "lt" : "lo"; break;
471 case pn_Cmp_Le: suffix = is_signed ? "le" : "ls"; break;
472 case pn_Cmp_Gt: suffix = is_signed ? "gt" : "hi"; break;
473 case pn_Cmp_Ge: suffix = is_signed ? "ge" : "hs"; break;
474 case pn_Cmp_Lg: suffix = "ne"; break;
475 case pn_Cmp_Leg: suffix = "al"; break;
476 default: panic("Cmp has unsupported pnc");
479 /* emit the true proj */
480 be_emit_irprintf("\tb%s ", suffix);
481 arm_emit_cfop_target(proj_true);
482 be_emit_finish_line_gas(proj_true);
484 if (get_cfop_target_block(proj_false) == next_block) {
485 be_emit_cstring("\t/* fallthrough to ");
486 arm_emit_cfop_target(proj_false);
487 be_emit_cstring(" */");
488 be_emit_finish_line_gas(proj_false);
490 be_emit_cstring("\tb ");
491 arm_emit_cfop_target(proj_false);
492 be_emit_finish_line_gas(proj_false);
496 /** Sort register in ascending order. */
497 static int reg_cmp(const void *a, const void *b)
499 const arch_register_t * const *ra = a;
500 const arch_register_t * const *rb = b;
502 return *ra < *rb ? -1 : (*ra != *rb);
506 * Create the CopyB instruction sequence.
508 static void emit_arm_CopyB(const ir_node *irn)
510 const arm_CopyB_attr_t *attr = get_irn_generic_attr_const(irn);
511 unsigned size = attr->size;
513 const char *tgt = arch_register_get_name(get_in_reg(irn, 0));
514 const char *src = arch_register_get_name(get_in_reg(irn, 1));
515 const char *t0, *t1, *t2, *t3;
517 const arch_register_t *tmpregs[4];
519 /* collect the temporary registers and sort them, we need ascending order */
520 tmpregs[0] = get_in_reg(irn, 2);
521 tmpregs[1] = get_in_reg(irn, 3);
522 tmpregs[2] = get_in_reg(irn, 4);
523 tmpregs[3] = &arm_gp_regs[REG_R12];
525 /* Note: R12 is always the last register because the RA did not assign higher ones */
526 qsort((void *)tmpregs, 3, sizeof(tmpregs[0]), reg_cmp);
528 /* need ascending order */
529 t0 = arch_register_get_name(tmpregs[0]);
530 t1 = arch_register_get_name(tmpregs[1]);
531 t2 = arch_register_get_name(tmpregs[2]);
532 t3 = arch_register_get_name(tmpregs[3]);
534 be_emit_cstring("/* MemCopy (");
536 be_emit_cstring(")->(");
537 arm_emit_source_register(irn, 0);
538 be_emit_irprintf(" [%u bytes], Uses ", size);
540 be_emit_cstring(", ");
542 be_emit_cstring(", ");
544 be_emit_cstring(", and ");
546 be_emit_cstring("*/");
547 be_emit_finish_line_gas(NULL);
549 assert(size > 0 && "CopyB needs size > 0" );
552 fprintf(stderr, "strange hack enabled: copy more bytes than needed!");
561 be_emit_cstring("\tldr ");
563 be_emit_cstring(", [");
565 be_emit_cstring(", #0]");
566 be_emit_finish_line_gas(NULL);
568 be_emit_cstring("\tstr ");
570 be_emit_cstring(", [");
572 be_emit_cstring(", #0]");
573 be_emit_finish_line_gas(irn);
576 be_emit_cstring("\tldmia ");
578 be_emit_cstring("!, {");
580 be_emit_cstring(", ");
583 be_emit_finish_line_gas(NULL);
585 be_emit_cstring("\tstmia ");
587 be_emit_cstring("!, {");
589 be_emit_cstring(", ");
592 be_emit_finish_line_gas(irn);
595 be_emit_cstring("\tldmia ");
597 be_emit_cstring("!, {");
599 be_emit_cstring(", ");
601 be_emit_cstring(", ");
604 be_emit_finish_line_gas(NULL);
606 be_emit_cstring("\tstmia ");
608 be_emit_cstring("!, {");
610 be_emit_cstring(", ");
612 be_emit_cstring(", ");
615 be_emit_finish_line_gas(irn);
620 be_emit_cstring("\tldmia ");
622 be_emit_cstring("!, {");
624 be_emit_cstring(", ");
626 be_emit_cstring(", ");
628 be_emit_cstring(", ");
631 be_emit_finish_line_gas(NULL);
633 be_emit_cstring("\tstmia ");
635 be_emit_cstring("!, {");
637 be_emit_cstring(", ");
639 be_emit_cstring(", ");
641 be_emit_cstring(", ");
644 be_emit_finish_line_gas(irn);
649 static void emit_arm_SwitchJmp(const ir_node *irn)
651 const ir_edge_t *edge;
657 ir_node *default_proj = NULL;
659 block_nr = get_irn_node_nr(irn);
660 n_projs = get_arm_SwitchJmp_n_projs(irn);
662 projs = XMALLOCNZ(ir_node*, n_projs);
664 foreach_out_edge(irn, edge) {
665 proj = get_edge_src_irn(edge);
666 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
668 if (get_Proj_proj(proj) == get_arm_SwitchJmp_default_proj_num(irn))
671 projs[get_Proj_proj(proj)] = proj;
673 assert(default_proj != NULL && "SwitchJmp should have a Default Proj");
680 be_emit_cstring("\tcmp ");
681 arm_emit_source_register(irn, 0);
682 be_emit_irprintf(", #%u", n_projs - 1);
683 be_emit_finish_line_gas(irn);
685 be_emit_cstring("\tbhi ");
686 arm_emit_cfop_target(default_proj);
687 be_emit_finish_line_gas(default_proj);
690 LDR %r12, .TABLE_X_START
691 ADD %r12, %r12, [%1S, LSL #2]
695 be_emit_irprintf("\tldr %%r12, TABLE_%d_START", block_nr);
696 be_emit_finish_line_gas(NULL);
698 be_emit_irprintf("\tadd %%r12, %%r12, ");
699 arm_emit_source_register(irn, 0);
700 be_emit_cstring(", LSL #2");
701 be_emit_finish_line_gas(NULL);
703 be_emit_cstring("\tldr %r15, [%r12, #0]");
704 be_emit_finish_line_gas(NULL);
706 be_emit_irprintf("TABLE_%d_START:\n\t.word\tTABLE_%d", block_nr, block_nr);
707 be_emit_finish_line_gas(NULL);
708 be_emit_irprintf("\t.align 2");
709 be_emit_finish_line_gas(NULL);
710 be_emit_irprintf("TABLE_%d:", block_nr);
711 be_emit_finish_line_gas(NULL);
713 for (i = 0; i < n_projs; ++i) {
716 proj = projs[get_arm_SwitchJmp_default_proj_num(irn)];
718 be_emit_cstring("\t.word\t");
719 arm_emit_cfop_target(proj);
720 be_emit_finish_line_gas(proj);
722 be_emit_irprintf("\t.align 2\n");
723 be_emit_finish_line_gas(NULL);
728 static void arm_emit_entity(ir_entity *entity)
730 be_emit_ident(get_entity_ld_ident(entity));
733 static void emit_be_Call(const ir_node *irn)
735 ir_entity *entity = be_Call_get_entity(irn);
737 if (entity != NULL) {
738 be_emit_cstring("\tbl ");
739 arm_emit_entity(entity);
740 be_emit_finish_line_gas(irn);
742 be_emit_cstring("\tmov lr, pc");
743 be_emit_finish_line_gas(irn);
744 be_emit_cstring("\tmov pc, ");
745 arm_emit_source_register(irn, be_pos_Call_ptr);
746 be_emit_finish_line_gas(irn);
750 /** Emit an IncSP node */
751 static void emit_be_IncSP(const ir_node *irn)
753 int offs = -be_get_IncSP_offset(irn);
757 be_emit_cstring("\tsub ");
760 be_emit_cstring("\tadd ");
762 arm_emit_dest_register(irn, 0);
763 be_emit_cstring(", ");
764 arm_emit_source_register(irn, 0);
765 be_emit_irprintf(", #0x%X", offs);
767 /* omitted IncSP(0) */
770 be_emit_finish_line_gas(irn);
773 static void emit_be_Copy(const ir_node *irn)
775 ir_mode *mode = get_irn_mode(irn);
777 if (get_in_reg(irn, 0) == get_out_reg(irn, 0)) {
782 if (mode_is_float(mode)) {
783 if (USE_FPA(cg->isa)) {
784 be_emit_cstring("\tmvf");
786 arm_emit_dest_register(irn, 0);
787 be_emit_cstring(", ");
788 arm_emit_source_register(irn, 0);
789 be_emit_finish_line_gas(irn);
791 panic("emit_be_Copy: move not supported for this mode");
793 } else if (mode_is_data(mode)) {
794 be_emit_cstring("\tmov ");
795 arm_emit_dest_register(irn, 0);
796 be_emit_cstring(", ");
797 arm_emit_source_register(irn, 0);
798 be_emit_finish_line_gas(irn);
800 panic("emit_be_Copy: move not supported for this mode");
804 static void emit_be_Perm(const ir_node *irn)
806 be_emit_cstring("\teor ");
807 arm_emit_source_register(irn, 0);
808 be_emit_cstring(", ");
809 arm_emit_source_register(irn, 0);
810 be_emit_cstring(", ");
811 arm_emit_source_register(irn, 1);
812 be_emit_finish_line_gas(NULL);
814 be_emit_cstring("\teor ");
815 arm_emit_source_register(irn, 1);
816 be_emit_cstring(", ");
817 arm_emit_source_register(irn, 0);
818 be_emit_cstring(", ");
819 arm_emit_source_register(irn, 1);
820 be_emit_finish_line_gas(NULL);
822 be_emit_cstring("\teor ");
823 arm_emit_source_register(irn, 0);
824 be_emit_cstring(", ");
825 arm_emit_source_register(irn, 0);
826 be_emit_cstring(", ");
827 arm_emit_source_register(irn, 1);
828 be_emit_finish_line_gas(irn);
831 static void emit_be_MemPerm(const ir_node *node)
837 /* TODO: this implementation is slower than necessary.
838 The longterm goal is however to avoid the memperm node completely */
840 memperm_arity = be_get_MemPerm_entity_arity(node);
841 if (memperm_arity > 12)
842 panic("memperm with more than 12 inputs not supported yet");
844 for (i = 0; i < memperm_arity; ++i) {
846 ir_entity *entity = be_get_MemPerm_in_entity(node, i);
849 be_emit_irprintf("\tstr r%d, [sp, #-4]!", i);
850 be_emit_finish_line_gas(node);
852 /* load from entity */
853 offset = get_entity_offset(entity) + sp_change;
854 be_emit_irprintf("\tldr r%d, [sp, #%d]", i, offset);
855 be_emit_finish_line_gas(node);
858 for (i = memperm_arity-1; i >= 0; --i) {
860 ir_entity *entity = be_get_MemPerm_out_entity(node, i);
862 /* store to new entity */
863 offset = get_entity_offset(entity) + sp_change;
864 be_emit_irprintf("\tstr r%d, [sp, #%d]", i, offset);
865 be_emit_finish_line_gas(node);
866 /* restore register */
867 be_emit_irprintf("\tldr r%d, [sp], #4", i);
869 be_emit_finish_line_gas(node);
871 assert(sp_change == 0);
874 static void emit_be_Return(const ir_node *node)
876 be_emit_cstring("\tmov pc, lr");
877 be_emit_finish_line_gas(node);
881 static void emit_arm_Jmp(const ir_node *node)
883 ir_node *block, *next_block;
885 /* for now, the code works for scheduled and non-schedules blocks */
886 block = get_nodes_block(node);
888 /* we have a block schedule */
889 next_block = sched_next_block(block);
890 if (get_cfop_target_block(node) != next_block) {
891 be_emit_cstring("\tb ");
892 arm_emit_cfop_target(node);
894 be_emit_cstring("\t/* fallthrough to ");
895 arm_emit_cfop_target(node);
896 be_emit_cstring(" */");
898 be_emit_finish_line_gas(node);
901 static void emit_nothing(const ir_node *irn)
907 * The type of a emitter function.
909 typedef void (emit_func)(const ir_node *irn);
912 * Set a node emitter. Make it a bit more type safe.
914 static inline void set_emitter(ir_op *op, emit_func arm_emit_node)
916 op->ops.generic = (op_func)arm_emit_node;
920 * Enters the emitter functions for handled nodes into the generic
921 * pointer of an opcode.
923 static void arm_register_emitters(void)
925 /* first clear the generic function pointer for all ops */
926 clear_irp_opcodes_generic_func();
928 /* register all emitter functions defined in spec */
929 arm_register_spec_emitters();
932 set_emitter(op_arm_B, emit_arm_B);
933 set_emitter(op_arm_CopyB, emit_arm_CopyB);
934 set_emitter(op_arm_fConst, emit_arm_fConst);
935 set_emitter(op_arm_FrameAddr, emit_arm_FrameAddr);
936 set_emitter(op_arm_Jmp, emit_arm_Jmp);
937 set_emitter(op_arm_SwitchJmp, emit_arm_SwitchJmp);
938 set_emitter(op_arm_SymConst, emit_arm_SymConst);
939 set_emitter(op_be_Call, emit_be_Call);
940 set_emitter(op_be_Copy, emit_be_Copy);
941 set_emitter(op_be_CopyKeep, emit_be_Copy);
942 set_emitter(op_be_IncSP, emit_be_IncSP);
943 set_emitter(op_be_MemPerm, emit_be_MemPerm);
944 set_emitter(op_be_Perm, emit_be_Perm);
945 set_emitter(op_be_Return, emit_be_Return);
947 /* no need to emit anything for the following nodes */
948 set_emitter(op_Phi, emit_nothing);
949 set_emitter(op_be_Keep, emit_nothing);
950 set_emitter(op_be_Start, emit_nothing);
951 set_emitter(op_be_Barrier, emit_nothing);
955 * Emits code for a node.
957 static void arm_emit_node(const ir_node *irn)
959 ir_op *op = get_irn_op(irn);
961 if (op->ops.generic) {
962 emit_func *emit = (emit_func *)op->ops.generic;
963 be_dbg_set_dbg_info(get_irn_dbg_info(irn));
966 panic("Error: No emit handler for node %+F (graph %+F)\n",
967 irn, current_ir_graph);
972 * emit the block label if needed.
974 static void arm_emit_block_header(ir_node *block, ir_node *prev)
979 ir_exec_freq *exec_freq = be_get_irg_exec_freq(cg->irg);
982 n_cfgpreds = get_Block_n_cfgpreds(block);
983 if (n_cfgpreds == 1) {
984 ir_node *pred = get_Block_cfgpred(block, 0);
985 ir_node *pred_block = get_nodes_block(pred);
987 /* we don't need labels for fallthrough blocks, however switch-jmps
988 * are no fallthroughs */
989 if (pred_block == prev &&
990 !(is_Proj(pred) && is_arm_SwitchJmp(get_Proj_pred(pred)))) {
1000 be_gas_emit_block_name(block);
1003 be_emit_pad_comment();
1004 be_emit_cstring(" /* preds:");
1006 /* emit list of pred blocks in comment */
1007 arity = get_irn_arity(block);
1008 for (i = 0; i < arity; ++i) {
1009 ir_node *predblock = get_Block_cfgpred_block(block, i);
1010 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1013 be_emit_cstring("\t/* ");
1014 be_gas_emit_block_name(block);
1015 be_emit_cstring(": ");
1017 if (exec_freq != NULL) {
1018 be_emit_irprintf(" freq: %f",
1019 get_block_execfreq(exec_freq, block));
1021 be_emit_cstring(" */\n");
1022 be_emit_write_line();
1026 * Walks over the nodes in a block connected by scheduling edges
1027 * and emits code for each node.
1029 static void arm_gen_block(ir_node *block, ir_node *prev_block)
1033 arm_emit_block_header(block, prev_block);
1034 be_dbg_set_dbg_info(get_irn_dbg_info(block));
1035 sched_foreach(block, irn) {
1042 * Sets labels for control flow nodes (jump target)
1044 static void arm_gen_labels(ir_node *block, void *env)
1047 int n = get_Block_n_cfgpreds(block);
1050 for (n--; n >= 0; n--) {
1051 pred = get_Block_cfgpred(block, n);
1052 set_irn_link(pred, block);
1057 * Compare two entries of the symbol or tarval set.
1059 static int cmp_sym_or_tv(const void *elt, const void *key, size_t size)
1061 const sym_or_tv_t *p1 = elt;
1062 const sym_or_tv_t *p2 = key;
1065 /* as an identifier NEVER can point to a tarval, it's enough
1066 to compare it this way */
1067 return p1->u.generic != p2->u.generic;
1070 void arm_gen_routine(const arm_code_gen_t *arm_cg, ir_graph *irg)
1072 ir_node **blk_sched;
1074 ir_node *last_block = NULL;
1075 ir_entity *entity = get_irg_entity(irg);
1078 sym_or_tv = new_set(cmp_sym_or_tv, 8);
1080 be_gas_elf_type_char = '%';
1082 arm_register_emitters();
1084 be_dbg_method_begin(entity);
1086 /* create the block schedule */
1087 blk_sched = be_create_block_schedule(irg);
1089 be_gas_emit_function_prolog(entity, 4);
1091 irg_block_walk_graph(irg, arm_gen_labels, NULL, NULL);
1093 n = ARR_LEN(blk_sched);
1094 for (i = 0; i < n;) {
1095 ir_node *block, *next_bl;
1097 block = blk_sched[i];
1099 next_bl = i < n ? blk_sched[i] : NULL;
1101 /* set here the link. the emitter expects to find the next block here */
1102 set_irn_link(block, next_bl);
1103 arm_gen_block(block, last_block);
1107 /* emit SymConst values */
1108 if (set_count(sym_or_tv) > 0) {
1111 be_emit_cstring("\t.align 2\n");
1113 foreach_set(sym_or_tv, entry) {
1114 emit_constant_name(entry);
1115 be_emit_cstring(":\n");
1116 be_emit_write_line();
1118 if (entry->is_entity) {
1119 be_emit_cstring("\t.word\t");
1120 be_gas_emit_entity(entry->u.entity);
1122 be_emit_write_line();
1124 tarval *tv = entry->u.tv;
1125 int i, size = get_mode_size_bytes(get_tarval_mode(tv));
1128 /* beware: ARM fpa uses big endian format */
1129 for (i = ((size + 3) & ~3) - 4; i >= 0; i -= 4) {
1131 v = get_tarval_sub_bits(tv, i+3);
1132 v = (v << 8) | get_tarval_sub_bits(tv, i+2);
1133 v = (v << 8) | get_tarval_sub_bits(tv, i+1);
1134 v = (v << 8) | get_tarval_sub_bits(tv, i+0);
1135 be_emit_irprintf("\t.word\t%u\n", v);
1136 be_emit_write_line();
1141 be_emit_write_line();
1145 be_gas_emit_function_epilog(entity);
1146 be_dbg_method_end();
1149 void arm_init_emitter(void)
1151 FIRM_DBG_REGISTER(dbg, "firm.be.arm.emit");