2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
45 #include "raw_bitset.h"
48 #include "../besched.h"
49 #include "../beblocksched.h"
50 #include "../beirg_t.h"
51 #include "../begnuas.h"
52 #include "../be_dbgout.h"
54 #include "arm_emitter.h"
55 #include "gen_arm_emitter.h"
56 #include "arm_nodes_attr.h"
57 #include "arm_new_nodes.h"
58 #include "arm_map_regs.h"
59 #include "gen_arm_regalloc_if.h"
61 #include "../benode_t.h"
63 #define BLOCK_PREFIX ".L"
65 #define SNPRINTF_BUF_LEN 128
67 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
69 static const arch_env_t *arch_env = NULL;
70 static const arm_code_gen_t *cg;
71 static const arm_isa_t *isa;
72 static set *sym_or_tv;
75 * Returns the register at in position pos.
77 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
79 const arch_register_t *reg = NULL;
81 assert(get_irn_arity(irn) > pos && "Invalid IN position");
83 /* The out register of the operator at position pos is the
84 in register we need. */
85 op = get_irn_n(irn, pos);
87 reg = arch_get_irn_register(arch_env, op);
89 assert(reg && "no in register found");
91 /* in case of a joker register: just return a valid register */
92 if (arch_register_type_is(reg, joker)) {
93 const arch_register_req_t *req;
95 /* ask for the requirements */
96 req = arch_get_register_req(arch_env, irn, pos);
98 if (arch_register_req_is(req, limited)) {
99 /* in case of limited requirements: get the first allowed register */
100 unsigned idx = rbitset_next(req->limited, 0, 1);
101 reg = arch_register_for_index(req->cls, idx);
103 /* otherwise get first register in class */
104 reg = arch_register_for_index(req->cls, 0);
112 * Returns the register at out position pos.
114 static const arch_register_t *get_out_reg(const ir_node *node, int pos)
117 const arch_register_t *reg = NULL;
119 /* 1st case: irn is not of mode_T, so it has only */
120 /* one OUT register -> good */
121 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
122 /* Proj with the corresponding projnum for the register */
124 if (get_irn_mode(node) != mode_T) {
125 reg = arch_get_irn_register(arch_env, node);
126 } else if (is_arm_irn(node)) {
127 reg = get_arm_out_reg(node, pos);
129 const ir_edge_t *edge;
131 foreach_out_edge(node, edge) {
132 proj = get_edge_src_irn(edge);
133 assert(is_Proj(proj) && "non-Proj from mode_T node");
134 if (get_Proj_proj(proj) == pos) {
135 reg = arch_get_irn_register(arch_env, proj);
141 assert(reg && "no out register found");
145 /*************************************************************
147 * (_) | | / _| | | | |
148 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
149 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
150 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
151 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
154 *************************************************************/
157 * Emit the name of the source register at given input position.
159 void arm_emit_source_register(const ir_node *node, int pos) {
160 const arch_register_t *reg = get_in_reg(node, pos);
161 be_emit_string(arch_register_get_name(reg));
165 * Emit the name of the destination register at given output position.
167 void arm_emit_dest_register(const ir_node *node, int pos) {
168 const arch_register_t *reg = get_out_reg(node, pos);
169 be_emit_string(arch_register_get_name(reg));
173 * Emit a node's offset.
175 void arm_emit_offset(const ir_node *node) {
177 ir_opcode opc = get_irn_opcode(node);
179 if (opc == beo_Reload || opc == beo_Spill) {
180 ir_entity *ent = be_get_frame_entity(node);
181 offset = get_entity_offset(ent);
182 } else if (opc == beo_IncSP) {
183 offset = - be_get_IncSP_offset(node);
185 assert(!"unimplemented arm_emit_offset for this node type");
186 panic("unimplemented arm_emit_offset for this node type");
188 be_emit_irprintf("%d", offset);
192 * Emit the arm fpa instruction suffix depending on the mode.
194 static void arm_emit_fpa_postfix(const ir_mode *mode) {
195 int bits = get_mode_size_bits(mode);
206 * Emit the instruction suffix depending on the mode.
208 void arm_emit_mode(const ir_node *node) {
211 if (is_arm_irn(node)) {
212 const arm_attr_t *attr = get_arm_attr_const(node);
213 mode = attr->op_mode ? attr->op_mode : get_irn_mode(node);
215 mode = get_irn_mode(node);
217 arm_emit_fpa_postfix(mode);
221 * Emit a const or SymConst value.
223 void arm_emit_immediate(const ir_node *node) {
224 const arm_attr_t *attr = get_arm_attr_const(node);
226 if (ARM_GET_SHF_MOD(attr) == ARM_SHF_IMM) {
227 be_emit_irprintf("#0x%X", arm_decode_imm_w_shift(get_arm_imm_value(node)));
228 } else if (ARM_GET_FPA_IMM(attr)) {
229 be_emit_irprintf("#%s", arm_get_fpa_imm_name(get_arm_imm_value(node)));
230 } else if (is_arm_SymConst(node))
231 be_emit_ident(get_arm_symconst_id(node));
233 assert(!"not a Constant");
238 * Returns the tarval or offset of an arm node as a string.
240 void arm_emit_shift(const ir_node *node) {
241 arm_shift_modifier mod;
243 mod = get_arm_shift_modifier(node);
244 if (ARM_HAS_SHIFT(mod)) {
245 long v = get_arm_imm_value(node);
247 be_emit_irprintf(", %s #%l", arm_shf_mod_name(mod), v);
251 /** An entry in the sym_or_tv set. */
252 typedef struct sym_or_tv_t {
254 ident *id; /**< An ident. */
255 tarval *tv; /**< A tarval. */
256 const void *generic; /**< For generic compare. */
258 unsigned label; /**< the associated label. */
259 char is_ident; /**< Non-zero if an ident is stored. */
263 * Returns a unique label. This number will not be used a second time.
265 static unsigned get_unique_label(void) {
266 static unsigned id = 0;
273 static void emit_arm_SymConst(const ir_node *irn) {
274 sym_or_tv_t key, *entry;
277 key.u.id = get_arm_symconst_id(irn);
280 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
281 if (entry->label == 0) {
282 /* allocate a label */
283 entry->label = get_unique_label();
285 label = entry->label;
287 /* load the symbol indirect */
288 be_emit_cstring("\tldr ");
289 arm_emit_dest_register(irn, 0);
290 be_emit_irprintf(", .L%u", label);
291 be_emit_finish_line_gas(irn);
295 * Emit a floating point fpa constant.
297 static void emit_arm_fpaConst(const ir_node *irn) {
298 sym_or_tv_t key, *entry;
302 key.u.tv = get_fpaConst_value(irn);
305 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
306 if (entry->label == 0) {
307 /* allocate a label */
308 entry->label = get_unique_label();
310 label = entry->label;
312 /* load the tarval indirect */
313 mode = get_irn_mode(irn);
314 be_emit_cstring("\tldf");
315 arm_emit_fpa_postfix(mode);
318 arm_emit_dest_register(irn, 0);
319 be_emit_irprintf(", .L%u", label);
320 be_emit_finish_line_gas(irn);
324 * Returns the next block in a block schedule.
326 static ir_node *sched_next_block(const ir_node *block) {
327 return get_irn_link(block);
331 * Returns the target block for a control flow node.
333 static ir_node *get_cfop_target_block(const ir_node *irn) {
334 return get_irn_link(irn);
338 * Emits a block label for the given block.
340 static void arm_emit_block_name(const ir_node *block) {
341 if (has_Block_label(block)) {
342 be_emit_string(be_gas_label_prefix());
343 be_emit_irprintf("%lu", get_Block_label(block));
345 be_emit_cstring(BLOCK_PREFIX);
346 be_emit_irprintf("%d", get_irn_node_nr(block));
351 * Emit the target label for a control flow node.
353 static void arm_emit_cfop_target(const ir_node *irn) {
354 ir_node *block = get_cfop_target_block(irn);
356 arm_emit_block_name(block);
360 * Emit a Compare with conditional branch.
362 static void emit_arm_CmpBra(const ir_node *irn) {
363 const ir_edge_t *edge;
364 const ir_node *proj_true = NULL;
365 const ir_node *proj_false = NULL;
366 const ir_node *block;
367 const ir_node *next_block;
368 ir_node *op1 = get_irn_n(irn, 0);
369 ir_mode *opmode = get_irn_mode(op1);
371 int proj_num = get_arm_CondJmp_proj_num(irn);
373 foreach_out_edge(irn, edge) {
374 ir_node *proj = get_edge_src_irn(edge);
375 long nr = get_Proj_proj(proj);
376 if (nr == pn_Cond_true) {
383 /* for now, the code works for scheduled and non-schedules blocks */
384 block = get_nodes_block(irn);
386 /* we have a block schedule */
387 next_block = sched_next_block(block);
389 if (proj_num == pn_Cmp_False) {
390 /* always false: should not happen */
391 be_emit_cstring("\tb ");
392 arm_emit_cfop_target(proj_false);
393 be_emit_finish_line_gas(proj_false);
394 } else if (proj_num == pn_Cmp_True) {
395 /* always true: should not happen */
396 be_emit_cstring("\tb ");
397 arm_emit_cfop_target(proj_true);
398 be_emit_finish_line_gas(proj_true);
400 if (mode_is_float(opmode)) {
401 suffix = "ICHWILLIMPLEMENTIERTWERDEN";
403 be_emit_cstring("\tfcmp ");
404 arm_emit_source_register(irn, 0);
405 be_emit_cstring(", ");
406 arm_emit_source_register(irn, 1);
407 be_emit_finish_line_gas(irn);
409 be_emit_cstring("\tfmstat");
410 be_emit_pad_comment();
411 be_emit_cstring("/* FCSPR -> CPSR */");
412 be_emit_finish_line_gas(NULL);
414 if (get_cfop_target_block(proj_true) == next_block) {
415 /* exchange both proj's so the second one can be omitted */
416 const ir_node *t = proj_true;
418 proj_true = proj_false;
420 proj_num = get_negated_pnc(proj_num, mode_Iu);
423 case pn_Cmp_Eq: suffix = "eq"; break;
424 case pn_Cmp_Lt: suffix = "lt"; break;
425 case pn_Cmp_Le: suffix = "le"; break;
426 case pn_Cmp_Gt: suffix = "gt"; break;
427 case pn_Cmp_Ge: suffix = "ge"; break;
428 case pn_Cmp_Lg: suffix = "ne"; break;
429 case pn_Cmp_Leg: suffix = "al"; break;
430 default: assert(!"Cmp unsupported"); suffix = "al";
432 be_emit_cstring("\tcmp ");
433 arm_emit_source_register(irn, 0);
434 be_emit_cstring(", ");
435 arm_emit_source_register(irn, 1);
436 be_emit_finish_line_gas(irn);
439 /* emit the true proj */
440 be_emit_irprintf("\tb%s ", suffix);
441 arm_emit_cfop_target(proj_true);
442 be_emit_finish_line_gas(proj_true);
444 if (get_cfop_target_block(proj_false) == next_block) {
445 be_emit_cstring("\t/* fallthrough to ");
446 arm_emit_cfop_target(proj_false);
447 be_emit_cstring(" */");
448 be_emit_finish_line_gas(proj_false);
450 be_emit_cstring("b ");
451 arm_emit_cfop_target(proj_false);
452 be_emit_finish_line_gas(proj_false);
458 * Emit a Compare with conditional branch.
460 static void emit_arm_fpaCmfBra(const ir_node *irn) {
465 * Emit a Compare with conditional branch.
467 static void emit_arm_fpaCmfeBra(const ir_node *irn) {
471 /** Sort register in ascending order. */
472 static int reg_cmp(const void *a, const void *b) {
473 const arch_register_t * const *ra = a;
474 const arch_register_t * const *rb = b;
476 return *ra < *rb ? -1 : (*ra != *rb);
480 * Create the CopyB instruction sequence.
482 static void emit_arm_CopyB(const ir_node *irn) {
483 unsigned size = (unsigned)get_arm_imm_value(irn);
485 const char *tgt = arch_register_get_name(get_in_reg(irn, 0));
486 const char *src = arch_register_get_name(get_in_reg(irn, 1));
487 const char *t0, *t1, *t2, *t3;
489 const arch_register_t *tmpregs[4];
491 /* collect the temporary registers and sort them, we need ascending order */
492 tmpregs[0] = get_in_reg(irn, 2);
493 tmpregs[1] = get_in_reg(irn, 3);
494 tmpregs[2] = get_in_reg(irn, 4);
495 tmpregs[3] = &arm_gp_regs[REG_R12];
497 /* Note: R12 is always the last register because the RA did not assign higher ones */
498 qsort((void *)tmpregs, 3, sizeof(tmpregs[0]), reg_cmp);
500 /* need ascending order */
501 t0 = arch_register_get_name(tmpregs[0]);
502 t1 = arch_register_get_name(tmpregs[1]);
503 t2 = arch_register_get_name(tmpregs[2]);
504 t3 = arch_register_get_name(tmpregs[3]);
506 be_emit_cstring("/* MemCopy (");
508 be_emit_cstring(")->(");
509 arm_emit_source_register(irn, 0);
510 be_emit_irprintf(" [%u bytes], Uses ", size);
512 be_emit_cstring(", ");
514 be_emit_cstring(", ");
516 be_emit_cstring(", and ");
518 be_emit_cstring("*/");
519 be_emit_finish_line_gas(NULL);
521 assert(size > 0 && "CopyB needs size > 0" );
524 assert(!"strange hack enabled: copy more bytes than needed!");
533 be_emit_cstring("\tldr ");
535 be_emit_cstring(", [");
537 be_emit_cstring(", #0]");
538 be_emit_finish_line_gas(NULL);
540 be_emit_cstring("\tstr ");
542 be_emit_cstring(", [");
544 be_emit_cstring(", #0]");
545 be_emit_finish_line_gas(irn);
548 be_emit_cstring("\tldmia ");
550 be_emit_cstring("!, {");
552 be_emit_cstring(", ");
555 be_emit_finish_line_gas(NULL);
557 be_emit_cstring("\tstmia ");
559 be_emit_cstring("!, {");
561 be_emit_cstring(", ");
564 be_emit_finish_line_gas(irn);
567 be_emit_cstring("\tldmia ");
569 be_emit_cstring("!, {");
571 be_emit_cstring(", ");
573 be_emit_cstring(", ");
576 be_emit_finish_line_gas(NULL);
578 be_emit_cstring("\tstmia ");
580 be_emit_cstring("!, {");
582 be_emit_cstring(", ");
584 be_emit_cstring(", ");
587 be_emit_finish_line_gas(irn);
592 be_emit_cstring("\tldmia ");
594 be_emit_cstring("!, {");
596 be_emit_cstring(", ");
598 be_emit_cstring(", ");
600 be_emit_cstring(", ");
603 be_emit_finish_line_gas(NULL);
605 be_emit_cstring("\tstmia ");
607 be_emit_cstring("!, {");
609 be_emit_cstring(", ");
611 be_emit_cstring(", ");
613 be_emit_cstring(", ");
616 be_emit_finish_line_gas(irn);
621 static void emit_arm_SwitchJmp(const ir_node *irn) {
622 const ir_edge_t *edge;
628 ir_node *default_proj = NULL;
630 block_nr = get_irn_node_nr(irn);
631 n_projs = get_arm_SwitchJmp_n_projs(irn);
633 projs = xcalloc(n_projs , sizeof(ir_node*));
635 foreach_out_edge(irn, edge) {
636 proj = get_edge_src_irn(edge);
637 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
639 if (get_Proj_proj(proj) == get_arm_SwitchJmp_default_proj_num(irn))
642 projs[get_Proj_proj(proj)] = proj;
644 assert(default_proj != NULL && "SwitchJmp should have a Default Proj");
651 be_emit_cstring("\tcmp ");
652 arm_emit_source_register(irn, 0);
653 be_emit_irprintf(", #%u", n_projs - 1);
654 be_emit_finish_line_gas(irn);
656 be_emit_cstring("\tbhi ");
657 arm_emit_cfop_target(default_proj);
658 be_emit_finish_line_gas(default_proj);
661 LDR %r12, .TABLE_X_START
662 ADD %r12, %r12, [%1S, LSL #2]
666 be_emit_irprintf("\tldr %%r12, TABLE_%d_START", block_nr);
667 be_emit_finish_line_gas(NULL);
669 be_emit_irprintf("\tadd %%r12, %%r12, ");
670 arm_emit_source_register(irn, 0);
671 be_emit_cstring(", LSL #2");
672 be_emit_finish_line_gas(NULL);
674 be_emit_cstring("\tldr %r15, [%r12, #0]");
675 be_emit_finish_line_gas(NULL);
677 be_emit_irprintf("TABLE_%d_START:\n\t.word\tTABLE_%d", block_nr, block_nr);
678 be_emit_finish_line_gas(NULL);
679 be_emit_irprintf("\t.align 2");
680 be_emit_finish_line_gas(NULL);
681 be_emit_irprintf("TABLE_%d:", block_nr);
682 be_emit_finish_line_gas(NULL);
684 for (i = 0; i < n_projs; ++i) {
687 proj = projs[get_arm_SwitchJmp_default_proj_num(irn)];
689 be_emit_cstring("\t.word\t");
690 arm_emit_cfop_target(proj);
691 be_emit_finish_line_gas(proj);
693 be_emit_irprintf("\t.align 2\n");
694 be_emit_finish_line_gas(NULL);
698 /************************************************************************/
700 /************************************************************************/
702 static void emit_be_Call(const ir_node *irn) {
703 ir_entity *ent = be_Call_get_entity(irn);
705 be_emit_cstring("\tbl ");
707 set_entity_backend_marked(ent, 1);
708 be_emit_ident(get_entity_ld_ident(ent));
710 arm_emit_source_register(irn, be_pos_Call_ptr);
712 be_emit_finish_line_gas(irn);
715 /** Emit an IncSP node */
716 static void emit_be_IncSP(const ir_node *irn) {
717 int offs = be_get_IncSP_offset(irn);
720 be_emit_cstring("\tadd ");
721 arm_emit_dest_register(irn, 0);
722 be_emit_cstring(", ");
723 arm_emit_source_register(irn, 0);
724 be_emit_cstring(", #");
725 arm_emit_offset(irn);
727 be_emit_cstring("\t/* omitted IncSP(");
728 arm_emit_offset(irn);
729 be_emit_cstring(") */");
731 be_emit_finish_line_gas(irn);
734 static void emit_be_Copy(const ir_node *irn) {
735 ir_mode *mode = get_irn_mode(irn);
737 if (get_in_reg(irn, 0) == get_out_reg(irn, 0)) {
738 be_emit_cstring("\t/* omitted Copy: ");
739 arm_emit_source_register(irn, 0);
740 be_emit_cstring(" -> ");
741 arm_emit_dest_register(irn, 0);
742 be_emit_finish_line_gas(irn);
746 if (mode_is_float(mode)) {
748 be_emit_cstring("\tmvf");
751 arm_emit_dest_register(irn, 0);
752 be_emit_cstring(", ");
753 arm_emit_source_register(irn, 0);
754 be_emit_finish_line_gas(irn);
756 assert(0 && "move not supported for this mode");
757 panic("emit_be_Copy: move not supported for this mode");
759 } else if (mode_is_data(mode)) {
760 be_emit_cstring("\tmov ");
761 arm_emit_dest_register(irn, 0);
762 be_emit_cstring(", ");
763 arm_emit_source_register(irn, 0);
764 be_emit_finish_line_gas(irn);
766 assert(0 && "move not supported for this mode");
767 panic("emit_be_Copy: move not supported for this mode");
772 * Emit code for a Spill.
774 static void emit_be_Spill(const ir_node *irn) {
775 ir_mode *mode = get_irn_mode(be_get_Spill_val(irn));
777 if (mode_is_float(mode)) {
778 if (USE_FPA(cg->isa)) {
779 be_emit_cstring("\tstf");
780 arm_emit_fpa_postfix(mode);
783 assert(0 && "spill not supported for this mode");
784 panic("emit_be_Spill: spill not supported for this mode");
786 } else if (mode_is_dataM(mode)) {
787 be_emit_cstring("\tstr ");
789 assert(0 && "spill not supported for this mode");
790 panic("emit_be_Spill: spill not supported for this mode");
792 arm_emit_source_register(irn, 1);
793 be_emit_cstring(", [");
794 arm_emit_source_register(irn, 0);
795 be_emit_cstring(", #");
796 arm_emit_offset(irn);
798 be_emit_finish_line_gas(irn);
802 * Emit code for a Reload.
804 static void emit_be_Reload(const ir_node *irn) {
805 ir_mode *mode = get_irn_mode(irn);
807 if (mode_is_float(mode)) {
808 if (USE_FPA(cg->isa)) {
809 be_emit_cstring("\tldf");
810 arm_emit_fpa_postfix(mode);
813 assert(0 && "reload not supported for this mode");
814 panic("emit_be_Reload: reload not supported for this mode");
816 } else if (mode_is_dataM(mode)) {
817 be_emit_cstring("\tldr ");
819 assert(0 && "reload not supported for this mode");
820 panic("emit_be_Reload: reload not supported for this mode");
822 arm_emit_dest_register(irn, 0);
823 be_emit_cstring(", [");
824 arm_emit_source_register(irn, 0);
825 be_emit_cstring(", #");
826 arm_emit_offset(irn);
828 be_emit_finish_line_gas(irn);
831 static void emit_be_Perm(const ir_node *irn) {
832 be_emit_cstring("\teor ");
833 arm_emit_source_register(irn, 0);
834 be_emit_cstring(", ");
835 arm_emit_source_register(irn, 0);
836 be_emit_cstring(", ");
837 arm_emit_source_register(irn, 1);
838 be_emit_finish_line_gas(NULL);
840 be_emit_cstring("\teor ");
841 arm_emit_source_register(irn, 1);
842 be_emit_cstring(", ");
843 arm_emit_source_register(irn, 0);
844 be_emit_cstring(", ");
845 arm_emit_source_register(irn, 1);
846 be_emit_finish_line_gas(NULL);
848 be_emit_cstring("\teor ");
849 arm_emit_source_register(irn, 0);
850 be_emit_cstring(", ");
851 arm_emit_source_register(irn, 0);
852 be_emit_cstring(", ");
853 arm_emit_source_register(irn, 1);
854 be_emit_finish_line_gas(irn);
857 /************************************************************************/
859 /************************************************************************/
861 static void emit_Jmp(const ir_node *node) {
862 ir_node *block, *next_block;
864 /* for now, the code works for scheduled and non-schedules blocks */
865 block = get_nodes_block(node);
867 /* we have a block schedule */
868 next_block = sched_next_block(block);
869 if (get_cfop_target_block(node) != next_block) {
870 be_emit_cstring("\tb ");
871 arm_emit_cfop_target(node);
873 be_emit_cstring("\t/* fallthrough to ");
874 arm_emit_cfop_target(node);
875 be_emit_cstring(" */");
877 be_emit_finish_line_gas(node);
880 static void emit_arm_fpaDbl2GP(const ir_node *irn) {
881 be_emit_cstring("\tstfd ");
882 arm_emit_source_register(irn, 0);
883 be_emit_cstring(", [sp, #-8]!");
884 be_emit_pad_comment();
885 be_emit_cstring("/* Push fp to stack */");
886 be_emit_finish_line_gas(NULL);
888 be_emit_cstring("\tldmfd sp!, {");
889 arm_emit_dest_register(irn, 1);
890 be_emit_cstring(", ");
891 arm_emit_dest_register(irn, 0);
893 be_emit_pad_comment();
894 be_emit_cstring("/* Pop destination */");
895 be_emit_finish_line_gas(irn);
898 static void emit_arm_LdTls(const ir_node *irn) {
900 panic("TLS not supported for this target\n");
901 /* Er... our gcc does not support it... Install a newer toolchain. */
904 /***********************************************************************************
907 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
908 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
909 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
910 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
912 ***********************************************************************************/
914 static void emit_silence(const ir_node *irn) {
920 * The type of a emitter function.
922 typedef void (emit_func)(const ir_node *irn);
925 * Set a node emitter. Make it a bit more type safe.
927 static INLINE void set_emitter(ir_op *op, emit_func arm_emit_node) {
928 op->ops.generic = (op_func)arm_emit_node;
932 * Enters the emitter functions for handled nodes into the generic
933 * pointer of an opcode.
935 static void arm_register_emitters(void) {
937 #define ARM_EMIT(a) set_emitter(op_arm_##a, emit_arm_##a)
938 #define EMIT(a) set_emitter(op_##a, emit_##a)
939 #define BE_EMIT(a) set_emitter(op_be_##a, emit_be_##a)
940 #define SILENCE(a) set_emitter(op_##a, emit_silence)
942 /* first clear the generic function pointer for all ops */
943 clear_irp_opcodes_generic_func();
945 /* register all emitter functions defined in spec */
946 arm_register_spec_emitters();
948 /* other emitter functions */
951 ARM_EMIT(fpaCmfeBra);
953 // ARM_EMIT(CopyB_i);
978 SILENCE(be_CopyKeep);
979 SILENCE(be_RegParams);
991 * Emits code for a node.
993 static void arm_emit_node(const ir_node *irn) {
994 ir_op *op = get_irn_op(irn);
996 if (op->ops.generic) {
997 emit_func *emit = (emit_func *)op->ops.generic;
998 be_dbg_set_dbg_info(get_irn_dbg_info(irn));
1001 be_emit_cstring("\t/* TODO */");
1002 be_emit_finish_line_gas(irn);
1007 * emit the block label if needed.
1009 static void arm_emit_block_header(ir_node *block, ir_node *prev)
1014 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1017 n_cfgpreds = get_Block_n_cfgpreds(block);
1018 if (n_cfgpreds == 1) {
1019 ir_node *pred = get_Block_cfgpred(block, 0);
1020 ir_node *pred_block = get_nodes_block(pred);
1022 /* we don't need labels for fallthrough blocks, however switch-jmps
1023 * are no fallthroughs */
1024 if (pred_block == prev &&
1025 !(is_Proj(pred) && is_arm_SwitchJmp(get_Proj_pred(pred)))) {
1035 arm_emit_block_name(block);
1038 be_emit_pad_comment();
1039 be_emit_cstring(" /* preds:");
1041 /* emit list of pred blocks in comment */
1042 arity = get_irn_arity(block);
1043 for (i = 0; i < arity; ++i) {
1044 ir_node *predblock = get_Block_cfgpred_block(block, i);
1045 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1048 be_emit_cstring("\t/* ");
1049 arm_emit_block_name(block);
1050 be_emit_cstring(": ");
1052 if (exec_freq != NULL) {
1053 be_emit_irprintf(" freq: %f",
1054 get_block_execfreq(exec_freq, block));
1056 be_emit_cstring(" */\n");
1057 be_emit_write_line();
1061 * Walks over the nodes in a block connected by scheduling edges
1062 * and emits code for each node.
1064 static void arm_gen_block(ir_node *block, ir_node *prev_block) {
1067 arm_emit_block_header(block, prev_block);
1068 be_dbg_set_dbg_info(get_irn_dbg_info(block));
1069 sched_foreach(block, irn) {
1075 * Emits code for function start.
1077 void arm_func_prolog(ir_graph *irg) {
1078 ir_entity *ent = get_irg_entity(irg);
1079 const char *irg_name = get_entity_ld_name(ent);
1081 be_emit_write_line();
1082 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1083 be_emit_cstring("\t.align 2\n");
1085 if (get_entity_visibility(ent) == visibility_external_visible)
1086 be_emit_irprintf("\t.global %s\n", irg_name);
1087 be_emit_irprintf("%s:\n", irg_name);
1091 * Emits code for function end
1093 void arm_emit_end(FILE *F, ir_graph *irg) {
1095 fprintf(F, "\t.ident \"firmcc\"\n");
1100 * Sets labels for control flow nodes (jump target)
1102 static void arm_gen_labels(ir_node *block, void *env) {
1104 int n = get_Block_n_cfgpreds(block);
1107 for (n--; n >= 0; n--) {
1108 pred = get_Block_cfgpred(block, n);
1109 set_irn_link(pred, block);
1114 * Compare two entries of the symbol or tarval set.
1116 static int cmp_sym_or_tv(const void *elt, const void *key, size_t size) {
1117 const sym_or_tv_t *p1 = elt;
1118 const sym_or_tv_t *p2 = key;
1121 /* as an identifier NEVER can point to a tarval, it's enough
1122 to compare it this way */
1123 return p1->u.generic != p2->u.generic;
1127 * Main driver. Emits the code for one routine.
1129 void arm_gen_routine(const arm_code_gen_t *arm_cg, ir_graph *irg) {
1130 ir_node **blk_sched;
1132 ir_node *last_block = NULL;
1135 isa = (const arm_isa_t *)cg->arch_env;
1136 arch_env = cg->arch_env;
1137 sym_or_tv = new_set(cmp_sym_or_tv, 8);
1139 arm_register_emitters();
1141 /* create the block schedule. For now, we don't need it earlier. */
1142 blk_sched = be_create_block_schedule(cg->irg, cg->birg->exec_freq);
1144 arm_func_prolog(irg);
1145 irg_block_walk_graph(irg, arm_gen_labels, NULL, NULL);
1147 n = ARR_LEN(blk_sched);
1148 for (i = 0; i < n;) {
1149 ir_node *block, *next_bl;
1151 block = blk_sched[i];
1153 next_bl = i < n ? blk_sched[i] : NULL;
1155 /* set here the link. the emitter expects to find the next block here */
1156 set_irn_link(block, next_bl);
1157 arm_gen_block(block, last_block);
1161 /* emit SymConst values */
1162 if (set_count(sym_or_tv) > 0) {
1165 be_emit_cstring("\t.align 2\n");
1167 foreach_set(sym_or_tv, entry) {
1168 be_emit_irprintf(".L%u:\n", entry->label);
1170 if (entry->is_ident) {
1171 be_emit_cstring("\t.word\t");
1172 be_emit_ident(entry->u.id);
1174 be_emit_write_line();
1176 tarval *tv = entry->u.tv;
1177 int i, size = get_mode_size_bytes(get_tarval_mode(tv));
1180 /* beware: ARM fpa uses big endian format */
1181 for (i = ((size + 3) & ~3) - 4; i >= 0; i -= 4) {
1183 v = get_tarval_sub_bits(tv, i+3);
1184 v = (v << 8) | get_tarval_sub_bits(tv, i+2);
1185 v = (v << 8) | get_tarval_sub_bits(tv, i+1);
1186 v = (v << 8) | get_tarval_sub_bits(tv, i+0);
1187 be_emit_irprintf("\t.word\t%u\n", v);
1188 be_emit_write_line();
1193 be_emit_write_line();
1198 void arm_init_emitter(void)
1200 FIRM_DBG_REGISTER(dbg, "firm.be.arm.emit");