2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
42 #include "raw_bitset.h"
45 #include "../besched.h"
46 #include "../beblocksched.h"
48 #include "../begnuas.h"
49 #include "../be_dbgout.h"
51 #include "arm_emitter.h"
52 #include "arm_optimize.h"
53 #include "gen_arm_emitter.h"
54 #include "arm_nodes_attr.h"
55 #include "arm_new_nodes.h"
56 #include "arm_map_regs.h"
57 #include "gen_arm_regalloc_if.h"
59 #include "../benode.h"
61 #define SNPRINTF_BUF_LEN 128
63 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
65 static set *sym_or_tv;
66 static arm_isa_t *isa;
69 * Returns the register at in position pos.
71 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
74 const arch_register_t *reg = NULL;
76 assert(get_irn_arity(irn) > pos && "Invalid IN position");
78 /* The out register of the operator at position pos is the
79 in register we need. */
80 op = get_irn_n(irn, pos);
82 reg = arch_get_irn_register(op);
84 assert(reg && "no in register found");
86 /* in case of a joker register: just return a valid register */
87 if (reg->type & arch_register_type_joker) {
88 const arch_register_req_t *req = arch_get_register_req(irn, pos);
90 if (arch_register_req_is(req, limited)) {
91 /* in case of limited requirements: get the first allowed register */
92 unsigned idx = rbitset_next(req->limited, 0, 1);
93 reg = arch_register_for_index(req->cls, idx);
95 /* otherwise get first register in class */
96 reg = arch_register_for_index(req->cls, 0);
104 * Returns the register at out position pos.
106 static const arch_register_t *get_out_reg(const ir_node *node, int pos)
109 const arch_register_t *reg = NULL;
111 /* 1st case: irn is not of mode_T, so it has only */
112 /* one OUT register -> good */
113 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
114 /* Proj with the corresponding projnum for the register */
116 if (get_irn_mode(node) != mode_T) {
117 reg = arch_get_irn_register(node);
118 } else if (is_arm_irn(node)) {
119 reg = arch_irn_get_register(node, pos);
121 const ir_edge_t *edge;
123 foreach_out_edge(node, edge) {
124 proj = get_edge_src_irn(edge);
125 assert(is_Proj(proj) && "non-Proj from mode_T node");
126 if (get_Proj_proj(proj) == pos) {
127 reg = arch_get_irn_register(proj);
133 assert(reg && "no out register found");
137 static void arm_emit_register(const arch_register_t *reg)
139 be_emit_string(arch_register_get_name(reg));
142 void arm_emit_source_register(const ir_node *node, int pos)
144 const arch_register_t *reg = get_in_reg(node, pos);
145 arm_emit_register(reg);
148 void arm_emit_dest_register(const ir_node *node, int pos)
150 const arch_register_t *reg = get_out_reg(node, pos);
151 arm_emit_register(reg);
154 void arm_emit_offset(const ir_node *node)
156 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
157 assert(attr->base.is_load_store);
159 be_emit_irprintf("0x%X", attr->offset);
163 * Emit the arm fpa instruction suffix depending on the mode.
165 static void arm_emit_fpa_postfix(const ir_mode *mode)
167 int bits = get_mode_size_bits(mode);
177 void arm_emit_float_load_store_mode(const ir_node *node)
179 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
180 arm_emit_fpa_postfix(attr->load_store_mode);
183 void arm_emit_float_arithmetic_mode(const ir_node *node)
185 const arm_farith_attr_t *attr = get_arm_farith_attr_const(node);
186 arm_emit_fpa_postfix(attr->mode);
189 void arm_emit_symconst(const ir_node *node)
191 const arm_SymConst_attr_t *symconst = get_arm_SymConst_attr_const(node);
192 ir_entity *entity = symconst->entity;
194 be_gas_emit_entity(entity);
196 /* TODO do something with offset */
199 void arm_emit_load_mode(const ir_node *node)
201 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
202 ir_mode *mode = attr->load_store_mode;
203 int bits = get_mode_size_bits(mode);
204 bool is_signed = mode_is_signed(mode);
206 be_emit_string(is_signed ? "sh" : "h");
207 } else if (bits == 8) {
208 be_emit_string(is_signed ? "sb" : "b");
214 void arm_emit_store_mode(const ir_node *node)
216 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
217 ir_mode *mode = attr->load_store_mode;
218 int bits = get_mode_size_bits(mode);
220 be_emit_cstring("h");
221 } else if (bits == 8) {
222 be_emit_cstring("b");
228 static void emit_shf_mod_name(arm_shift_modifier_t mod)
231 case ARM_SHF_ASR_REG:
232 case ARM_SHF_ASR_IMM:
233 be_emit_cstring("asr");
235 case ARM_SHF_LSL_REG:
236 case ARM_SHF_LSL_IMM:
237 be_emit_cstring("lsl");
239 case ARM_SHF_LSR_REG:
240 case ARM_SHF_LSR_IMM:
241 be_emit_cstring("lsr");
243 case ARM_SHF_ROR_REG:
244 case ARM_SHF_ROR_IMM:
245 be_emit_cstring("ror");
250 panic("can't emit this shf_mod_name %d", (int) mod);
253 void arm_emit_shifter_operand(const ir_node *node)
255 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(node);
257 switch (attr->shift_modifier) {
259 arm_emit_source_register(node, get_irn_arity(node) - 1);
262 unsigned val = attr->immediate_value;
263 val = (val >> attr->shift_immediate)
264 | (val << (32-attr->shift_immediate));
266 be_emit_irprintf("#0x%X", val);
269 case ARM_SHF_ASR_IMM:
270 case ARM_SHF_LSL_IMM:
271 case ARM_SHF_LSR_IMM:
272 case ARM_SHF_ROR_IMM:
273 arm_emit_source_register(node, get_irn_arity(node) - 1);
274 be_emit_cstring(", ");
275 emit_shf_mod_name(attr->shift_modifier);
276 be_emit_irprintf(" #0x%X", attr->shift_immediate);
279 case ARM_SHF_ASR_REG:
280 case ARM_SHF_LSL_REG:
281 case ARM_SHF_LSR_REG:
282 case ARM_SHF_ROR_REG:
283 arm_emit_source_register(node, get_irn_arity(node) - 2);
284 be_emit_cstring(", ");
285 emit_shf_mod_name(attr->shift_modifier);
286 be_emit_cstring(" ");
287 arm_emit_source_register(node, get_irn_arity(node) - 1);
291 arm_emit_source_register(node, get_irn_arity(node) - 1);
292 panic("RRX shifter emitter TODO");
294 case ARM_SHF_INVALID:
297 panic("Invalid shift_modifier while emitting %+F", node);
300 /** An entry in the sym_or_tv set. */
301 typedef struct sym_or_tv_t {
303 ir_entity *entity; /**< An entity. */
304 ir_tarval *tv; /**< A tarval. */
305 const void *generic; /**< For generic compare. */
307 unsigned label; /**< the associated label. */
308 bool is_entity; /**< true if an entity is stored. */
312 * Returns a unique label. This number will not be used a second time.
314 static unsigned get_unique_label(void)
316 static unsigned id = 0;
320 static void emit_constant_name(const sym_or_tv_t *entry)
322 be_emit_irprintf("%sC%u", be_gas_get_private_prefix(), entry->label);
328 static void emit_arm_SymConst(const ir_node *irn)
330 const arm_SymConst_attr_t *attr = get_arm_SymConst_attr_const(irn);
331 sym_or_tv_t key, *entry;
333 key.u.entity = attr->entity;
334 key.is_entity = true;
336 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
337 if (entry->label == 0) {
338 /* allocate a label */
339 entry->label = get_unique_label();
342 /* load the symbol indirect */
343 be_emit_cstring("\tldr ");
344 arm_emit_dest_register(irn, 0);
345 be_emit_cstring(", ");
346 emit_constant_name(entry);
347 be_emit_finish_line_gas(irn);
350 static void emit_arm_FrameAddr(const ir_node *irn)
352 const arm_SymConst_attr_t *attr = get_arm_SymConst_attr_const(irn);
354 be_emit_cstring("\tadd ");
355 arm_emit_dest_register(irn, 0);
356 be_emit_cstring(", ");
357 arm_emit_source_register(irn, 0);
358 be_emit_cstring(", ");
359 be_emit_irprintf("#0x%X", attr->fp_offset);
360 be_emit_finish_line_gas(irn);
364 * Emit a floating point fpa constant.
366 static void emit_arm_fConst(const ir_node *irn)
368 sym_or_tv_t key, *entry;
371 key.u.tv = get_fConst_value(irn);
372 key.is_entity = false;
374 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
375 if (entry->label == 0) {
376 /* allocate a label */
377 entry->label = get_unique_label();
380 /* load the tarval indirect */
381 mode = get_irn_mode(irn);
382 be_emit_cstring("\tldf");
383 arm_emit_fpa_postfix(mode);
386 arm_emit_dest_register(irn, 0);
387 be_emit_cstring(", ");
388 emit_constant_name(entry);
389 be_emit_finish_line_gas(irn);
393 * Returns the next block in a block schedule.
395 static ir_node *sched_next_block(const ir_node *block)
397 return (ir_node*)get_irn_link(block);
401 * Returns the target block for a control flow node.
403 static ir_node *get_cfop_target_block(const ir_node *irn)
405 return (ir_node*)get_irn_link(irn);
409 * Emit the target label for a control flow node.
411 static void arm_emit_cfop_target(const ir_node *irn)
413 ir_node *block = get_cfop_target_block(irn);
415 be_gas_emit_block_name(block);
419 * Emit a Compare with conditional branch.
421 static void emit_arm_B(const ir_node *irn)
423 const ir_edge_t *edge;
424 const ir_node *proj_true = NULL;
425 const ir_node *proj_false = NULL;
426 const ir_node *block;
427 const ir_node *next_block;
428 ir_node *op1 = get_irn_n(irn, 0);
430 ir_relation relation = get_arm_CondJmp_relation(irn);
431 const arm_cmp_attr_t *cmp_attr = get_arm_cmp_attr_const(op1);
432 bool is_signed = !cmp_attr->is_unsigned;
434 assert(is_arm_Cmp(op1) || is_arm_Tst(op1));
436 foreach_out_edge(irn, edge) {
437 ir_node *proj = get_edge_src_irn(edge);
438 long nr = get_Proj_proj(proj);
439 if (nr == pn_Cond_true) {
446 if (cmp_attr->ins_permuted) {
447 relation = get_inversed_relation(relation);
450 /* for now, the code works for scheduled and non-schedules blocks */
451 block = get_nodes_block(irn);
453 /* we have a block schedule */
454 next_block = sched_next_block(block);
456 assert(relation != ir_relation_false);
457 assert(relation != ir_relation_true);
459 if (get_cfop_target_block(proj_true) == next_block) {
460 /* exchange both proj's so the second one can be omitted */
461 const ir_node *t = proj_true;
463 proj_true = proj_false;
465 relation = get_negated_relation(relation);
468 switch (relation & (ir_relation_less_equal_greater)) {
469 case ir_relation_equal: suffix = "eq"; break;
470 case ir_relation_less: suffix = is_signed ? "lt" : "lo"; break;
471 case ir_relation_less_equal: suffix = is_signed ? "le" : "ls"; break;
472 case ir_relation_greater: suffix = is_signed ? "gt" : "hi"; break;
473 case ir_relation_greater_equal: suffix = is_signed ? "ge" : "hs"; break;
474 case ir_relation_less_greater: suffix = "ne"; break;
475 case ir_relation_less_equal_greater: suffix = "al"; break;
476 default: panic("Cmp has unsupported relation");
479 /* emit the true proj */
480 be_emit_irprintf("\tb%s ", suffix);
481 arm_emit_cfop_target(proj_true);
482 be_emit_finish_line_gas(proj_true);
484 if (get_cfop_target_block(proj_false) == next_block) {
485 be_emit_cstring("\t/* fallthrough to ");
486 arm_emit_cfop_target(proj_false);
487 be_emit_cstring(" */");
488 be_emit_finish_line_gas(proj_false);
490 be_emit_cstring("\tb ");
491 arm_emit_cfop_target(proj_false);
492 be_emit_finish_line_gas(proj_false);
496 /** Sort register in ascending order. */
497 static int reg_cmp(const void *a, const void *b)
499 const arch_register_t * const *ra = (const arch_register_t**)a;
500 const arch_register_t * const *rb = (const arch_register_t**)b;
502 return *ra < *rb ? -1 : (*ra != *rb);
506 * Create the CopyB instruction sequence.
508 static void emit_arm_CopyB(const ir_node *irn)
510 const arm_CopyB_attr_t *attr = get_arm_CopyB_attr_const(irn);
511 unsigned size = attr->size;
513 const char *tgt = arch_register_get_name(get_in_reg(irn, 0));
514 const char *src = arch_register_get_name(get_in_reg(irn, 1));
515 const char *t0, *t1, *t2, *t3;
517 const arch_register_t *tmpregs[4];
519 /* collect the temporary registers and sort them, we need ascending order */
520 tmpregs[0] = get_in_reg(irn, 2);
521 tmpregs[1] = get_in_reg(irn, 3);
522 tmpregs[2] = get_in_reg(irn, 4);
523 tmpregs[3] = &arm_registers[REG_R12];
525 /* Note: R12 is always the last register because the RA did not assign higher ones */
526 qsort((void *)tmpregs, 3, sizeof(tmpregs[0]), reg_cmp);
528 /* need ascending order */
529 t0 = arch_register_get_name(tmpregs[0]);
530 t1 = arch_register_get_name(tmpregs[1]);
531 t2 = arch_register_get_name(tmpregs[2]);
532 t3 = arch_register_get_name(tmpregs[3]);
534 be_emit_cstring("/* MemCopy (");
536 be_emit_cstring(")->(");
537 arm_emit_source_register(irn, 0);
538 be_emit_irprintf(" [%u bytes], Uses ", size);
540 be_emit_cstring(", ");
542 be_emit_cstring(", ");
544 be_emit_cstring(", and ");
546 be_emit_cstring("*/");
547 be_emit_finish_line_gas(NULL);
549 assert(size > 0 && "CopyB needs size > 0" );
552 fprintf(stderr, "strange hack enabled: copy more bytes than needed!");
561 be_emit_cstring("\tldr ");
563 be_emit_cstring(", [");
565 be_emit_cstring(", #0]");
566 be_emit_finish_line_gas(NULL);
568 be_emit_cstring("\tstr ");
570 be_emit_cstring(", [");
572 be_emit_cstring(", #0]");
573 be_emit_finish_line_gas(irn);
576 be_emit_cstring("\tldmia ");
578 be_emit_cstring("!, {");
580 be_emit_cstring(", ");
583 be_emit_finish_line_gas(NULL);
585 be_emit_cstring("\tstmia ");
587 be_emit_cstring("!, {");
589 be_emit_cstring(", ");
592 be_emit_finish_line_gas(irn);
595 be_emit_cstring("\tldmia ");
597 be_emit_cstring("!, {");
599 be_emit_cstring(", ");
601 be_emit_cstring(", ");
604 be_emit_finish_line_gas(NULL);
606 be_emit_cstring("\tstmia ");
608 be_emit_cstring("!, {");
610 be_emit_cstring(", ");
612 be_emit_cstring(", ");
615 be_emit_finish_line_gas(irn);
620 be_emit_cstring("\tldmia ");
622 be_emit_cstring("!, {");
624 be_emit_cstring(", ");
626 be_emit_cstring(", ");
628 be_emit_cstring(", ");
631 be_emit_finish_line_gas(NULL);
633 be_emit_cstring("\tstmia ");
635 be_emit_cstring("!, {");
637 be_emit_cstring(", ");
639 be_emit_cstring(", ");
641 be_emit_cstring(", ");
644 be_emit_finish_line_gas(irn);
649 static void emit_arm_SwitchJmp(const ir_node *irn)
651 const ir_edge_t *edge;
657 ir_node *default_proj = NULL;
659 block_nr = get_irn_node_nr(irn);
660 n_projs = get_arm_SwitchJmp_n_projs(irn);
662 projs = XMALLOCNZ(ir_node*, n_projs);
664 foreach_out_edge(irn, edge) {
665 proj = get_edge_src_irn(edge);
666 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
668 if (get_Proj_proj(proj) == get_arm_SwitchJmp_default_proj_num(irn))
671 projs[get_Proj_proj(proj)] = proj;
673 assert(default_proj != NULL && "SwitchJmp should have a Default Proj");
680 be_emit_cstring("\tcmp ");
681 arm_emit_source_register(irn, 0);
682 be_emit_irprintf(", #%u", n_projs - 1);
683 be_emit_finish_line_gas(irn);
685 be_emit_cstring("\tbhi ");
686 arm_emit_cfop_target(default_proj);
687 be_emit_finish_line_gas(default_proj);
690 LDR %r12, .TABLE_X_START
691 ADD %r12, %r12, [%1S, LSL #2]
695 be_emit_irprintf("\tldr %%r12, TABLE_%d_START", block_nr);
696 be_emit_finish_line_gas(NULL);
698 be_emit_irprintf("\tadd %%r12, %%r12, ");
699 arm_emit_source_register(irn, 0);
700 be_emit_cstring(", LSL #2");
701 be_emit_finish_line_gas(NULL);
703 be_emit_cstring("\tldr %r15, [%r12, #0]");
704 be_emit_finish_line_gas(NULL);
706 be_emit_irprintf("TABLE_%d_START:\n\t.word\tTABLE_%d", block_nr, block_nr);
707 be_emit_finish_line_gas(NULL);
708 be_emit_irprintf("\t.align 2");
709 be_emit_finish_line_gas(NULL);
710 be_emit_irprintf("TABLE_%d:", block_nr);
711 be_emit_finish_line_gas(NULL);
713 for (i = 0; i < n_projs; ++i) {
716 proj = projs[get_arm_SwitchJmp_default_proj_num(irn)];
718 be_emit_cstring("\t.word\t");
719 arm_emit_cfop_target(proj);
720 be_emit_finish_line_gas(proj);
722 be_emit_irprintf("\t.align 2\n");
723 be_emit_finish_line_gas(NULL);
727 /** Emit an IncSP node */
728 static void emit_be_IncSP(const ir_node *irn)
730 int offs = -be_get_IncSP_offset(irn);
734 be_emit_cstring("\tsub ");
737 be_emit_cstring("\tadd ");
739 arm_emit_dest_register(irn, 0);
740 be_emit_cstring(", ");
741 arm_emit_source_register(irn, 0);
742 be_emit_irprintf(", #0x%X", offs);
743 be_emit_finish_line_gas(irn);
745 /* omitted IncSP(0) */
750 static void emit_be_Copy(const ir_node *irn)
752 ir_mode *mode = get_irn_mode(irn);
754 if (get_in_reg(irn, 0) == get_out_reg(irn, 0)) {
759 if (mode_is_float(mode)) {
761 be_emit_cstring("\tmvf");
763 arm_emit_dest_register(irn, 0);
764 be_emit_cstring(", ");
765 arm_emit_source_register(irn, 0);
766 be_emit_finish_line_gas(irn);
768 panic("emit_be_Copy: move not supported for this mode");
770 } else if (mode_is_data(mode)) {
771 be_emit_cstring("\tmov ");
772 arm_emit_dest_register(irn, 0);
773 be_emit_cstring(", ");
774 arm_emit_source_register(irn, 0);
775 be_emit_finish_line_gas(irn);
777 panic("emit_be_Copy: move not supported for this mode");
781 static void emit_be_Perm(const ir_node *irn)
783 be_emit_cstring("\teor ");
784 arm_emit_source_register(irn, 0);
785 be_emit_cstring(", ");
786 arm_emit_source_register(irn, 0);
787 be_emit_cstring(", ");
788 arm_emit_source_register(irn, 1);
789 be_emit_finish_line_gas(NULL);
791 be_emit_cstring("\teor ");
792 arm_emit_source_register(irn, 1);
793 be_emit_cstring(", ");
794 arm_emit_source_register(irn, 0);
795 be_emit_cstring(", ");
796 arm_emit_source_register(irn, 1);
797 be_emit_finish_line_gas(NULL);
799 be_emit_cstring("\teor ");
800 arm_emit_source_register(irn, 0);
801 be_emit_cstring(", ");
802 arm_emit_source_register(irn, 0);
803 be_emit_cstring(", ");
804 arm_emit_source_register(irn, 1);
805 be_emit_finish_line_gas(irn);
808 static void emit_be_MemPerm(const ir_node *node)
814 /* TODO: this implementation is slower than necessary.
815 The longterm goal is however to avoid the memperm node completely */
817 memperm_arity = be_get_MemPerm_entity_arity(node);
818 if (memperm_arity > 12)
819 panic("memperm with more than 12 inputs not supported yet");
821 for (i = 0; i < memperm_arity; ++i) {
823 ir_entity *entity = be_get_MemPerm_in_entity(node, i);
826 be_emit_irprintf("\tstr r%d, [sp, #-4]!", i);
827 be_emit_finish_line_gas(node);
829 /* load from entity */
830 offset = get_entity_offset(entity) + sp_change;
831 be_emit_irprintf("\tldr r%d, [sp, #%d]", i, offset);
832 be_emit_finish_line_gas(node);
835 for (i = memperm_arity-1; i >= 0; --i) {
837 ir_entity *entity = be_get_MemPerm_out_entity(node, i);
839 /* store to new entity */
840 offset = get_entity_offset(entity) + sp_change;
841 be_emit_irprintf("\tstr r%d, [sp, #%d]", i, offset);
842 be_emit_finish_line_gas(node);
843 /* restore register */
844 be_emit_irprintf("\tldr r%d, [sp], #4", i);
846 be_emit_finish_line_gas(node);
848 assert(sp_change == 0);
851 static void emit_be_Start(const ir_node *node)
853 ir_graph *irg = get_irn_irg(node);
854 ir_type *frame_type = get_irg_frame_type(irg);
855 unsigned size = get_type_size_bytes(frame_type);
857 /* allocate stackframe */
859 be_emit_cstring("\tsub ");
860 arm_emit_register(&arm_registers[REG_SP]);
861 be_emit_cstring(", ");
862 arm_emit_register(&arm_registers[REG_SP]);
863 be_emit_irprintf(", #0x%X", size);
864 be_emit_finish_line_gas(node);
868 static void emit_be_Return(const ir_node *node)
870 ir_graph *irg = get_irn_irg(node);
871 ir_type *frame_type = get_irg_frame_type(irg);
872 unsigned size = get_type_size_bytes(frame_type);
874 /* deallocate stackframe */
876 be_emit_cstring("\tadd ");
877 arm_emit_register(&arm_registers[REG_SP]);
878 be_emit_cstring(", ");
879 arm_emit_register(&arm_registers[REG_SP]);
880 be_emit_irprintf(", #0x%X", size);
881 be_emit_finish_line_gas(node);
884 be_emit_cstring("\tmov pc, lr");
885 be_emit_finish_line_gas(node);
889 static void emit_arm_Jmp(const ir_node *node)
891 ir_node *block, *next_block;
893 /* for now, the code works for scheduled and non-schedules blocks */
894 block = get_nodes_block(node);
896 /* we have a block schedule */
897 next_block = sched_next_block(block);
898 if (get_cfop_target_block(node) != next_block) {
899 be_emit_cstring("\tb ");
900 arm_emit_cfop_target(node);
902 be_emit_cstring("\t/* fallthrough to ");
903 arm_emit_cfop_target(node);
904 be_emit_cstring(" */");
906 be_emit_finish_line_gas(node);
909 static void emit_nothing(const ir_node *irn)
915 * The type of a emitter function.
917 typedef void (emit_func)(const ir_node *irn);
920 * Set a node emitter. Make it a bit more type safe.
922 static inline void set_emitter(ir_op *op, emit_func arm_emit_node)
924 op->ops.generic = (op_func)arm_emit_node;
928 * Enters the emitter functions for handled nodes into the generic
929 * pointer of an opcode.
931 static void arm_register_emitters(void)
933 /* first clear the generic function pointer for all ops */
934 clear_irp_opcodes_generic_func();
936 /* register all emitter functions defined in spec */
937 arm_register_spec_emitters();
940 set_emitter(op_arm_B, emit_arm_B);
941 set_emitter(op_arm_CopyB, emit_arm_CopyB);
942 set_emitter(op_arm_fConst, emit_arm_fConst);
943 set_emitter(op_arm_FrameAddr, emit_arm_FrameAddr);
944 set_emitter(op_arm_Jmp, emit_arm_Jmp);
945 set_emitter(op_arm_SwitchJmp, emit_arm_SwitchJmp);
946 set_emitter(op_arm_SymConst, emit_arm_SymConst);
947 set_emitter(op_be_Copy, emit_be_Copy);
948 set_emitter(op_be_CopyKeep, emit_be_Copy);
949 set_emitter(op_be_IncSP, emit_be_IncSP);
950 set_emitter(op_be_MemPerm, emit_be_MemPerm);
951 set_emitter(op_be_Perm, emit_be_Perm);
952 set_emitter(op_be_Return, emit_be_Return);
953 set_emitter(op_be_Start, emit_be_Start);
955 /* no need to emit anything for the following nodes */
956 set_emitter(op_Phi, emit_nothing);
957 set_emitter(op_be_Keep, emit_nothing);
961 * Emits code for a node.
963 static void arm_emit_node(const ir_node *irn)
965 ir_op *op = get_irn_op(irn);
967 if (op->ops.generic) {
968 emit_func *emit = (emit_func *)op->ops.generic;
969 be_dbg_set_dbg_info(get_irn_dbg_info(irn));
972 panic("Error: No emit handler for node %+F (graph %+F)\n",
973 irn, current_ir_graph);
978 * emit the block label if needed.
980 static void arm_emit_block_header(ir_node *block, ir_node *prev)
985 ir_graph *irg = get_irn_irg(block);
986 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
989 n_cfgpreds = get_Block_n_cfgpreds(block);
990 if (n_cfgpreds == 1) {
991 ir_node *pred = get_Block_cfgpred(block, 0);
992 ir_node *pred_block = get_nodes_block(pred);
994 /* we don't need labels for fallthrough blocks, however switch-jmps
995 * are no fallthroughs */
996 if (pred_block == prev &&
997 !(is_Proj(pred) && is_arm_SwitchJmp(get_Proj_pred(pred)))) {
1007 be_gas_emit_block_name(block);
1010 be_emit_pad_comment();
1011 be_emit_cstring(" /* preds:");
1013 /* emit list of pred blocks in comment */
1014 arity = get_irn_arity(block);
1015 for (i = 0; i < arity; ++i) {
1016 ir_node *predblock = get_Block_cfgpred_block(block, i);
1017 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1020 be_emit_cstring("\t/* ");
1021 be_gas_emit_block_name(block);
1022 be_emit_cstring(": ");
1024 if (exec_freq != NULL) {
1025 be_emit_irprintf(" freq: %f",
1026 get_block_execfreq(exec_freq, block));
1028 be_emit_cstring(" */\n");
1029 be_emit_write_line();
1033 * Walks over the nodes in a block connected by scheduling edges
1034 * and emits code for each node.
1036 static void arm_gen_block(ir_node *block, ir_node *prev_block)
1040 arm_emit_block_header(block, prev_block);
1041 be_dbg_set_dbg_info(get_irn_dbg_info(block));
1042 sched_foreach(block, irn) {
1049 * Sets labels for control flow nodes (jump target)
1051 static void arm_gen_labels(ir_node *block, void *env)
1054 int n = get_Block_n_cfgpreds(block);
1057 for (n--; n >= 0; n--) {
1058 pred = get_Block_cfgpred(block, n);
1059 set_irn_link(pred, block);
1064 * Compare two entries of the symbol or tarval set.
1066 static int cmp_sym_or_tv(const void *elt, const void *key, size_t size)
1068 const sym_or_tv_t *p1 = (const sym_or_tv_t*)elt;
1069 const sym_or_tv_t *p2 = (const sym_or_tv_t*)key;
1072 /* as an identifier NEVER can point to a tarval, it's enough
1073 to compare it this way */
1074 return p1->u.generic != p2->u.generic;
1077 void arm_gen_routine(ir_graph *irg)
1079 ir_node *last_block = NULL;
1080 ir_entity *entity = get_irg_entity(irg);
1081 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1082 ir_node **blk_sched;
1085 isa = (arm_isa_t*) arch_env;
1086 sym_or_tv = new_set(cmp_sym_or_tv, 8);
1088 be_gas_elf_type_char = '%';
1090 arm_register_emitters();
1092 be_dbg_method_begin(entity);
1094 /* create the block schedule */
1095 blk_sched = be_create_block_schedule(irg);
1097 be_gas_emit_function_prolog(entity, 4);
1099 irg_block_walk_graph(irg, arm_gen_labels, NULL, NULL);
1101 n = ARR_LEN(blk_sched);
1102 for (i = 0; i < n;) {
1103 ir_node *block, *next_bl;
1105 block = blk_sched[i];
1107 next_bl = i < n ? blk_sched[i] : NULL;
1109 /* set here the link. the emitter expects to find the next block here */
1110 set_irn_link(block, next_bl);
1111 arm_gen_block(block, last_block);
1115 /* emit SymConst values */
1116 if (set_count(sym_or_tv) > 0) {
1119 be_emit_cstring("\t.align 2\n");
1121 foreach_set(sym_or_tv, sym_or_tv_t*, entry) {
1122 emit_constant_name(entry);
1123 be_emit_cstring(":\n");
1124 be_emit_write_line();
1126 if (entry->is_entity) {
1127 be_emit_cstring("\t.word\t");
1128 be_gas_emit_entity(entry->u.entity);
1130 be_emit_write_line();
1132 ir_tarval *tv = entry->u.tv;
1134 int size = get_mode_size_bytes(get_tarval_mode(tv));
1136 /* beware: ARM fpa uses big endian format */
1137 for (vi = ((size + 3) & ~3) - 4; vi >= 0; vi -= 4) {
1140 v = get_tarval_sub_bits(tv, vi+3);
1141 v = (v << 8) | get_tarval_sub_bits(tv, vi+2);
1142 v = (v << 8) | get_tarval_sub_bits(tv, vi+1);
1143 v = (v << 8) | get_tarval_sub_bits(tv, vi+0);
1144 be_emit_irprintf("\t.word\t%u\n", v);
1145 be_emit_write_line();
1150 be_emit_write_line();
1154 be_gas_emit_function_epilog(entity);
1155 be_dbg_method_end();
1158 void arm_init_emitter(void)
1160 FIRM_DBG_REGISTER(dbg, "firm.be.arm.emit");