2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
45 #include "raw_bitset.h"
47 #include "../besched.h"
48 #include "../beblocksched.h"
49 #include "../beirg_t.h"
50 #include "../begnuas.h"
52 #include "arm_emitter.h"
53 #include "gen_arm_emitter.h"
54 #include "arm_nodes_attr.h"
55 #include "arm_new_nodes.h"
56 #include "arm_map_regs.h"
57 #include "gen_arm_regalloc_if.h"
59 #include "../benode_t.h"
61 #define BLOCK_PREFIX ".L"
63 #define SNPRINTF_BUF_LEN 128
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 static const arch_env_t *arch_env = NULL;
68 static const arm_code_gen_t *cg;
69 static const arm_isa_t *isa;
70 static set *sym_or_tv;
73 * Returns the register at in position pos.
75 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
77 const arch_register_t *reg = NULL;
79 assert(get_irn_arity(irn) > pos && "Invalid IN position");
81 /* The out register of the operator at position pos is the
82 in register we need. */
83 op = get_irn_n(irn, pos);
85 reg = arch_get_irn_register(arch_env, op);
87 assert(reg && "no in register found");
89 /* in case of a joker register: just return a valid register */
90 if (arch_register_type_is(reg, joker)) {
91 const arch_register_req_t *req;
93 /* ask for the requirements */
94 req = arch_get_register_req(arch_env, irn, pos);
96 if (arch_register_req_is(req, limited)) {
97 /* in case of limited requirements: get the first allowed register */
98 unsigned idx = rbitset_next(req->limited, 0, 1);
99 reg = arch_register_for_index(req->cls, idx);
101 /* otherwise get first register in class */
102 reg = arch_register_for_index(req->cls, 0);
110 * Returns the register at out position pos.
112 static const arch_register_t *get_out_reg(const ir_node *node, int pos)
115 const arch_register_t *reg = NULL;
117 /* 1st case: irn is not of mode_T, so it has only */
118 /* one OUT register -> good */
119 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
120 /* Proj with the corresponding projnum for the register */
122 if (get_irn_mode(node) != mode_T) {
123 reg = arch_get_irn_register(arch_env, node);
124 } else if (is_arm_irn(node)) {
125 reg = get_arm_out_reg(node, pos);
127 const ir_edge_t *edge;
129 foreach_out_edge(node, edge) {
130 proj = get_edge_src_irn(edge);
131 assert(is_Proj(proj) && "non-Proj from mode_T node");
132 if (get_Proj_proj(proj) == pos) {
133 reg = arch_get_irn_register(arch_env, proj);
139 assert(reg && "no out register found");
143 /*************************************************************
145 * (_) | | / _| | | | |
146 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
147 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
148 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
149 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
152 *************************************************************/
155 * Emit the name of the source register at given input position.
157 void arm_emit_source_register(const ir_node *node, int pos) {
158 const arch_register_t *reg = get_in_reg(node, pos);
159 be_emit_string(arch_register_get_name(reg));
163 * Emit the name of the destination register at given output position.
165 void arm_emit_dest_register(const ir_node *node, int pos) {
166 const arch_register_t *reg = get_out_reg(node, pos);
167 be_emit_string(arch_register_get_name(reg));
171 * Emit a node's offset.
173 void arm_emit_offset(const ir_node *node) {
175 ir_op *irn_op = get_irn_op(node);
177 if (irn_op == op_be_Reload || irn_op == op_be_Spill) {
178 ir_entity *ent = be_get_frame_entity(node);
179 offset = get_entity_offset(ent);
180 } else if (irn_op == op_be_IncSP) {
181 offset = - be_get_IncSP_offset(node);
183 assert(!"unimplemented arm_emit_offset for this node type");
184 panic("unimplemented arm_emit_offset for this node type");
186 be_emit_irprintf("%d", offset);
190 * Emit the arm fpa instruction suffix depending on the mode.
192 static void arm_emit_fpa_postfix(const ir_mode *mode) {
193 int bits = get_mode_size_bits(mode);
203 * Emit the instruction suffix depending on the mode.
205 void arm_emit_mode(const ir_node *node) {
208 if (is_arm_irn(node)) {
209 const arm_attr_t *attr = get_arm_attr_const(node);
210 mode = attr->op_mode ? attr->op_mode : get_irn_mode(node);
212 mode = get_irn_mode(node);
214 arm_emit_fpa_postfix(mode);
218 * Emit a const or SymConst value.
220 void arm_emit_immediate(const ir_node *node) {
221 const arm_attr_t *attr = get_arm_attr_const(node);
223 if (ARM_GET_SHF_MOD(attr) == ARM_SHF_IMM) {
224 be_emit_irprintf("#0x%X", arm_decode_imm_w_shift(get_arm_value(node)));
225 } else if (ARM_GET_FPA_IMM(attr)) {
226 be_emit_irprintf("#0x%F", get_arm_value(node));
227 } else if (is_arm_SymConst(node))
228 be_emit_ident(get_arm_symconst_id(node));
230 assert(!"not a Constant");
235 * Returns the tarval or offset of an arm node as a string.
237 void arm_emit_shift(const ir_node *node) {
238 arm_shift_modifier mod;
240 mod = get_arm_shift_modifier(node);
241 if (ARM_HAS_SHIFT(mod)) {
242 long v = get_tarval_long(get_arm_value(node));
244 be_emit_irprintf(", %s #%l", arm_shf_mod_name(mod), v);
248 /** An entry in the sym_or_tv set. */
249 typedef struct sym_or_tv_t {
251 ident *id; /**< An ident. */
252 tarval *tv; /**< A tarval. */
253 const void *generic; /**< For generic compare. */
255 unsigned label; /**< the associated label. */
256 char is_ident; /**< Non-zero if an ident is stored. */
260 * Returns a unique label. This number will not be used a second time.
262 static unsigned get_unique_label(void) {
263 static unsigned id = 0;
270 static void emit_arm_SymConst(const ir_node *irn) {
271 sym_or_tv_t key, *entry;
274 key.u.id = get_arm_symconst_id(irn);
277 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
278 if (entry->label == 0) {
279 /* allocate a label */
280 entry->label = get_unique_label();
282 label = entry->label;
284 /* load the symbol indirect */
285 be_emit_cstring("\tldr ");
286 arm_emit_dest_register(irn, 0);
287 be_emit_irprintf(", .L%u", label);
288 be_emit_finish_line_gas(irn);
292 * Emit a floating point fpa constant.
294 static void emit_arm_fpaConst(const ir_node *irn) {
295 sym_or_tv_t key, *entry;
299 key.u.tv = get_arm_value(irn);
302 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
303 if (entry->label == 0) {
304 /* allocate a label */
305 entry->label = get_unique_label();
307 label = entry->label;
309 /* load the tarval indirect */
310 mode = get_irn_mode(irn);
311 be_emit_cstring("\tldf");
312 arm_emit_fpa_postfix(mode);
315 arm_emit_dest_register(irn, 0);
316 be_emit_irprintf(", .L%u", label);
317 be_emit_finish_line_gas(irn);
321 * Returns the next block in a block schedule.
323 static ir_node *sched_next_block(const ir_node *block) {
324 return get_irn_link(block);
328 * Returns the target block for a control flow node.
330 static ir_node *get_cfop_target_block(const ir_node *irn) {
331 return get_irn_link(irn);
335 * Emits a block label for the given block.
337 static void arm_emit_block_name(const ir_node *block) {
338 if (has_Block_label(block)) {
339 be_emit_string(be_gas_label_prefix());
340 be_emit_irprintf("%lu", get_Block_label(block));
342 be_emit_cstring(BLOCK_PREFIX);
343 be_emit_irprintf("%d", get_irn_node_nr(block));
348 * Emit the target label for a control flow node.
350 static void arm_emit_cfop_target(const ir_node *irn) {
351 ir_node *block = get_cfop_target_block(irn);
353 arm_emit_block_name(block);
357 * Emit a Compare with conditional branch.
359 static void emit_arm_CmpBra(const ir_node *irn) {
360 const ir_edge_t *edge;
361 const ir_node *proj_true = NULL;
362 const ir_node *proj_false = NULL;
363 const ir_node *block;
364 const ir_node *next_block;
365 ir_node *op1 = get_irn_n(irn, 0);
366 ir_mode *opmode = get_irn_mode(op1);
368 int proj_num = get_arm_CondJmp_proj_num(irn);
370 foreach_out_edge(irn, edge) {
371 ir_node *proj = get_edge_src_irn(edge);
372 long nr = get_Proj_proj(proj);
373 if (nr == pn_Cond_true) {
380 /* for now, the code works for scheduled and non-schedules blocks */
381 block = get_nodes_block(irn);
383 /* we have a block schedule */
384 next_block = sched_next_block(block);
386 if (proj_num == pn_Cmp_False) {
387 /* always false: should not happen */
388 be_emit_cstring("\tb ");
389 arm_emit_cfop_target(proj_false);
390 be_emit_finish_line_gas(proj_false);
391 } else if (proj_num == pn_Cmp_True) {
392 /* always true: should not happen */
393 be_emit_cstring("\tb ");
394 arm_emit_cfop_target(proj_true);
395 be_emit_finish_line_gas(proj_true);
397 if (mode_is_float(opmode)) {
398 suffix = "ICHWILLIMPLEMENTIERTWERDEN";
400 be_emit_cstring("\tfcmp ");
401 arm_emit_source_register(irn, 0);
402 be_emit_cstring(", ");
403 arm_emit_source_register(irn, 1);
404 be_emit_finish_line_gas(irn);
406 be_emit_cstring("\tfmstat");
407 be_emit_pad_comment();
408 be_emit_cstring("/* FCSPR -> CPSR */");
409 be_emit_finish_line_gas(NULL);
411 if (get_cfop_target_block(proj_true) == next_block) {
412 /* exchange both proj's so the second one can be omitted */
413 const ir_node *t = proj_true;
415 proj_true = proj_false;
417 proj_num = get_negated_pnc(proj_num, mode_Iu);
420 case pn_Cmp_Eq: suffix = "eq"; break;
421 case pn_Cmp_Lt: suffix = "lt"; break;
422 case pn_Cmp_Le: suffix = "le"; break;
423 case pn_Cmp_Gt: suffix = "gt"; break;
424 case pn_Cmp_Ge: suffix = "ge"; break;
425 case pn_Cmp_Lg: suffix = "ne"; break;
426 case pn_Cmp_Leg: suffix = "al"; break;
427 default: assert(!"Cmp unsupported"); suffix = "al";
429 be_emit_cstring("\tcmp ");
430 arm_emit_source_register(irn, 0);
431 be_emit_cstring(", ");
432 arm_emit_source_register(irn, 1);
433 be_emit_finish_line_gas(irn);
436 /* emit the true proj */
437 be_emit_irprintf("\tb%s ", suffix);
438 arm_emit_cfop_target(proj_true);
439 be_emit_finish_line_gas(proj_true);
441 if (get_cfop_target_block(proj_false) == next_block) {
442 be_emit_cstring("\t/* fallthrough to ");
443 arm_emit_cfop_target(proj_false);
444 be_emit_cstring(" */");
445 be_emit_finish_line_gas(proj_false);
447 be_emit_cstring("b ");
448 arm_emit_cfop_target(proj_false);
449 be_emit_finish_line_gas(proj_false);
455 * Emit a Compare with conditional branch.
457 static void emit_arm_fpaCmfBra(const ir_node *irn) {
462 * Emit a Compare with conditional branch.
464 static void emit_arm_fpaCmfeBra(const ir_node *irn) {
468 /** Sort register in ascending order. */
469 static int reg_cmp(const void *a, const void *b) {
470 const arch_register_t * const *ra = a;
471 const arch_register_t * const *rb = b;
473 return *ra < *rb ? -1 : (*ra != *rb);
477 * Create the CopyB instruction sequence.
479 static void emit_arm_CopyB(const ir_node *irn) {
480 unsigned int size = get_tarval_long(get_arm_value(irn));
482 const char *tgt = arch_register_get_name(get_in_reg(irn, 0));
483 const char *src = arch_register_get_name(get_in_reg(irn, 1));
484 const char *t0, *t1, *t2, *t3;
486 const arch_register_t *tmpregs[4];
488 /* collect the temporary registers and sort them, we need ascending order */
489 tmpregs[0] = get_in_reg(irn, 2);
490 tmpregs[1] = get_in_reg(irn, 3);
491 tmpregs[2] = get_in_reg(irn, 4);
492 tmpregs[3] = &arm_gp_regs[REG_R12];
494 /* Note: R12 is always the last register because the RA did not assign higher ones */
495 qsort((void *)tmpregs, 3, sizeof(tmpregs[0]), reg_cmp);
497 /* need ascending order */
498 t0 = arch_register_get_name(tmpregs[0]);
499 t1 = arch_register_get_name(tmpregs[1]);
500 t2 = arch_register_get_name(tmpregs[2]);
501 t3 = arch_register_get_name(tmpregs[3]);
503 be_emit_cstring("/* MemCopy (");
505 be_emit_cstring(")->(");
506 arm_emit_source_register(irn, 0);
507 be_emit_irprintf(" [%d bytes], Uses ", size);
509 be_emit_cstring(", ");
511 be_emit_cstring(", ");
513 be_emit_cstring(", and ");
515 be_emit_cstring("*/");
516 be_emit_finish_line_gas(NULL);
518 assert(size > 0 && "CopyB needs size > 0" );
521 assert(!"strange hack enabled: copy more bytes than needed!");
530 be_emit_cstring("\tldr ");
532 be_emit_cstring(", [");
534 be_emit_cstring(", #0]");
535 be_emit_finish_line_gas(NULL);
537 be_emit_cstring("\tstr ");
539 be_emit_cstring(", [");
541 be_emit_cstring(", #0]");
542 be_emit_finish_line_gas(irn);
545 be_emit_cstring("\tldmia ");
547 be_emit_cstring("!, {");
549 be_emit_cstring(", ");
552 be_emit_finish_line_gas(NULL);
554 be_emit_cstring("\tstmia ");
556 be_emit_cstring("!, {");
558 be_emit_cstring(", ");
561 be_emit_finish_line_gas(irn);
564 be_emit_cstring("\tldmia ");
566 be_emit_cstring("!, {");
568 be_emit_cstring(", ");
570 be_emit_cstring(", ");
573 be_emit_finish_line_gas(NULL);
575 be_emit_cstring("\tstmia ");
577 be_emit_cstring("!, {");
579 be_emit_cstring(", ");
581 be_emit_cstring(", ");
584 be_emit_finish_line_gas(irn);
589 be_emit_cstring("\tldmia ");
591 be_emit_cstring("!, {");
593 be_emit_cstring(", ");
595 be_emit_cstring(", ");
597 be_emit_cstring(", ");
600 be_emit_finish_line_gas(NULL);
602 be_emit_cstring("\tstmia ");
604 be_emit_cstring("!, {");
606 be_emit_cstring(", ");
608 be_emit_cstring(", ");
610 be_emit_cstring(", ");
613 be_emit_finish_line_gas(irn);
618 static void emit_arm_SwitchJmp(const ir_node *irn) {
619 const ir_edge_t *edge;
625 ir_node *default_proj = NULL;
627 block_nr = get_irn_node_nr(irn);
628 n_projs = get_arm_SwitchJmp_n_projs(irn);
630 projs = xcalloc(n_projs , sizeof(ir_node*));
632 foreach_out_edge(irn, edge) {
633 proj = get_edge_src_irn(edge);
634 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
636 if (get_Proj_proj(proj) == get_arm_SwitchJmp_default_proj_num(irn))
639 projs[get_Proj_proj(proj)] = proj;
641 assert(default_proj != NULL && "SwitchJmp should have a Default Proj");
648 be_emit_cstring("\tcmp ");
649 arm_emit_source_register(irn, 0);
650 be_emit_irprintf(", #%u", n_projs - 1);
651 be_emit_finish_line_gas(irn);
653 be_emit_cstring("\tbhi ");
654 arm_emit_cfop_target(default_proj);
655 be_emit_finish_line_gas(default_proj);
658 LDR %r12, .TABLE_X_START
659 ADD %r12, %r12, [%1S, LSL #2]
663 be_emit_irprintf("\tldr %%r12, TABLE_%d_START", block_nr);
664 be_emit_finish_line_gas(NULL);
666 be_emit_irprintf("\tadd %%r12, %%r12, ");
667 arm_emit_source_register(irn, 0);
668 be_emit_cstring(", LSL #2");
669 be_emit_finish_line_gas(NULL);
671 be_emit_cstring("\tldr %r15, [%r12, #0]");
672 be_emit_finish_line_gas(NULL);
674 be_emit_irprintf("TABLE_%d_START:\n\t.word\tTABLE_%d", block_nr, block_nr);
675 be_emit_finish_line_gas(NULL);
676 be_emit_irprintf("\t.align 2");
677 be_emit_finish_line_gas(NULL);
678 be_emit_irprintf("TABLE_%d:", block_nr);
679 be_emit_finish_line_gas(NULL);
681 for (i = 0; i < n_projs; ++i) {
684 proj = projs[get_arm_SwitchJmp_default_proj_num(irn)];
686 be_emit_cstring("\t.word\t");
687 arm_emit_cfop_target(proj);
688 be_emit_finish_line_gas(proj);
690 be_emit_irprintf("\t.align 2\n");
691 be_emit_finish_line_gas(NULL);
695 /************************************************************************/
697 /************************************************************************/
699 static void emit_be_Call(const ir_node *irn) {
700 ir_entity *ent = be_Call_get_entity(irn);
702 be_emit_cstring("\tbl ");
704 set_entity_backend_marked(ent, 1);
705 be_emit_ident(get_entity_ld_ident(ent));
707 arm_emit_source_register(irn, be_pos_Call_ptr);
709 be_emit_finish_line_gas(irn);
712 /** Emit an IncSP node */
713 static void emit_be_IncSP(const ir_node *irn) {
714 int offs = be_get_IncSP_offset(irn);
717 be_emit_cstring("\tadd ");
718 arm_emit_dest_register(irn, 0);
719 be_emit_cstring(", ");
720 arm_emit_source_register(irn, 0);
721 be_emit_cstring(", #");
722 arm_emit_offset(irn);
724 be_emit_cstring("\t/* omitted IncSP(");
725 arm_emit_offset(irn);
726 be_emit_cstring(") */");
728 be_emit_finish_line_gas(irn);
731 static void emit_be_Copy(const ir_node *irn) {
732 ir_mode *mode = get_irn_mode(irn);
734 if (get_in_reg(irn, 0) == get_out_reg(irn, 0)) {
735 be_emit_cstring("\t/* omitted Copy: ");
736 arm_emit_source_register(irn, 0);
737 be_emit_cstring(" -> ");
738 arm_emit_dest_register(irn, 0);
739 be_emit_finish_line_gas(irn);
743 if (mode_is_float(mode)) {
745 be_emit_cstring("\tmvf");
748 arm_emit_dest_register(irn, 0);
749 be_emit_cstring(", ");
750 arm_emit_source_register(irn, 0);
751 be_emit_finish_line_gas(irn);
753 assert(0 && "move not supported for this mode");
754 panic("emit_be_Copy: move not supported for this mode");
756 } else if (mode_is_data(mode)) {
757 be_emit_cstring("\tmov ");
758 arm_emit_dest_register(irn, 0);
759 be_emit_cstring(", ");
760 arm_emit_source_register(irn, 0);
761 be_emit_finish_line_gas(irn);
763 assert(0 && "move not supported for this mode");
764 panic("emit_be_Copy: move not supported for this mode");
769 * Emit code for a Spill.
771 static void emit_be_Spill(const ir_node *irn) {
772 ir_mode *mode = get_irn_mode(be_get_Spill_val(irn));
774 if (mode_is_float(mode)) {
775 if (USE_FPA(cg->isa)) {
776 be_emit_cstring("\tstf");
777 arm_emit_fpa_postfix(mode);
780 assert(0 && "spill not supported for this mode");
781 panic("emit_be_Spill: spill not supported for this mode");
783 } else if (mode_is_dataM(mode)) {
784 be_emit_cstring("\tstr ");
786 assert(0 && "spill not supported for this mode");
787 panic("emit_be_Spill: spill not supported for this mode");
789 arm_emit_source_register(irn, 1);
790 be_emit_cstring(", [");
791 arm_emit_source_register(irn, 0);
792 be_emit_cstring(", #");
793 arm_emit_offset(irn);
795 be_emit_finish_line_gas(irn);
799 * Emit code for a Reload.
801 static void emit_be_Reload(const ir_node *irn) {
802 ir_mode *mode = get_irn_mode(irn);
804 if (mode_is_float(mode)) {
805 if (USE_FPA(cg->isa)) {
806 be_emit_cstring("\tldf");
807 arm_emit_fpa_postfix(mode);
810 assert(0 && "reload not supported for this mode");
811 panic("emit_be_Reload: reload not supported for this mode");
813 } else if (mode_is_dataM(mode)) {
814 be_emit_cstring("\tldr ");
816 assert(0 && "reload not supported for this mode");
817 panic("emit_be_Reload: reload not supported for this mode");
819 arm_emit_dest_register(irn, 0);
820 be_emit_cstring(", [");
821 arm_emit_source_register(irn, 0);
822 be_emit_cstring(", #");
823 arm_emit_offset(irn);
825 be_emit_finish_line_gas(irn);
828 static void emit_be_Perm(const ir_node *irn) {
829 be_emit_cstring("\teor ");
830 arm_emit_source_register(irn, 0);
831 be_emit_cstring(", ");
832 arm_emit_source_register(irn, 0);
833 be_emit_cstring(", ");
834 arm_emit_source_register(irn, 1);
835 be_emit_finish_line_gas(NULL);
837 be_emit_cstring("\teor ");
838 arm_emit_source_register(irn, 1);
839 be_emit_cstring(", ");
840 arm_emit_source_register(irn, 0);
841 be_emit_cstring(", ");
842 arm_emit_source_register(irn, 1);
843 be_emit_finish_line_gas(NULL);
845 be_emit_cstring("\teor ");
846 arm_emit_source_register(irn, 0);
847 be_emit_cstring(", ");
848 arm_emit_source_register(irn, 0);
849 be_emit_cstring(", ");
850 arm_emit_source_register(irn, 1);
851 be_emit_finish_line_gas(irn);
854 /************************************************************************/
856 /************************************************************************/
858 static void emit_Jmp(const ir_node *node) {
859 ir_node *block, *next_block;
861 /* for now, the code works for scheduled and non-schedules blocks */
862 block = get_nodes_block(node);
864 /* we have a block schedule */
865 next_block = sched_next_block(block);
866 if (get_cfop_target_block(node) != next_block) {
867 be_emit_cstring("\tb ");
868 arm_emit_cfop_target(node);
870 be_emit_cstring("\t/* fallthrough to ");
871 arm_emit_cfop_target(node);
872 be_emit_cstring(" */");
874 be_emit_finish_line_gas(node);
877 static void emit_arm_fpaDbl2GP(const ir_node *irn) {
878 be_emit_cstring("\tstfd ");
879 arm_emit_source_register(irn, 0);
880 be_emit_cstring(", [sp, #-8]!");
881 be_emit_pad_comment();
882 be_emit_cstring("/* Push fp to stack */");
883 be_emit_finish_line_gas(NULL);
885 be_emit_cstring("\tldmfd sp!, {");
886 arm_emit_dest_register(irn, 1);
887 be_emit_cstring(", ");
888 arm_emit_dest_register(irn, 0);
890 be_emit_pad_comment();
891 be_emit_cstring("/* Pop destination */");
892 be_emit_finish_line_gas(irn);
895 static void emit_arm_LdTls(const ir_node *irn) {
897 panic("TLS not supported for this target\n");
898 /* Er... our gcc does not support it... Install a newer toolchain. */
901 /***********************************************************************************
904 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
905 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
906 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
907 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
909 ***********************************************************************************/
911 static void emit_silence(const ir_node *irn) {
917 * The type of a emitter function.
919 typedef void (emit_func)(const ir_node *irn);
922 * Set a node emitter. Make it a bit more type safe.
924 static INLINE void set_emitter(ir_op *op, emit_func arm_emit_node) {
925 op->ops.generic = (op_func)arm_emit_node;
929 * Enters the emitter functions for handled nodes into the generic
930 * pointer of an opcode.
932 static void arm_register_emitters(void) {
934 #define ARM_EMIT(a) set_emitter(op_arm_##a, emit_arm_##a)
935 #define EMIT(a) set_emitter(op_##a, emit_##a)
936 #define BE_EMIT(a) set_emitter(op_be_##a, emit_be_##a)
937 #define SILENCE(a) set_emitter(op_##a, emit_silence)
939 /* first clear the generic function pointer for all ops */
940 clear_irp_opcodes_generic_func();
942 /* register all emitter functions defined in spec */
943 arm_register_spec_emitters();
945 /* other emitter functions */
948 ARM_EMIT(fpaCmfeBra);
950 // ARM_EMIT(CopyB_i);
975 SILENCE(be_CopyKeep);
976 SILENCE(be_RegParams);
987 static const char *last_name = NULL;
988 static unsigned last_line = -1;
989 static unsigned num = -1;
992 * Emit the debug support for node node.
994 static void arm_emit_dbg(const ir_node *irn) {
995 dbg_info *db = get_irn_dbg_info(irn);
997 const char *fname = be_retrieve_dbg_info(db, &lineno);
999 if (! cg->birg->main_env->options->stabs_debug_support)
1003 if (last_name != fname) {
1005 be_dbg_include_begin(cg->birg->main_env->db_handle, fname);
1008 if (last_line != lineno) {
1011 snprintf(name, sizeof(name), ".LM%u", ++num);
1013 be_dbg_line(cg->birg->main_env->db_handle, lineno, name);
1014 be_emit_string(name);
1015 be_emit_cstring(":\n");
1016 be_emit_write_line();
1022 * Emits code for a node.
1024 static void arm_emit_node(const ir_node *irn) {
1025 ir_op *op = get_irn_op(irn);
1027 if (op->ops.generic) {
1028 emit_func *emit = (emit_func *)op->ops.generic;
1032 be_emit_cstring("\t/* TODO */");
1033 be_emit_finish_line_gas(irn);
1038 * emit the block label if needed.
1040 static void arm_emit_block_header(ir_node *block, ir_node *prev)
1045 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1048 n_cfgpreds = get_Block_n_cfgpreds(block);
1049 if (n_cfgpreds == 1) {
1050 ir_node *pred = get_Block_cfgpred(block, 0);
1051 ir_node *pred_block = get_nodes_block(pred);
1053 /* we don't need labels for fallthrough blocks, however switch-jmps
1054 * are no fallthroughs */
1055 if (pred_block == prev &&
1056 !(is_Proj(pred) && is_arm_SwitchJmp(get_Proj_pred(pred)))) {
1066 arm_emit_block_name(block);
1069 be_emit_pad_comment();
1070 be_emit_cstring(" /* preds:");
1072 /* emit list of pred blocks in comment */
1073 arity = get_irn_arity(block);
1074 for (i = 0; i < arity; ++i) {
1075 ir_node *predblock = get_Block_cfgpred_block(block, i);
1076 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1079 be_emit_cstring("\t/* ");
1080 arm_emit_block_name(block);
1081 be_emit_cstring(": ");
1083 if (exec_freq != NULL) {
1084 be_emit_irprintf(" freq: %f",
1085 get_block_execfreq(exec_freq, block));
1087 be_emit_cstring(" */\n");
1088 be_emit_write_line();
1092 * Walks over the nodes in a block connected by scheduling edges
1093 * and emits code for each node.
1095 static void arm_gen_block(ir_node *block, ir_node *prev_block) {
1098 arm_emit_block_header(block, prev_block);
1099 arm_emit_dbg(block);
1100 sched_foreach(block, irn) {
1106 * Emits code for function start.
1108 void arm_func_prolog(ir_graph *irg) {
1109 ir_entity *ent = get_irg_entity(irg);
1110 const char *irg_name = get_entity_ld_name(ent);
1112 be_emit_write_line();
1113 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1114 be_emit_cstring("\t.align 2\n");
1116 if (get_entity_visibility(ent) == visibility_external_visible)
1117 be_emit_irprintf("\t.global %s\n", irg_name);
1118 be_emit_irprintf("%s:\n", irg_name);
1122 * Emits code for function end
1124 void arm_emit_end(FILE *F, ir_graph *irg) {
1126 fprintf(F, "\t.ident \"firmcc\"\n");
1131 * Sets labels for control flow nodes (jump target)
1133 static void arm_gen_labels(ir_node *block, void *env) {
1135 int n = get_Block_n_cfgpreds(block);
1138 for (n--; n >= 0; n--) {
1139 pred = get_Block_cfgpred(block, n);
1140 set_irn_link(pred, block);
1145 * Compare two entries of the symbol or tarval set.
1147 static int cmp_sym_or_tv(const void *elt, const void *key, size_t size) {
1148 const sym_or_tv_t *p1 = elt;
1149 const sym_or_tv_t *p2 = key;
1152 /* as an identifier NEVER can point to a tarval, it's enough
1153 to compare it this way */
1154 return p1->u.generic != p2->u.generic;
1158 * Main driver. Emits the code for one routine.
1160 void arm_gen_routine(const arm_code_gen_t *arm_cg, ir_graph *irg) {
1161 ir_node **blk_sched;
1163 ir_node *last_block = NULL;
1166 arch_env = cg->arch_env;
1167 sym_or_tv = new_set(cmp_sym_or_tv, 8);
1170 arm_register_emitters();
1172 /* create the block schedule. For now, we don't need it earlier. */
1173 blk_sched = be_create_block_schedule(cg->irg, cg->birg->exec_freq);
1175 arm_func_prolog(irg);
1176 irg_block_walk_graph(irg, arm_gen_labels, NULL, NULL);
1178 n = ARR_LEN(blk_sched);
1179 for (i = 0; i < n;) {
1180 ir_node *block, *next_bl;
1182 block = blk_sched[i];
1184 next_bl = i < n ? blk_sched[i] : NULL;
1186 /* set here the link. the emitter expects to find the next block here */
1187 set_irn_link(block, next_bl);
1188 arm_gen_block(block, last_block);
1192 /* emit SymConst values */
1193 if (set_count(sym_or_tv) > 0) {
1196 be_emit_cstring("\t.align 2\n");
1198 foreach_set(sym_or_tv, entry) {
1199 be_emit_irprintf(".L%u:\n", entry->label);
1201 if (entry->is_ident) {
1202 be_emit_cstring("\t.word\t");
1203 be_emit_ident(entry->u.id);
1205 be_emit_write_line();
1207 tarval *tv = entry->u.tv;
1208 int i, size = get_mode_size_bytes(get_tarval_mode(tv));
1211 /* beware: ARM fpa uses big endian format */
1212 for (i = ((size + 3) & ~3) - 4; i >= 0; i -= 4) {
1214 v = get_tarval_sub_bits(tv, i+3);
1215 v = (v << 8) | get_tarval_sub_bits(tv, i+2);
1216 v = (v << 8) | get_tarval_sub_bits(tv, i+1);
1217 v = (v << 8) | get_tarval_sub_bits(tv, i+0);
1218 be_emit_irprintf("\t.word\t%u\n", v);
1219 be_emit_write_line();
1224 be_emit_write_line();
1229 void arm_init_emitter(void)
1231 FIRM_DBG_REGISTER(dbg, "firm.be.arm.emit");