2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
45 #include "raw_bitset.h"
48 #include "../besched.h"
49 #include "../beblocksched.h"
50 #include "../beirg_t.h"
51 #include "../begnuas.h"
52 #include "../be_dbgout.h"
54 #include "arm_emitter.h"
55 #include "arm_optimize.h"
56 #include "gen_arm_emitter.h"
57 #include "arm_nodes_attr.h"
58 #include "arm_new_nodes.h"
59 #include "arm_map_regs.h"
60 #include "gen_arm_regalloc_if.h"
62 #include "../benode_t.h"
64 #define BLOCK_PREFIX ".L"
66 #define SNPRINTF_BUF_LEN 128
68 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
70 static const arch_env_t *arch_env = NULL;
71 static const arm_code_gen_t *cg;
72 static const arm_isa_t *isa;
73 static set *sym_or_tv;
76 * Returns the register at in position pos.
78 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
80 const arch_register_t *reg = NULL;
82 assert(get_irn_arity(irn) > pos && "Invalid IN position");
84 /* The out register of the operator at position pos is the
85 in register we need. */
86 op = get_irn_n(irn, pos);
88 reg = arch_get_irn_register(arch_env, op);
90 assert(reg && "no in register found");
92 /* in case of a joker register: just return a valid register */
93 if (arch_register_type_is(reg, joker)) {
94 const arch_register_req_t *req;
96 /* ask for the requirements */
97 req = arch_get_register_req(arch_env, irn, pos);
99 if (arch_register_req_is(req, limited)) {
100 /* in case of limited requirements: get the first allowed register */
101 unsigned idx = rbitset_next(req->limited, 0, 1);
102 reg = arch_register_for_index(req->cls, idx);
104 /* otherwise get first register in class */
105 reg = arch_register_for_index(req->cls, 0);
113 * Returns the register at out position pos.
115 static const arch_register_t *get_out_reg(const ir_node *node, int pos)
118 const arch_register_t *reg = NULL;
120 /* 1st case: irn is not of mode_T, so it has only */
121 /* one OUT register -> good */
122 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
123 /* Proj with the corresponding projnum for the register */
125 if (get_irn_mode(node) != mode_T) {
126 reg = arch_get_irn_register(arch_env, node);
127 } else if (is_arm_irn(node)) {
128 reg = get_arm_out_reg(node, pos);
130 const ir_edge_t *edge;
132 foreach_out_edge(node, edge) {
133 proj = get_edge_src_irn(edge);
134 assert(is_Proj(proj) && "non-Proj from mode_T node");
135 if (get_Proj_proj(proj) == pos) {
136 reg = arch_get_irn_register(arch_env, proj);
142 assert(reg && "no out register found");
146 /*************************************************************
148 * (_) | | / _| | | | |
149 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
150 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
151 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
152 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
155 *************************************************************/
158 * Emit the name of the source register at given input position.
160 void arm_emit_source_register(const ir_node *node, int pos) {
161 const arch_register_t *reg = get_in_reg(node, pos);
162 be_emit_string(arch_register_get_name(reg));
166 * Emit the name of the destination register at given output position.
168 void arm_emit_dest_register(const ir_node *node, int pos) {
169 const arch_register_t *reg = get_out_reg(node, pos);
170 be_emit_string(arch_register_get_name(reg));
174 * Emit a node's offset.
176 void arm_emit_offset(const ir_node *node) {
178 ir_opcode opc = get_irn_opcode(node);
180 if (opc == beo_Reload || opc == beo_Spill) {
181 ir_entity *ent = be_get_frame_entity(node);
182 offset = get_entity_offset(ent);
184 assert(!"unimplemented arm_emit_offset for this node type");
185 panic("unimplemented arm_emit_offset for this node type");
187 be_emit_irprintf("%d", offset);
191 * Emit the arm fpa instruction suffix depending on the mode.
193 static void arm_emit_fpa_postfix(const ir_mode *mode) {
194 int bits = get_mode_size_bits(mode);
205 * Emit the instruction suffix depending on the mode.
207 void arm_emit_mode(const ir_node *node) {
210 if (is_arm_irn(node)) {
211 const arm_attr_t *attr = get_arm_attr_const(node);
212 mode = attr->op_mode ? attr->op_mode : get_irn_mode(node);
214 mode = get_irn_mode(node);
216 arm_emit_fpa_postfix(mode);
220 * Emit a const or SymConst value.
222 void arm_emit_immediate(const ir_node *node) {
223 const arm_attr_t *attr = get_arm_attr_const(node);
225 if (ARM_GET_SHF_MOD(attr) == ARM_SHF_IMM) {
226 be_emit_irprintf("#0x%X", arm_decode_imm_w_shift(get_arm_imm_value(node)));
227 } else if (ARM_GET_FPA_IMM(attr)) {
228 be_emit_irprintf("#%s", arm_get_fpa_imm_name(get_arm_imm_value(node)));
229 } else if (is_arm_SymConst(node))
230 be_emit_ident(get_arm_symconst_id(node));
232 assert(!"not a Constant");
237 * Returns the tarval or offset of an arm node as a string.
239 void arm_emit_shift(const ir_node *node) {
240 arm_shift_modifier mod;
242 mod = get_arm_shift_modifier(node);
243 if (ARM_HAS_SHIFT(mod)) {
244 int v = get_arm_imm_value(node);
246 be_emit_irprintf(", %s #%d", arm_shf_mod_name(mod), v);
250 /** An entry in the sym_or_tv set. */
251 typedef struct sym_or_tv_t {
253 ident *id; /**< An ident. */
254 tarval *tv; /**< A tarval. */
255 const void *generic; /**< For generic compare. */
257 unsigned label; /**< the associated label. */
258 char is_ident; /**< Non-zero if an ident is stored. */
262 * Returns a unique label. This number will not be used a second time.
264 static unsigned get_unique_label(void) {
265 static unsigned id = 0;
272 static void emit_arm_SymConst(const ir_node *irn) {
273 sym_or_tv_t key, *entry;
276 key.u.id = get_arm_symconst_id(irn);
279 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
280 if (entry->label == 0) {
281 /* allocate a label */
282 entry->label = get_unique_label();
284 label = entry->label;
286 /* load the symbol indirect */
287 be_emit_cstring("\tldr ");
288 arm_emit_dest_register(irn, 0);
289 be_emit_irprintf(", .L%u", label);
290 be_emit_finish_line_gas(irn);
294 * Emit a floating point fpa constant.
296 static void emit_arm_fpaConst(const ir_node *irn) {
297 sym_or_tv_t key, *entry;
301 key.u.tv = get_fpaConst_value(irn);
304 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
305 if (entry->label == 0) {
306 /* allocate a label */
307 entry->label = get_unique_label();
309 label = entry->label;
311 /* load the tarval indirect */
312 mode = get_irn_mode(irn);
313 be_emit_cstring("\tldf");
314 arm_emit_fpa_postfix(mode);
317 arm_emit_dest_register(irn, 0);
318 be_emit_irprintf(", .L%u", label);
319 be_emit_finish_line_gas(irn);
323 * Returns the next block in a block schedule.
325 static ir_node *sched_next_block(const ir_node *block) {
326 return get_irn_link(block);
330 * Returns the target block for a control flow node.
332 static ir_node *get_cfop_target_block(const ir_node *irn) {
333 return get_irn_link(irn);
337 * Emits a block label for the given block.
339 static void arm_emit_block_name(const ir_node *block) {
340 if (has_Block_label(block)) {
341 be_emit_string(be_gas_block_label_prefix());
342 be_emit_irprintf("%lu", get_Block_label(block));
344 be_emit_cstring(BLOCK_PREFIX);
345 be_emit_irprintf("%d", get_irn_node_nr(block));
350 * Emit the target label for a control flow node.
352 static void arm_emit_cfop_target(const ir_node *irn) {
353 ir_node *block = get_cfop_target_block(irn);
355 arm_emit_block_name(block);
359 * Emit a Compare with conditional branch.
361 static void emit_arm_CmpBra(const ir_node *irn) {
362 const ir_edge_t *edge;
363 const ir_node *proj_true = NULL;
364 const ir_node *proj_false = NULL;
365 const ir_node *block;
366 const ir_node *next_block;
367 ir_node *op1 = get_irn_n(irn, 0);
368 ir_mode *opmode = get_irn_mode(op1);
370 int proj_num = get_arm_CondJmp_proj_num(irn);
372 foreach_out_edge(irn, edge) {
373 ir_node *proj = get_edge_src_irn(edge);
374 long nr = get_Proj_proj(proj);
375 if (nr == pn_Cond_true) {
382 /* for now, the code works for scheduled and non-schedules blocks */
383 block = get_nodes_block(irn);
385 /* we have a block schedule */
386 next_block = sched_next_block(block);
388 if (proj_num == pn_Cmp_False) {
389 /* always false: should not happen */
390 be_emit_cstring("\tb ");
391 arm_emit_cfop_target(proj_false);
392 be_emit_finish_line_gas(proj_false);
393 } else if (proj_num == pn_Cmp_True) {
394 /* always true: should not happen */
395 be_emit_cstring("\tb ");
396 arm_emit_cfop_target(proj_true);
397 be_emit_finish_line_gas(proj_true);
399 if (mode_is_float(opmode)) {
400 suffix = "ICHWILLIMPLEMENTIERTWERDEN";
402 be_emit_cstring("\tfcmp ");
403 arm_emit_source_register(irn, 0);
404 be_emit_cstring(", ");
405 arm_emit_source_register(irn, 1);
406 be_emit_finish_line_gas(irn);
408 be_emit_cstring("\tfmstat");
409 be_emit_pad_comment();
410 be_emit_cstring("/* FCSPR -> CPSR */");
411 be_emit_finish_line_gas(NULL);
413 if (get_cfop_target_block(proj_true) == next_block) {
414 /* exchange both proj's so the second one can be omitted */
415 const ir_node *t = proj_true;
417 proj_true = proj_false;
419 proj_num = get_negated_pnc(proj_num, mode_Iu);
422 case pn_Cmp_Eq: suffix = "eq"; break;
423 case pn_Cmp_Lt: suffix = "lt"; break;
424 case pn_Cmp_Le: suffix = "le"; break;
425 case pn_Cmp_Gt: suffix = "gt"; break;
426 case pn_Cmp_Ge: suffix = "ge"; break;
427 case pn_Cmp_Lg: suffix = "ne"; break;
428 case pn_Cmp_Leg: suffix = "al"; break;
429 default: assert(!"Cmp unsupported"); suffix = "al";
431 be_emit_cstring("\tcmp ");
432 arm_emit_source_register(irn, 0);
433 be_emit_cstring(", ");
434 arm_emit_source_register(irn, 1);
435 be_emit_finish_line_gas(irn);
438 /* emit the true proj */
439 be_emit_irprintf("\tb%s ", suffix);
440 arm_emit_cfop_target(proj_true);
441 be_emit_finish_line_gas(proj_true);
443 if (get_cfop_target_block(proj_false) == next_block) {
444 be_emit_cstring("\t/* fallthrough to ");
445 arm_emit_cfop_target(proj_false);
446 be_emit_cstring(" */");
447 be_emit_finish_line_gas(proj_false);
449 be_emit_cstring("b ");
450 arm_emit_cfop_target(proj_false);
451 be_emit_finish_line_gas(proj_false);
458 * Emit a Tst with conditional branch.
460 static void emit_arm_TstBra(const ir_node *irn)
462 const ir_edge_t *edge;
463 const ir_node *proj_true = NULL;
464 const ir_node *proj_false = NULL;
465 const ir_node *block;
466 const ir_node *next_block;
468 int proj_num = get_arm_CondJmp_proj_num(irn);
470 foreach_out_edge(irn, edge) {
471 ir_node *proj = get_edge_src_irn(edge);
472 long nr = get_Proj_proj(proj);
473 if (nr == pn_Cond_true) {
480 /* for now, the code works for scheduled and non-schedules blocks */
481 block = get_nodes_block(irn);
483 /* we have a block schedule */
484 next_block = sched_next_block(block);
486 assert(proj_num != pn_Cmp_False);
487 assert(proj_num != pn_Cmp_True);
489 if (get_cfop_target_block(proj_true) == next_block) {
490 /* exchange both proj's so the second one can be omitted */
491 const ir_node *t = proj_true;
493 proj_true = proj_false;
495 proj_num = get_negated_pnc(proj_num, mode_Iu);
498 case pn_Cmp_Eq: suffix = "eq"; break;
499 case pn_Cmp_Lt: suffix = "lt"; break;
500 case pn_Cmp_Le: suffix = "le"; break;
501 case pn_Cmp_Gt: suffix = "gt"; break;
502 case pn_Cmp_Ge: suffix = "ge"; break;
503 case pn_Cmp_Lg: suffix = "ne"; break;
504 case pn_Cmp_Leg: suffix = "al"; break;
505 default: assert(!"Cmp unsupported"); suffix = "al";
507 be_emit_cstring("\ttst ");
508 arm_emit_source_register(irn, 0);
509 be_emit_cstring(", ");
510 arm_emit_source_register(irn, 1);
511 be_emit_finish_line_gas(irn);
513 /* emit the true proj */
514 be_emit_irprintf("\tb%s ", suffix);
515 arm_emit_cfop_target(proj_true);
516 be_emit_finish_line_gas(proj_true);
518 if (get_cfop_target_block(proj_false) == next_block) {
519 be_emit_cstring("\t/* fallthrough to ");
520 arm_emit_cfop_target(proj_false);
521 be_emit_cstring(" */");
522 be_emit_finish_line_gas(proj_false);
524 be_emit_cstring("b ");
525 arm_emit_cfop_target(proj_false);
526 be_emit_finish_line_gas(proj_false);
531 * Emit a Compare with conditional branch.
533 static void emit_arm_fpaCmfBra(const ir_node *irn) {
538 * Emit a Compare with conditional branch.
540 static void emit_arm_fpaCmfeBra(const ir_node *irn) {
544 /** Sort register in ascending order. */
545 static int reg_cmp(const void *a, const void *b) {
546 const arch_register_t * const *ra = a;
547 const arch_register_t * const *rb = b;
549 return *ra < *rb ? -1 : (*ra != *rb);
553 * Create the CopyB instruction sequence.
555 static void emit_arm_CopyB(const ir_node *irn) {
556 unsigned size = (unsigned)get_arm_imm_value(irn);
558 const char *tgt = arch_register_get_name(get_in_reg(irn, 0));
559 const char *src = arch_register_get_name(get_in_reg(irn, 1));
560 const char *t0, *t1, *t2, *t3;
562 const arch_register_t *tmpregs[4];
564 /* collect the temporary registers and sort them, we need ascending order */
565 tmpregs[0] = get_in_reg(irn, 2);
566 tmpregs[1] = get_in_reg(irn, 3);
567 tmpregs[2] = get_in_reg(irn, 4);
568 tmpregs[3] = &arm_gp_regs[REG_R12];
570 /* Note: R12 is always the last register because the RA did not assign higher ones */
571 qsort((void *)tmpregs, 3, sizeof(tmpregs[0]), reg_cmp);
573 /* need ascending order */
574 t0 = arch_register_get_name(tmpregs[0]);
575 t1 = arch_register_get_name(tmpregs[1]);
576 t2 = arch_register_get_name(tmpregs[2]);
577 t3 = arch_register_get_name(tmpregs[3]);
579 be_emit_cstring("/* MemCopy (");
581 be_emit_cstring(")->(");
582 arm_emit_source_register(irn, 0);
583 be_emit_irprintf(" [%u bytes], Uses ", size);
585 be_emit_cstring(", ");
587 be_emit_cstring(", ");
589 be_emit_cstring(", and ");
591 be_emit_cstring("*/");
592 be_emit_finish_line_gas(NULL);
594 assert(size > 0 && "CopyB needs size > 0" );
597 assert(!"strange hack enabled: copy more bytes than needed!");
606 be_emit_cstring("\tldr ");
608 be_emit_cstring(", [");
610 be_emit_cstring(", #0]");
611 be_emit_finish_line_gas(NULL);
613 be_emit_cstring("\tstr ");
615 be_emit_cstring(", [");
617 be_emit_cstring(", #0]");
618 be_emit_finish_line_gas(irn);
621 be_emit_cstring("\tldmia ");
623 be_emit_cstring("!, {");
625 be_emit_cstring(", ");
628 be_emit_finish_line_gas(NULL);
630 be_emit_cstring("\tstmia ");
632 be_emit_cstring("!, {");
634 be_emit_cstring(", ");
637 be_emit_finish_line_gas(irn);
640 be_emit_cstring("\tldmia ");
642 be_emit_cstring("!, {");
644 be_emit_cstring(", ");
646 be_emit_cstring(", ");
649 be_emit_finish_line_gas(NULL);
651 be_emit_cstring("\tstmia ");
653 be_emit_cstring("!, {");
655 be_emit_cstring(", ");
657 be_emit_cstring(", ");
660 be_emit_finish_line_gas(irn);
665 be_emit_cstring("\tldmia ");
667 be_emit_cstring("!, {");
669 be_emit_cstring(", ");
671 be_emit_cstring(", ");
673 be_emit_cstring(", ");
676 be_emit_finish_line_gas(NULL);
678 be_emit_cstring("\tstmia ");
680 be_emit_cstring("!, {");
682 be_emit_cstring(", ");
684 be_emit_cstring(", ");
686 be_emit_cstring(", ");
689 be_emit_finish_line_gas(irn);
694 static void emit_arm_SwitchJmp(const ir_node *irn) {
695 const ir_edge_t *edge;
701 ir_node *default_proj = NULL;
703 block_nr = get_irn_node_nr(irn);
704 n_projs = get_arm_SwitchJmp_n_projs(irn);
706 projs = xcalloc(n_projs , sizeof(ir_node*));
708 foreach_out_edge(irn, edge) {
709 proj = get_edge_src_irn(edge);
710 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
712 if (get_Proj_proj(proj) == get_arm_SwitchJmp_default_proj_num(irn))
715 projs[get_Proj_proj(proj)] = proj;
717 assert(default_proj != NULL && "SwitchJmp should have a Default Proj");
724 be_emit_cstring("\tcmp ");
725 arm_emit_source_register(irn, 0);
726 be_emit_irprintf(", #%u", n_projs - 1);
727 be_emit_finish_line_gas(irn);
729 be_emit_cstring("\tbhi ");
730 arm_emit_cfop_target(default_proj);
731 be_emit_finish_line_gas(default_proj);
734 LDR %r12, .TABLE_X_START
735 ADD %r12, %r12, [%1S, LSL #2]
739 be_emit_irprintf("\tldr %%r12, TABLE_%d_START", block_nr);
740 be_emit_finish_line_gas(NULL);
742 be_emit_irprintf("\tadd %%r12, %%r12, ");
743 arm_emit_source_register(irn, 0);
744 be_emit_cstring(", LSL #2");
745 be_emit_finish_line_gas(NULL);
747 be_emit_cstring("\tldr %r15, [%r12, #0]");
748 be_emit_finish_line_gas(NULL);
750 be_emit_irprintf("TABLE_%d_START:\n\t.word\tTABLE_%d", block_nr, block_nr);
751 be_emit_finish_line_gas(NULL);
752 be_emit_irprintf("\t.align 2");
753 be_emit_finish_line_gas(NULL);
754 be_emit_irprintf("TABLE_%d:", block_nr);
755 be_emit_finish_line_gas(NULL);
757 for (i = 0; i < n_projs; ++i) {
760 proj = projs[get_arm_SwitchJmp_default_proj_num(irn)];
762 be_emit_cstring("\t.word\t");
763 arm_emit_cfop_target(proj);
764 be_emit_finish_line_gas(proj);
766 be_emit_irprintf("\t.align 2\n");
767 be_emit_finish_line_gas(NULL);
771 /************************************************************************/
773 /************************************************************************/
775 static void emit_be_Call(const ir_node *irn) {
776 ir_entity *ent = be_Call_get_entity(irn);
778 be_emit_cstring("\tbl ");
780 set_entity_backend_marked(ent, 1);
781 be_emit_ident(get_entity_ld_ident(ent));
783 arm_emit_source_register(irn, be_pos_Call_ptr);
785 be_emit_finish_line_gas(irn);
788 /** Emit an IncSP node */
789 static void emit_be_IncSP(const ir_node *irn) {
790 int offs = -be_get_IncSP_offset(irn);
794 be_emit_cstring("\tsub ");
797 be_emit_cstring("\tadd ");
799 arm_emit_dest_register(irn, 0);
800 be_emit_cstring(", ");
801 arm_emit_source_register(irn, 0);
802 be_emit_irprintf(", #0x%X", offs);
804 /* omitted IncSP(0) */
807 be_emit_finish_line_gas(irn);
810 static void emit_be_Copy(const ir_node *irn) {
811 ir_mode *mode = get_irn_mode(irn);
813 if (get_in_reg(irn, 0) == get_out_reg(irn, 0)) {
818 if (mode_is_float(mode)) {
820 be_emit_cstring("\tmvf");
823 arm_emit_dest_register(irn, 0);
824 be_emit_cstring(", ");
825 arm_emit_source_register(irn, 0);
826 be_emit_finish_line_gas(irn);
828 assert(0 && "move not supported for this mode");
829 panic("emit_be_Copy: move not supported for this mode");
831 } else if (mode_is_data(mode)) {
832 be_emit_cstring("\tmov ");
833 arm_emit_dest_register(irn, 0);
834 be_emit_cstring(", ");
835 arm_emit_source_register(irn, 0);
836 be_emit_finish_line_gas(irn);
838 assert(0 && "move not supported for this mode");
839 panic("emit_be_Copy: move not supported for this mode");
844 * Emit code for a Spill.
846 static void emit_be_Spill(const ir_node *irn) {
847 ir_mode *mode = get_irn_mode(be_get_Spill_val(irn));
849 if (mode_is_float(mode)) {
850 if (USE_FPA(cg->isa)) {
851 be_emit_cstring("\tstf");
852 arm_emit_fpa_postfix(mode);
855 assert(0 && "spill not supported for this mode");
856 panic("emit_be_Spill: spill not supported for this mode");
858 } else if (mode_is_dataM(mode)) {
859 be_emit_cstring("\tstr ");
861 assert(0 && "spill not supported for this mode");
862 panic("emit_be_Spill: spill not supported for this mode");
864 arm_emit_source_register(irn, 1);
865 be_emit_cstring(", [");
866 arm_emit_source_register(irn, 0);
867 be_emit_cstring(", #");
868 arm_emit_offset(irn);
870 be_emit_finish_line_gas(irn);
874 * Emit code for a Reload.
876 static void emit_be_Reload(const ir_node *irn) {
877 ir_mode *mode = get_irn_mode(irn);
879 if (mode_is_float(mode)) {
880 if (USE_FPA(cg->isa)) {
881 be_emit_cstring("\tldf");
882 arm_emit_fpa_postfix(mode);
885 assert(0 && "reload not supported for this mode");
886 panic("emit_be_Reload: reload not supported for this mode");
888 } else if (mode_is_dataM(mode)) {
889 be_emit_cstring("\tldr ");
891 assert(0 && "reload not supported for this mode");
892 panic("emit_be_Reload: reload not supported for this mode");
894 arm_emit_dest_register(irn, 0);
895 be_emit_cstring(", [");
896 arm_emit_source_register(irn, 0);
897 be_emit_cstring(", #");
898 arm_emit_offset(irn);
900 be_emit_finish_line_gas(irn);
903 static void emit_be_Perm(const ir_node *irn) {
904 be_emit_cstring("\teor ");
905 arm_emit_source_register(irn, 0);
906 be_emit_cstring(", ");
907 arm_emit_source_register(irn, 0);
908 be_emit_cstring(", ");
909 arm_emit_source_register(irn, 1);
910 be_emit_finish_line_gas(NULL);
912 be_emit_cstring("\teor ");
913 arm_emit_source_register(irn, 1);
914 be_emit_cstring(", ");
915 arm_emit_source_register(irn, 0);
916 be_emit_cstring(", ");
917 arm_emit_source_register(irn, 1);
918 be_emit_finish_line_gas(NULL);
920 be_emit_cstring("\teor ");
921 arm_emit_source_register(irn, 0);
922 be_emit_cstring(", ");
923 arm_emit_source_register(irn, 0);
924 be_emit_cstring(", ");
925 arm_emit_source_register(irn, 1);
926 be_emit_finish_line_gas(irn);
929 /************************************************************************/
931 /************************************************************************/
933 static void emit_Jmp(const ir_node *node) {
934 ir_node *block, *next_block;
936 /* for now, the code works for scheduled and non-schedules blocks */
937 block = get_nodes_block(node);
939 /* we have a block schedule */
940 next_block = sched_next_block(block);
941 if (get_cfop_target_block(node) != next_block) {
942 be_emit_cstring("\tb ");
943 arm_emit_cfop_target(node);
945 be_emit_cstring("\t/* fallthrough to ");
946 arm_emit_cfop_target(node);
947 be_emit_cstring(" */");
949 be_emit_finish_line_gas(node);
952 static void emit_arm_fpaDbl2GP(const ir_node *irn) {
953 be_emit_cstring("\tstfd ");
954 arm_emit_source_register(irn, 0);
955 be_emit_cstring(", [sp, #-8]!");
956 be_emit_pad_comment();
957 be_emit_cstring("/* Push fp to stack */");
958 be_emit_finish_line_gas(NULL);
960 be_emit_cstring("\tldmfd sp!, {");
961 arm_emit_dest_register(irn, 1);
962 be_emit_cstring(", ");
963 arm_emit_dest_register(irn, 0);
965 be_emit_pad_comment();
966 be_emit_cstring("/* Pop destination */");
967 be_emit_finish_line_gas(irn);
970 static void emit_arm_LdTls(const ir_node *irn) {
972 panic("TLS not supported for this target");
973 /* Er... our gcc does not support it... Install a newer toolchain. */
976 /***********************************************************************************
979 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
980 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
981 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
982 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
984 ***********************************************************************************/
986 static void emit_silence(const ir_node *irn) {
992 * The type of a emitter function.
994 typedef void (emit_func)(const ir_node *irn);
997 * Set a node emitter. Make it a bit more type safe.
999 static INLINE void set_emitter(ir_op *op, emit_func arm_emit_node) {
1000 op->ops.generic = (op_func)arm_emit_node;
1004 * Enters the emitter functions for handled nodes into the generic
1005 * pointer of an opcode.
1007 static void arm_register_emitters(void) {
1009 #define ARM_EMIT(a) set_emitter(op_arm_##a, emit_arm_##a)
1010 #define EMIT(a) set_emitter(op_##a, emit_##a)
1011 #define BE_EMIT(a) set_emitter(op_be_##a, emit_be_##a)
1012 #define SILENCE(a) set_emitter(op_##a, emit_silence)
1014 /* first clear the generic function pointer for all ops */
1015 clear_irp_opcodes_generic_func();
1017 /* register all emitter functions defined in spec */
1018 arm_register_spec_emitters();
1020 /* other emitter functions */
1023 ARM_EMIT(fpaCmfBra);
1024 ARM_EMIT(fpaCmfeBra);
1026 // ARM_EMIT(CopyB_i);
1029 ARM_EMIT(SwitchJmp);
1030 ARM_EMIT(fpaDbl2GP);
1034 /* benode emitter */
1051 SILENCE(be_CopyKeep);
1052 SILENCE(be_RegParams);
1053 SILENCE(be_Barrier);
1064 * Emits code for a node.
1066 static void arm_emit_node(const ir_node *irn) {
1067 ir_op *op = get_irn_op(irn);
1069 if (op->ops.generic) {
1070 emit_func *emit = (emit_func *)op->ops.generic;
1071 be_dbg_set_dbg_info(get_irn_dbg_info(irn));
1074 be_emit_cstring("\t/* TODO */");
1075 be_emit_finish_line_gas(irn);
1080 * emit the block label if needed.
1082 static void arm_emit_block_header(ir_node *block, ir_node *prev)
1087 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1090 n_cfgpreds = get_Block_n_cfgpreds(block);
1091 if (n_cfgpreds == 1) {
1092 ir_node *pred = get_Block_cfgpred(block, 0);
1093 ir_node *pred_block = get_nodes_block(pred);
1095 /* we don't need labels for fallthrough blocks, however switch-jmps
1096 * are no fallthroughs */
1097 if (pred_block == prev &&
1098 !(is_Proj(pred) && is_arm_SwitchJmp(get_Proj_pred(pred)))) {
1108 arm_emit_block_name(block);
1111 be_emit_pad_comment();
1112 be_emit_cstring(" /* preds:");
1114 /* emit list of pred blocks in comment */
1115 arity = get_irn_arity(block);
1116 for (i = 0; i < arity; ++i) {
1117 ir_node *predblock = get_Block_cfgpred_block(block, i);
1118 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1121 be_emit_cstring("\t/* ");
1122 arm_emit_block_name(block);
1123 be_emit_cstring(": ");
1125 if (exec_freq != NULL) {
1126 be_emit_irprintf(" freq: %f",
1127 get_block_execfreq(exec_freq, block));
1129 be_emit_cstring(" */\n");
1130 be_emit_write_line();
1134 * Walks over the nodes in a block connected by scheduling edges
1135 * and emits code for each node.
1137 static void arm_gen_block(ir_node *block, ir_node *prev_block) {
1140 arm_emit_block_header(block, prev_block);
1141 be_dbg_set_dbg_info(get_irn_dbg_info(block));
1142 sched_foreach(block, irn) {
1148 * Emits code for function start.
1150 void arm_func_prolog(ir_graph *irg) {
1151 ir_entity *ent = get_irg_entity(irg);
1152 const char *irg_name = get_entity_ld_name(ent);
1154 be_emit_write_line();
1155 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1156 be_emit_cstring("\t.align 2\n");
1158 if (get_entity_visibility(ent) == visibility_external_visible)
1159 be_emit_irprintf("\t.global %s\n", irg_name);
1160 be_emit_irprintf("%s:\n", irg_name);
1164 * Emits code for function end
1166 void arm_emit_end(FILE *F, ir_graph *irg) {
1168 fprintf(F, "\t.ident \"firmcc\"\n");
1173 * Sets labels for control flow nodes (jump target)
1175 static void arm_gen_labels(ir_node *block, void *env) {
1177 int n = get_Block_n_cfgpreds(block);
1180 for (n--; n >= 0; n--) {
1181 pred = get_Block_cfgpred(block, n);
1182 set_irn_link(pred, block);
1187 * Compare two entries of the symbol or tarval set.
1189 static int cmp_sym_or_tv(const void *elt, const void *key, size_t size) {
1190 const sym_or_tv_t *p1 = elt;
1191 const sym_or_tv_t *p2 = key;
1194 /* as an identifier NEVER can point to a tarval, it's enough
1195 to compare it this way */
1196 return p1->u.generic != p2->u.generic;
1200 * Main driver. Emits the code for one routine.
1202 void arm_gen_routine(const arm_code_gen_t *arm_cg, ir_graph *irg) {
1203 ir_node **blk_sched;
1205 ir_node *last_block = NULL;
1206 ir_entity *entity = get_irg_entity(irg);
1209 isa = (const arm_isa_t *)cg->arch_env;
1210 arch_env = cg->arch_env;
1211 sym_or_tv = new_set(cmp_sym_or_tv, 8);
1213 arm_register_emitters();
1215 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
1217 /* create the block schedule. For now, we don't need it earlier. */
1218 blk_sched = be_create_block_schedule(cg->irg, cg->birg->exec_freq);
1220 arm_func_prolog(irg);
1221 irg_block_walk_graph(irg, arm_gen_labels, NULL, NULL);
1223 n = ARR_LEN(blk_sched);
1224 for (i = 0; i < n;) {
1225 ir_node *block, *next_bl;
1227 block = blk_sched[i];
1229 next_bl = i < n ? blk_sched[i] : NULL;
1231 /* set here the link. the emitter expects to find the next block here */
1232 set_irn_link(block, next_bl);
1233 arm_gen_block(block, last_block);
1237 be_dbg_method_end();
1239 /* emit SymConst values */
1240 if (set_count(sym_or_tv) > 0) {
1243 be_emit_cstring("\t.align 2\n");
1245 foreach_set(sym_or_tv, entry) {
1246 be_emit_irprintf(".L%u:\n", entry->label);
1248 if (entry->is_ident) {
1249 be_emit_cstring("\t.word\t");
1250 be_emit_ident(entry->u.id);
1252 be_emit_write_line();
1254 tarval *tv = entry->u.tv;
1255 int i, size = get_mode_size_bytes(get_tarval_mode(tv));
1258 /* beware: ARM fpa uses big endian format */
1259 for (i = ((size + 3) & ~3) - 4; i >= 0; i -= 4) {
1261 v = get_tarval_sub_bits(tv, i+3);
1262 v = (v << 8) | get_tarval_sub_bits(tv, i+2);
1263 v = (v << 8) | get_tarval_sub_bits(tv, i+1);
1264 v = (v << 8) | get_tarval_sub_bits(tv, i+0);
1265 be_emit_irprintf("\t.word\t%u\n", v);
1266 be_emit_write_line();
1271 be_emit_write_line();
1276 void arm_init_emitter(void)
1278 FIRM_DBG_REGISTER(dbg, "firm.be.arm.emit");