2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
43 #include "raw_bitset.h"
46 #include "../besched.h"
47 #include "../beblocksched.h"
48 #include "../beirg_t.h"
49 #include "../begnuas.h"
50 #include "../be_dbgout.h"
52 #include "arm_emitter.h"
53 #include "arm_optimize.h"
54 #include "gen_arm_emitter.h"
55 #include "arm_nodes_attr.h"
56 #include "arm_new_nodes.h"
57 #include "arm_map_regs.h"
58 #include "gen_arm_regalloc_if.h"
60 #include "../benode_t.h"
62 #define BLOCK_PREFIX ".L"
64 #define SNPRINTF_BUF_LEN 128
66 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
68 static const arm_code_gen_t *cg;
69 static set *sym_or_tv;
72 * Returns the register at in position pos.
74 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
76 const arch_register_t *reg = NULL;
78 assert(get_irn_arity(irn) > pos && "Invalid IN position");
80 /* The out register of the operator at position pos is the
81 in register we need. */
82 op = get_irn_n(irn, pos);
84 reg = arch_get_irn_register(op);
86 assert(reg && "no in register found");
88 /* in case of a joker register: just return a valid register */
89 if (arch_register_type_is(reg, joker)) {
90 const arch_register_req_t *req = arch_get_register_req(irn, pos);
92 if (arch_register_req_is(req, limited)) {
93 /* in case of limited requirements: get the first allowed register */
94 unsigned idx = rbitset_next(req->limited, 0, 1);
95 reg = arch_register_for_index(req->cls, idx);
97 /* otherwise get first register in class */
98 reg = arch_register_for_index(req->cls, 0);
106 * Returns the register at out position pos.
108 static const arch_register_t *get_out_reg(const ir_node *node, int pos)
111 const arch_register_t *reg = NULL;
113 /* 1st case: irn is not of mode_T, so it has only */
114 /* one OUT register -> good */
115 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
116 /* Proj with the corresponding projnum for the register */
118 if (get_irn_mode(node) != mode_T) {
119 reg = arch_get_irn_register(node);
120 } else if (is_arm_irn(node)) {
121 reg = get_arm_out_reg(node, pos);
123 const ir_edge_t *edge;
125 foreach_out_edge(node, edge) {
126 proj = get_edge_src_irn(edge);
127 assert(is_Proj(proj) && "non-Proj from mode_T node");
128 if (get_Proj_proj(proj) == pos) {
129 reg = arch_get_irn_register(proj);
135 assert(reg && "no out register found");
139 /*************************************************************
141 * (_) | | / _| | | | |
142 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
143 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
144 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
145 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
148 *************************************************************/
151 * Emit the name of the source register at given input position.
153 void arm_emit_source_register(const ir_node *node, int pos) {
154 const arch_register_t *reg = get_in_reg(node, pos);
155 be_emit_string(arch_register_get_name(reg));
159 * Emit the name of the destination register at given output position.
161 void arm_emit_dest_register(const ir_node *node, int pos) {
162 const arch_register_t *reg = get_out_reg(node, pos);
163 be_emit_string(arch_register_get_name(reg));
167 * Emit a node's offset.
169 void arm_emit_offset(const ir_node *node) {
171 ir_opcode opc = get_irn_opcode(node);
173 if (opc == beo_Reload || opc == beo_Spill) {
174 ir_entity *ent = be_get_frame_entity(node);
175 offset = get_entity_offset(ent);
177 assert(!"unimplemented arm_emit_offset for this node type");
178 panic("unimplemented arm_emit_offset for this node type");
180 be_emit_irprintf("%d", offset);
184 * Emit the arm fpa instruction suffix depending on the mode.
186 static void arm_emit_fpa_postfix(const ir_mode *mode) {
187 int bits = get_mode_size_bits(mode);
198 * Emit the instruction suffix depending on the mode.
200 void arm_emit_mode(const ir_node *node) {
203 if (is_arm_irn(node)) {
204 const arm_attr_t *attr = get_arm_attr_const(node);
205 mode = attr->op_mode ? attr->op_mode : get_irn_mode(node);
207 mode = get_irn_mode(node);
209 arm_emit_fpa_postfix(mode);
213 * Emit a const or SymConst value.
215 void arm_emit_immediate(const ir_node *node) {
216 const arm_attr_t *attr = get_arm_attr_const(node);
218 if (ARM_GET_SHF_MOD(attr) == ARM_SHF_IMM) {
219 be_emit_irprintf("#0x%X", arm_decode_imm_w_shift(get_arm_imm_value(node)));
220 } else if (ARM_GET_FPA_IMM(attr)) {
221 be_emit_irprintf("#%s", arm_get_fpa_imm_name(get_arm_imm_value(node)));
222 } else if (is_arm_SymConst(node))
223 be_emit_ident(get_arm_symconst_id(node));
225 assert(!"not a Constant");
230 * Returns the tarval or offset of an arm node as a string.
232 void arm_emit_shift(const ir_node *node) {
233 arm_shift_modifier mod;
235 mod = get_arm_shift_modifier(node);
236 if (ARM_HAS_SHIFT(mod)) {
237 int v = get_arm_imm_value(node);
239 be_emit_irprintf(", %s #%d", arm_shf_mod_name(mod), v);
243 /** An entry in the sym_or_tv set. */
244 typedef struct sym_or_tv_t {
246 ident *id; /**< An ident. */
247 tarval *tv; /**< A tarval. */
248 const void *generic; /**< For generic compare. */
250 unsigned label; /**< the associated label. */
251 char is_ident; /**< Non-zero if an ident is stored. */
255 * Returns a unique label. This number will not be used a second time.
257 static unsigned get_unique_label(void) {
258 static unsigned id = 0;
265 static void emit_arm_SymConst(const ir_node *irn) {
266 sym_or_tv_t key, *entry;
269 key.u.id = get_arm_symconst_id(irn);
272 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
273 if (entry->label == 0) {
274 /* allocate a label */
275 entry->label = get_unique_label();
277 label = entry->label;
279 /* load the symbol indirect */
280 be_emit_cstring("\tldr ");
281 arm_emit_dest_register(irn, 0);
282 be_emit_irprintf(", .L%u", label);
283 be_emit_finish_line_gas(irn);
287 * Emit a floating point fpa constant.
289 static void emit_arm_fpaConst(const ir_node *irn) {
290 sym_or_tv_t key, *entry;
294 key.u.tv = get_fpaConst_value(irn);
297 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
298 if (entry->label == 0) {
299 /* allocate a label */
300 entry->label = get_unique_label();
302 label = entry->label;
304 /* load the tarval indirect */
305 mode = get_irn_mode(irn);
306 be_emit_cstring("\tldf");
307 arm_emit_fpa_postfix(mode);
310 arm_emit_dest_register(irn, 0);
311 be_emit_irprintf(", .L%u", label);
312 be_emit_finish_line_gas(irn);
316 * Returns the next block in a block schedule.
318 static ir_node *sched_next_block(const ir_node *block) {
319 return get_irn_link(block);
323 * Returns the target block for a control flow node.
325 static ir_node *get_cfop_target_block(const ir_node *irn) {
326 return get_irn_link(irn);
330 * Emits a block label for the given block.
332 static void arm_emit_block_name(const ir_node *block) {
333 if (has_Block_label(block)) {
334 be_emit_string(be_gas_block_label_prefix());
335 be_emit_irprintf("%lu", get_Block_label(block));
337 be_emit_cstring(BLOCK_PREFIX);
338 be_emit_irprintf("%d", get_irn_node_nr(block));
343 * Emit the target label for a control flow node.
345 static void arm_emit_cfop_target(const ir_node *irn) {
346 ir_node *block = get_cfop_target_block(irn);
348 arm_emit_block_name(block);
352 * Emit a Compare with conditional branch.
354 static void emit_arm_CmpBra(const ir_node *irn) {
355 const ir_edge_t *edge;
356 const ir_node *proj_true = NULL;
357 const ir_node *proj_false = NULL;
358 const ir_node *block;
359 const ir_node *next_block;
360 ir_node *op1 = get_irn_n(irn, 0);
361 ir_mode *opmode = get_irn_mode(op1);
363 int proj_num = get_arm_CondJmp_proj_num(irn);
365 foreach_out_edge(irn, edge) {
366 ir_node *proj = get_edge_src_irn(edge);
367 long nr = get_Proj_proj(proj);
368 if (nr == pn_Cond_true) {
375 /* for now, the code works for scheduled and non-schedules blocks */
376 block = get_nodes_block(irn);
378 /* we have a block schedule */
379 next_block = sched_next_block(block);
381 if (proj_num == pn_Cmp_False) {
382 /* always false: should not happen */
383 be_emit_cstring("\tb ");
384 arm_emit_cfop_target(proj_false);
385 be_emit_finish_line_gas(proj_false);
386 } else if (proj_num == pn_Cmp_True) {
387 /* always true: should not happen */
388 be_emit_cstring("\tb ");
389 arm_emit_cfop_target(proj_true);
390 be_emit_finish_line_gas(proj_true);
392 if (mode_is_float(opmode)) {
393 suffix = "ICHWILLIMPLEMENTIERTWERDEN";
395 be_emit_cstring("\tfcmp ");
396 arm_emit_source_register(irn, 0);
397 be_emit_cstring(", ");
398 arm_emit_source_register(irn, 1);
399 be_emit_finish_line_gas(irn);
401 be_emit_cstring("\tfmstat");
402 be_emit_pad_comment();
403 be_emit_cstring("/* FCSPR -> CPSR */");
404 be_emit_finish_line_gas(NULL);
406 if (get_cfop_target_block(proj_true) == next_block) {
407 /* exchange both proj's so the second one can be omitted */
408 const ir_node *t = proj_true;
410 proj_true = proj_false;
412 proj_num = get_negated_pnc(proj_num, mode_Iu);
415 case pn_Cmp_Eq: suffix = "eq"; break;
416 case pn_Cmp_Lt: suffix = "lt"; break;
417 case pn_Cmp_Le: suffix = "le"; break;
418 case pn_Cmp_Gt: suffix = "gt"; break;
419 case pn_Cmp_Ge: suffix = "ge"; break;
420 case pn_Cmp_Lg: suffix = "ne"; break;
421 case pn_Cmp_Leg: suffix = "al"; break;
422 default: assert(!"Cmp unsupported"); suffix = "al";
424 be_emit_cstring("\tcmp ");
425 arm_emit_source_register(irn, 0);
426 be_emit_cstring(", ");
427 arm_emit_source_register(irn, 1);
428 be_emit_finish_line_gas(irn);
431 /* emit the true proj */
432 be_emit_irprintf("\tb%s ", suffix);
433 arm_emit_cfop_target(proj_true);
434 be_emit_finish_line_gas(proj_true);
436 if (get_cfop_target_block(proj_false) == next_block) {
437 be_emit_cstring("\t/* fallthrough to ");
438 arm_emit_cfop_target(proj_false);
439 be_emit_cstring(" */");
440 be_emit_finish_line_gas(proj_false);
442 be_emit_cstring("b ");
443 arm_emit_cfop_target(proj_false);
444 be_emit_finish_line_gas(proj_false);
451 * Emit a Tst with conditional branch.
453 static void emit_arm_TstBra(const ir_node *irn)
455 const ir_edge_t *edge;
456 const ir_node *proj_true = NULL;
457 const ir_node *proj_false = NULL;
458 const ir_node *block;
459 const ir_node *next_block;
461 int proj_num = get_arm_CondJmp_proj_num(irn);
463 foreach_out_edge(irn, edge) {
464 ir_node *proj = get_edge_src_irn(edge);
465 long nr = get_Proj_proj(proj);
466 if (nr == pn_Cond_true) {
473 /* for now, the code works for scheduled and non-schedules blocks */
474 block = get_nodes_block(irn);
476 /* we have a block schedule */
477 next_block = sched_next_block(block);
479 assert(proj_num != pn_Cmp_False);
480 assert(proj_num != pn_Cmp_True);
482 if (get_cfop_target_block(proj_true) == next_block) {
483 /* exchange both proj's so the second one can be omitted */
484 const ir_node *t = proj_true;
486 proj_true = proj_false;
488 proj_num = get_negated_pnc(proj_num, mode_Iu);
491 case pn_Cmp_Eq: suffix = "eq"; break;
492 case pn_Cmp_Lt: suffix = "lt"; break;
493 case pn_Cmp_Le: suffix = "le"; break;
494 case pn_Cmp_Gt: suffix = "gt"; break;
495 case pn_Cmp_Ge: suffix = "ge"; break;
496 case pn_Cmp_Lg: suffix = "ne"; break;
497 case pn_Cmp_Leg: suffix = "al"; break;
498 default: assert(!"Cmp unsupported"); suffix = "al";
500 be_emit_cstring("\ttst ");
501 arm_emit_source_register(irn, 0);
502 be_emit_cstring(", ");
503 arm_emit_source_register(irn, 1);
504 be_emit_finish_line_gas(irn);
506 /* emit the true proj */
507 be_emit_irprintf("\tb%s ", suffix);
508 arm_emit_cfop_target(proj_true);
509 be_emit_finish_line_gas(proj_true);
511 if (get_cfop_target_block(proj_false) == next_block) {
512 be_emit_cstring("\t/* fallthrough to ");
513 arm_emit_cfop_target(proj_false);
514 be_emit_cstring(" */");
515 be_emit_finish_line_gas(proj_false);
517 be_emit_cstring("b ");
518 arm_emit_cfop_target(proj_false);
519 be_emit_finish_line_gas(proj_false);
524 * Emit a Compare with conditional branch.
526 static void emit_arm_fpaCmfBra(const ir_node *irn) {
531 * Emit a Compare with conditional branch.
533 static void emit_arm_fpaCmfeBra(const ir_node *irn) {
537 /** Sort register in ascending order. */
538 static int reg_cmp(const void *a, const void *b) {
539 const arch_register_t * const *ra = a;
540 const arch_register_t * const *rb = b;
542 return *ra < *rb ? -1 : (*ra != *rb);
546 * Create the CopyB instruction sequence.
548 static void emit_arm_CopyB(const ir_node *irn) {
549 unsigned size = (unsigned)get_arm_imm_value(irn);
551 const char *tgt = arch_register_get_name(get_in_reg(irn, 0));
552 const char *src = arch_register_get_name(get_in_reg(irn, 1));
553 const char *t0, *t1, *t2, *t3;
555 const arch_register_t *tmpregs[4];
557 /* collect the temporary registers and sort them, we need ascending order */
558 tmpregs[0] = get_in_reg(irn, 2);
559 tmpregs[1] = get_in_reg(irn, 3);
560 tmpregs[2] = get_in_reg(irn, 4);
561 tmpregs[3] = &arm_gp_regs[REG_R12];
563 /* Note: R12 is always the last register because the RA did not assign higher ones */
564 qsort((void *)tmpregs, 3, sizeof(tmpregs[0]), reg_cmp);
566 /* need ascending order */
567 t0 = arch_register_get_name(tmpregs[0]);
568 t1 = arch_register_get_name(tmpregs[1]);
569 t2 = arch_register_get_name(tmpregs[2]);
570 t3 = arch_register_get_name(tmpregs[3]);
572 be_emit_cstring("/* MemCopy (");
574 be_emit_cstring(")->(");
575 arm_emit_source_register(irn, 0);
576 be_emit_irprintf(" [%u bytes], Uses ", size);
578 be_emit_cstring(", ");
580 be_emit_cstring(", ");
582 be_emit_cstring(", and ");
584 be_emit_cstring("*/");
585 be_emit_finish_line_gas(NULL);
587 assert(size > 0 && "CopyB needs size > 0" );
590 assert(!"strange hack enabled: copy more bytes than needed!");
599 be_emit_cstring("\tldr ");
601 be_emit_cstring(", [");
603 be_emit_cstring(", #0]");
604 be_emit_finish_line_gas(NULL);
606 be_emit_cstring("\tstr ");
608 be_emit_cstring(", [");
610 be_emit_cstring(", #0]");
611 be_emit_finish_line_gas(irn);
614 be_emit_cstring("\tldmia ");
616 be_emit_cstring("!, {");
618 be_emit_cstring(", ");
621 be_emit_finish_line_gas(NULL);
623 be_emit_cstring("\tstmia ");
625 be_emit_cstring("!, {");
627 be_emit_cstring(", ");
630 be_emit_finish_line_gas(irn);
633 be_emit_cstring("\tldmia ");
635 be_emit_cstring("!, {");
637 be_emit_cstring(", ");
639 be_emit_cstring(", ");
642 be_emit_finish_line_gas(NULL);
644 be_emit_cstring("\tstmia ");
646 be_emit_cstring("!, {");
648 be_emit_cstring(", ");
650 be_emit_cstring(", ");
653 be_emit_finish_line_gas(irn);
658 be_emit_cstring("\tldmia ");
660 be_emit_cstring("!, {");
662 be_emit_cstring(", ");
664 be_emit_cstring(", ");
666 be_emit_cstring(", ");
669 be_emit_finish_line_gas(NULL);
671 be_emit_cstring("\tstmia ");
673 be_emit_cstring("!, {");
675 be_emit_cstring(", ");
677 be_emit_cstring(", ");
679 be_emit_cstring(", ");
682 be_emit_finish_line_gas(irn);
687 static void emit_arm_SwitchJmp(const ir_node *irn) {
688 const ir_edge_t *edge;
694 ir_node *default_proj = NULL;
696 block_nr = get_irn_node_nr(irn);
697 n_projs = get_arm_SwitchJmp_n_projs(irn);
699 projs = XMALLOCNZ(ir_node*, n_projs);
701 foreach_out_edge(irn, edge) {
702 proj = get_edge_src_irn(edge);
703 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
705 if (get_Proj_proj(proj) == get_arm_SwitchJmp_default_proj_num(irn))
708 projs[get_Proj_proj(proj)] = proj;
710 assert(default_proj != NULL && "SwitchJmp should have a Default Proj");
717 be_emit_cstring("\tcmp ");
718 arm_emit_source_register(irn, 0);
719 be_emit_irprintf(", #%u", n_projs - 1);
720 be_emit_finish_line_gas(irn);
722 be_emit_cstring("\tbhi ");
723 arm_emit_cfop_target(default_proj);
724 be_emit_finish_line_gas(default_proj);
727 LDR %r12, .TABLE_X_START
728 ADD %r12, %r12, [%1S, LSL #2]
732 be_emit_irprintf("\tldr %%r12, TABLE_%d_START", block_nr);
733 be_emit_finish_line_gas(NULL);
735 be_emit_irprintf("\tadd %%r12, %%r12, ");
736 arm_emit_source_register(irn, 0);
737 be_emit_cstring(", LSL #2");
738 be_emit_finish_line_gas(NULL);
740 be_emit_cstring("\tldr %r15, [%r12, #0]");
741 be_emit_finish_line_gas(NULL);
743 be_emit_irprintf("TABLE_%d_START:\n\t.word\tTABLE_%d", block_nr, block_nr);
744 be_emit_finish_line_gas(NULL);
745 be_emit_irprintf("\t.align 2");
746 be_emit_finish_line_gas(NULL);
747 be_emit_irprintf("TABLE_%d:", block_nr);
748 be_emit_finish_line_gas(NULL);
750 for (i = 0; i < n_projs; ++i) {
753 proj = projs[get_arm_SwitchJmp_default_proj_num(irn)];
755 be_emit_cstring("\t.word\t");
756 arm_emit_cfop_target(proj);
757 be_emit_finish_line_gas(proj);
759 be_emit_irprintf("\t.align 2\n");
760 be_emit_finish_line_gas(NULL);
764 /************************************************************************/
766 /************************************************************************/
768 static void emit_be_Call(const ir_node *irn) {
769 ir_entity *ent = be_Call_get_entity(irn);
771 be_emit_cstring("\tbl ");
773 set_entity_backend_marked(ent, 1);
774 be_emit_ident(get_entity_ld_ident(ent));
776 arm_emit_source_register(irn, be_pos_Call_ptr);
778 be_emit_finish_line_gas(irn);
781 /** Emit an IncSP node */
782 static void emit_be_IncSP(const ir_node *irn) {
783 int offs = -be_get_IncSP_offset(irn);
787 be_emit_cstring("\tsub ");
790 be_emit_cstring("\tadd ");
792 arm_emit_dest_register(irn, 0);
793 be_emit_cstring(", ");
794 arm_emit_source_register(irn, 0);
795 be_emit_irprintf(", #0x%X", offs);
797 /* omitted IncSP(0) */
800 be_emit_finish_line_gas(irn);
803 static void emit_be_Copy(const ir_node *irn) {
804 ir_mode *mode = get_irn_mode(irn);
806 if (get_in_reg(irn, 0) == get_out_reg(irn, 0)) {
811 if (mode_is_float(mode)) {
812 if (USE_FPA(cg->isa)) {
813 be_emit_cstring("\tmvf");
816 arm_emit_dest_register(irn, 0);
817 be_emit_cstring(", ");
818 arm_emit_source_register(irn, 0);
819 be_emit_finish_line_gas(irn);
821 assert(0 && "move not supported for this mode");
822 panic("emit_be_Copy: move not supported for this mode");
824 } else if (mode_is_data(mode)) {
825 be_emit_cstring("\tmov ");
826 arm_emit_dest_register(irn, 0);
827 be_emit_cstring(", ");
828 arm_emit_source_register(irn, 0);
829 be_emit_finish_line_gas(irn);
831 assert(0 && "move not supported for this mode");
832 panic("emit_be_Copy: move not supported for this mode");
837 * Emit code for a Spill.
839 static void emit_be_Spill(const ir_node *irn) {
840 ir_mode *mode = get_irn_mode(be_get_Spill_val(irn));
842 if (mode_is_float(mode)) {
843 if (USE_FPA(cg->isa)) {
844 be_emit_cstring("\tstf");
845 arm_emit_fpa_postfix(mode);
848 assert(0 && "spill not supported for this mode");
849 panic("emit_be_Spill: spill not supported for this mode");
851 } else if (mode_is_dataM(mode)) {
852 be_emit_cstring("\tstr ");
854 assert(0 && "spill not supported for this mode");
855 panic("emit_be_Spill: spill not supported for this mode");
857 arm_emit_source_register(irn, 1);
858 be_emit_cstring(", [");
859 arm_emit_source_register(irn, 0);
860 be_emit_cstring(", #");
861 arm_emit_offset(irn);
863 be_emit_finish_line_gas(irn);
867 * Emit code for a Reload.
869 static void emit_be_Reload(const ir_node *irn) {
870 ir_mode *mode = get_irn_mode(irn);
872 if (mode_is_float(mode)) {
873 if (USE_FPA(cg->isa)) {
874 be_emit_cstring("\tldf");
875 arm_emit_fpa_postfix(mode);
878 assert(0 && "reload not supported for this mode");
879 panic("emit_be_Reload: reload not supported for this mode");
881 } else if (mode_is_dataM(mode)) {
882 be_emit_cstring("\tldr ");
884 assert(0 && "reload not supported for this mode");
885 panic("emit_be_Reload: reload not supported for this mode");
887 arm_emit_dest_register(irn, 0);
888 be_emit_cstring(", [");
889 arm_emit_source_register(irn, 0);
890 be_emit_cstring(", #");
891 arm_emit_offset(irn);
893 be_emit_finish_line_gas(irn);
896 static void emit_be_Perm(const ir_node *irn) {
897 be_emit_cstring("\teor ");
898 arm_emit_source_register(irn, 0);
899 be_emit_cstring(", ");
900 arm_emit_source_register(irn, 0);
901 be_emit_cstring(", ");
902 arm_emit_source_register(irn, 1);
903 be_emit_finish_line_gas(NULL);
905 be_emit_cstring("\teor ");
906 arm_emit_source_register(irn, 1);
907 be_emit_cstring(", ");
908 arm_emit_source_register(irn, 0);
909 be_emit_cstring(", ");
910 arm_emit_source_register(irn, 1);
911 be_emit_finish_line_gas(NULL);
913 be_emit_cstring("\teor ");
914 arm_emit_source_register(irn, 0);
915 be_emit_cstring(", ");
916 arm_emit_source_register(irn, 0);
917 be_emit_cstring(", ");
918 arm_emit_source_register(irn, 1);
919 be_emit_finish_line_gas(irn);
922 /************************************************************************/
924 /************************************************************************/
926 static void emit_Jmp(const ir_node *node) {
927 ir_node *block, *next_block;
929 /* for now, the code works for scheduled and non-schedules blocks */
930 block = get_nodes_block(node);
932 /* we have a block schedule */
933 next_block = sched_next_block(block);
934 if (get_cfop_target_block(node) != next_block) {
935 be_emit_cstring("\tb ");
936 arm_emit_cfop_target(node);
938 be_emit_cstring("\t/* fallthrough to ");
939 arm_emit_cfop_target(node);
940 be_emit_cstring(" */");
942 be_emit_finish_line_gas(node);
945 static void emit_arm_fpaDbl2GP(const ir_node *irn) {
946 be_emit_cstring("\tstfd ");
947 arm_emit_source_register(irn, 0);
948 be_emit_cstring(", [sp, #-8]!");
949 be_emit_pad_comment();
950 be_emit_cstring("/* Push fp to stack */");
951 be_emit_finish_line_gas(NULL);
953 be_emit_cstring("\tldmfd sp!, {");
954 arm_emit_dest_register(irn, 1);
955 be_emit_cstring(", ");
956 arm_emit_dest_register(irn, 0);
958 be_emit_pad_comment();
959 be_emit_cstring("/* Pop destination */");
960 be_emit_finish_line_gas(irn);
963 static void emit_arm_LdTls(const ir_node *irn) {
965 panic("TLS not supported for this target");
966 /* Er... our gcc does not support it... Install a newer toolchain. */
969 /***********************************************************************************
972 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
973 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
974 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
975 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
977 ***********************************************************************************/
979 static void emit_silence(const ir_node *irn) {
985 * The type of a emitter function.
987 typedef void (emit_func)(const ir_node *irn);
990 * Set a node emitter. Make it a bit more type safe.
992 static inline void set_emitter(ir_op *op, emit_func arm_emit_node) {
993 op->ops.generic = (op_func)arm_emit_node;
997 * Enters the emitter functions for handled nodes into the generic
998 * pointer of an opcode.
1000 static void arm_register_emitters(void) {
1002 #define ARM_EMIT(a) set_emitter(op_arm_##a, emit_arm_##a)
1003 #define EMIT(a) set_emitter(op_##a, emit_##a)
1004 #define BE_EMIT(a) set_emitter(op_be_##a, emit_be_##a)
1005 #define SILENCE(a) set_emitter(op_##a, emit_silence)
1007 /* first clear the generic function pointer for all ops */
1008 clear_irp_opcodes_generic_func();
1010 /* register all emitter functions defined in spec */
1011 arm_register_spec_emitters();
1013 /* other emitter functions */
1016 ARM_EMIT(fpaCmfBra);
1017 ARM_EMIT(fpaCmfeBra);
1019 // ARM_EMIT(CopyB_i);
1022 ARM_EMIT(SwitchJmp);
1023 ARM_EMIT(fpaDbl2GP);
1027 /* benode emitter */
1044 SILENCE(be_CopyKeep);
1045 SILENCE(be_RegParams);
1046 SILENCE(be_Barrier);
1057 * Emits code for a node.
1059 static void arm_emit_node(const ir_node *irn) {
1060 ir_op *op = get_irn_op(irn);
1062 if (op->ops.generic) {
1063 emit_func *emit = (emit_func *)op->ops.generic;
1064 be_dbg_set_dbg_info(get_irn_dbg_info(irn));
1067 be_emit_cstring("\t/* TODO */");
1068 be_emit_finish_line_gas(irn);
1073 * emit the block label if needed.
1075 static void arm_emit_block_header(ir_node *block, ir_node *prev)
1080 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1083 n_cfgpreds = get_Block_n_cfgpreds(block);
1084 if (n_cfgpreds == 1) {
1085 ir_node *pred = get_Block_cfgpred(block, 0);
1086 ir_node *pred_block = get_nodes_block(pred);
1088 /* we don't need labels for fallthrough blocks, however switch-jmps
1089 * are no fallthroughs */
1090 if (pred_block == prev &&
1091 !(is_Proj(pred) && is_arm_SwitchJmp(get_Proj_pred(pred)))) {
1101 arm_emit_block_name(block);
1104 be_emit_pad_comment();
1105 be_emit_cstring(" /* preds:");
1107 /* emit list of pred blocks in comment */
1108 arity = get_irn_arity(block);
1109 for (i = 0; i < arity; ++i) {
1110 ir_node *predblock = get_Block_cfgpred_block(block, i);
1111 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1114 be_emit_cstring("\t/* ");
1115 arm_emit_block_name(block);
1116 be_emit_cstring(": ");
1118 if (exec_freq != NULL) {
1119 be_emit_irprintf(" freq: %f",
1120 get_block_execfreq(exec_freq, block));
1122 be_emit_cstring(" */\n");
1123 be_emit_write_line();
1127 * Walks over the nodes in a block connected by scheduling edges
1128 * and emits code for each node.
1130 static void arm_gen_block(ir_node *block, ir_node *prev_block) {
1133 arm_emit_block_header(block, prev_block);
1134 be_dbg_set_dbg_info(get_irn_dbg_info(block));
1135 sched_foreach(block, irn) {
1141 * Emits code for function start.
1143 void arm_func_prolog(ir_graph *irg) {
1144 ir_entity *ent = get_irg_entity(irg);
1145 const char *irg_name = get_entity_ld_name(ent);
1147 be_emit_write_line();
1148 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1149 be_emit_cstring("\t.align 2\n");
1151 if (get_entity_visibility(ent) == visibility_external_visible)
1152 be_emit_irprintf("\t.global %s\n", irg_name);
1153 be_emit_irprintf("%s:\n", irg_name);
1157 * Emits code for function end
1159 void arm_emit_end(FILE *F, ir_graph *irg) {
1161 fprintf(F, "\t.ident \"firmcc\"\n");
1166 * Sets labels for control flow nodes (jump target)
1168 static void arm_gen_labels(ir_node *block, void *env) {
1170 int n = get_Block_n_cfgpreds(block);
1173 for (n--; n >= 0; n--) {
1174 pred = get_Block_cfgpred(block, n);
1175 set_irn_link(pred, block);
1180 * Compare two entries of the symbol or tarval set.
1182 static int cmp_sym_or_tv(const void *elt, const void *key, size_t size) {
1183 const sym_or_tv_t *p1 = elt;
1184 const sym_or_tv_t *p2 = key;
1187 /* as an identifier NEVER can point to a tarval, it's enough
1188 to compare it this way */
1189 return p1->u.generic != p2->u.generic;
1193 * Main driver. Emits the code for one routine.
1195 void arm_gen_routine(const arm_code_gen_t *arm_cg, ir_graph *irg) {
1196 ir_node **blk_sched;
1198 ir_node *last_block = NULL;
1199 ir_entity *entity = get_irg_entity(irg);
1202 sym_or_tv = new_set(cmp_sym_or_tv, 8);
1204 arm_register_emitters();
1206 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
1208 /* create the block schedule. For now, we don't need it earlier. */
1209 blk_sched = be_create_block_schedule(cg->irg, cg->birg->exec_freq);
1211 arm_func_prolog(irg);
1212 irg_block_walk_graph(irg, arm_gen_labels, NULL, NULL);
1214 n = ARR_LEN(blk_sched);
1215 for (i = 0; i < n;) {
1216 ir_node *block, *next_bl;
1218 block = blk_sched[i];
1220 next_bl = i < n ? blk_sched[i] : NULL;
1222 /* set here the link. the emitter expects to find the next block here */
1223 set_irn_link(block, next_bl);
1224 arm_gen_block(block, last_block);
1228 be_dbg_method_end();
1230 /* emit SymConst values */
1231 if (set_count(sym_or_tv) > 0) {
1234 be_emit_cstring("\t.align 2\n");
1236 foreach_set(sym_or_tv, entry) {
1237 be_emit_irprintf(".L%u:\n", entry->label);
1239 if (entry->is_ident) {
1240 be_emit_cstring("\t.word\t");
1241 be_emit_ident(entry->u.id);
1243 be_emit_write_line();
1245 tarval *tv = entry->u.tv;
1246 int i, size = get_mode_size_bytes(get_tarval_mode(tv));
1249 /* beware: ARM fpa uses big endian format */
1250 for (i = ((size + 3) & ~3) - 4; i >= 0; i -= 4) {
1252 v = get_tarval_sub_bits(tv, i+3);
1253 v = (v << 8) | get_tarval_sub_bits(tv, i+2);
1254 v = (v << 8) | get_tarval_sub_bits(tv, i+1);
1255 v = (v << 8) | get_tarval_sub_bits(tv, i+0);
1256 be_emit_irprintf("\t.word\t%u\n", v);
1257 be_emit_write_line();
1262 be_emit_write_line();
1267 void arm_init_emitter(void)
1269 FIRM_DBG_REGISTER(dbg, "firm.be.arm.emit");