2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
41 #include "raw_bitset.h"
44 #include "../besched.h"
45 #include "../beblocksched.h"
47 #include "../begnuas.h"
48 #include "../be_dbgout.h"
50 #include "arm_emitter.h"
51 #include "arm_optimize.h"
52 #include "gen_arm_emitter.h"
53 #include "arm_nodes_attr.h"
54 #include "arm_new_nodes.h"
55 #include "arm_map_regs.h"
56 #include "gen_arm_regalloc_if.h"
58 #include "../benode.h"
60 #define SNPRINTF_BUF_LEN 128
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 static const arm_code_gen_t *cg;
65 static set *sym_or_tv;
68 * Returns the register at in position pos.
70 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
73 const arch_register_t *reg = NULL;
75 assert(get_irn_arity(irn) > pos && "Invalid IN position");
77 /* The out register of the operator at position pos is the
78 in register we need. */
79 op = get_irn_n(irn, pos);
81 reg = arch_get_irn_register(op);
83 assert(reg && "no in register found");
85 /* in case of a joker register: just return a valid register */
86 if (arch_register_type_is(reg, joker)) {
87 const arch_register_req_t *req = arch_get_register_req(irn, pos);
89 if (arch_register_req_is(req, limited)) {
90 /* in case of limited requirements: get the first allowed register */
91 unsigned idx = rbitset_next(req->limited, 0, 1);
92 reg = arch_register_for_index(req->cls, idx);
94 /* otherwise get first register in class */
95 reg = arch_register_for_index(req->cls, 0);
103 * Returns the register at out position pos.
105 static const arch_register_t *get_out_reg(const ir_node *node, int pos)
108 const arch_register_t *reg = NULL;
110 /* 1st case: irn is not of mode_T, so it has only */
111 /* one OUT register -> good */
112 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
113 /* Proj with the corresponding projnum for the register */
115 if (get_irn_mode(node) != mode_T) {
116 reg = arch_get_irn_register(node);
117 } else if (is_arm_irn(node)) {
118 reg = arch_irn_get_register(node, pos);
120 const ir_edge_t *edge;
122 foreach_out_edge(node, edge) {
123 proj = get_edge_src_irn(edge);
124 assert(is_Proj(proj) && "non-Proj from mode_T node");
125 if (get_Proj_proj(proj) == pos) {
126 reg = arch_get_irn_register(proj);
132 assert(reg && "no out register found");
137 * Emit the name of the source register at given input position.
139 void arm_emit_source_register(const ir_node *node, int pos)
141 const arch_register_t *reg = get_in_reg(node, pos);
142 be_emit_string(arch_register_get_name(reg));
146 * Emit the name of the destination register at given output position.
148 void arm_emit_dest_register(const ir_node *node, int pos)
150 const arch_register_t *reg = get_out_reg(node, pos);
151 be_emit_string(arch_register_get_name(reg));
155 * Emit a node's offset.
157 void arm_emit_offset(const ir_node *node)
159 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
160 assert(attr->base.is_load_store);
162 be_emit_irprintf("0x%X", attr->offset);
166 * Emit the arm fpa instruction suffix depending on the mode.
168 static void arm_emit_fpa_postfix(const ir_mode *mode)
170 int bits = get_mode_size_bits(mode);
181 * Emit the instruction suffix depending on the mode.
183 void arm_emit_mode(const ir_node *node)
187 if (is_arm_irn(node)) {
188 const arm_attr_t *attr = get_arm_attr_const(node);
189 mode = attr->op_mode ? attr->op_mode : get_irn_mode(node);
191 mode = get_irn_mode(node);
193 arm_emit_fpa_postfix(mode);
196 void arm_emit_load_mode(const ir_node *node)
198 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
199 ir_mode *mode = attr->load_store_mode;
200 int bits = get_mode_size_bits(mode);
201 bool is_signed = mode_is_signed(mode);
203 be_emit_string(is_signed ? "sh" : "h");
204 } else if (bits == 8) {
205 be_emit_string(is_signed ? "sb" : "b");
211 void arm_emit_store_mode(const ir_node *node)
213 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
214 ir_mode *mode = attr->load_store_mode;
215 int bits = get_mode_size_bits(mode);
217 be_emit_cstring("h");
218 } else if (bits == 8) {
219 be_emit_cstring("b");
226 static void emit_shf_mod_name(arm_shift_modifier mod)
229 case ARM_SHF_ASR_REG:
230 case ARM_SHF_ASR_IMM:
231 be_emit_cstring("asr");
233 case ARM_SHF_LSL_REG:
234 case ARM_SHF_LSL_IMM:
235 be_emit_cstring("lsl");
237 case ARM_SHF_LSR_REG:
238 case ARM_SHF_LSR_IMM:
239 be_emit_cstring("lsr");
241 case ARM_SHF_ROR_REG:
242 case ARM_SHF_ROR_IMM:
243 be_emit_cstring("ror");
248 panic("can't emit this shf_mod_name %d", (int) mod);
251 void arm_emit_shifter_operand(const ir_node *node)
253 const arm_shifter_operand_t *attr = get_irn_generic_attr_const(node);
255 switch (attr->shift_modifier) {
257 arm_emit_source_register(node, get_irn_arity(node) - 1);
260 unsigned val = attr->immediate_value;
261 val = (val >> attr->shift_immediate)
262 | (val << (32-attr->shift_immediate));
264 be_emit_irprintf("#0x%X", val);
267 case ARM_SHF_ASR_IMM:
268 case ARM_SHF_LSL_IMM:
269 case ARM_SHF_LSR_IMM:
270 case ARM_SHF_ROR_IMM:
271 arm_emit_source_register(node, get_irn_arity(node) - 1);
272 be_emit_cstring(", ");
273 emit_shf_mod_name(attr->shift_modifier);
274 be_emit_irprintf(" #0x%X", attr->shift_immediate);
277 case ARM_SHF_ASR_REG:
278 case ARM_SHF_LSL_REG:
279 case ARM_SHF_LSR_REG:
280 case ARM_SHF_ROR_REG:
281 arm_emit_source_register(node, get_irn_arity(node) - 2);
282 be_emit_cstring(", ");
283 emit_shf_mod_name(attr->shift_modifier);
284 be_emit_cstring(" ");
285 arm_emit_source_register(node, get_irn_arity(node) - 1);
289 arm_emit_source_register(node, get_irn_arity(node) - 1);
290 panic("RRX shifter emitter TODO");
293 case ARM_SHF_INVALID:
296 panic("Invalid shift_modifier while emitting %+F", node);
299 /** An entry in the sym_or_tv set. */
300 typedef struct sym_or_tv_t {
302 ident *id; /**< An ident. */
303 tarval *tv; /**< A tarval. */
304 const void *generic; /**< For generic compare. */
306 unsigned label; /**< the associated label. */
307 char is_ident; /**< Non-zero if an ident is stored. */
311 * Returns a unique label. This number will not be used a second time.
313 static unsigned get_unique_label(void)
315 static unsigned id = 0;
322 static void emit_arm_SymConst(const ir_node *irn)
324 const arm_SymConst_attr_t *attr = get_arm_SymConst_attr_const(irn);
325 sym_or_tv_t key, *entry;
328 key.u.id = get_entity_ld_ident(attr->entity);
331 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
332 if (entry->label == 0) {
333 /* allocate a label */
334 entry->label = get_unique_label();
336 label = entry->label;
338 /* load the symbol indirect */
339 be_emit_cstring("\tldr ");
340 arm_emit_dest_register(irn, 0);
341 be_emit_irprintf(", .L%u", label);
342 be_emit_finish_line_gas(irn);
345 static void emit_arm_FrameAddr(const ir_node *irn)
347 const arm_SymConst_attr_t *attr = get_irn_generic_attr_const(irn);
349 be_emit_cstring("\tadd ");
350 arm_emit_dest_register(irn, 0);
351 be_emit_cstring(", ");
352 arm_emit_source_register(irn, 0);
353 be_emit_cstring(", ");
354 be_emit_irprintf("#0x%X", attr->fp_offset);
355 be_emit_finish_line_gas(irn);
359 * Emit a floating point fpa constant.
361 static void emit_arm_fpaConst(const ir_node *irn)
363 sym_or_tv_t key, *entry;
367 key.u.tv = get_fpaConst_value(irn);
370 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
371 if (entry->label == 0) {
372 /* allocate a label */
373 entry->label = get_unique_label();
375 label = entry->label;
377 /* load the tarval indirect */
378 mode = get_irn_mode(irn);
379 be_emit_cstring("\tldf");
380 arm_emit_fpa_postfix(mode);
383 arm_emit_dest_register(irn, 0);
384 be_emit_irprintf(", .L%u", label);
385 be_emit_finish_line_gas(irn);
389 * Returns the next block in a block schedule.
391 static ir_node *sched_next_block(const ir_node *block)
393 return get_irn_link(block);
397 * Returns the target block for a control flow node.
399 static ir_node *get_cfop_target_block(const ir_node *irn)
401 return get_irn_link(irn);
405 * Emit the target label for a control flow node.
407 static void arm_emit_cfop_target(const ir_node *irn)
409 ir_node *block = get_cfop_target_block(irn);
411 be_gas_emit_block_name(block);
415 * Emit a Compare with conditional branch.
417 static void emit_arm_B(const ir_node *irn)
419 const ir_edge_t *edge;
420 const ir_node *proj_true = NULL;
421 const ir_node *proj_false = NULL;
422 const ir_node *block;
423 const ir_node *next_block;
424 ir_node *op1 = get_irn_n(irn, 0);
426 int proj_num = get_arm_CondJmp_proj_num(irn);
427 const arm_cmp_attr_t *cmp_attr = get_irn_generic_attr_const(op1);
428 bool is_signed = !cmp_attr->is_unsigned;
430 assert(is_arm_Cmp(op1) || is_arm_Tst(op1));
432 foreach_out_edge(irn, edge) {
433 ir_node *proj = get_edge_src_irn(edge);
434 long nr = get_Proj_proj(proj);
435 if (nr == pn_Cond_true) {
442 if (cmp_attr->ins_permuted) {
443 proj_num = get_mirrored_pnc(proj_num);
446 /* for now, the code works for scheduled and non-schedules blocks */
447 block = get_nodes_block(irn);
449 /* we have a block schedule */
450 next_block = sched_next_block(block);
452 assert(proj_num != pn_Cmp_False);
453 assert(proj_num != pn_Cmp_True);
455 if (get_cfop_target_block(proj_true) == next_block) {
456 /* exchange both proj's so the second one can be omitted */
457 const ir_node *t = proj_true;
459 proj_true = proj_false;
461 proj_num = get_negated_pnc(proj_num, mode_Iu);
465 case pn_Cmp_Eq: suffix = "eq"; break;
466 case pn_Cmp_Lt: suffix = is_signed ? "lt" : "lo"; break;
467 case pn_Cmp_Le: suffix = is_signed ? "le" : "ls"; break;
468 case pn_Cmp_Gt: suffix = is_signed ? "gt" : "hi"; break;
469 case pn_Cmp_Ge: suffix = is_signed ? "ge" : "hs"; break;
470 case pn_Cmp_Lg: suffix = "ne"; break;
471 case pn_Cmp_Leg: suffix = "al"; break;
472 default: panic("Cmp has unsupported pnc");
475 /* emit the true proj */
476 be_emit_irprintf("\tb%s ", suffix);
477 arm_emit_cfop_target(proj_true);
478 be_emit_finish_line_gas(proj_true);
480 if (get_cfop_target_block(proj_false) == next_block) {
481 be_emit_cstring("\t/* fallthrough to ");
482 arm_emit_cfop_target(proj_false);
483 be_emit_cstring(" */");
484 be_emit_finish_line_gas(proj_false);
486 be_emit_cstring("\tb ");
487 arm_emit_cfop_target(proj_false);
488 be_emit_finish_line_gas(proj_false);
492 /** Sort register in ascending order. */
493 static int reg_cmp(const void *a, const void *b)
495 const arch_register_t * const *ra = a;
496 const arch_register_t * const *rb = b;
498 return *ra < *rb ? -1 : (*ra != *rb);
502 * Create the CopyB instruction sequence.
504 static void emit_arm_CopyB(const ir_node *irn)
506 const arm_CopyB_attr_t *attr = get_irn_generic_attr_const(irn);
507 unsigned size = attr->size;
509 const char *tgt = arch_register_get_name(get_in_reg(irn, 0));
510 const char *src = arch_register_get_name(get_in_reg(irn, 1));
511 const char *t0, *t1, *t2, *t3;
513 const arch_register_t *tmpregs[4];
515 /* collect the temporary registers and sort them, we need ascending order */
516 tmpregs[0] = get_in_reg(irn, 2);
517 tmpregs[1] = get_in_reg(irn, 3);
518 tmpregs[2] = get_in_reg(irn, 4);
519 tmpregs[3] = &arm_gp_regs[REG_R12];
521 /* Note: R12 is always the last register because the RA did not assign higher ones */
522 qsort((void *)tmpregs, 3, sizeof(tmpregs[0]), reg_cmp);
524 /* need ascending order */
525 t0 = arch_register_get_name(tmpregs[0]);
526 t1 = arch_register_get_name(tmpregs[1]);
527 t2 = arch_register_get_name(tmpregs[2]);
528 t3 = arch_register_get_name(tmpregs[3]);
530 be_emit_cstring("/* MemCopy (");
532 be_emit_cstring(")->(");
533 arm_emit_source_register(irn, 0);
534 be_emit_irprintf(" [%u bytes], Uses ", size);
536 be_emit_cstring(", ");
538 be_emit_cstring(", ");
540 be_emit_cstring(", and ");
542 be_emit_cstring("*/");
543 be_emit_finish_line_gas(NULL);
545 assert(size > 0 && "CopyB needs size > 0" );
548 assert(!"strange hack enabled: copy more bytes than needed!");
557 be_emit_cstring("\tldr ");
559 be_emit_cstring(", [");
561 be_emit_cstring(", #0]");
562 be_emit_finish_line_gas(NULL);
564 be_emit_cstring("\tstr ");
566 be_emit_cstring(", [");
568 be_emit_cstring(", #0]");
569 be_emit_finish_line_gas(irn);
572 be_emit_cstring("\tldmia ");
574 be_emit_cstring("!, {");
576 be_emit_cstring(", ");
579 be_emit_finish_line_gas(NULL);
581 be_emit_cstring("\tstmia ");
583 be_emit_cstring("!, {");
585 be_emit_cstring(", ");
588 be_emit_finish_line_gas(irn);
591 be_emit_cstring("\tldmia ");
593 be_emit_cstring("!, {");
595 be_emit_cstring(", ");
597 be_emit_cstring(", ");
600 be_emit_finish_line_gas(NULL);
602 be_emit_cstring("\tstmia ");
604 be_emit_cstring("!, {");
606 be_emit_cstring(", ");
608 be_emit_cstring(", ");
611 be_emit_finish_line_gas(irn);
616 be_emit_cstring("\tldmia ");
618 be_emit_cstring("!, {");
620 be_emit_cstring(", ");
622 be_emit_cstring(", ");
624 be_emit_cstring(", ");
627 be_emit_finish_line_gas(NULL);
629 be_emit_cstring("\tstmia ");
631 be_emit_cstring("!, {");
633 be_emit_cstring(", ");
635 be_emit_cstring(", ");
637 be_emit_cstring(", ");
640 be_emit_finish_line_gas(irn);
645 static void emit_arm_SwitchJmp(const ir_node *irn)
647 const ir_edge_t *edge;
653 ir_node *default_proj = NULL;
655 block_nr = get_irn_node_nr(irn);
656 n_projs = get_arm_SwitchJmp_n_projs(irn);
658 projs = XMALLOCNZ(ir_node*, n_projs);
660 foreach_out_edge(irn, edge) {
661 proj = get_edge_src_irn(edge);
662 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
664 if (get_Proj_proj(proj) == get_arm_SwitchJmp_default_proj_num(irn))
667 projs[get_Proj_proj(proj)] = proj;
669 assert(default_proj != NULL && "SwitchJmp should have a Default Proj");
676 be_emit_cstring("\tcmp ");
677 arm_emit_source_register(irn, 0);
678 be_emit_irprintf(", #%u", n_projs - 1);
679 be_emit_finish_line_gas(irn);
681 be_emit_cstring("\tbhi ");
682 arm_emit_cfop_target(default_proj);
683 be_emit_finish_line_gas(default_proj);
686 LDR %r12, .TABLE_X_START
687 ADD %r12, %r12, [%1S, LSL #2]
691 be_emit_irprintf("\tldr %%r12, TABLE_%d_START", block_nr);
692 be_emit_finish_line_gas(NULL);
694 be_emit_irprintf("\tadd %%r12, %%r12, ");
695 arm_emit_source_register(irn, 0);
696 be_emit_cstring(", LSL #2");
697 be_emit_finish_line_gas(NULL);
699 be_emit_cstring("\tldr %r15, [%r12, #0]");
700 be_emit_finish_line_gas(NULL);
702 be_emit_irprintf("TABLE_%d_START:\n\t.word\tTABLE_%d", block_nr, block_nr);
703 be_emit_finish_line_gas(NULL);
704 be_emit_irprintf("\t.align 2");
705 be_emit_finish_line_gas(NULL);
706 be_emit_irprintf("TABLE_%d:", block_nr);
707 be_emit_finish_line_gas(NULL);
709 for (i = 0; i < n_projs; ++i) {
712 proj = projs[get_arm_SwitchJmp_default_proj_num(irn)];
714 be_emit_cstring("\t.word\t");
715 arm_emit_cfop_target(proj);
716 be_emit_finish_line_gas(proj);
718 be_emit_irprintf("\t.align 2\n");
719 be_emit_finish_line_gas(NULL);
723 /************************************************************************/
725 /************************************************************************/
727 static void arm_emit_entity(ir_entity *entity)
729 be_emit_ident(get_entity_ld_ident(entity));
732 static void emit_be_Call(const ir_node *irn)
734 ir_entity *entity = be_Call_get_entity(irn);
736 if (entity != NULL) {
737 be_emit_cstring("\tbl ");
738 arm_emit_entity(entity);
739 be_emit_finish_line_gas(irn);
741 be_emit_cstring("\tmov lr, pc");
742 be_emit_finish_line_gas(irn);
743 be_emit_cstring("\tmov pc, ");
744 arm_emit_source_register(irn, be_pos_Call_ptr);
745 be_emit_finish_line_gas(irn);
749 /** Emit an IncSP node */
750 static void emit_be_IncSP(const ir_node *irn)
752 int offs = -be_get_IncSP_offset(irn);
756 be_emit_cstring("\tsub ");
759 be_emit_cstring("\tadd ");
761 arm_emit_dest_register(irn, 0);
762 be_emit_cstring(", ");
763 arm_emit_source_register(irn, 0);
764 be_emit_irprintf(", #0x%X", offs);
766 /* omitted IncSP(0) */
769 be_emit_finish_line_gas(irn);
772 static void emit_be_Copy(const ir_node *irn)
774 ir_mode *mode = get_irn_mode(irn);
776 if (get_in_reg(irn, 0) == get_out_reg(irn, 0)) {
781 if (mode_is_float(mode)) {
782 if (USE_FPA(cg->isa)) {
783 be_emit_cstring("\tmvf");
786 arm_emit_dest_register(irn, 0);
787 be_emit_cstring(", ");
788 arm_emit_source_register(irn, 0);
789 be_emit_finish_line_gas(irn);
791 assert(0 && "move not supported for this mode");
792 panic("emit_be_Copy: move not supported for this mode");
794 } else if (mode_is_data(mode)) {
795 be_emit_cstring("\tmov ");
796 arm_emit_dest_register(irn, 0);
797 be_emit_cstring(", ");
798 arm_emit_source_register(irn, 0);
799 be_emit_finish_line_gas(irn);
801 assert(0 && "move not supported for this mode");
802 panic("emit_be_Copy: move not supported for this mode");
806 static void emit_be_Perm(const ir_node *irn)
808 be_emit_cstring("\teor ");
809 arm_emit_source_register(irn, 0);
810 be_emit_cstring(", ");
811 arm_emit_source_register(irn, 0);
812 be_emit_cstring(", ");
813 arm_emit_source_register(irn, 1);
814 be_emit_finish_line_gas(NULL);
816 be_emit_cstring("\teor ");
817 arm_emit_source_register(irn, 1);
818 be_emit_cstring(", ");
819 arm_emit_source_register(irn, 0);
820 be_emit_cstring(", ");
821 arm_emit_source_register(irn, 1);
822 be_emit_finish_line_gas(NULL);
824 be_emit_cstring("\teor ");
825 arm_emit_source_register(irn, 0);
826 be_emit_cstring(", ");
827 arm_emit_source_register(irn, 0);
828 be_emit_cstring(", ");
829 arm_emit_source_register(irn, 1);
830 be_emit_finish_line_gas(irn);
833 static void emit_be_MemPerm(const ir_node *node)
839 /* TODO: this implementation is slower than necessary.
840 The longterm goal is however to avoid the memperm node completely */
842 memperm_arity = be_get_MemPerm_entity_arity(node);
843 if (memperm_arity > 12)
844 panic("memperm with more than 12 inputs not supported yet");
846 for (i = 0; i < memperm_arity; ++i) {
848 ir_entity *entity = be_get_MemPerm_in_entity(node, i);
851 be_emit_irprintf("\tstr r%d, [sp, #-4]!", i);
852 be_emit_finish_line_gas(node);
854 /* load from entity */
855 offset = get_entity_offset(entity) + sp_change;
856 be_emit_irprintf("\tldr r%d, [sp, #%d]", i, offset);
857 be_emit_finish_line_gas(node);
860 for (i = memperm_arity-1; i >= 0; --i) {
862 ir_entity *entity = be_get_MemPerm_out_entity(node, i);
864 /* store to new entity */
865 offset = get_entity_offset(entity) + sp_change;
866 be_emit_irprintf("\tstr r%d, [sp, #%d]", i, offset);
867 be_emit_finish_line_gas(node);
868 /* restore register */
869 be_emit_irprintf("\tldr r%d, [sp], #4", i);
871 be_emit_finish_line_gas(node);
873 assert(sp_change == 0);
876 static void emit_be_Return(const ir_node *node)
878 be_emit_cstring("\tmov pc, lr");
879 be_emit_finish_line_gas(node);
882 /************************************************************************/
884 /************************************************************************/
886 static void emit_arm_Jmp(const ir_node *node)
888 ir_node *block, *next_block;
890 /* for now, the code works for scheduled and non-schedules blocks */
891 block = get_nodes_block(node);
893 /* we have a block schedule */
894 next_block = sched_next_block(block);
895 if (get_cfop_target_block(node) != next_block) {
896 be_emit_cstring("\tb ");
897 arm_emit_cfop_target(node);
899 be_emit_cstring("\t/* fallthrough to ");
900 arm_emit_cfop_target(node);
901 be_emit_cstring(" */");
903 be_emit_finish_line_gas(node);
906 static void emit_arm_fpaDbl2GP(const ir_node *irn)
908 be_emit_cstring("\tstfd ");
909 arm_emit_source_register(irn, 0);
910 be_emit_cstring(", [sp, #-8]!");
911 be_emit_pad_comment();
912 be_emit_cstring("/* Push fp to stack */");
913 be_emit_finish_line_gas(NULL);
915 be_emit_cstring("\tldmfd sp!, {");
916 arm_emit_dest_register(irn, 1);
917 be_emit_cstring(", ");
918 arm_emit_dest_register(irn, 0);
920 be_emit_pad_comment();
921 be_emit_cstring("/* Pop destination */");
922 be_emit_finish_line_gas(irn);
925 static void emit_arm_LdTls(const ir_node *irn)
928 panic("TLS not supported for this target");
929 /* Er... our gcc does not support it... Install a newer toolchain. */
932 static void emit_nothing(const ir_node *irn)
938 * The type of a emitter function.
940 typedef void (emit_func)(const ir_node *irn);
943 * Set a node emitter. Make it a bit more type safe.
945 static inline void set_emitter(ir_op *op, emit_func arm_emit_node)
947 op->ops.generic = (op_func)arm_emit_node;
951 * Enters the emitter functions for handled nodes into the generic
952 * pointer of an opcode.
954 static void arm_register_emitters(void)
956 /* first clear the generic function pointer for all ops */
957 clear_irp_opcodes_generic_func();
959 /* register all emitter functions defined in spec */
960 arm_register_spec_emitters();
963 set_emitter(op_arm_B, emit_arm_B);
964 set_emitter(op_arm_CopyB, emit_arm_CopyB);
965 set_emitter(op_arm_fpaConst, emit_arm_fpaConst);
966 set_emitter(op_arm_fpaDbl2GP, emit_arm_fpaDbl2GP);
967 set_emitter(op_arm_FrameAddr, emit_arm_FrameAddr);
968 set_emitter(op_arm_Jmp, emit_arm_Jmp);
969 set_emitter(op_arm_LdTls, emit_arm_LdTls);
970 set_emitter(op_arm_SwitchJmp, emit_arm_SwitchJmp);
971 set_emitter(op_arm_SymConst, emit_arm_SymConst);
972 set_emitter(op_be_Call, emit_be_Call);
973 set_emitter(op_be_Copy, emit_be_Copy);
974 set_emitter(op_be_CopyKeep, emit_be_Copy);
975 set_emitter(op_be_IncSP, emit_be_IncSP);
976 set_emitter(op_be_MemPerm, emit_be_MemPerm);
977 set_emitter(op_be_Perm, emit_be_Perm);
978 set_emitter(op_be_Return, emit_be_Return);
980 /* no need to emit anything for the following nodes */
981 set_emitter(op_Phi, emit_nothing);
982 set_emitter(op_be_Keep, emit_nothing);
983 set_emitter(op_be_Start, emit_nothing);
984 set_emitter(op_be_Barrier, emit_nothing);
988 * Emits code for a node.
990 static void arm_emit_node(const ir_node *irn)
992 ir_op *op = get_irn_op(irn);
994 if (op->ops.generic) {
995 emit_func *emit = (emit_func *)op->ops.generic;
996 be_dbg_set_dbg_info(get_irn_dbg_info(irn));
999 panic("Error: No emit handler for node %+F (graph %+F)\n",
1000 irn, current_ir_graph);
1005 * emit the block label if needed.
1007 static void arm_emit_block_header(ir_node *block, ir_node *prev)
1012 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1015 n_cfgpreds = get_Block_n_cfgpreds(block);
1016 if (n_cfgpreds == 1) {
1017 ir_node *pred = get_Block_cfgpred(block, 0);
1018 ir_node *pred_block = get_nodes_block(pred);
1020 /* we don't need labels for fallthrough blocks, however switch-jmps
1021 * are no fallthroughs */
1022 if (pred_block == prev &&
1023 !(is_Proj(pred) && is_arm_SwitchJmp(get_Proj_pred(pred)))) {
1033 be_gas_emit_block_name(block);
1036 be_emit_pad_comment();
1037 be_emit_cstring(" /* preds:");
1039 /* emit list of pred blocks in comment */
1040 arity = get_irn_arity(block);
1041 for (i = 0; i < arity; ++i) {
1042 ir_node *predblock = get_Block_cfgpred_block(block, i);
1043 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1046 be_emit_cstring("\t/* ");
1047 be_gas_emit_block_name(block);
1048 be_emit_cstring(": ");
1050 if (exec_freq != NULL) {
1051 be_emit_irprintf(" freq: %f",
1052 get_block_execfreq(exec_freq, block));
1054 be_emit_cstring(" */\n");
1055 be_emit_write_line();
1059 * Walks over the nodes in a block connected by scheduling edges
1060 * and emits code for each node.
1062 static void arm_gen_block(ir_node *block, ir_node *prev_block)
1066 arm_emit_block_header(block, prev_block);
1067 be_dbg_set_dbg_info(get_irn_dbg_info(block));
1068 sched_foreach(block, irn) {
1075 * Sets labels for control flow nodes (jump target)
1077 static void arm_gen_labels(ir_node *block, void *env)
1080 int n = get_Block_n_cfgpreds(block);
1083 for (n--; n >= 0; n--) {
1084 pred = get_Block_cfgpred(block, n);
1085 set_irn_link(pred, block);
1090 * Compare two entries of the symbol or tarval set.
1092 static int cmp_sym_or_tv(const void *elt, const void *key, size_t size)
1094 const sym_or_tv_t *p1 = elt;
1095 const sym_or_tv_t *p2 = key;
1098 /* as an identifier NEVER can point to a tarval, it's enough
1099 to compare it this way */
1100 return p1->u.generic != p2->u.generic;
1104 * Main driver. Emits the code for one routine.
1106 void arm_gen_routine(const arm_code_gen_t *arm_cg, ir_graph *irg)
1108 ir_node **blk_sched;
1110 ir_node *last_block = NULL;
1111 ir_entity *entity = get_irg_entity(irg);
1114 sym_or_tv = new_set(cmp_sym_or_tv, 8);
1116 be_gas_elf_type_char = '%';
1118 arm_register_emitters();
1120 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
1122 /* create the block schedule. For now, we don't need it earlier. */
1123 blk_sched = be_create_block_schedule(cg->irg, cg->birg->exec_freq);
1125 be_gas_emit_function_prolog(entity, 4);
1127 irg_block_walk_graph(irg, arm_gen_labels, NULL, NULL);
1129 n = ARR_LEN(blk_sched);
1130 for (i = 0; i < n;) {
1131 ir_node *block, *next_bl;
1133 block = blk_sched[i];
1135 next_bl = i < n ? blk_sched[i] : NULL;
1137 /* set here the link. the emitter expects to find the next block here */
1138 set_irn_link(block, next_bl);
1139 arm_gen_block(block, last_block);
1143 be_gas_emit_function_epilog(entity);
1144 be_dbg_method_end();
1146 /* emit SymConst values */
1147 if (set_count(sym_or_tv) > 0) {
1150 be_emit_cstring("\t.align 2\n");
1152 foreach_set(sym_or_tv, entry) {
1153 be_emit_irprintf(".L%u:\n", entry->label);
1155 if (entry->is_ident) {
1156 be_emit_cstring("\t.word\t");
1157 be_emit_ident(entry->u.id);
1159 be_emit_write_line();
1161 tarval *tv = entry->u.tv;
1162 int i, size = get_mode_size_bytes(get_tarval_mode(tv));
1165 /* beware: ARM fpa uses big endian format */
1166 for (i = ((size + 3) & ~3) - 4; i >= 0; i -= 4) {
1168 v = get_tarval_sub_bits(tv, i+3);
1169 v = (v << 8) | get_tarval_sub_bits(tv, i+2);
1170 v = (v << 8) | get_tarval_sub_bits(tv, i+1);
1171 v = (v << 8) | get_tarval_sub_bits(tv, i+0);
1172 be_emit_irprintf("\t.word\t%u\n", v);
1173 be_emit_write_line();
1178 be_emit_write_line();
1183 void arm_init_emitter(void)
1185 FIRM_DBG_REGISTER(dbg, "firm.be.arm.emit");