2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
45 #include "raw_bitset.h"
48 #include "../besched.h"
49 #include "../beblocksched.h"
50 #include "../beirg_t.h"
51 #include "../begnuas.h"
52 #include "../be_dbgout.h"
54 #include "arm_emitter.h"
55 #include "gen_arm_emitter.h"
56 #include "arm_nodes_attr.h"
57 #include "arm_new_nodes.h"
58 #include "arm_map_regs.h"
59 #include "gen_arm_regalloc_if.h"
61 #include "../benode_t.h"
63 #define BLOCK_PREFIX ".L"
65 #define SNPRINTF_BUF_LEN 128
67 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
69 static const arch_env_t *arch_env = NULL;
70 static const arm_code_gen_t *cg;
71 static const arm_isa_t *isa;
72 static set *sym_or_tv;
75 * Returns the register at in position pos.
77 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
79 const arch_register_t *reg = NULL;
81 assert(get_irn_arity(irn) > pos && "Invalid IN position");
83 /* The out register of the operator at position pos is the
84 in register we need. */
85 op = get_irn_n(irn, pos);
87 reg = arch_get_irn_register(arch_env, op);
89 assert(reg && "no in register found");
91 /* in case of a joker register: just return a valid register */
92 if (arch_register_type_is(reg, joker)) {
93 const arch_register_req_t *req;
95 /* ask for the requirements */
96 req = arch_get_register_req(arch_env, irn, pos);
98 if (arch_register_req_is(req, limited)) {
99 /* in case of limited requirements: get the first allowed register */
100 unsigned idx = rbitset_next(req->limited, 0, 1);
101 reg = arch_register_for_index(req->cls, idx);
103 /* otherwise get first register in class */
104 reg = arch_register_for_index(req->cls, 0);
112 * Returns the register at out position pos.
114 static const arch_register_t *get_out_reg(const ir_node *node, int pos)
117 const arch_register_t *reg = NULL;
119 /* 1st case: irn is not of mode_T, so it has only */
120 /* one OUT register -> good */
121 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
122 /* Proj with the corresponding projnum for the register */
124 if (get_irn_mode(node) != mode_T) {
125 reg = arch_get_irn_register(arch_env, node);
126 } else if (is_arm_irn(node)) {
127 reg = get_arm_out_reg(node, pos);
129 const ir_edge_t *edge;
131 foreach_out_edge(node, edge) {
132 proj = get_edge_src_irn(edge);
133 assert(is_Proj(proj) && "non-Proj from mode_T node");
134 if (get_Proj_proj(proj) == pos) {
135 reg = arch_get_irn_register(arch_env, proj);
141 assert(reg && "no out register found");
145 /*************************************************************
147 * (_) | | / _| | | | |
148 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
149 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
150 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
151 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
154 *************************************************************/
157 * Emit the name of the source register at given input position.
159 void arm_emit_source_register(const ir_node *node, int pos) {
160 const arch_register_t *reg = get_in_reg(node, pos);
161 be_emit_string(arch_register_get_name(reg));
165 * Emit the name of the destination register at given output position.
167 void arm_emit_dest_register(const ir_node *node, int pos) {
168 const arch_register_t *reg = get_out_reg(node, pos);
169 be_emit_string(arch_register_get_name(reg));
173 * Emit a node's offset.
175 void arm_emit_offset(const ir_node *node) {
177 ir_op *irn_op = get_irn_op(node);
179 if (irn_op == op_be_Reload || irn_op == op_be_Spill) {
180 ir_entity *ent = be_get_frame_entity(node);
181 offset = get_entity_offset(ent);
182 } else if (irn_op == op_be_IncSP) {
183 offset = - be_get_IncSP_offset(node);
185 assert(!"unimplemented arm_emit_offset for this node type");
186 panic("unimplemented arm_emit_offset for this node type");
188 be_emit_irprintf("%d", offset);
192 * Emit the arm fpa instruction suffix depending on the mode.
194 static void arm_emit_fpa_postfix(const ir_mode *mode) {
195 int bits = get_mode_size_bits(mode);
205 * Emit the instruction suffix depending on the mode.
207 void arm_emit_mode(const ir_node *node) {
210 if (is_arm_irn(node)) {
211 const arm_attr_t *attr = get_arm_attr_const(node);
212 mode = attr->op_mode ? attr->op_mode : get_irn_mode(node);
214 mode = get_irn_mode(node);
216 arm_emit_fpa_postfix(mode);
220 * Emit a const or SymConst value.
222 void arm_emit_immediate(const ir_node *node) {
223 const arm_attr_t *attr = get_arm_attr_const(node);
225 if (ARM_GET_SHF_MOD(attr) == ARM_SHF_IMM) {
226 be_emit_irprintf("#0x%X", arm_decode_imm_w_shift(get_arm_imm_value(node)));
227 } else if (ARM_GET_FPA_IMM(attr)) {
228 be_emit_irprintf("#%s", arm_get_fpa_imm_name(get_arm_imm_value(node)));
229 } else if (is_arm_SymConst(node))
230 be_emit_ident(get_arm_symconst_id(node));
232 assert(!"not a Constant");
237 * Returns the tarval or offset of an arm node as a string.
239 void arm_emit_shift(const ir_node *node) {
240 arm_shift_modifier mod;
242 mod = get_arm_shift_modifier(node);
243 if (ARM_HAS_SHIFT(mod)) {
244 long v = get_arm_imm_value(node);
246 be_emit_irprintf(", %s #%l", arm_shf_mod_name(mod), v);
250 /** An entry in the sym_or_tv set. */
251 typedef struct sym_or_tv_t {
253 ident *id; /**< An ident. */
254 tarval *tv; /**< A tarval. */
255 const void *generic; /**< For generic compare. */
257 unsigned label; /**< the associated label. */
258 char is_ident; /**< Non-zero if an ident is stored. */
262 * Returns a unique label. This number will not be used a second time.
264 static unsigned get_unique_label(void) {
265 static unsigned id = 0;
272 static void emit_arm_SymConst(const ir_node *irn) {
273 sym_or_tv_t key, *entry;
276 key.u.id = get_arm_symconst_id(irn);
279 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
280 if (entry->label == 0) {
281 /* allocate a label */
282 entry->label = get_unique_label();
284 label = entry->label;
286 /* load the symbol indirect */
287 be_emit_cstring("\tldr ");
288 arm_emit_dest_register(irn, 0);
289 be_emit_irprintf(", .L%u", label);
290 be_emit_finish_line_gas(irn);
294 * Emit a floating point fpa constant.
296 static void emit_arm_fpaConst(const ir_node *irn) {
297 sym_or_tv_t key, *entry;
301 key.u.tv = get_fpaConst_value(irn);
304 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
305 if (entry->label == 0) {
306 /* allocate a label */
307 entry->label = get_unique_label();
309 label = entry->label;
311 /* load the tarval indirect */
312 mode = get_irn_mode(irn);
313 be_emit_cstring("\tldf");
314 arm_emit_fpa_postfix(mode);
317 arm_emit_dest_register(irn, 0);
318 be_emit_irprintf(", .L%u", label);
319 be_emit_finish_line_gas(irn);
323 * Returns the next block in a block schedule.
325 static ir_node *sched_next_block(const ir_node *block) {
326 return get_irn_link(block);
330 * Returns the target block for a control flow node.
332 static ir_node *get_cfop_target_block(const ir_node *irn) {
333 return get_irn_link(irn);
337 * Emits a block label for the given block.
339 static void arm_emit_block_name(const ir_node *block) {
340 if (has_Block_label(block)) {
341 be_emit_string(be_gas_label_prefix());
342 be_emit_irprintf("%lu", get_Block_label(block));
344 be_emit_cstring(BLOCK_PREFIX);
345 be_emit_irprintf("%d", get_irn_node_nr(block));
350 * Emit the target label for a control flow node.
352 static void arm_emit_cfop_target(const ir_node *irn) {
353 ir_node *block = get_cfop_target_block(irn);
355 arm_emit_block_name(block);
359 * Emit a Compare with conditional branch.
361 static void emit_arm_CmpBra(const ir_node *irn) {
362 const ir_edge_t *edge;
363 const ir_node *proj_true = NULL;
364 const ir_node *proj_false = NULL;
365 const ir_node *block;
366 const ir_node *next_block;
367 ir_node *op1 = get_irn_n(irn, 0);
368 ir_mode *opmode = get_irn_mode(op1);
370 int proj_num = get_arm_CondJmp_proj_num(irn);
372 foreach_out_edge(irn, edge) {
373 ir_node *proj = get_edge_src_irn(edge);
374 long nr = get_Proj_proj(proj);
375 if (nr == pn_Cond_true) {
382 /* for now, the code works for scheduled and non-schedules blocks */
383 block = get_nodes_block(irn);
385 /* we have a block schedule */
386 next_block = sched_next_block(block);
388 if (proj_num == pn_Cmp_False) {
389 /* always false: should not happen */
390 be_emit_cstring("\tb ");
391 arm_emit_cfop_target(proj_false);
392 be_emit_finish_line_gas(proj_false);
393 } else if (proj_num == pn_Cmp_True) {
394 /* always true: should not happen */
395 be_emit_cstring("\tb ");
396 arm_emit_cfop_target(proj_true);
397 be_emit_finish_line_gas(proj_true);
399 if (mode_is_float(opmode)) {
400 suffix = "ICHWILLIMPLEMENTIERTWERDEN";
402 be_emit_cstring("\tfcmp ");
403 arm_emit_source_register(irn, 0);
404 be_emit_cstring(", ");
405 arm_emit_source_register(irn, 1);
406 be_emit_finish_line_gas(irn);
408 be_emit_cstring("\tfmstat");
409 be_emit_pad_comment();
410 be_emit_cstring("/* FCSPR -> CPSR */");
411 be_emit_finish_line_gas(NULL);
413 if (get_cfop_target_block(proj_true) == next_block) {
414 /* exchange both proj's so the second one can be omitted */
415 const ir_node *t = proj_true;
417 proj_true = proj_false;
419 proj_num = get_negated_pnc(proj_num, mode_Iu);
422 case pn_Cmp_Eq: suffix = "eq"; break;
423 case pn_Cmp_Lt: suffix = "lt"; break;
424 case pn_Cmp_Le: suffix = "le"; break;
425 case pn_Cmp_Gt: suffix = "gt"; break;
426 case pn_Cmp_Ge: suffix = "ge"; break;
427 case pn_Cmp_Lg: suffix = "ne"; break;
428 case pn_Cmp_Leg: suffix = "al"; break;
429 default: assert(!"Cmp unsupported"); suffix = "al";
431 be_emit_cstring("\tcmp ");
432 arm_emit_source_register(irn, 0);
433 be_emit_cstring(", ");
434 arm_emit_source_register(irn, 1);
435 be_emit_finish_line_gas(irn);
438 /* emit the true proj */
439 be_emit_irprintf("\tb%s ", suffix);
440 arm_emit_cfop_target(proj_true);
441 be_emit_finish_line_gas(proj_true);
443 if (get_cfop_target_block(proj_false) == next_block) {
444 be_emit_cstring("\t/* fallthrough to ");
445 arm_emit_cfop_target(proj_false);
446 be_emit_cstring(" */");
447 be_emit_finish_line_gas(proj_false);
449 be_emit_cstring("b ");
450 arm_emit_cfop_target(proj_false);
451 be_emit_finish_line_gas(proj_false);
457 * Emit a Compare with conditional branch.
459 static void emit_arm_fpaCmfBra(const ir_node *irn) {
464 * Emit a Compare with conditional branch.
466 static void emit_arm_fpaCmfeBra(const ir_node *irn) {
470 /** Sort register in ascending order. */
471 static int reg_cmp(const void *a, const void *b) {
472 const arch_register_t * const *ra = a;
473 const arch_register_t * const *rb = b;
475 return *ra < *rb ? -1 : (*ra != *rb);
479 * Create the CopyB instruction sequence.
481 static void emit_arm_CopyB(const ir_node *irn) {
482 unsigned size = (unsigned)get_arm_imm_value(irn);
484 const char *tgt = arch_register_get_name(get_in_reg(irn, 0));
485 const char *src = arch_register_get_name(get_in_reg(irn, 1));
486 const char *t0, *t1, *t2, *t3;
488 const arch_register_t *tmpregs[4];
490 /* collect the temporary registers and sort them, we need ascending order */
491 tmpregs[0] = get_in_reg(irn, 2);
492 tmpregs[1] = get_in_reg(irn, 3);
493 tmpregs[2] = get_in_reg(irn, 4);
494 tmpregs[3] = &arm_gp_regs[REG_R12];
496 /* Note: R12 is always the last register because the RA did not assign higher ones */
497 qsort((void *)tmpregs, 3, sizeof(tmpregs[0]), reg_cmp);
499 /* need ascending order */
500 t0 = arch_register_get_name(tmpregs[0]);
501 t1 = arch_register_get_name(tmpregs[1]);
502 t2 = arch_register_get_name(tmpregs[2]);
503 t3 = arch_register_get_name(tmpregs[3]);
505 be_emit_cstring("/* MemCopy (");
507 be_emit_cstring(")->(");
508 arm_emit_source_register(irn, 0);
509 be_emit_irprintf(" [%u bytes], Uses ", size);
511 be_emit_cstring(", ");
513 be_emit_cstring(", ");
515 be_emit_cstring(", and ");
517 be_emit_cstring("*/");
518 be_emit_finish_line_gas(NULL);
520 assert(size > 0 && "CopyB needs size > 0" );
523 assert(!"strange hack enabled: copy more bytes than needed!");
532 be_emit_cstring("\tldr ");
534 be_emit_cstring(", [");
536 be_emit_cstring(", #0]");
537 be_emit_finish_line_gas(NULL);
539 be_emit_cstring("\tstr ");
541 be_emit_cstring(", [");
543 be_emit_cstring(", #0]");
544 be_emit_finish_line_gas(irn);
547 be_emit_cstring("\tldmia ");
549 be_emit_cstring("!, {");
551 be_emit_cstring(", ");
554 be_emit_finish_line_gas(NULL);
556 be_emit_cstring("\tstmia ");
558 be_emit_cstring("!, {");
560 be_emit_cstring(", ");
563 be_emit_finish_line_gas(irn);
566 be_emit_cstring("\tldmia ");
568 be_emit_cstring("!, {");
570 be_emit_cstring(", ");
572 be_emit_cstring(", ");
575 be_emit_finish_line_gas(NULL);
577 be_emit_cstring("\tstmia ");
579 be_emit_cstring("!, {");
581 be_emit_cstring(", ");
583 be_emit_cstring(", ");
586 be_emit_finish_line_gas(irn);
591 be_emit_cstring("\tldmia ");
593 be_emit_cstring("!, {");
595 be_emit_cstring(", ");
597 be_emit_cstring(", ");
599 be_emit_cstring(", ");
602 be_emit_finish_line_gas(NULL);
604 be_emit_cstring("\tstmia ");
606 be_emit_cstring("!, {");
608 be_emit_cstring(", ");
610 be_emit_cstring(", ");
612 be_emit_cstring(", ");
615 be_emit_finish_line_gas(irn);
620 static void emit_arm_SwitchJmp(const ir_node *irn) {
621 const ir_edge_t *edge;
627 ir_node *default_proj = NULL;
629 block_nr = get_irn_node_nr(irn);
630 n_projs = get_arm_SwitchJmp_n_projs(irn);
632 projs = xcalloc(n_projs , sizeof(ir_node*));
634 foreach_out_edge(irn, edge) {
635 proj = get_edge_src_irn(edge);
636 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
638 if (get_Proj_proj(proj) == get_arm_SwitchJmp_default_proj_num(irn))
641 projs[get_Proj_proj(proj)] = proj;
643 assert(default_proj != NULL && "SwitchJmp should have a Default Proj");
650 be_emit_cstring("\tcmp ");
651 arm_emit_source_register(irn, 0);
652 be_emit_irprintf(", #%u", n_projs - 1);
653 be_emit_finish_line_gas(irn);
655 be_emit_cstring("\tbhi ");
656 arm_emit_cfop_target(default_proj);
657 be_emit_finish_line_gas(default_proj);
660 LDR %r12, .TABLE_X_START
661 ADD %r12, %r12, [%1S, LSL #2]
665 be_emit_irprintf("\tldr %%r12, TABLE_%d_START", block_nr);
666 be_emit_finish_line_gas(NULL);
668 be_emit_irprintf("\tadd %%r12, %%r12, ");
669 arm_emit_source_register(irn, 0);
670 be_emit_cstring(", LSL #2");
671 be_emit_finish_line_gas(NULL);
673 be_emit_cstring("\tldr %r15, [%r12, #0]");
674 be_emit_finish_line_gas(NULL);
676 be_emit_irprintf("TABLE_%d_START:\n\t.word\tTABLE_%d", block_nr, block_nr);
677 be_emit_finish_line_gas(NULL);
678 be_emit_irprintf("\t.align 2");
679 be_emit_finish_line_gas(NULL);
680 be_emit_irprintf("TABLE_%d:", block_nr);
681 be_emit_finish_line_gas(NULL);
683 for (i = 0; i < n_projs; ++i) {
686 proj = projs[get_arm_SwitchJmp_default_proj_num(irn)];
688 be_emit_cstring("\t.word\t");
689 arm_emit_cfop_target(proj);
690 be_emit_finish_line_gas(proj);
692 be_emit_irprintf("\t.align 2\n");
693 be_emit_finish_line_gas(NULL);
697 /************************************************************************/
699 /************************************************************************/
701 static void emit_be_Call(const ir_node *irn) {
702 ir_entity *ent = be_Call_get_entity(irn);
704 be_emit_cstring("\tbl ");
706 set_entity_backend_marked(ent, 1);
707 be_emit_ident(get_entity_ld_ident(ent));
709 arm_emit_source_register(irn, be_pos_Call_ptr);
711 be_emit_finish_line_gas(irn);
714 /** Emit an IncSP node */
715 static void emit_be_IncSP(const ir_node *irn) {
716 int offs = be_get_IncSP_offset(irn);
719 be_emit_cstring("\tadd ");
720 arm_emit_dest_register(irn, 0);
721 be_emit_cstring(", ");
722 arm_emit_source_register(irn, 0);
723 be_emit_cstring(", #");
724 arm_emit_offset(irn);
726 be_emit_cstring("\t/* omitted IncSP(");
727 arm_emit_offset(irn);
728 be_emit_cstring(") */");
730 be_emit_finish_line_gas(irn);
733 static void emit_be_Copy(const ir_node *irn) {
734 ir_mode *mode = get_irn_mode(irn);
736 if (get_in_reg(irn, 0) == get_out_reg(irn, 0)) {
737 be_emit_cstring("\t/* omitted Copy: ");
738 arm_emit_source_register(irn, 0);
739 be_emit_cstring(" -> ");
740 arm_emit_dest_register(irn, 0);
741 be_emit_finish_line_gas(irn);
745 if (mode_is_float(mode)) {
747 be_emit_cstring("\tmvf");
750 arm_emit_dest_register(irn, 0);
751 be_emit_cstring(", ");
752 arm_emit_source_register(irn, 0);
753 be_emit_finish_line_gas(irn);
755 assert(0 && "move not supported for this mode");
756 panic("emit_be_Copy: move not supported for this mode");
758 } else if (mode_is_data(mode)) {
759 be_emit_cstring("\tmov ");
760 arm_emit_dest_register(irn, 0);
761 be_emit_cstring(", ");
762 arm_emit_source_register(irn, 0);
763 be_emit_finish_line_gas(irn);
765 assert(0 && "move not supported for this mode");
766 panic("emit_be_Copy: move not supported for this mode");
771 * Emit code for a Spill.
773 static void emit_be_Spill(const ir_node *irn) {
774 ir_mode *mode = get_irn_mode(be_get_Spill_val(irn));
776 if (mode_is_float(mode)) {
777 if (USE_FPA(cg->isa)) {
778 be_emit_cstring("\tstf");
779 arm_emit_fpa_postfix(mode);
782 assert(0 && "spill not supported for this mode");
783 panic("emit_be_Spill: spill not supported for this mode");
785 } else if (mode_is_dataM(mode)) {
786 be_emit_cstring("\tstr ");
788 assert(0 && "spill not supported for this mode");
789 panic("emit_be_Spill: spill not supported for this mode");
791 arm_emit_source_register(irn, 1);
792 be_emit_cstring(", [");
793 arm_emit_source_register(irn, 0);
794 be_emit_cstring(", #");
795 arm_emit_offset(irn);
797 be_emit_finish_line_gas(irn);
801 * Emit code for a Reload.
803 static void emit_be_Reload(const ir_node *irn) {
804 ir_mode *mode = get_irn_mode(irn);
806 if (mode_is_float(mode)) {
807 if (USE_FPA(cg->isa)) {
808 be_emit_cstring("\tldf");
809 arm_emit_fpa_postfix(mode);
812 assert(0 && "reload not supported for this mode");
813 panic("emit_be_Reload: reload not supported for this mode");
815 } else if (mode_is_dataM(mode)) {
816 be_emit_cstring("\tldr ");
818 assert(0 && "reload not supported for this mode");
819 panic("emit_be_Reload: reload not supported for this mode");
821 arm_emit_dest_register(irn, 0);
822 be_emit_cstring(", [");
823 arm_emit_source_register(irn, 0);
824 be_emit_cstring(", #");
825 arm_emit_offset(irn);
827 be_emit_finish_line_gas(irn);
830 static void emit_be_Perm(const ir_node *irn) {
831 be_emit_cstring("\teor ");
832 arm_emit_source_register(irn, 0);
833 be_emit_cstring(", ");
834 arm_emit_source_register(irn, 0);
835 be_emit_cstring(", ");
836 arm_emit_source_register(irn, 1);
837 be_emit_finish_line_gas(NULL);
839 be_emit_cstring("\teor ");
840 arm_emit_source_register(irn, 1);
841 be_emit_cstring(", ");
842 arm_emit_source_register(irn, 0);
843 be_emit_cstring(", ");
844 arm_emit_source_register(irn, 1);
845 be_emit_finish_line_gas(NULL);
847 be_emit_cstring("\teor ");
848 arm_emit_source_register(irn, 0);
849 be_emit_cstring(", ");
850 arm_emit_source_register(irn, 0);
851 be_emit_cstring(", ");
852 arm_emit_source_register(irn, 1);
853 be_emit_finish_line_gas(irn);
856 /************************************************************************/
858 /************************************************************************/
860 static void emit_Jmp(const ir_node *node) {
861 ir_node *block, *next_block;
863 /* for now, the code works for scheduled and non-schedules blocks */
864 block = get_nodes_block(node);
866 /* we have a block schedule */
867 next_block = sched_next_block(block);
868 if (get_cfop_target_block(node) != next_block) {
869 be_emit_cstring("\tb ");
870 arm_emit_cfop_target(node);
872 be_emit_cstring("\t/* fallthrough to ");
873 arm_emit_cfop_target(node);
874 be_emit_cstring(" */");
876 be_emit_finish_line_gas(node);
879 static void emit_arm_fpaDbl2GP(const ir_node *irn) {
880 be_emit_cstring("\tstfd ");
881 arm_emit_source_register(irn, 0);
882 be_emit_cstring(", [sp, #-8]!");
883 be_emit_pad_comment();
884 be_emit_cstring("/* Push fp to stack */");
885 be_emit_finish_line_gas(NULL);
887 be_emit_cstring("\tldmfd sp!, {");
888 arm_emit_dest_register(irn, 1);
889 be_emit_cstring(", ");
890 arm_emit_dest_register(irn, 0);
892 be_emit_pad_comment();
893 be_emit_cstring("/* Pop destination */");
894 be_emit_finish_line_gas(irn);
897 static void emit_arm_LdTls(const ir_node *irn) {
899 panic("TLS not supported for this target\n");
900 /* Er... our gcc does not support it... Install a newer toolchain. */
903 /***********************************************************************************
906 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
907 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
908 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
909 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
911 ***********************************************************************************/
913 static void emit_silence(const ir_node *irn) {
919 * The type of a emitter function.
921 typedef void (emit_func)(const ir_node *irn);
924 * Set a node emitter. Make it a bit more type safe.
926 static INLINE void set_emitter(ir_op *op, emit_func arm_emit_node) {
927 op->ops.generic = (op_func)arm_emit_node;
931 * Enters the emitter functions for handled nodes into the generic
932 * pointer of an opcode.
934 static void arm_register_emitters(void) {
936 #define ARM_EMIT(a) set_emitter(op_arm_##a, emit_arm_##a)
937 #define EMIT(a) set_emitter(op_##a, emit_##a)
938 #define BE_EMIT(a) set_emitter(op_be_##a, emit_be_##a)
939 #define SILENCE(a) set_emitter(op_##a, emit_silence)
941 /* first clear the generic function pointer for all ops */
942 clear_irp_opcodes_generic_func();
944 /* register all emitter functions defined in spec */
945 arm_register_spec_emitters();
947 /* other emitter functions */
950 ARM_EMIT(fpaCmfeBra);
952 // ARM_EMIT(CopyB_i);
977 SILENCE(be_CopyKeep);
978 SILENCE(be_RegParams);
990 * Emits code for a node.
992 static void arm_emit_node(const ir_node *irn) {
993 ir_op *op = get_irn_op(irn);
995 if (op->ops.generic) {
996 emit_func *emit = (emit_func *)op->ops.generic;
997 be_dbg_set_dbg_info(get_irn_dbg_info(irn));
1000 be_emit_cstring("\t/* TODO */");
1001 be_emit_finish_line_gas(irn);
1006 * emit the block label if needed.
1008 static void arm_emit_block_header(ir_node *block, ir_node *prev)
1013 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1016 n_cfgpreds = get_Block_n_cfgpreds(block);
1017 if (n_cfgpreds == 1) {
1018 ir_node *pred = get_Block_cfgpred(block, 0);
1019 ir_node *pred_block = get_nodes_block(pred);
1021 /* we don't need labels for fallthrough blocks, however switch-jmps
1022 * are no fallthroughs */
1023 if (pred_block == prev &&
1024 !(is_Proj(pred) && is_arm_SwitchJmp(get_Proj_pred(pred)))) {
1034 arm_emit_block_name(block);
1037 be_emit_pad_comment();
1038 be_emit_cstring(" /* preds:");
1040 /* emit list of pred blocks in comment */
1041 arity = get_irn_arity(block);
1042 for (i = 0; i < arity; ++i) {
1043 ir_node *predblock = get_Block_cfgpred_block(block, i);
1044 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1047 be_emit_cstring("\t/* ");
1048 arm_emit_block_name(block);
1049 be_emit_cstring(": ");
1051 if (exec_freq != NULL) {
1052 be_emit_irprintf(" freq: %f",
1053 get_block_execfreq(exec_freq, block));
1055 be_emit_cstring(" */\n");
1056 be_emit_write_line();
1060 * Walks over the nodes in a block connected by scheduling edges
1061 * and emits code for each node.
1063 static void arm_gen_block(ir_node *block, ir_node *prev_block) {
1066 arm_emit_block_header(block, prev_block);
1067 be_dbg_set_dbg_info(get_irn_dbg_info(block));
1068 sched_foreach(block, irn) {
1074 * Emits code for function start.
1076 void arm_func_prolog(ir_graph *irg) {
1077 ir_entity *ent = get_irg_entity(irg);
1078 const char *irg_name = get_entity_ld_name(ent);
1080 be_emit_write_line();
1081 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1082 be_emit_cstring("\t.align 2\n");
1084 if (get_entity_visibility(ent) == visibility_external_visible)
1085 be_emit_irprintf("\t.global %s\n", irg_name);
1086 be_emit_irprintf("%s:\n", irg_name);
1090 * Emits code for function end
1092 void arm_emit_end(FILE *F, ir_graph *irg) {
1094 fprintf(F, "\t.ident \"firmcc\"\n");
1099 * Sets labels for control flow nodes (jump target)
1101 static void arm_gen_labels(ir_node *block, void *env) {
1103 int n = get_Block_n_cfgpreds(block);
1106 for (n--; n >= 0; n--) {
1107 pred = get_Block_cfgpred(block, n);
1108 set_irn_link(pred, block);
1113 * Compare two entries of the symbol or tarval set.
1115 static int cmp_sym_or_tv(const void *elt, const void *key, size_t size) {
1116 const sym_or_tv_t *p1 = elt;
1117 const sym_or_tv_t *p2 = key;
1120 /* as an identifier NEVER can point to a tarval, it's enough
1121 to compare it this way */
1122 return p1->u.generic != p2->u.generic;
1126 * Main driver. Emits the code for one routine.
1128 void arm_gen_routine(const arm_code_gen_t *arm_cg, ir_graph *irg) {
1129 ir_node **blk_sched;
1131 ir_node *last_block = NULL;
1134 isa = (const arm_isa_t *)cg->arch_env->isa;
1135 arch_env = cg->arch_env;
1136 sym_or_tv = new_set(cmp_sym_or_tv, 8);
1138 arm_register_emitters();
1140 /* create the block schedule. For now, we don't need it earlier. */
1141 blk_sched = be_create_block_schedule(cg->irg, cg->birg->exec_freq);
1143 arm_func_prolog(irg);
1144 irg_block_walk_graph(irg, arm_gen_labels, NULL, NULL);
1146 n = ARR_LEN(blk_sched);
1147 for (i = 0; i < n;) {
1148 ir_node *block, *next_bl;
1150 block = blk_sched[i];
1152 next_bl = i < n ? blk_sched[i] : NULL;
1154 /* set here the link. the emitter expects to find the next block here */
1155 set_irn_link(block, next_bl);
1156 arm_gen_block(block, last_block);
1160 /* emit SymConst values */
1161 if (set_count(sym_or_tv) > 0) {
1164 be_emit_cstring("\t.align 2\n");
1166 foreach_set(sym_or_tv, entry) {
1167 be_emit_irprintf(".L%u:\n", entry->label);
1169 if (entry->is_ident) {
1170 be_emit_cstring("\t.word\t");
1171 be_emit_ident(entry->u.id);
1173 be_emit_write_line();
1175 tarval *tv = entry->u.tv;
1176 int i, size = get_mode_size_bytes(get_tarval_mode(tv));
1179 /* beware: ARM fpa uses big endian format */
1180 for (i = ((size + 3) & ~3) - 4; i >= 0; i -= 4) {
1182 v = get_tarval_sub_bits(tv, i+3);
1183 v = (v << 8) | get_tarval_sub_bits(tv, i+2);
1184 v = (v << 8) | get_tarval_sub_bits(tv, i+1);
1185 v = (v << 8) | get_tarval_sub_bits(tv, i+0);
1186 be_emit_irprintf("\t.word\t%u\n", v);
1187 be_emit_write_line();
1192 be_emit_write_line();
1197 void arm_init_emitter(void)
1199 FIRM_DBG_REGISTER(dbg, "firm.be.arm.emit");