2 * This file is part of libFirm.
3 * Copyright (C) 2012 University of Karlsruhe.
9 * @author Oliver Richter, Tobias Gneist, Michael Beck
27 #include "raw_bitset.h"
31 #include "beblocksched.h"
36 #include "arm_emitter.h"
37 #include "arm_optimize.h"
38 #include "gen_arm_emitter.h"
39 #include "arm_nodes_attr.h"
40 #include "arm_new_nodes.h"
41 #include "arm_map_regs.h"
42 #include "gen_arm_regalloc_if.h"
46 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
48 static set *sym_or_tv;
49 static arm_isa_t *isa;
51 static void arm_emit_register(const arch_register_t *reg)
53 be_emit_string(reg->name);
56 static void arm_emit_source_register(const ir_node *node, int pos)
58 const arch_register_t *reg = arch_get_irn_register_in(node, pos);
59 arm_emit_register(reg);
62 static void arm_emit_dest_register(const ir_node *node, int pos)
64 const arch_register_t *reg = arch_get_irn_register_out(node, pos);
65 arm_emit_register(reg);
68 static void arm_emit_offset(const ir_node *node)
70 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
71 assert(attr->base.is_load_store);
73 be_emit_irprintf("0x%X", attr->offset);
77 * Emit the arm fpa instruction suffix depending on the mode.
79 static void arm_emit_fpa_postfix(const ir_mode *mode)
81 int bits = get_mode_size_bits(mode);
91 static void arm_emit_float_load_store_mode(const ir_node *node)
93 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
94 arm_emit_fpa_postfix(attr->load_store_mode);
97 static void arm_emit_float_arithmetic_mode(const ir_node *node)
99 const arm_farith_attr_t *attr = get_arm_farith_attr_const(node);
100 arm_emit_fpa_postfix(attr->mode);
103 static void arm_emit_symconst(const ir_node *node)
105 const arm_SymConst_attr_t *symconst = get_arm_SymConst_attr_const(node);
106 ir_entity *entity = symconst->entity;
108 be_gas_emit_entity(entity);
110 /* TODO do something with offset */
113 static void arm_emit_load_mode(const ir_node *node)
115 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
116 ir_mode *mode = attr->load_store_mode;
117 int bits = get_mode_size_bits(mode);
118 bool is_signed = mode_is_signed(mode);
120 be_emit_string(is_signed ? "sh" : "h");
121 } else if (bits == 8) {
122 be_emit_string(is_signed ? "sb" : "b");
128 static void arm_emit_store_mode(const ir_node *node)
130 const arm_load_store_attr_t *attr = get_arm_load_store_attr_const(node);
131 ir_mode *mode = attr->load_store_mode;
132 int bits = get_mode_size_bits(mode);
134 be_emit_cstring("h");
135 } else if (bits == 8) {
136 be_emit_cstring("b");
142 static void emit_shf_mod_name(arm_shift_modifier_t mod)
145 case ARM_SHF_ASR_REG:
146 case ARM_SHF_ASR_IMM:
147 be_emit_cstring("asr");
149 case ARM_SHF_LSL_REG:
150 case ARM_SHF_LSL_IMM:
151 be_emit_cstring("lsl");
153 case ARM_SHF_LSR_REG:
154 case ARM_SHF_LSR_IMM:
155 be_emit_cstring("lsr");
157 case ARM_SHF_ROR_REG:
158 case ARM_SHF_ROR_IMM:
159 be_emit_cstring("ror");
164 panic("can't emit this shf_mod_name %d", (int) mod);
167 static void arm_emit_shifter_operand(const ir_node *node)
169 const arm_shifter_operand_t *attr = get_arm_shifter_operand_attr_const(node);
171 switch (attr->shift_modifier) {
173 arm_emit_source_register(node, get_irn_arity(node) - 1);
176 unsigned val = attr->immediate_value;
177 val = (val >> attr->shift_immediate)
178 | (val << (32-attr->shift_immediate));
180 be_emit_irprintf("#0x%X", val);
183 case ARM_SHF_ASR_IMM:
184 case ARM_SHF_LSL_IMM:
185 case ARM_SHF_LSR_IMM:
186 case ARM_SHF_ROR_IMM:
187 arm_emit_source_register(node, get_irn_arity(node) - 1);
188 be_emit_cstring(", ");
189 emit_shf_mod_name(attr->shift_modifier);
190 be_emit_irprintf(" #0x%X", attr->shift_immediate);
193 case ARM_SHF_ASR_REG:
194 case ARM_SHF_LSL_REG:
195 case ARM_SHF_LSR_REG:
196 case ARM_SHF_ROR_REG:
197 arm_emit_source_register(node, get_irn_arity(node) - 2);
198 be_emit_cstring(", ");
199 emit_shf_mod_name(attr->shift_modifier);
200 be_emit_cstring(" ");
201 arm_emit_source_register(node, get_irn_arity(node) - 1);
205 arm_emit_source_register(node, get_irn_arity(node) - 1);
206 panic("RRX shifter emitter TODO");
208 case ARM_SHF_INVALID:
211 panic("Invalid shift_modifier while emitting %+F", node);
214 /** An entry in the sym_or_tv set. */
215 typedef struct sym_or_tv_t {
217 ir_entity *entity; /**< An entity. */
218 ir_tarval *tv; /**< A tarval. */
219 const void *generic; /**< For generic compare. */
221 unsigned label; /**< the associated label. */
222 bool is_entity; /**< true if an entity is stored. */
226 * Returns a unique label. This number will not be used a second time.
228 static unsigned get_unique_label(void)
230 static unsigned id = 0;
234 static void emit_constant_name(const sym_or_tv_t *entry)
236 be_emit_irprintf("%sC%u", be_gas_get_private_prefix(), entry->label);
240 * Returns the target block for a control flow node.
242 static ir_node *get_cfop_target_block(const ir_node *irn)
244 return (ir_node*)get_irn_link(irn);
248 * Emit the target label for a control flow node.
250 static void arm_emit_cfop_target(const ir_node *irn)
252 ir_node *block = get_cfop_target_block(irn);
254 be_gas_emit_block_name(block);
257 void arm_emitf(const ir_node *node, const char *format, ...)
260 va_start(ap, format);
263 const char *start = format;
264 while (*format != '%' && *format != '\n' && *format != '\0')
266 be_emit_string_len(start, format - start);
271 if (*format == '\n') {
274 be_emit_write_line();
287 if (*format < '0' || '9' <= *format)
289 unsigned const pos = *format++ - '0';
290 arm_emit_source_register(node, pos);
295 if (*format < '0' || '9' <= *format)
297 unsigned const pos = *format++ - '0';
298 arm_emit_dest_register(node, pos);
303 arm_emit_symconst(node);
307 arm_emit_offset(node);
311 arm_emit_shifter_operand(node);
315 const sym_or_tv_t *name = va_arg(ap, const sym_or_tv_t*);
316 emit_constant_name(name);
321 ir_mode *mode = va_arg(ap, ir_mode*);
322 arm_emit_fpa_postfix(mode);
328 case 'L': arm_emit_load_mode(node); break;
329 case 'S': arm_emit_store_mode(node); break;
330 case 'A': arm_emit_float_arithmetic_mode(node); break;
331 case 'F': arm_emit_float_load_store_mode(node); break;
339 int num = va_arg(ap, int);
340 be_emit_irprintf("%X", num);
345 unsigned num = va_arg(ap, unsigned);
346 be_emit_irprintf("%u", num);
351 int num = va_arg(ap, int);
352 be_emit_irprintf("%d", num);
357 const char *string = va_arg(ap, const char *);
358 be_emit_string(string);
363 arch_register_t *reg = va_arg(ap, arch_register_t*);
364 arm_emit_register(reg);
369 const ir_node *n = va_arg(ap, const ir_node*);
370 arm_emit_cfop_target(n);
376 panic("unknown format conversion");
380 be_emit_finish_line_gas(node);
386 static void emit_arm_SymConst(const ir_node *irn)
388 const arm_SymConst_attr_t *attr = get_arm_SymConst_attr_const(irn);
389 sym_or_tv_t key, *entry;
391 key.u.entity = attr->entity;
392 key.is_entity = true;
394 entry = set_insert(sym_or_tv_t, sym_or_tv, &key, sizeof(key), hash_ptr(key.u.generic));
395 if (entry->label == 0) {
396 /* allocate a label */
397 entry->label = get_unique_label();
400 /* load the symbol indirect */
401 arm_emitf(irn, "ldr %D0, %C", entry);
404 static void emit_arm_FrameAddr(const ir_node *irn)
406 const arm_SymConst_attr_t *attr = get_arm_SymConst_attr_const(irn);
407 arm_emitf(irn, "add %D0, %S0, #0x%X", attr->fp_offset);
411 * Emit a floating point fpa constant.
413 static void emit_arm_fConst(const ir_node *irn)
417 key.u.tv = get_fConst_value(irn);
418 key.is_entity = false;
420 sym_or_tv_t *entry = set_insert(sym_or_tv_t, sym_or_tv, &key, sizeof(key), hash_ptr(key.u.generic));
421 if (entry->label == 0) {
422 /* allocate a label */
423 entry->label = get_unique_label();
426 /* load the tarval indirect */
427 ir_mode *mode = get_irn_mode(irn);
428 arm_emitf(irn, "ldf%m %D0, %C", mode, entry);
432 * Returns the next block in a block schedule.
434 static ir_node *sched_next_block(const ir_node *block)
436 return (ir_node*)get_irn_link(block);
440 * Emit a Compare with conditional branch.
442 static void emit_arm_B(const ir_node *irn)
444 const ir_node *proj_true = NULL;
445 const ir_node *proj_false = NULL;
446 const ir_node *block;
447 const ir_node *next_block;
448 ir_node *op1 = get_irn_n(irn, 0);
450 ir_relation relation = get_arm_CondJmp_relation(irn);
451 const arm_cmp_attr_t *cmp_attr = get_arm_cmp_attr_const(op1);
452 bool is_signed = !cmp_attr->is_unsigned;
454 assert(is_arm_Cmp(op1) || is_arm_Tst(op1));
456 foreach_out_edge(irn, edge) {
457 ir_node *proj = get_edge_src_irn(edge);
458 long nr = get_Proj_proj(proj);
459 if (nr == pn_Cond_true) {
466 if (cmp_attr->ins_permuted) {
467 relation = get_inversed_relation(relation);
470 /* for now, the code works for scheduled and non-schedules blocks */
471 block = get_nodes_block(irn);
473 /* we have a block schedule */
474 next_block = sched_next_block(block);
476 assert(relation != ir_relation_false);
477 assert(relation != ir_relation_true);
479 if (get_cfop_target_block(proj_true) == next_block) {
480 /* exchange both proj's so the second one can be omitted */
481 const ir_node *t = proj_true;
483 proj_true = proj_false;
485 relation = get_negated_relation(relation);
488 switch (relation & (ir_relation_less_equal_greater)) {
489 case ir_relation_equal: suffix = "eq"; break;
490 case ir_relation_less: suffix = is_signed ? "lt" : "lo"; break;
491 case ir_relation_less_equal: suffix = is_signed ? "le" : "ls"; break;
492 case ir_relation_greater: suffix = is_signed ? "gt" : "hi"; break;
493 case ir_relation_greater_equal: suffix = is_signed ? "ge" : "hs"; break;
494 case ir_relation_less_greater: suffix = "ne"; break;
495 case ir_relation_less_equal_greater: suffix = "al"; break;
496 default: panic("Cmp has unsupported relation");
499 /* emit the true proj */
500 arm_emitf(irn, "b%s %t", suffix, proj_true);
502 if (get_cfop_target_block(proj_false) == next_block) {
503 if (be_options.verbose_asm) {
504 arm_emitf(irn, "/* fallthrough to %t */", proj_false);
507 arm_emitf(irn, "b %t", proj_false);
511 /** Sort register in ascending order. */
512 static int reg_cmp(const void *a, const void *b)
514 const arch_register_t * const *ra = (const arch_register_t**)a;
515 const arch_register_t * const *rb = (const arch_register_t**)b;
517 return *ra < *rb ? -1 : (*ra != *rb);
521 * Create the CopyB instruction sequence.
523 static void emit_arm_CopyB(const ir_node *irn)
525 const arm_CopyB_attr_t *attr = get_arm_CopyB_attr_const(irn);
526 unsigned size = attr->size;
527 const arch_register_t *tmpregs[4];
529 /* collect the temporary registers and sort them, we need ascending order */
530 tmpregs[0] = arch_get_irn_register_in(irn, 2);
531 tmpregs[1] = arch_get_irn_register_in(irn, 3);
532 tmpregs[2] = arch_get_irn_register_in(irn, 4);
533 tmpregs[3] = &arm_registers[REG_R12];
535 /* Note: R12 is always the last register because the RA did not assign higher ones */
536 qsort((void *)tmpregs, 3, sizeof(tmpregs[0]), reg_cmp);
538 if (be_options.verbose_asm) {
539 arm_emitf(irn, "/* MemCopy (%S1)->(%S0) [%u bytes], Uses %r, %r, %r and %r */",
540 size, tmpregs[0], tmpregs[1], tmpregs[2], tmpregs[3]);
543 assert(size > 0 && "CopyB needs size > 0" );
546 fprintf(stderr, "strange hack enabled: copy more bytes than needed!");
555 arm_emitf(irn, "ldr %r, [%S1, #0]", tmpregs[3]);
556 arm_emitf(irn, "str %r, [%S0, #0]", tmpregs[3]);
559 arm_emitf(irn, "ldmia %S1!, {%r, %r}", tmpregs[0], tmpregs[1]);
560 arm_emitf(irn, "stmia %S0!, {%r, %r}", tmpregs[0], tmpregs[1]);
563 arm_emitf(irn, "ldmia %S1!, {%r, %r, %r}", tmpregs[0], tmpregs[1], tmpregs[2]);
564 arm_emitf(irn, "stmia %S0!, {%r, %r, %r}", tmpregs[0], tmpregs[1], tmpregs[2]);
569 arm_emitf(irn, "ldmia %S1!, {%r, %r, %r}", tmpregs[0], tmpregs[1], tmpregs[2], tmpregs[3]);
570 arm_emitf(irn, "stmia %S0!, {%r, %r, %r}", tmpregs[0], tmpregs[1], tmpregs[2], tmpregs[3]);
575 static void emit_arm_SwitchJmp(const ir_node *irn)
577 const arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr_const(irn);
578 arm_emitf(irn, "ldrls pc, [pc, %S0, asl #2]");
580 be_emit_jump_table(irn, attr->table, NULL, get_cfop_target_block);
583 /** Emit an IncSP node */
584 static void emit_be_IncSP(const ir_node *irn)
586 int offs = -be_get_IncSP_offset(irn);
591 const char *op = "add";
596 arm_emitf(irn, "%s %D0, %S0, #0x%X", op, offs);
599 static void emit_be_Copy(const ir_node *irn)
601 ir_mode *mode = get_irn_mode(irn);
603 if (arch_get_irn_register_in(irn, 0) == arch_get_irn_register_out(irn, 0)) {
608 if (mode_is_float(mode)) {
610 arm_emitf(irn, "mvf %D0, %S0");
612 panic("move not supported for this mode");
614 } else if (mode_is_data(mode)) {
615 arm_emitf(irn, "mov %D0, %S0");
617 panic("move not supported for this mode");
621 static void emit_be_Perm(const ir_node *irn)
624 "eor %S0, %S0, %S1\n"
625 "eor %S1, %S0, %S1\n"
626 "eor %S0, %S0, %S1");
629 static void emit_be_MemPerm(const ir_node *node)
635 /* TODO: this implementation is slower than necessary.
636 The longterm goal is however to avoid the memperm node completely */
638 memperm_arity = be_get_MemPerm_entity_arity(node);
639 if (memperm_arity > 12)
640 panic("memperm with more than 12 inputs not supported yet");
642 for (i = 0; i < memperm_arity; ++i) {
644 arm_emitf(node, "str r%d, [sp, #-4]!", i);
646 /* load from entity */
647 ir_entity *entity = be_get_MemPerm_in_entity(node, i);
648 int offset = get_entity_offset(entity) + sp_change;
649 arm_emitf(node, "ldr r%d, [sp, #%d]", i, offset);
652 for (i = memperm_arity-1; i >= 0; --i) {
653 /* store to new entity */
654 ir_entity *entity = be_get_MemPerm_out_entity(node, i);
655 int offset = get_entity_offset(entity) + sp_change;
656 arm_emitf(node, "str r%d, [sp, #%d]", i, offset);
657 /* restore register */
658 arm_emitf(node, "ldr r%d, [sp], #4", i);
661 assert(sp_change == 0);
664 static void emit_be_Start(const ir_node *node)
666 ir_graph *irg = get_irn_irg(node);
667 ir_type *frame_type = get_irg_frame_type(irg);
668 unsigned size = get_type_size_bytes(frame_type);
670 /* allocate stackframe */
672 arm_emitf(node, "sub sp, sp, #0x%X", size);
676 static void emit_be_Return(const ir_node *node)
678 ir_graph *irg = get_irn_irg(node);
679 ir_type *frame_type = get_irg_frame_type(irg);
680 unsigned size = get_type_size_bytes(frame_type);
682 /* deallocate stackframe */
684 arm_emitf(node, "add sp, sp, #0x%X", size);
686 arm_emitf(node, "mov pc, lr");
690 static void emit_arm_Jmp(const ir_node *node)
692 ir_node *block, *next_block;
694 /* for now, the code works for scheduled and non-schedules blocks */
695 block = get_nodes_block(node);
697 /* we have a block schedule */
698 next_block = sched_next_block(block);
699 if (get_cfop_target_block(node) != next_block) {
700 arm_emitf(node, "b %t", node);
702 if (be_options.verbose_asm) {
703 arm_emitf(node, "/* fallthrough to %t */", node);
709 * Enters the emitter functions for handled nodes into the generic
710 * pointer of an opcode.
712 static void arm_register_emitters(void)
714 /* first clear the generic function pointer for all ops */
715 ir_clear_opcodes_generic_func();
717 /* register all emitter functions defined in spec */
718 arm_register_spec_emitters();
721 be_set_emitter(op_arm_B, emit_arm_B);
722 be_set_emitter(op_arm_CopyB, emit_arm_CopyB);
723 be_set_emitter(op_arm_FrameAddr, emit_arm_FrameAddr);
724 be_set_emitter(op_arm_Jmp, emit_arm_Jmp);
725 be_set_emitter(op_arm_SwitchJmp, emit_arm_SwitchJmp);
726 be_set_emitter(op_arm_SymConst, emit_arm_SymConst);
727 be_set_emitter(op_arm_fConst, emit_arm_fConst);
728 be_set_emitter(op_be_Copy, emit_be_Copy);
729 be_set_emitter(op_be_CopyKeep, emit_be_Copy);
730 be_set_emitter(op_be_IncSP, emit_be_IncSP);
731 be_set_emitter(op_be_MemPerm, emit_be_MemPerm);
732 be_set_emitter(op_be_Perm, emit_be_Perm);
733 be_set_emitter(op_be_Return, emit_be_Return);
734 be_set_emitter(op_be_Start, emit_be_Start);
736 /* no need to emit anything for the following nodes */
737 be_set_emitter(op_Phi, be_emit_nothing);
738 be_set_emitter(op_be_Keep, be_emit_nothing);
742 * emit the block label if needed.
744 static void arm_emit_block_header(ir_node *block, ir_node *prev)
746 bool need_label = false;
749 n_cfgpreds = get_Block_n_cfgpreds(block);
750 if (n_cfgpreds == 1) {
751 ir_node *pred = get_Block_cfgpred(block, 0);
752 ir_node *pred_block = get_nodes_block(pred);
754 /* we don't need labels for fallthrough blocks, however switch-jmps
755 * are no fallthroughs */
757 pred_block != prev ||
758 (is_Proj(pred) && is_arm_SwitchJmp(get_Proj_pred(pred)));
763 be_gas_begin_block(block, need_label);
767 * Walks over the nodes in a block connected by scheduling edges
768 * and emits code for each node.
770 static void arm_gen_block(ir_node *block, ir_node *prev_block)
772 arm_emit_block_header(block, prev_block);
773 be_dwarf_location(get_irn_dbg_info(block));
774 sched_foreach(block, irn) {
781 * Sets labels for control flow nodes (jump target)
783 static void arm_gen_labels(ir_node *block, void *env)
786 int n = get_Block_n_cfgpreds(block);
789 for (n--; n >= 0; n--) {
790 pred = get_Block_cfgpred(block, n);
791 set_irn_link(pred, block);
796 * Compare two entries of the symbol or tarval set.
798 static int cmp_sym_or_tv(const void *elt, const void *key, size_t size)
800 const sym_or_tv_t *p1 = (const sym_or_tv_t*)elt;
801 const sym_or_tv_t *p2 = (const sym_or_tv_t*)key;
804 /* as an identifier NEVER can point to a tarval, it's enough
805 to compare it this way */
806 return p1->u.generic != p2->u.generic;
809 void arm_gen_routine(ir_graph *irg)
811 ir_node *last_block = NULL;
812 ir_entity *entity = get_irg_entity(irg);
813 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
817 isa = (arm_isa_t*) arch_env;
818 sym_or_tv = new_set(cmp_sym_or_tv, 8);
820 be_gas_elf_type_char = '%';
822 arm_register_emitters();
824 /* create the block schedule */
825 blk_sched = be_create_block_schedule(irg);
827 be_gas_emit_function_prolog(entity, 4, NULL);
829 irg_block_walk_graph(irg, arm_gen_labels, NULL, NULL);
831 n = ARR_LEN(blk_sched);
832 for (i = 0; i < n;) {
833 ir_node *block, *next_bl;
835 block = blk_sched[i];
837 next_bl = i < n ? blk_sched[i] : NULL;
839 /* set here the link. the emitter expects to find the next block here */
840 set_irn_link(block, next_bl);
841 arm_gen_block(block, last_block);
845 /* emit SymConst values */
846 if (set_count(sym_or_tv) > 0) {
847 be_emit_cstring("\t.align 2\n");
849 foreach_set(sym_or_tv, sym_or_tv_t, entry) {
850 emit_constant_name(entry);
851 be_emit_cstring(":\n");
852 be_emit_write_line();
854 if (entry->is_entity) {
855 be_emit_cstring("\t.word\t");
856 be_gas_emit_entity(entry->u.entity);
858 be_emit_write_line();
860 ir_tarval *tv = entry->u.tv;
862 int size = get_mode_size_bytes(get_tarval_mode(tv));
864 /* beware: ARM fpa uses big endian format */
865 for (vi = ((size + 3) & ~3) - 4; vi >= 0; vi -= 4) {
868 v = get_tarval_sub_bits(tv, vi+3);
869 v = (v << 8) | get_tarval_sub_bits(tv, vi+2);
870 v = (v << 8) | get_tarval_sub_bits(tv, vi+1);
871 v = (v << 8) | get_tarval_sub_bits(tv, vi+0);
872 be_emit_irprintf("\t.word\t%u\n", v);
873 be_emit_write_line();
878 be_emit_write_line();
882 be_gas_emit_function_epilog(entity);
885 void arm_init_emitter(void)
887 FIRM_DBG_REGISTER(dbg, "firm.be.arm.emit");