2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * @author Oliver Richter, Tobias Gneist, Michael Beck
45 #include "raw_bitset.h"
48 #include "../besched.h"
49 #include "../beblocksched.h"
50 #include "../beirg_t.h"
51 #include "../begnuas.h"
53 #include "arm_emitter.h"
54 #include "gen_arm_emitter.h"
55 #include "arm_nodes_attr.h"
56 #include "arm_new_nodes.h"
57 #include "arm_map_regs.h"
58 #include "gen_arm_regalloc_if.h"
60 #include "../benode_t.h"
62 #define BLOCK_PREFIX ".L"
64 #define SNPRINTF_BUF_LEN 128
66 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
68 static const arch_env_t *arch_env = NULL;
69 static const arm_code_gen_t *cg;
70 static const arm_isa_t *isa;
71 static set *sym_or_tv;
74 * Returns the register at in position pos.
76 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
78 const arch_register_t *reg = NULL;
80 assert(get_irn_arity(irn) > pos && "Invalid IN position");
82 /* The out register of the operator at position pos is the
83 in register we need. */
84 op = get_irn_n(irn, pos);
86 reg = arch_get_irn_register(arch_env, op);
88 assert(reg && "no in register found");
90 /* in case of a joker register: just return a valid register */
91 if (arch_register_type_is(reg, joker)) {
92 const arch_register_req_t *req;
94 /* ask for the requirements */
95 req = arch_get_register_req(arch_env, irn, pos);
97 if (arch_register_req_is(req, limited)) {
98 /* in case of limited requirements: get the first allowed register */
99 unsigned idx = rbitset_next(req->limited, 0, 1);
100 reg = arch_register_for_index(req->cls, idx);
102 /* otherwise get first register in class */
103 reg = arch_register_for_index(req->cls, 0);
111 * Returns the register at out position pos.
113 static const arch_register_t *get_out_reg(const ir_node *node, int pos)
116 const arch_register_t *reg = NULL;
118 /* 1st case: irn is not of mode_T, so it has only */
119 /* one OUT register -> good */
120 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
121 /* Proj with the corresponding projnum for the register */
123 if (get_irn_mode(node) != mode_T) {
124 reg = arch_get_irn_register(arch_env, node);
125 } else if (is_arm_irn(node)) {
126 reg = get_arm_out_reg(node, pos);
128 const ir_edge_t *edge;
130 foreach_out_edge(node, edge) {
131 proj = get_edge_src_irn(edge);
132 assert(is_Proj(proj) && "non-Proj from mode_T node");
133 if (get_Proj_proj(proj) == pos) {
134 reg = arch_get_irn_register(arch_env, proj);
140 assert(reg && "no out register found");
144 /*************************************************************
146 * (_) | | / _| | | | |
147 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
148 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
149 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
150 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
153 *************************************************************/
156 * Emit the name of the source register at given input position.
158 void arm_emit_source_register(const ir_node *node, int pos) {
159 const arch_register_t *reg = get_in_reg(node, pos);
160 be_emit_string(arch_register_get_name(reg));
164 * Emit the name of the destination register at given output position.
166 void arm_emit_dest_register(const ir_node *node, int pos) {
167 const arch_register_t *reg = get_out_reg(node, pos);
168 be_emit_string(arch_register_get_name(reg));
172 * Emit a node's offset.
174 void arm_emit_offset(const ir_node *node) {
176 ir_op *irn_op = get_irn_op(node);
178 if (irn_op == op_be_Reload || irn_op == op_be_Spill) {
179 ir_entity *ent = be_get_frame_entity(node);
180 offset = get_entity_offset(ent);
181 } else if (irn_op == op_be_IncSP) {
182 offset = - be_get_IncSP_offset(node);
184 assert(!"unimplemented arm_emit_offset for this node type");
185 panic("unimplemented arm_emit_offset for this node type");
187 be_emit_irprintf("%d", offset);
191 * Emit the arm fpa instruction suffix depending on the mode.
193 static void arm_emit_fpa_postfix(const ir_mode *mode) {
194 int bits = get_mode_size_bits(mode);
204 * Emit the instruction suffix depending on the mode.
206 void arm_emit_mode(const ir_node *node) {
209 if (is_arm_irn(node)) {
210 const arm_attr_t *attr = get_arm_attr_const(node);
211 mode = attr->op_mode ? attr->op_mode : get_irn_mode(node);
213 mode = get_irn_mode(node);
215 arm_emit_fpa_postfix(mode);
219 * Emit a const or SymConst value.
221 void arm_emit_immediate(const ir_node *node) {
222 const arm_attr_t *attr = get_arm_attr_const(node);
224 if (ARM_GET_SHF_MOD(attr) == ARM_SHF_IMM) {
225 be_emit_irprintf("#0x%X", arm_decode_imm_w_shift(get_arm_imm_value(node)));
226 } else if (ARM_GET_FPA_IMM(attr)) {
227 be_emit_irprintf("#%s", arm_get_fpa_imm_name(get_arm_imm_value(node)));
228 } else if (is_arm_SymConst(node))
229 be_emit_ident(get_arm_symconst_id(node));
231 assert(!"not a Constant");
236 * Returns the tarval or offset of an arm node as a string.
238 void arm_emit_shift(const ir_node *node) {
239 arm_shift_modifier mod;
241 mod = get_arm_shift_modifier(node);
242 if (ARM_HAS_SHIFT(mod)) {
243 long v = get_arm_imm_value(node);
245 be_emit_irprintf(", %s #%l", arm_shf_mod_name(mod), v);
249 /** An entry in the sym_or_tv set. */
250 typedef struct sym_or_tv_t {
252 ident *id; /**< An ident. */
253 tarval *tv; /**< A tarval. */
254 const void *generic; /**< For generic compare. */
256 unsigned label; /**< the associated label. */
257 char is_ident; /**< Non-zero if an ident is stored. */
261 * Returns a unique label. This number will not be used a second time.
263 static unsigned get_unique_label(void) {
264 static unsigned id = 0;
271 static void emit_arm_SymConst(const ir_node *irn) {
272 sym_or_tv_t key, *entry;
275 key.u.id = get_arm_symconst_id(irn);
278 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
279 if (entry->label == 0) {
280 /* allocate a label */
281 entry->label = get_unique_label();
283 label = entry->label;
285 /* load the symbol indirect */
286 be_emit_cstring("\tldr ");
287 arm_emit_dest_register(irn, 0);
288 be_emit_irprintf(", .L%u", label);
289 be_emit_finish_line_gas(irn);
293 * Emit a floating point fpa constant.
295 static void emit_arm_fpaConst(const ir_node *irn) {
296 sym_or_tv_t key, *entry;
300 key.u.tv = get_fpaConst_value(irn);
303 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
304 if (entry->label == 0) {
305 /* allocate a label */
306 entry->label = get_unique_label();
308 label = entry->label;
310 /* load the tarval indirect */
311 mode = get_irn_mode(irn);
312 be_emit_cstring("\tldf");
313 arm_emit_fpa_postfix(mode);
316 arm_emit_dest_register(irn, 0);
317 be_emit_irprintf(", .L%u", label);
318 be_emit_finish_line_gas(irn);
322 * Returns the next block in a block schedule.
324 static ir_node *sched_next_block(const ir_node *block) {
325 return get_irn_link(block);
329 * Returns the target block for a control flow node.
331 static ir_node *get_cfop_target_block(const ir_node *irn) {
332 return get_irn_link(irn);
336 * Emits a block label for the given block.
338 static void arm_emit_block_name(const ir_node *block) {
339 if (has_Block_label(block)) {
340 be_emit_string(be_gas_label_prefix());
341 be_emit_irprintf("%lu", get_Block_label(block));
343 be_emit_cstring(BLOCK_PREFIX);
344 be_emit_irprintf("%d", get_irn_node_nr(block));
349 * Emit the target label for a control flow node.
351 static void arm_emit_cfop_target(const ir_node *irn) {
352 ir_node *block = get_cfop_target_block(irn);
354 arm_emit_block_name(block);
358 * Emit a Compare with conditional branch.
360 static void emit_arm_CmpBra(const ir_node *irn) {
361 const ir_edge_t *edge;
362 const ir_node *proj_true = NULL;
363 const ir_node *proj_false = NULL;
364 const ir_node *block;
365 const ir_node *next_block;
366 ir_node *op1 = get_irn_n(irn, 0);
367 ir_mode *opmode = get_irn_mode(op1);
369 int proj_num = get_arm_CondJmp_proj_num(irn);
371 foreach_out_edge(irn, edge) {
372 ir_node *proj = get_edge_src_irn(edge);
373 long nr = get_Proj_proj(proj);
374 if (nr == pn_Cond_true) {
381 /* for now, the code works for scheduled and non-schedules blocks */
382 block = get_nodes_block(irn);
384 /* we have a block schedule */
385 next_block = sched_next_block(block);
387 if (proj_num == pn_Cmp_False) {
388 /* always false: should not happen */
389 be_emit_cstring("\tb ");
390 arm_emit_cfop_target(proj_false);
391 be_emit_finish_line_gas(proj_false);
392 } else if (proj_num == pn_Cmp_True) {
393 /* always true: should not happen */
394 be_emit_cstring("\tb ");
395 arm_emit_cfop_target(proj_true);
396 be_emit_finish_line_gas(proj_true);
398 if (mode_is_float(opmode)) {
399 suffix = "ICHWILLIMPLEMENTIERTWERDEN";
401 be_emit_cstring("\tfcmp ");
402 arm_emit_source_register(irn, 0);
403 be_emit_cstring(", ");
404 arm_emit_source_register(irn, 1);
405 be_emit_finish_line_gas(irn);
407 be_emit_cstring("\tfmstat");
408 be_emit_pad_comment();
409 be_emit_cstring("/* FCSPR -> CPSR */");
410 be_emit_finish_line_gas(NULL);
412 if (get_cfop_target_block(proj_true) == next_block) {
413 /* exchange both proj's so the second one can be omitted */
414 const ir_node *t = proj_true;
416 proj_true = proj_false;
418 proj_num = get_negated_pnc(proj_num, mode_Iu);
421 case pn_Cmp_Eq: suffix = "eq"; break;
422 case pn_Cmp_Lt: suffix = "lt"; break;
423 case pn_Cmp_Le: suffix = "le"; break;
424 case pn_Cmp_Gt: suffix = "gt"; break;
425 case pn_Cmp_Ge: suffix = "ge"; break;
426 case pn_Cmp_Lg: suffix = "ne"; break;
427 case pn_Cmp_Leg: suffix = "al"; break;
428 default: assert(!"Cmp unsupported"); suffix = "al";
430 be_emit_cstring("\tcmp ");
431 arm_emit_source_register(irn, 0);
432 be_emit_cstring(", ");
433 arm_emit_source_register(irn, 1);
434 be_emit_finish_line_gas(irn);
437 /* emit the true proj */
438 be_emit_irprintf("\tb%s ", suffix);
439 arm_emit_cfop_target(proj_true);
440 be_emit_finish_line_gas(proj_true);
442 if (get_cfop_target_block(proj_false) == next_block) {
443 be_emit_cstring("\t/* fallthrough to ");
444 arm_emit_cfop_target(proj_false);
445 be_emit_cstring(" */");
446 be_emit_finish_line_gas(proj_false);
448 be_emit_cstring("b ");
449 arm_emit_cfop_target(proj_false);
450 be_emit_finish_line_gas(proj_false);
456 * Emit a Compare with conditional branch.
458 static void emit_arm_fpaCmfBra(const ir_node *irn) {
463 * Emit a Compare with conditional branch.
465 static void emit_arm_fpaCmfeBra(const ir_node *irn) {
469 /** Sort register in ascending order. */
470 static int reg_cmp(const void *a, const void *b) {
471 const arch_register_t * const *ra = a;
472 const arch_register_t * const *rb = b;
474 return *ra < *rb ? -1 : (*ra != *rb);
478 * Create the CopyB instruction sequence.
480 static void emit_arm_CopyB(const ir_node *irn) {
481 unsigned size = (unsigned)get_arm_imm_value(irn);
483 const char *tgt = arch_register_get_name(get_in_reg(irn, 0));
484 const char *src = arch_register_get_name(get_in_reg(irn, 1));
485 const char *t0, *t1, *t2, *t3;
487 const arch_register_t *tmpregs[4];
489 /* collect the temporary registers and sort them, we need ascending order */
490 tmpregs[0] = get_in_reg(irn, 2);
491 tmpregs[1] = get_in_reg(irn, 3);
492 tmpregs[2] = get_in_reg(irn, 4);
493 tmpregs[3] = &arm_gp_regs[REG_R12];
495 /* Note: R12 is always the last register because the RA did not assign higher ones */
496 qsort((void *)tmpregs, 3, sizeof(tmpregs[0]), reg_cmp);
498 /* need ascending order */
499 t0 = arch_register_get_name(tmpregs[0]);
500 t1 = arch_register_get_name(tmpregs[1]);
501 t2 = arch_register_get_name(tmpregs[2]);
502 t3 = arch_register_get_name(tmpregs[3]);
504 be_emit_cstring("/* MemCopy (");
506 be_emit_cstring(")->(");
507 arm_emit_source_register(irn, 0);
508 be_emit_irprintf(" [%u bytes], Uses ", size);
510 be_emit_cstring(", ");
512 be_emit_cstring(", ");
514 be_emit_cstring(", and ");
516 be_emit_cstring("*/");
517 be_emit_finish_line_gas(NULL);
519 assert(size > 0 && "CopyB needs size > 0" );
522 assert(!"strange hack enabled: copy more bytes than needed!");
531 be_emit_cstring("\tldr ");
533 be_emit_cstring(", [");
535 be_emit_cstring(", #0]");
536 be_emit_finish_line_gas(NULL);
538 be_emit_cstring("\tstr ");
540 be_emit_cstring(", [");
542 be_emit_cstring(", #0]");
543 be_emit_finish_line_gas(irn);
546 be_emit_cstring("\tldmia ");
548 be_emit_cstring("!, {");
550 be_emit_cstring(", ");
553 be_emit_finish_line_gas(NULL);
555 be_emit_cstring("\tstmia ");
557 be_emit_cstring("!, {");
559 be_emit_cstring(", ");
562 be_emit_finish_line_gas(irn);
565 be_emit_cstring("\tldmia ");
567 be_emit_cstring("!, {");
569 be_emit_cstring(", ");
571 be_emit_cstring(", ");
574 be_emit_finish_line_gas(NULL);
576 be_emit_cstring("\tstmia ");
578 be_emit_cstring("!, {");
580 be_emit_cstring(", ");
582 be_emit_cstring(", ");
585 be_emit_finish_line_gas(irn);
590 be_emit_cstring("\tldmia ");
592 be_emit_cstring("!, {");
594 be_emit_cstring(", ");
596 be_emit_cstring(", ");
598 be_emit_cstring(", ");
601 be_emit_finish_line_gas(NULL);
603 be_emit_cstring("\tstmia ");
605 be_emit_cstring("!, {");
607 be_emit_cstring(", ");
609 be_emit_cstring(", ");
611 be_emit_cstring(", ");
614 be_emit_finish_line_gas(irn);
619 static void emit_arm_SwitchJmp(const ir_node *irn) {
620 const ir_edge_t *edge;
626 ir_node *default_proj = NULL;
628 block_nr = get_irn_node_nr(irn);
629 n_projs = get_arm_SwitchJmp_n_projs(irn);
631 projs = xcalloc(n_projs , sizeof(ir_node*));
633 foreach_out_edge(irn, edge) {
634 proj = get_edge_src_irn(edge);
635 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
637 if (get_Proj_proj(proj) == get_arm_SwitchJmp_default_proj_num(irn))
640 projs[get_Proj_proj(proj)] = proj;
642 assert(default_proj != NULL && "SwitchJmp should have a Default Proj");
649 be_emit_cstring("\tcmp ");
650 arm_emit_source_register(irn, 0);
651 be_emit_irprintf(", #%u", n_projs - 1);
652 be_emit_finish_line_gas(irn);
654 be_emit_cstring("\tbhi ");
655 arm_emit_cfop_target(default_proj);
656 be_emit_finish_line_gas(default_proj);
659 LDR %r12, .TABLE_X_START
660 ADD %r12, %r12, [%1S, LSL #2]
664 be_emit_irprintf("\tldr %%r12, TABLE_%d_START", block_nr);
665 be_emit_finish_line_gas(NULL);
667 be_emit_irprintf("\tadd %%r12, %%r12, ");
668 arm_emit_source_register(irn, 0);
669 be_emit_cstring(", LSL #2");
670 be_emit_finish_line_gas(NULL);
672 be_emit_cstring("\tldr %r15, [%r12, #0]");
673 be_emit_finish_line_gas(NULL);
675 be_emit_irprintf("TABLE_%d_START:\n\t.word\tTABLE_%d", block_nr, block_nr);
676 be_emit_finish_line_gas(NULL);
677 be_emit_irprintf("\t.align 2");
678 be_emit_finish_line_gas(NULL);
679 be_emit_irprintf("TABLE_%d:", block_nr);
680 be_emit_finish_line_gas(NULL);
682 for (i = 0; i < n_projs; ++i) {
685 proj = projs[get_arm_SwitchJmp_default_proj_num(irn)];
687 be_emit_cstring("\t.word\t");
688 arm_emit_cfop_target(proj);
689 be_emit_finish_line_gas(proj);
691 be_emit_irprintf("\t.align 2\n");
692 be_emit_finish_line_gas(NULL);
696 /************************************************************************/
698 /************************************************************************/
700 static void emit_be_Call(const ir_node *irn) {
701 ir_entity *ent = be_Call_get_entity(irn);
703 be_emit_cstring("\tbl ");
705 set_entity_backend_marked(ent, 1);
706 be_emit_ident(get_entity_ld_ident(ent));
708 arm_emit_source_register(irn, be_pos_Call_ptr);
710 be_emit_finish_line_gas(irn);
713 /** Emit an IncSP node */
714 static void emit_be_IncSP(const ir_node *irn) {
715 int offs = be_get_IncSP_offset(irn);
718 be_emit_cstring("\tadd ");
719 arm_emit_dest_register(irn, 0);
720 be_emit_cstring(", ");
721 arm_emit_source_register(irn, 0);
722 be_emit_cstring(", #");
723 arm_emit_offset(irn);
725 be_emit_cstring("\t/* omitted IncSP(");
726 arm_emit_offset(irn);
727 be_emit_cstring(") */");
729 be_emit_finish_line_gas(irn);
732 static void emit_be_Copy(const ir_node *irn) {
733 ir_mode *mode = get_irn_mode(irn);
735 if (get_in_reg(irn, 0) == get_out_reg(irn, 0)) {
736 be_emit_cstring("\t/* omitted Copy: ");
737 arm_emit_source_register(irn, 0);
738 be_emit_cstring(" -> ");
739 arm_emit_dest_register(irn, 0);
740 be_emit_finish_line_gas(irn);
744 if (mode_is_float(mode)) {
746 be_emit_cstring("\tmvf");
749 arm_emit_dest_register(irn, 0);
750 be_emit_cstring(", ");
751 arm_emit_source_register(irn, 0);
752 be_emit_finish_line_gas(irn);
754 assert(0 && "move not supported for this mode");
755 panic("emit_be_Copy: move not supported for this mode");
757 } else if (mode_is_data(mode)) {
758 be_emit_cstring("\tmov ");
759 arm_emit_dest_register(irn, 0);
760 be_emit_cstring(", ");
761 arm_emit_source_register(irn, 0);
762 be_emit_finish_line_gas(irn);
764 assert(0 && "move not supported for this mode");
765 panic("emit_be_Copy: move not supported for this mode");
770 * Emit code for a Spill.
772 static void emit_be_Spill(const ir_node *irn) {
773 ir_mode *mode = get_irn_mode(be_get_Spill_val(irn));
775 if (mode_is_float(mode)) {
776 if (USE_FPA(cg->isa)) {
777 be_emit_cstring("\tstf");
778 arm_emit_fpa_postfix(mode);
781 assert(0 && "spill not supported for this mode");
782 panic("emit_be_Spill: spill not supported for this mode");
784 } else if (mode_is_dataM(mode)) {
785 be_emit_cstring("\tstr ");
787 assert(0 && "spill not supported for this mode");
788 panic("emit_be_Spill: spill not supported for this mode");
790 arm_emit_source_register(irn, 1);
791 be_emit_cstring(", [");
792 arm_emit_source_register(irn, 0);
793 be_emit_cstring(", #");
794 arm_emit_offset(irn);
796 be_emit_finish_line_gas(irn);
800 * Emit code for a Reload.
802 static void emit_be_Reload(const ir_node *irn) {
803 ir_mode *mode = get_irn_mode(irn);
805 if (mode_is_float(mode)) {
806 if (USE_FPA(cg->isa)) {
807 be_emit_cstring("\tldf");
808 arm_emit_fpa_postfix(mode);
811 assert(0 && "reload not supported for this mode");
812 panic("emit_be_Reload: reload not supported for this mode");
814 } else if (mode_is_dataM(mode)) {
815 be_emit_cstring("\tldr ");
817 assert(0 && "reload not supported for this mode");
818 panic("emit_be_Reload: reload not supported for this mode");
820 arm_emit_dest_register(irn, 0);
821 be_emit_cstring(", [");
822 arm_emit_source_register(irn, 0);
823 be_emit_cstring(", #");
824 arm_emit_offset(irn);
826 be_emit_finish_line_gas(irn);
829 static void emit_be_Perm(const ir_node *irn) {
830 be_emit_cstring("\teor ");
831 arm_emit_source_register(irn, 0);
832 be_emit_cstring(", ");
833 arm_emit_source_register(irn, 0);
834 be_emit_cstring(", ");
835 arm_emit_source_register(irn, 1);
836 be_emit_finish_line_gas(NULL);
838 be_emit_cstring("\teor ");
839 arm_emit_source_register(irn, 1);
840 be_emit_cstring(", ");
841 arm_emit_source_register(irn, 0);
842 be_emit_cstring(", ");
843 arm_emit_source_register(irn, 1);
844 be_emit_finish_line_gas(NULL);
846 be_emit_cstring("\teor ");
847 arm_emit_source_register(irn, 0);
848 be_emit_cstring(", ");
849 arm_emit_source_register(irn, 0);
850 be_emit_cstring(", ");
851 arm_emit_source_register(irn, 1);
852 be_emit_finish_line_gas(irn);
855 /************************************************************************/
857 /************************************************************************/
859 static void emit_Jmp(const ir_node *node) {
860 ir_node *block, *next_block;
862 /* for now, the code works for scheduled and non-schedules blocks */
863 block = get_nodes_block(node);
865 /* we have a block schedule */
866 next_block = sched_next_block(block);
867 if (get_cfop_target_block(node) != next_block) {
868 be_emit_cstring("\tb ");
869 arm_emit_cfop_target(node);
871 be_emit_cstring("\t/* fallthrough to ");
872 arm_emit_cfop_target(node);
873 be_emit_cstring(" */");
875 be_emit_finish_line_gas(node);
878 static void emit_arm_fpaDbl2GP(const ir_node *irn) {
879 be_emit_cstring("\tstfd ");
880 arm_emit_source_register(irn, 0);
881 be_emit_cstring(", [sp, #-8]!");
882 be_emit_pad_comment();
883 be_emit_cstring("/* Push fp to stack */");
884 be_emit_finish_line_gas(NULL);
886 be_emit_cstring("\tldmfd sp!, {");
887 arm_emit_dest_register(irn, 1);
888 be_emit_cstring(", ");
889 arm_emit_dest_register(irn, 0);
891 be_emit_pad_comment();
892 be_emit_cstring("/* Pop destination */");
893 be_emit_finish_line_gas(irn);
896 static void emit_arm_LdTls(const ir_node *irn) {
898 panic("TLS not supported for this target\n");
899 /* Er... our gcc does not support it... Install a newer toolchain. */
902 /***********************************************************************************
905 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
906 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
907 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
908 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
910 ***********************************************************************************/
912 static void emit_silence(const ir_node *irn) {
918 * The type of a emitter function.
920 typedef void (emit_func)(const ir_node *irn);
923 * Set a node emitter. Make it a bit more type safe.
925 static INLINE void set_emitter(ir_op *op, emit_func arm_emit_node) {
926 op->ops.generic = (op_func)arm_emit_node;
930 * Enters the emitter functions for handled nodes into the generic
931 * pointer of an opcode.
933 static void arm_register_emitters(void) {
935 #define ARM_EMIT(a) set_emitter(op_arm_##a, emit_arm_##a)
936 #define EMIT(a) set_emitter(op_##a, emit_##a)
937 #define BE_EMIT(a) set_emitter(op_be_##a, emit_be_##a)
938 #define SILENCE(a) set_emitter(op_##a, emit_silence)
940 /* first clear the generic function pointer for all ops */
941 clear_irp_opcodes_generic_func();
943 /* register all emitter functions defined in spec */
944 arm_register_spec_emitters();
946 /* other emitter functions */
949 ARM_EMIT(fpaCmfeBra);
951 // ARM_EMIT(CopyB_i);
976 SILENCE(be_CopyKeep);
977 SILENCE(be_RegParams);
988 static const char *last_name = NULL;
989 static unsigned last_line = -1;
990 static unsigned num = -1;
993 * Emit the debug support for node node.
995 static void arm_emit_dbg(const ir_node *irn) {
996 dbg_info *db = get_irn_dbg_info(irn);
998 const char *fname = ir_retrieve_dbg_info(db, &lineno);
1000 if (! cg->birg->main_env->options->stabs_debug_support)
1004 if (last_name != fname) {
1006 be_dbg_include_begin(cg->birg->main_env->db_handle, fname);
1009 if (last_line != lineno) {
1012 snprintf(name, sizeof(name), ".LM%u", ++num);
1014 be_dbg_line(cg->birg->main_env->db_handle, lineno, name);
1015 be_emit_string(name);
1016 be_emit_cstring(":\n");
1017 be_emit_write_line();
1023 * Emits code for a node.
1025 static void arm_emit_node(const ir_node *irn) {
1026 ir_op *op = get_irn_op(irn);
1028 if (op->ops.generic) {
1029 emit_func *emit = (emit_func *)op->ops.generic;
1033 be_emit_cstring("\t/* TODO */");
1034 be_emit_finish_line_gas(irn);
1039 * emit the block label if needed.
1041 static void arm_emit_block_header(ir_node *block, ir_node *prev)
1046 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1049 n_cfgpreds = get_Block_n_cfgpreds(block);
1050 if (n_cfgpreds == 1) {
1051 ir_node *pred = get_Block_cfgpred(block, 0);
1052 ir_node *pred_block = get_nodes_block(pred);
1054 /* we don't need labels for fallthrough blocks, however switch-jmps
1055 * are no fallthroughs */
1056 if (pred_block == prev &&
1057 !(is_Proj(pred) && is_arm_SwitchJmp(get_Proj_pred(pred)))) {
1067 arm_emit_block_name(block);
1070 be_emit_pad_comment();
1071 be_emit_cstring(" /* preds:");
1073 /* emit list of pred blocks in comment */
1074 arity = get_irn_arity(block);
1075 for (i = 0; i < arity; ++i) {
1076 ir_node *predblock = get_Block_cfgpred_block(block, i);
1077 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1080 be_emit_cstring("\t/* ");
1081 arm_emit_block_name(block);
1082 be_emit_cstring(": ");
1084 if (exec_freq != NULL) {
1085 be_emit_irprintf(" freq: %f",
1086 get_block_execfreq(exec_freq, block));
1088 be_emit_cstring(" */\n");
1089 be_emit_write_line();
1093 * Walks over the nodes in a block connected by scheduling edges
1094 * and emits code for each node.
1096 static void arm_gen_block(ir_node *block, ir_node *prev_block) {
1099 arm_emit_block_header(block, prev_block);
1100 arm_emit_dbg(block);
1101 sched_foreach(block, irn) {
1107 * Emits code for function start.
1109 void arm_func_prolog(ir_graph *irg) {
1110 ir_entity *ent = get_irg_entity(irg);
1111 const char *irg_name = get_entity_ld_name(ent);
1113 be_emit_write_line();
1114 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1115 be_emit_cstring("\t.align 2\n");
1117 if (get_entity_visibility(ent) == visibility_external_visible)
1118 be_emit_irprintf("\t.global %s\n", irg_name);
1119 be_emit_irprintf("%s:\n", irg_name);
1123 * Emits code for function end
1125 void arm_emit_end(FILE *F, ir_graph *irg) {
1127 fprintf(F, "\t.ident \"firmcc\"\n");
1132 * Sets labels for control flow nodes (jump target)
1134 static void arm_gen_labels(ir_node *block, void *env) {
1136 int n = get_Block_n_cfgpreds(block);
1139 for (n--; n >= 0; n--) {
1140 pred = get_Block_cfgpred(block, n);
1141 set_irn_link(pred, block);
1146 * Compare two entries of the symbol or tarval set.
1148 static int cmp_sym_or_tv(const void *elt, const void *key, size_t size) {
1149 const sym_or_tv_t *p1 = elt;
1150 const sym_or_tv_t *p2 = key;
1153 /* as an identifier NEVER can point to a tarval, it's enough
1154 to compare it this way */
1155 return p1->u.generic != p2->u.generic;
1159 * Main driver. Emits the code for one routine.
1161 void arm_gen_routine(const arm_code_gen_t *arm_cg, ir_graph *irg) {
1162 ir_node **blk_sched;
1164 ir_node *last_block = NULL;
1167 isa = (const arm_isa_t *)cg->arch_env->isa;
1168 arch_env = cg->arch_env;
1169 sym_or_tv = new_set(cmp_sym_or_tv, 8);
1171 arm_register_emitters();
1173 /* create the block schedule. For now, we don't need it earlier. */
1174 blk_sched = be_create_block_schedule(cg->irg, cg->birg->exec_freq);
1176 arm_func_prolog(irg);
1177 irg_block_walk_graph(irg, arm_gen_labels, NULL, NULL);
1179 n = ARR_LEN(blk_sched);
1180 for (i = 0; i < n;) {
1181 ir_node *block, *next_bl;
1183 block = blk_sched[i];
1185 next_bl = i < n ? blk_sched[i] : NULL;
1187 /* set here the link. the emitter expects to find the next block here */
1188 set_irn_link(block, next_bl);
1189 arm_gen_block(block, last_block);
1193 /* emit SymConst values */
1194 if (set_count(sym_or_tv) > 0) {
1197 be_emit_cstring("\t.align 2\n");
1199 foreach_set(sym_or_tv, entry) {
1200 be_emit_irprintf(".L%u:\n", entry->label);
1202 if (entry->is_ident) {
1203 be_emit_cstring("\t.word\t");
1204 be_emit_ident(entry->u.id);
1206 be_emit_write_line();
1208 tarval *tv = entry->u.tv;
1209 int i, size = get_mode_size_bytes(get_tarval_mode(tv));
1212 /* beware: ARM fpa uses big endian format */
1213 for (i = ((size + 3) & ~3) - 4; i >= 0; i -= 4) {
1215 v = get_tarval_sub_bits(tv, i+3);
1216 v = (v << 8) | get_tarval_sub_bits(tv, i+2);
1217 v = (v << 8) | get_tarval_sub_bits(tv, i+1);
1218 v = (v << 8) | get_tarval_sub_bits(tv, i+0);
1219 be_emit_irprintf("\t.word\t%u\n", v);
1220 be_emit_write_line();
1225 be_emit_write_line();
1230 void arm_init_emitter(void)
1232 FIRM_DBG_REGISTER(dbg, "firm.be.arm.emit");