2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main amd64 backend driver file.
23 * @version $Id: bearch_amd64.c 26909 2010-01-05 15:56:54Z matze $
33 #include "lower_calls.h"
46 #include "belistsched.h"
48 #include "bespillslots.h"
49 #include "bespillutil.h"
52 #include "bearch_amd64_t.h"
54 #include "amd64_new_nodes.h"
55 #include "gen_amd64_regalloc_if.h"
56 #include "amd64_transform.h"
57 #include "amd64_emitter.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static arch_irn_class_t amd64_classify(const ir_node *irn)
64 return arch_irn_class_none;
67 static ir_entity *amd64_get_frame_entity(const ir_node *node)
69 if (is_amd64_FrameAddr(node)) {
70 const amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr_const(node);
73 } else if (is_amd64_Store(node)) {
74 const amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr_const(node);
77 } else if (is_amd64_Load(node)) {
78 const amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr_const(node);
83 /* TODO: return the ir_entity assigned to the frame */
88 * This function is called by the generic backend to correct offsets for
89 * nodes accessing the stack.
91 static void amd64_set_frame_offset(ir_node *irn, int offset)
93 if (is_amd64_FrameAddr(irn)) {
94 amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr(irn);
95 attr->fp_offset += offset;
97 } else if (is_amd64_Store(irn)) {
98 amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr(irn);
99 attr->fp_offset += offset;
101 } else if (is_amd64_Load(irn)) {
102 amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr(irn);
103 attr->fp_offset += offset;
108 static int amd64_get_sp_bias(const ir_node *irn)
114 /* fill register allocator interface */
116 static const arch_irn_ops_t amd64_irn_ops = {
118 amd64_get_frame_entity,
119 amd64_set_frame_offset,
121 NULL, /* get_inverse */
122 NULL, /* get_op_estimated_cost */
123 NULL, /* possible_memory_operand */
124 NULL, /* perform_memory_operand */
130 * Transforms the standard firm graph into
133 static void amd64_prepare_graph(ir_graph *irg)
135 amd64_irg_data_t *irg_data = amd64_get_irg_data(irg);
136 amd64_transform_graph(irg);
139 dump_ir_graph(irg, "transformed");
142 static void amd64_before_ra(ir_graph *irg)
144 be_sched_fix_flags(irg, &amd64_reg_classes[CLASS_amd64_flags], NULL, NULL);
147 static void transform_Reload(ir_node *node)
149 ir_graph *irg = get_irn_irg(node);
150 ir_node *block = get_nodes_block(node);
151 dbg_info *dbgi = get_irn_dbg_info(node);
152 ir_node *ptr = get_irg_frame(irg);
153 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
154 ir_mode *mode = get_irn_mode(node);
155 ir_entity *entity = be_get_frame_entity(node);
156 const arch_register_t *reg;
160 ir_node *sched_point = sched_prev(node);
162 load = new_bd_amd64_Load(dbgi, block, ptr, mem, entity);
163 sched_add_after(sched_point, load);
166 proj = new_rd_Proj(dbgi, load, mode, pn_amd64_Load_res);
168 reg = arch_get_irn_register(node);
169 arch_set_irn_register(proj, reg);
171 exchange(node, proj);
174 static void transform_Spill(ir_node *node)
176 ir_graph *irg = get_irn_irg(node);
177 ir_node *block = get_nodes_block(node);
178 dbg_info *dbgi = get_irn_dbg_info(node);
179 ir_node *ptr = get_irg_frame(irg);
180 ir_node *mem = get_irg_no_mem(irg);
181 ir_node *val = get_irn_n(node, n_be_Spill_val);
182 //ir_mode *mode = get_irn_mode(val);
183 ir_entity *entity = be_get_frame_entity(node);
184 ir_node *sched_point;
187 sched_point = sched_prev(node);
188 store = new_bd_amd64_Store(dbgi, block, ptr, val, mem, entity);
191 sched_add_after(sched_point, store);
193 exchange(node, store);
196 static void amd64_after_ra_walker(ir_node *block, void *data)
198 ir_node *node, *prev;
201 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
202 prev = sched_prev(node);
204 if (be_is_Reload(node)) {
205 transform_Reload(node);
206 } else if (be_is_Spill(node)) {
207 transform_Spill(node);
212 static void amd64_set_frame_entity(ir_node *node, ir_entity *entity)
214 assert(be_is_Reload(node));
215 be_node_set_frame_entity(node, entity);
219 * Collects nodes that need frame entities assigned.
221 static void amd64_collect_frame_entity_nodes(ir_node *node, void *data)
223 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
224 be_fec_env_t *env = (be_fec_env_t*)data;
225 const ir_mode *mode = get_irn_mode(node);
226 int align = get_mode_size_bytes(mode);
227 be_node_needs_frame_entity(env, node, mode, align);
232 * Called immediatly before emit phase.
234 static void amd64_finish_irg(ir_graph *irg)
236 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
237 bool at_begin = stack_layout->sp_relative ? true : false;
238 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
240 /* create and coalesce frame entities */
241 irg_walk_graph(irg, NULL, amd64_collect_frame_entity_nodes, fec_env);
242 be_assign_entities(fec_env, amd64_set_frame_entity, at_begin);
243 be_free_frame_entity_coalescer(fec_env);
245 irg_block_walk_graph(irg, NULL, amd64_after_ra_walker, NULL);
247 /* fix stack entity offsets */
248 be_abi_fix_stack_nodes(irg);
249 be_abi_fix_stack_bias(irg);
253 * Initializes the code generator.
255 static void amd64_init_graph(ir_graph *irg)
257 struct obstack *obst = be_get_be_obst(irg);
258 amd64_irg_data_t *irg_data = OALLOCZ(obst, amd64_irg_data_t);
259 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
261 be_birg_from_irg(irg)->isa_link = irg_data;
265 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
268 * Used to create per-graph unique pseudo nodes.
270 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
271 create_const_node_func func,
272 const arch_register_t* reg)
274 ir_node *block, *res;
279 block = get_irg_start_block(irg);
280 res = func(NULL, block);
281 arch_set_irn_register(res, reg);
287 extern const arch_isa_if_t amd64_isa_if;
288 static amd64_isa_t amd64_isa_template = {
290 &amd64_isa_if, /* isa interface implementation */
295 &amd64_registers[REG_RSP], /* stack pointer register */
296 &amd64_registers[REG_RBP], /* base pointer register */
297 &amd64_reg_classes[CLASS_amd64_gp], /* link pointer register class */
298 3, /* power of two stack alignment for calls, 2^2 == 4 */
299 NULL, /* main environment */
300 7, /* costs for a spill instruction */
301 5, /* costs for a reload instruction */
302 false, /* no custom abi handling */
307 * Initializes the backend ISA
309 static arch_env_t *amd64_init(const be_main_env_t *env)
311 amd64_isa_t *isa = XMALLOC(amd64_isa_t);
312 *isa = amd64_isa_template;
314 amd64_register_init();
315 amd64_create_opcodes(&amd64_irn_ops);
317 be_emit_init(env->file_handle);
318 be_gas_begin_compilation_unit(env);
326 * Closes the output file and frees the ISA structure.
328 static void amd64_done(void *self)
330 amd64_isa_t *isa = (amd64_isa_t*)self;
332 /* emit now all global declarations */
333 be_gas_end_compilation_unit(isa->base.main_env);
341 * Get the register class which shall be used to store a value of a given mode.
342 * @param self The this pointer.
343 * @param mode The mode in question.
344 * @return A register class which can hold values of the given mode.
346 static const arch_register_class_t *amd64_get_reg_class_for_mode(const ir_mode *mode)
348 assert(!mode_is_float(mode));
349 return &amd64_reg_classes[CLASS_amd64_gp];
355 be_abi_call_flags_bits_t flags;
360 * Get the between type for that call.
361 * @param self The callback object.
362 * @return The between type of for that call.
364 static ir_type *amd64_get_between_type(ir_graph *irg)
366 static ir_type *between_type = NULL;
367 static ir_entity *old_bp_ent = NULL;
371 ir_entity *ret_addr_ent;
372 ir_type *ret_addr_type = new_type_primitive(mode_P);
373 ir_type *old_bp_type = new_type_primitive(mode_P);
375 between_type = new_type_class(new_id_from_str("amd64_between_type"));
376 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
377 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
379 set_entity_offset(old_bp_ent, 0);
380 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
381 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
387 static const be_abi_callbacks_t amd64_abi_callbacks = {
388 amd64_get_between_type,
391 static const arch_register_t *gpreg_param_reg_std[] = {
392 &amd64_registers[REG_RDI],
393 &amd64_registers[REG_RSI],
394 &amd64_registers[REG_RDX],
395 &amd64_registers[REG_RCX],
396 &amd64_registers[REG_R8],
397 &amd64_registers[REG_R9],
400 static const arch_register_t *amd64_get_RegParam_reg(int n)
402 assert(n < 6 && n >=0 && "register param > 6 requested");
403 return gpreg_param_reg_std[n];
407 * Get the ABI restrictions for procedure calls.
408 * @param self The this pointer.
409 * @param method_type The type of the method (procedure) in question.
410 * @param abi The abi object to be modified
412 static void amd64_get_call_abi(const void *self, ir_type *method_type,
417 int i, n = get_method_n_params(method_type);
418 be_abi_call_flags_t call_flags;
423 /* set abi flags for calls */
424 call_flags.bits.store_args_sequential = 0;
425 call_flags.bits.try_omit_fp = 1;
426 call_flags.bits.fp_free = 0;
427 call_flags.bits.call_has_imm = 1;
429 /* set stack parameter passing style */
430 be_abi_call_set_flags(abi, call_flags, &amd64_abi_callbacks);
432 for (i = 0; i < n; i++) {
433 tp = get_method_param_type(method_type, i);
434 mode = get_type_mode(tp);
435 //d// printf ("MODE %p %p XX %d\n", mode, mode_Iu, i);
437 if (!no_reg && i < 6 && mode_is_data (mode)) {
438 //d// printf("TEST%d\n", i);
439 be_abi_call_param_reg(abi, i, amd64_get_RegParam_reg (i),
441 /* default: all parameters on stack */
444 be_abi_call_param_stack(abi, i, mode, 8, 0, 0, ABI_CONTEXT_BOTH);
448 /* TODO: set correct return register */
449 /* default: return value is in R0 resp. F0 */
450 if (get_method_n_ress(method_type) > 0) {
451 tp = get_method_res_type(method_type, 0);
452 mode = get_type_mode(tp);
454 /* FIXME: No floating point yet */
455 /* be_abi_call_res_reg(abi, 0,
456 mode_is_float(mode) ? &amd64_fp_regs[REG_F0] : &amd64_registers[REG_R0], ABI_CONTEXT_BOTH); */
458 be_abi_call_res_reg(abi, 0,
459 &amd64_registers[REG_RAX], ABI_CONTEXT_BOTH);
464 * Returns the necessary byte alignment for storing a register of given class.
466 static int amd64_get_reg_class_alignment(const arch_register_class_t *cls)
468 ir_mode *mode = arch_register_class_mode(cls);
469 return get_mode_size_bytes(mode);
472 static void amd64_lower_for_target(void)
474 size_t i, n_irgs = get_irp_n_irgs();
476 /* lower compound param handling */
477 lower_calls_with_compounds(LF_RETURN_HIDDEN);
479 for (i = 0; i < n_irgs; ++i) {
480 ir_graph *irg = get_irp_irg(i);
481 /* Turn all small CopyBs into loads/stores, and turn all bigger
482 * CopyBs into memcpy calls, because we cannot handle CopyB nodes
483 * during code generation yet.
484 * TODO: Adapt this once custom CopyB handling is implemented. */
485 lower_CopyB(irg, 64, 65, true);
489 static int amd64_is_mux_allowed(ir_node *sel, ir_node *mux_false,
499 * Returns the libFirm configuration parameter for this backend.
501 static const backend_params *amd64_get_backend_params(void) {
502 static backend_params p = {
503 0, /* no inline assembly */
504 1, /* support Rotl nodes */
505 0, /* little endian */
506 1, /* modulo shift is efficient */
507 0, /* non-modulo shift is not efficient */
508 NULL, /* will be set later */
509 amd64_is_mux_allowed, /* parameter for if conversion */
510 64, /* machine size */
511 NULL, /* float arithmetic mode */
512 NULL, /* long long type */
513 NULL, /* unsigned long long type */
514 NULL, /* long double type (not supported yet) */
515 0, /* no trampoline support: size 0 */
516 0, /* no trampoline support: align 0 */
517 NULL, /* no trampoline support: no trampoline builder */
518 8 /* alignment of stack parameter: typically 4 (32bit) or 8 (64bit) */
523 static ir_graph **amd64_get_backend_irg_list(const void *self,
531 static asm_constraint_flags_t amd64_parse_asm_constraint(const char **c)
534 return ASM_CONSTRAINT_FLAG_INVALID;
537 static int amd64_is_valid_clobber(const char *clobber)
543 static int amd64_register_saved_by(const arch_register_t *reg, int callee)
546 /* check for callee saved */
547 if (reg->reg_class == &amd64_reg_classes[CLASS_amd64_gp]) {
548 switch (reg->index) {
561 /* check for caller saved */
562 if (reg->reg_class == &amd64_reg_classes[CLASS_amd64_gp]) {
563 switch (reg->index) {
582 const arch_isa_if_t amd64_isa_if = {
584 amd64_lower_for_target,
586 NULL, /* handle intrinsics */
587 amd64_get_reg_class_for_mode,
589 amd64_get_reg_class_alignment,
590 amd64_get_backend_params,
591 amd64_get_backend_irg_list,
592 NULL, /* mark remat */
593 amd64_parse_asm_constraint,
594 amd64_is_valid_clobber,
597 NULL, /* get_pic_base */
598 NULL, /* before_abi */
603 amd64_register_saved_by,
608 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_amd64)
609 void be_init_arch_amd64(void)
611 be_register_isa_if("amd64", &amd64_isa_if);
612 FIRM_DBG_REGISTER(dbg, "firm.be.amd64.cg");
613 amd64_init_transform();