2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main amd64 backend driver file.
23 * @version $Id: bearch_amd64.c 26909 2010-01-05 15:56:54Z matze $
27 #include "pseudo_irg.h"
38 #include "../bearch.h"
39 #include "../benode.h"
40 #include "../belower.h"
41 #include "../besched.h"
43 #include "../bemodule.h"
44 #include "../begnuas.h"
45 #include "../belistsched.h"
47 #include "bearch_amd64_t.h"
49 #include "amd64_new_nodes.h"
50 #include "gen_amd64_regalloc_if.h"
51 #include "amd64_transform.h"
52 #include "amd64_emitter.h"
54 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
56 static arch_irn_class_t amd64_classify(const ir_node *irn)
62 static ir_entity *amd64_get_frame_entity(const ir_node *node)
65 /* TODO: return the ir_entity assigned to the frame */
69 static void amd64_set_frame_entity(ir_node *node, ir_entity *ent)
73 /* TODO: set the ir_entity assigned to the frame */
77 * This function is called by the generic backend to correct offsets for
78 * nodes accessing the stack.
80 static void amd64_set_frame_offset(ir_node *irn, int offset)
84 /* TODO: correct offset if irn accesses the stack */
87 static int amd64_get_sp_bias(const ir_node *irn)
93 /* fill register allocator interface */
95 static const arch_irn_ops_t amd64_irn_ops = {
98 amd64_get_frame_entity,
99 amd64_set_frame_entity,
100 amd64_set_frame_offset,
102 NULL, /* get_inverse */
103 NULL, /* get_op_estimated_cost */
104 NULL, /* possible_memory_operand */
105 NULL, /* perform_memory_operand */
111 * Transforms the standard firm graph into
114 static void amd64_prepare_graph(void *self)
116 amd64_code_gen_t *cg = self;
118 amd64_transform_graph (cg);
121 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
127 * Called immediatly before emit phase.
129 static void amd64_finish_irg(void *self)
131 amd64_code_gen_t *cg = self;
132 ir_graph *irg = cg->irg;
134 dump_ir_block_graph_sched(irg, "-amd64-finished");
138 static void amd64_before_ra(void *self)
141 /* Some stuff you need to do after scheduling but before register allocation */
144 static void amd64_after_ra(void *self)
147 /* Some stuff you need to do immediatly after register allocation */
153 * Emits the code, closes the output file and frees
154 * the code generator interface.
156 static void amd64_emit_and_done(void *self)
158 amd64_code_gen_t *cg = self;
159 ir_graph *irg = cg->irg;
161 amd64_gen_routine(cg, irg);
163 /* de-allocate code generator */
167 static void *amd64_cg_init(be_irg_t *birg);
169 static const arch_code_generator_if_t amd64_code_gen_if = {
171 NULL, /* get_pic_base hook */
172 NULL, /* before abi introduce hook */
174 NULL, /* spill hook */
175 amd64_before_ra, /* before register allocation hook */
176 amd64_after_ra, /* after register allocation hook */
182 * Initializes the code generator.
184 static void *amd64_cg_init(be_irg_t *birg)
186 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
187 amd64_isa_t *isa = (amd64_isa_t *) arch_env;
188 amd64_code_gen_t *cg = XMALLOC(amd64_code_gen_t);
190 cg->impl = &amd64_code_gen_if;
191 cg->irg = be_get_birg_irg(birg);
194 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
196 return (arch_code_generator_t *)cg;
201 const arch_isa_if_t amd64_isa_if;
202 static amd64_isa_t amd64_isa_template = {
204 &amd64_isa_if, /* isa interface implementation */
205 &amd64_gp_regs[REG_RSP], /* stack pointer register */
206 &amd64_gp_regs[REG_RBP], /* base pointer register */
207 &amd64_reg_classes[CLASS_amd64_gp], /* link pointer register class */
208 -1, /* stack direction */
209 2, /* power of two stack alignment for calls, 2^2 == 4 */
210 NULL, /* main environment */
211 7, /* costs for a spill instruction */
212 5, /* costs for a reload instruction */
217 * Initializes the backend ISA
219 static arch_env_t *amd64_init(FILE *outfile)
221 static int run_once = 0;
228 isa = XMALLOC(amd64_isa_t);
229 memcpy(isa, &amd64_isa_template, sizeof(*isa));
231 be_emit_init(outfile);
233 amd64_register_init();
234 amd64_create_opcodes(&amd64_irn_ops);
236 return &isa->arch_env;
242 * Closes the output file and frees the ISA structure.
244 static void amd64_done(void *self)
246 amd64_isa_t *isa = self;
248 /* emit now all global declarations */
249 be_gas_emit_decls(isa->arch_env.main_env);
256 static unsigned amd64_get_n_reg_class(void)
261 static const arch_register_class_t *amd64_get_reg_class(unsigned i)
263 assert(i < N_CLASSES);
264 return &amd64_reg_classes[i];
270 * Get the register class which shall be used to store a value of a given mode.
271 * @param self The this pointer.
272 * @param mode The mode in question.
273 * @return A register class which can hold values of the given mode.
275 static const arch_register_class_t *amd64_get_reg_class_for_mode(const ir_mode *mode)
277 if (mode_is_float(mode))
278 return &amd64_reg_classes[CLASS_amd64_fp];
280 return &amd64_reg_classes[CLASS_amd64_gp];
286 be_abi_call_flags_bits_t flags;
287 const arch_env_t *arch_env;
291 static void *amd64_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
293 amd64_abi_env_t *env = XMALLOC(amd64_abi_env_t);
294 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
295 env->flags = fl.bits;
297 env->arch_env = arch_env;
302 * Get the between type for that call.
303 * @param self The callback object.
304 * @return The between type of for that call.
306 static ir_type *amd64_get_between_type(void *self)
308 static ir_type *between_type = NULL;
309 static ir_entity *old_bp_ent = NULL;
313 ir_entity *ret_addr_ent;
314 ir_type *ret_addr_type = new_type_primitive(mode_P);
315 ir_type *old_bp_type = new_type_primitive(mode_P);
317 between_type = new_type_class(new_id_from_str("amd64_between_type"));
318 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
319 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
321 set_entity_offset(old_bp_ent, 0);
322 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
323 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
330 * Build the prolog, return the BASE POINTER register
332 static const arch_register_t *amd64_abi_prologue(void *self, ir_node **mem,
333 pmap *reg_map, int *stack_bias)
335 amd64_abi_env_t *env = self;
336 const arch_env_t *aenv = env->arch_env;
342 if (!env->flags.try_omit_fp) {
343 /* FIXME: maybe later here should be some code to generate
344 * the usual abi prologue */
345 return env->arch_env->bp;
348 return env->arch_env->sp;
351 /* Build the epilog */
352 static void amd64_abi_epilogue(void *self, ir_node *bl, ir_node **mem,
355 amd64_abi_env_t *env = self;
356 const arch_env_t *aenv = env->arch_env;
357 ir_node *curr_sp = be_abi_reg_map_get(reg_map, aenv->sp);
358 ir_node *curr_bp = be_abi_reg_map_get(reg_map, aenv->bp);
362 if (env->flags.try_omit_fp) {
363 curr_sp = be_new_IncSP(aenv->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
366 be_abi_reg_map_set(reg_map, aenv->sp, curr_sp);
367 be_abi_reg_map_set(reg_map, aenv->bp, curr_bp);
370 static const be_abi_callbacks_t amd64_abi_callbacks = {
373 amd64_get_between_type,
379 * Get the ABI restrictions for procedure calls.
380 * @param self The this pointer.
381 * @param method_type The type of the method (procedure) in question.
382 * @param abi The abi object to be modified
384 static void amd64_get_call_abi(const void *self, ir_type *method_type,
389 int i, n = get_method_n_params(method_type);
390 be_abi_call_flags_t call_flags;
393 /* set abi flags for calls */
394 call_flags.bits.left_to_right = 0;
395 call_flags.bits.store_args_sequential = 1;
396 call_flags.bits.try_omit_fp = 1;
397 call_flags.bits.fp_free = 0;
398 call_flags.bits.call_has_imm = 1;
400 /* set stack parameter passing style */
401 be_abi_call_set_flags(abi, call_flags, &amd64_abi_callbacks);
403 for (i = 0; i < n; i++) {
404 /* TODO: implement register parameter: */
405 /* reg = get reg for param i; */
406 /* be_abi_call_param_reg(abi, i, reg); */
408 /* default: all parameters on stack */
409 tp = get_method_param_type(method_type, i);
410 mode = get_type_mode(tp);
411 be_abi_call_param_stack(abi, i, mode, 4, 0, 0, ABI_CONTEXT_BOTH);
414 /* TODO: set correct return register */
415 /* default: return value is in R0 resp. F0 */
416 if (get_method_n_ress(method_type) > 0) {
417 tp = get_method_res_type(method_type, 0);
418 mode = get_type_mode(tp);
420 /* FIXME: No floating point yet */
421 /* be_abi_call_res_reg(abi, 0,
422 mode_is_float(mode) ? &amd64_fp_regs[REG_F0] : &amd64_gp_regs[REG_R0], ABI_CONTEXT_BOTH) */;
424 be_abi_call_res_reg(abi, 0,
425 &amd64_gp_regs[REG_RAX], ABI_CONTEXT_BOTH);
429 static int amd64_to_appear_in_schedule(void *block_env, const ir_node *irn)
433 if(!is_amd64_irn(irn))
440 * Initializes the code generator interface.
442 static const arch_code_generator_if_t *amd64_get_code_generator_if(
446 return &amd64_code_gen_if;
449 list_sched_selector_t amd64_sched_selector;
452 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
454 static const list_sched_selector_t *amd64_get_list_sched_selector(
455 const void *self, list_sched_selector_t *selector)
460 amd64_sched_selector = trivial_selector;
461 amd64_sched_selector.to_appear_in_schedule = amd64_to_appear_in_schedule;
462 return &amd64_sched_selector;
465 static const ilp_sched_selector_t *amd64_get_ilp_sched_selector(
473 * Returns the necessary byte alignment for storing a register of given class.
475 static int amd64_get_reg_class_alignment(const arch_register_class_t *cls)
477 ir_mode *mode = arch_register_class_mode(cls);
478 return get_mode_size_bytes(mode);
482 * Returns the libFirm configuration parameter for this backend.
484 static const backend_params *amd64_get_backend_params(void) {
485 static backend_params p = {
486 0, /* no dword lowering */
487 0, /* no inline assembly */
488 NULL, /* will be set later */
489 NULL, /* no creator function */
490 NULL, /* context for create_intrinsic_fkt */
491 NULL, /* parameter for if conversion */
492 NULL, /* float arithmetic mode */
493 0, /* no trampoline support: size 0 */
494 0, /* no trampoline support: align 0 */
495 NULL, /* no trampoline support: no trampoline builder */
496 4 /* alignment of stack parameter: typically 4 (32bit) or 8 (64bit) */
501 static const be_execution_unit_t ***amd64_get_allowed_execution_units(
510 static const be_machine_t *amd64_get_machine(const void *self)
518 static ir_graph **amd64_get_backend_irg_list(const void *self,
526 static asm_constraint_flags_t amd64_parse_asm_constraint(const char **c)
529 return ASM_CONSTRAINT_FLAG_INVALID;
532 static int amd64_is_valid_clobber(const char *clobber)
538 const arch_isa_if_t amd64_isa_if = {
541 NULL, /* handle intrinsics */
542 amd64_get_n_reg_class,
544 amd64_get_reg_class_for_mode,
546 amd64_get_code_generator_if,
547 amd64_get_list_sched_selector,
548 amd64_get_ilp_sched_selector,
549 amd64_get_reg_class_alignment,
550 amd64_get_backend_params,
551 amd64_get_allowed_execution_units,
553 amd64_get_backend_irg_list,
554 NULL, /* mark remat */
555 amd64_parse_asm_constraint,
556 amd64_is_valid_clobber
559 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_amd64);
560 void be_init_arch_amd64(void)
562 be_register_isa_if("amd64", &amd64_isa_if);
563 FIRM_DBG_REGISTER(dbg, "firm.be.amd64.cg");
564 amd64_init_transform();